In video coding, the output of the previous picture for a picture that starts a new coded video sequence

Abstract

To provide a method for decoding a coded video bitstream and a corresponding method for encoding.SOLUTION: A method includes receiving a coded video bitstream including a first flag having a first value and a clean random access (CRA) picture, setting a second value of a second flag to be equal to the first value of the first flag, emptying, by a video decoder, a decoded picture buffer (DPB) of any previously decoded pictures on the basis of the second flag having the second value, and decoding a current picture after the DPB is emptied.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This patent application claims priority to U.S. Provisional Patent Application No. 62 / 843,991, entitled "Output of Previous Picture for a Picture Starting a New Coded Video Sequence in Video Coding," filed May 6, 2019 by Ye-Kui Wang, the contents of which are incorporated herein by reference in their entirety.

[0002] [Technical field] Generally, this disclosure describes techniques for supporting output of previously decoded pictures during video coding. More specifically, this disclosure enables outputting from a decoded picture buffer a previously decoded picture that corresponds to a random access point picture that starts a video sequence (CVS) being coded. [Background technology]

[0003] The amount of video data required to render even a relatively short video can be substantial, which can be challenging when the data is streamed or otherwise communicated over communication networks with limited bandwidth capacity. As such, video data is typically compressed before being communicated over modern communication networks. Because memory resources may be limited, the size of the video can also be an issue when storing the video on a storage device. Video compression devices often use software and / or hardware at the source to code the video data before transmission or storage, thereby reducing the amount of data required to represent a digital video image. The compressed data is then received at the destination by a video decompression device, which decodes the video data. With limited network resources and ever-increasing demands for higher video quality, improved compression and decompression techniques that improve compression ratios without significantly sacrificing image quality are desirable. Summary of the Invention

[0004] A first aspect relates to a method of decoding implemented by a video decoder, the method including: receiving, by the video decoder, a video bitstream being coded, the video bitstream being coded including a first flag having a first value and a clean random access (CRA) picture; setting, by the video decoder, a second value of a second flag to be equal to the first value of the first flag; emptying, by the video decoder, a decoding picture buffer (DPB) of any previously decoded pictures based on the second flag having the second value; and decoding, by the video decoder, a current picture after the DPB is emptied.

[0005] The method provides a technique for outputting a previous picture (e.g., a previously decoded picture) in a decoding picture buffer (DPB) when a random access point picture other than an instantaneous decoder refresh (IDR) picture (e.g., a clean random access (CRA) picture, a gradual random access (GRA) picture, or a gradual decoding refresh (GDR) picture, a CVSS picture, etc.) is encountered in decoding order. Emptying previously decoded pictures from the DPB when a random access point picture is reached prevents the DPB from overflowing and promotes more continuous playback. Thus, the coder / decoder (also known as a "codec") in video coding is improved compared to current codecs. In practical terms, the improved video coding process provides a better user experience when video is transmitted, received, and / or viewed.

[0006] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the CRA picture is not the first picture of the video bitstream being coded.

[0007] Optionally, in any of the preceding aspects, another implementation of the aspect provides a step of setting a DPB fullness parameter to 0 when the first flag is set to the first value.

[0008] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the first flag is specified as no_output_of_prior_pics_flag and the second flag is specified as NoOutputOfPriorPicsFlag.

[0009] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the DPB is emptied after the CRA picture is decoded.

[0010] Optionally, in any of the preceding aspects, other implementations of the aspect provide displaying an image generated based on the current picture.

[0011] A second aspect relates to an encoding method implemented by a video encoder, the method including: determining, by the video encoder, a random access point for a video sequence; encoding, by the video encoder, a clean random access (CRA) picture into the video sequence at the random access point; setting, by the video encoder, a flag to a first value to instruct a video decoder to empty a decoded picture buffer (DPB) of any previously decoded pictures; generating, by the video encoder, a video bitstream including the video sequence with the CRA picture at the random access point and the flag; and storing, by the video encoder, the video bitstream for transmission to the video decoder.

[0012] The method provides a technique for outputting a previous picture (e.g., a previously decoded picture) in a decoding picture buffer (DPB) when a random access point picture other than an instantaneous decoder refresh (IDR) picture (e.g., a clean random access (CRA) picture, a gradual random access (GRA) picture, or a gradual decoding refresh (GDR) picture, a CVSS picture, etc.) is encountered in decoding order. Emptying previously decoded pictures from the DPB when a random access point picture is reached prevents the DPB from overflowing and promotes more continuous playback. Thus, the coder / decoder (also known as a "codec") in video coding is improved compared to current codecs. In practical terms, the improved video coding process provides a better user experience when video is transmitted, received, and / or viewed.

[0013] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the CRA picture is not the first picture in the video bitstream and the video decoder is instructed to empty the DPB after the CRA picture is decoded.

[0014] Optionally, in any of the preceding aspects, another implementation of the aspect provides a step of instructing the video decoder to set a DPB fullness parameter to 0 when the flag is set to the first value.

[0015] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the flag is specified as no_output_of_prior_pics_flag.

[0016] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the first value of the flag is one.

[0017] A third aspect relates to a decoding device including: a receiver configured to receive a coded video bitstream; a memory coupled to the receiver, the memory storing instructions; and a processor coupled to the memory, the processor configured to execute the instructions to cause the decoding device to receive the coded video bitstream, the coded video bitstream including a first flag having a first value and a clean random access (CRA) picture; set a second value of a second flag to be equal to the first value of the first flag; empty a decoding picture buffer (DPB) of any previously decoded pictures based on the second flag having the second value; and decode a current picture after the DPB is emptied.

[0018] When a random access point picture other than an instantaneous decoder refresh (IDR) picture (e.g., a clean random access (CRA) picture, a gradual random access (GRA) picture, or a gradual decoding refresh (GDR) picture, a CVSS picture, etc.) is encountered in decoding order, the decoding device provides a technique for outputting a previous picture (e.g., a previously decoded picture) in a decoding picture buffer (DPB). Emptying previously decoded pictures from the DPB when a random access point picture is reached prevents the DPB from overflowing and promotes more continuous playback. Thus, coders / decoders (also known as "codecs") in video coding are improved compared to current codecs. In practical terms, the improved video coding process provides users with a better user experience when video is transmitted, received, and / or viewed.

[0019] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the CRA picture is not the first picture of the video bitstream being coded.

[0020] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the first flag is specified as no_output_of_prior_pics_flag and the second flag is specified as NoOutputOfPriorPicsFlag.

[0021] Optionally, in any of the preceding aspects, another implementation of the aspect provides a display configured to display an image generated based on the current picture.

[0022] A fourth aspect relates to an encoding device including: a memory containing instructions; a processor coupled to the memory, the processor configured to implement the instructions to cause the encoding device to determine a random access point for a video sequence, encode a clean random access (CRA) picture into the video sequence at the random access point, set a flag to a first value to instruct a video decoder to empty any previously decoded pictures from a decoded picture buffer (DPB); and generate the video bitstream including the video sequence with the CRA picture at the random access point and the flag; and a transmitter coupled to the processor, the transmitter configured to transmit the video bitstream to a video decoder.

[0023] When a random access point picture other than an instantaneous decoder refresh (IDR) picture (e.g., a clean random access (CRA) picture, a gradual random access (GRA) picture, or a gradual decoding refresh (GDR) picture, a CVSS picture, etc.) is encountered in decoding order, the encoding device provides a technique for outputting a previous picture (e.g., a previously decoded picture) in a decoding picture buffer (DPB). Emptying previously decoded pictures from the DPB when a random access point picture is reached prevents the DPB from overflowing and promotes more continuous playback. Thus, coders / decoders (also known as "codecs") in video coding are improved compared to current codecs. In practical terms, the improved video coding process provides users with a better user experience when video is transmitted, received, and / or viewed.

[0024] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the CRA picture is not the first picture of the video bitstream.

[0025] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the flag is specified as no_output_of_prior_pics_flag.

[0026] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the memory stores the bitstream before the transmitter transmits the bitstream to the video decoder.

[0027] A fifth aspect relates to a coding apparatus including: a receiver configured to receive pictures for encoding or to receive a bitstream for decoding, a transmitter coupled to the receiver, the transmitter configured to transmit the bitstream to a decoder or transmit decoded images to a display, a memory coupled to at least one of the receiver or the transmitter, the memory configured to store instructions, and a processor coupled to the memory, the processor configured to execute the instructions stored in the memory to perform any of the methods disclosed herein.

[0028] When a random access point picture other than an instantaneous decoder refresh (IDR) picture (e.g., a clean random access (CRA) picture, a gradual random access (GRA) picture, or a gradual decoding refresh (GDR) picture, a CVSS picture, etc.) is encountered in decoding order, the coding device provides a technique for outputting a previous picture (e.g., a previously decoded picture) in a decoding picture buffer (DPB). Emptying previously decoded pictures from the DPB when a random access point picture is reached prevents the DPB from overflowing and promotes more continuous playback. Thus, the coder / decoder (also known as a "codec") in video coding is improved compared to current codecs. In practical terms, the improved video coding process provides a better user experience when video is transmitted, received, and / or viewed.

[0029] Optionally, in any of the preceding aspects, other implementations of the aspect provide a display configured to display the image.

[0030] A sixth aspect relates to a system, comprising an encoder and a decoder in communication with the encoder, wherein the encoder or the decoder comprises a decoding device, encoding device, or coding apparatus disclosed herein.

[0031] When a random access point picture other than an instantaneous decoder refresh (IDR) picture (e.g., a clean random access (CRA) picture, a gradual random access (GRA) picture, or a gradual decoding refresh (GDR) picture, a CVSS picture, etc.) is encountered in decoding order, the system provides a technique for outputting a previous picture (e.g., a previously decoded picture) in a decoding picture buffer (DPB). Emptying previously decoded pictures from the DPB when a random access point picture is reached prevents the DPB from overflowing and promotes more continuous playback. Thus, the coder / decoder (also known as a "codec") in video coding is improved compared to current codecs. In practical terms, the improved video coding process provides a better user experience when video is transmitted, received, and / or viewed.

[0032] A seventh aspect relates to means for coding, the means for coding including: receiving means configured to receive pictures for encoding or to receive a bitstream for decoding, transmitting means coupled to said receiving means, the transmitting means configured to transmit the bitstream to decoding means or to transmit decoded images to display means, storage means coupled to at least one of said receiving means or said transmitting means, the storage means configured to store instructions, and processing means coupled to said storage means, the processing means configured to execute the instructions stored in said storage means to perform any of the methods disclosed herein.

[0033] When a random access point picture other than an instantaneous decoder refresh (IDR) picture (e.g., a clean random access (CRA) picture, a gradual random access (GRA) picture, or a gradual decoding refresh (GDR) picture, a CVSS picture, etc.) is encountered in decoding order, the coding means provides a technique for outputting a previous picture (e.g., a previously decoded picture) in a decoding picture buffer (DPB). Emptying previously decoded pictures from the DPB when a random access point picture is reached prevents the DPB from overflowing and promotes more continuous playback. Thus, the coder / decoder (also known as a "codec") in video coding is improved compared to current codecs. In practical terms, the improved video coding process provides a better user experience when video is transmitted, received, and / or viewed.

[0034] For clarity, any one of the above embodiments may be combined with any one or more of the other embodiments described above to create new embodiments within the scope of this disclosure.

[0035] These and other features will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings and claims. [Brief explanation of the drawings]

[0036] For a more complete understanding of this disclosure, reference is now made to the following brief description taken in conjunction with the accompanying drawings and detailed description, in which like reference numerals represent like parts.

[0037] [Figure 1] FIG. 1 is a block diagram illustrating an exemplary coding system that can utilize GDR techniques. [Figure 2]1 is a block diagram illustrating an example video encoder capable of implementing GDR techniques. [Figure 3] 1 is a block diagram illustrating one example of a video decoder capable of implementing GDR techniques. [Figure 4] This represents the relationship between the IRAP pictures relative to the leading and trailing pictures in decoding order and the IRAP pictures relative to the leading and trailing pictures in presentation order. [Figure 5] 1 illustrates a gradual decoding refresh technique. [Figure 6] FIG. 1 is a schematic diagram illustrating undesirable motion estimation. [Figure 7] 1 illustrates a video bitstream configured to implement a clean random access (CRA) technique. [Figure 8] 1 is an embodiment of a method for decoding a coded video bitstream. [Figure 9] 1 is an embodiment of a method for encoding a video bitstream being coded; [Figure 10] 1 is a schematic diagram of a video coding device; [Figure 11] FIG. 11 is a schematic diagram of one embodiment of a means for coding. DETAILED DESCRIPTION OF THE INVENTION

[0038] First, while the following provides an exemplary implementation of one or more of the embodiments, it should be understood that any number of technologies, whether currently known or in existence, may be used to implement the disclosed systems and / or methods. This disclosure should in no way be limited to those exemplary implementations, drawings, and technologies described below, including the exemplary designs and implementations illustrated and described herein, but may be modified within the scope of the appended claims, along with the full scope of equivalents thereof.

[0039] FIG. 1 is a block diagram illustrating an exemplary coding system 10, which can utilize the video coding techniques described herein. As shown in FIG. 1, the coding system 10 includes a source device 12 that provides encoded video data that is later decoded by a destination device 14. In particular, the source device 12 may provide the video data to the destination device 14 via a computer-readable medium 16. The source device 12 and the destination device 14 may include any of a wide range of devices, including desktop computers, notebook computers (e.g., laptop computers), tablet computers, set-top boxes, telephone handsets such as so-called "smart" phones, so-called "smart" pads, televisions, cameras, display devices, digital media players, video game consoles, or video streaming devices. In some cases, the source device 12 and the destination device 14 may be capable of wireless communication.

[0040] The destination device 14 may receive the encoded video data to be decoded via a computer-readable medium 16. The computer-readable medium 16 may include any type of medium or device capable of transporting the encoded video data from the source device 12 to the destination device 14. In one example, the computer-readable medium 16 may include a communications medium that enables the source device 12 to transmit the encoded video data directly to the destination device 14 in real time. The encoded video data may be modulated according to a communications standard, such as a wireless communications protocol, and then transmitted to the destination device 14. The communications medium may include any wireless or wired communications medium, such as the radio frequency (RF) spectrum or one or more physical transmission lines. The communications medium may form part of a packet-based network, such as a local area network, a wide area network, or a global network such as the Internet. The communications medium may include routers, switches, base stations, or other equipment that may be useful in facilitating communication from the source device 12 to the destination device 14.

[0041] In some examples, the encoded data may be output from the output interface 22 to a storage device. Similarly, the encoded data may be accessed from the storage device by the input interface. The storage device may include any of a variety of distributed or locally accessed data storage media, such as a hard drive, Blu-ray Disc, digital video disc (DVD), compact disc read-only memory (CD-ROM), flash memory, volatile or non-volatile memory, or any other suitable digital storage medium for storing encoded video data. In a further example, the storage device may correspond to a file server or other intermediate storage device capable of storing the encoded video generated by the source device 12. The destination device 14 may access the stored video data from the storage device by streaming or downloading. The file server may be any type of server capable of storing the encoded video data and transmitting the encoded video data to the destination device 14. Exemplary file servers include a web server (e.g., for a website), a file transfer protocol (FTP) server, a network-attached storage (NAS) device, or a local disk drive. Destination device 14 can access the encoded video data over any standard data connection, including an Internet connection. This standard data connection may include a wireless channel (e.g., a Wi-Fi connection), a wired connection (e.g., a digital subscriber line (DSL), a cable modem, etc.), or a combination of both a wireless channel and a wired connection suitable for accessing encoded video data stored on a file server. Transmission of the encoded video data from the storage device may be a streaming transmission, a download transmission, or a combination thereof.

[0042] The techniques of this disclosure are not necessarily limited to wireless applications or settings. They may be applied to video coding in support of any of a variety of multimedia applications, such as over-the-air television broadcast, cable television transmission, satellite television transmission, Internet streaming video transmission such as Dynamic Adaptive Streaming over HTTP (DASH), digital video encoded on a data storage medium, decoding of digital video stored on a data storage medium, or other applications. In some examples, coding system 10 may be configured to support one-way or two-way video transmission to support applications such as video streaming, video playback, video broadcasting, and / or video telephony.

[0043] In the example of FIG. 1 , source device 12 includes video source 18, video encoder 20, and output interface 22. Destination device 14 includes input interface 28, video decoder 30, and display device 32. According to this disclosure, video encoder 20 of source device 12 and / or video decoder 30 of destination device 14 may be configured to apply multiple techniques for video coding. In other examples, the source and destination devices may include other components or arrangements. For example, source device 12 may receive video data from an external video source, such as an external camera. Similarly, destination device 14 may provide an interface to an external display device rather than including an integrated display device.

[0044] The illustrated coding system 10 of FIG. 1 is just one example. The techniques for video coding may be performed by any digital video encoding and / or decoding device. While the techniques of this disclosure are generally performed by a video coding device, the techniques may also be performed by a video encoder / decoder, typically referred to as a "CODEC." Furthermore, the techniques of this disclosure may also be performed by a video processor. The video encoder and / or video decoder may be a graphics processing unit or similar device.

[0045] Source device 12 and destination device 14 are merely examples of such coding devices where source device 12 generates video data that is coded for transmission to destination device 14. In some examples, source device 12 and destination device 14 may operate in a substantially symmetric manner, whereby source device 12 and destination device 14 each include video encoding and video decoding components. Thus, coding system 10 can support one-way or two-way video transmission between multiple video devices 12 and 14, e.g., for video streaming, video playback, video broadcasting, or video telephony.

[0046] Video source 18 of origin device 12 may include a video capture device such as a video camera, a video archive containing previously captured video, and / or a video feed interface for receiving video from a video content provider. As a further alternative, video source 18 may generate computer-graphics-based data as the originating video or a combination of live video, archived video, and computer-generated video.

[0047] In some cases, when video source 18 is a video camera, source device 12 and destination device 14 may form a so-called cameraphone or videophone. However, as mentioned above, the techniques described in this disclosure may be applicable to video coding generally, and may apply to wireless and / or wired applications. In each case, captured, pre-captured, or computer-generated video may be encoded by video encoder 20. The encoded video information may then be output to computer-readable medium 16 by output interface 22.

[0048] Computer-readable medium 16 may include a transitory medium, such as a wireless broadcast transmission or a wired network transmission, or a storage medium (i.e., a non-transitory medium), such as a hard disk, flash drive, compact disc, digital video disc, Blu-ray disc, or other computer-readable medium. In some examples, a network server (not shown) may receive encoded video data from source device 12 and provide the encoded video data to destination device 14, for example, via a network transmission. Similarly, a computing device at a media production facility, such as a disc engraving facility, may receive encoded video data from source device 12 and manufacture discs containing the encoded video data. Thus, computer-readable medium 16 may be understood to include one or more of various forms of computer-readable media in various examples.

[0049] Input interface 28 of destination device 14 receives information from computer-readable medium 16. That information on computer-readable medium 16 may include syntax information defined by video encoder 20, which is also used by video decoder 30, including syntax elements that describe the characteristics and / or processing of blocks and other coded units, such as groups of pictures (GOPs). Display device 32 displays the decoded video data to a user and may include any of a variety of display devices, such as a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, an organic light-emitting diode (OLED) display, or other types of display devices.

[0050] Video encoder 20 and video decoder 30 may operate in accordance with a video coding standard, such as the High Efficiency Video Coding (HEVC) standard currently under development, and may conform to the HEVC Test Model (HM). Alternatively, video encoder 20 and video decoder 30 may operate in accordance with other proprietary or industry standards, such as the Moving Picture Experts Group (MPEG) 4, Part 10, Advanced Video Coding (AVC), H.265 / HEVC, or the International Telecommunications Union Telecommunications Standardization Sector (ITU-T) H.264 standard, referred to as an extension of such a standard. However, the techniques of this disclosure are not limited to any particular coding standard. Other examples of video coding standards include MPEG-2 and ITU-T H.263. 1, in some embodiments, video encoder 20 and video decoder 30 may be integrated with an audio encoder and decoder, respectively, and may include a suitable multiplexer-demultiplexer (MUX-DEMUX) unit or other hardware and software to handle the encoding of both audio and video in a common data stream or separate data streams. Where applicable, the MUX-DEMUX unit may conform to the ITU H.223 multiplexer protocol or other protocols, such as the User Datagram Protocol (UDP).

[0051] Video encoder 20 and video decoder 30 may each be implemented as any of a variety of suitable encoder circuits, such as one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), discrete logic, software, hardware, firmware, or any combination thereof. When the techniques are implemented in part by software, a device may store instructions for the software in a suitable non-transitory computer-readable medium and execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Each of video encoder 20 and video decoder 30 may be included in one or more encoders or decoders, any of which may be integrated to form part of a combined encoder / decoder (CODEC) within the respective device. Devices including video encoder 20 and / or video decoder 30 may include integrated circuits, microprocessors, and / or wireless communication devices such as cellular telephones.

[0052] 2 is a block diagram illustrating one example of a video encoder 20 capable of implementing video coding techniques. The video encoder 20 may perform intra-frame and inter-frame coding of video blocks within a video slice. Intra-frame coding relies on spatial prediction to reduce or remove spatial redundancy in video within a given video frame or picture. Inter-frame coding relies on temporal prediction to reduce or remove temporal redundancy in video within adjacent frames or pictures of a video sequence. An intra-frame mode (I mode) may refer to any of several spatial-based coding modes. An inter-frame mode, such as uni-prediction (also known as uni-prediction) (P mode) or bi-prediction (also known as bi-prediction) (B mode), may refer to any of several temporal-based coding modes.

[0053] As shown in FIG. 2, video encoder 20 receives a current video block in a video frame to be encoded. In the example of FIG. 2, video encoder 20 includes a mode select unit 40, a reference frame memory 64, a summing adder 50, a transform processing unit 52, a quantization unit 54, and an entropy coding unit 56. Mode select unit 40 similarly includes a motion compensation unit 44, a motion estimation unit 42, an intraframe prediction unit 46 (also known as intra-prediction), and a partitioning unit 48. For video block reconstruction, video encoder 20 also includes an inverse quantization unit 58, an inverse transform unit 60, and a summing adder 62. Video encoder 20 may also include a deblocking filter (not shown in FIG. 2) for filtering block boundaries to remove blockiness artifacts from the reconstructed video. If necessary, the deblocking filter would typically filter the output of summing adder 62. In addition to the deblocking filter, additional filters (such as in-loop or post-loop filters) may also be used. Such a filter is not shown for simplicity, but may optionally filter the output of summing adder 50 (as an in-loop filter).

[0054] During the encoding process, video encoder 20 receives a video frame or slice to be coded. The frame or slice may be divided into multiple video blocks. Motion estimation unit 42 and motion compensation unit 44 perform inter-frame predictive coding of the received video block relative to one or more blocks in one or more reference frames to provide temporal prediction. Intra-frame prediction unit 46 may alternatively perform intra-frame predictive coding of the received video block relative to one or more neighboring blocks in the same frame or slice as the block to be coded to provide spatial prediction. Video encoder 20 may perform multiple coding passes, e.g., to select an appropriate coding mode for each block of video data.

[0055] Furthermore, partitioning unit 48 may partition blocks of video data into sub-blocks based on an evaluation of a previous partitioning scheme in a previous coding pass. For example, partitioning unit 48 first partitions a frame or slice into largest coding units (LCUs) and then partitions each of those LCUs into sub-coding units (sub-CUs) based on a rate-distortion analysis (e.g., rate-distortion optimization). Mode selection unit 40 may also generate a quadtree data structure indicating the partitioning of the LCUs into sub-CUs. A leaf-node CU of the quadtree may include one or more prediction units (PUs) and one or more transform units (TUs).

[0056] This disclosure uses the term "block" to refer to any of a CU, PU, ​​or TU in the context of HEVC, or similar data structures in the context of other standards (e.g., a macroblock and its subblocks in the context of H.264 / AVC). A CU includes a coding node, a PU, and a TU associated with the coding node. The size of a CU corresponds to the size of the coding node and is square in shape. The sizes of CUs range from 8x8 pixels up to the treeblock size of 64x64 pixels or larger. Each CU may include one or more PUs and one or more TUs. Syntax data associated with a CU may describe, for example, the partitioning of the CU into one or more PUs. The partitioning mode may differ depending on whether the CU is coded in skip mode or direct mode, in intra-frame prediction mode, or in inter-frame prediction mode (also known as inter-prediction). A PU may be partitioned into a non-square shape. Syntax data associated with a CU may also describe the partitioning of the CU into one or more TUs, for example according to a quadtree. The TUs may be square or non-square in shape (e.g., rectangular).

[0057] Mode select unit 40 may select one of the coding modes, such as an intra-frame coding mode or an inter-frame coding mode, based on the error result, provide the resulting intra-frame or inter-frame coded block to summing adder 50 to generate residual block data, and provide the residual block data to summing adder 62 to reconstruct the coded block for use as a reference frame. Mode select unit 40 also provides syntax elements, such as motion vectors, intra-frame mode indicators, partitioning information, and other such syntax information, to entropy coding unit 56.

[0058] Motion estimation unit 42 and motion compensation unit 44 may be highly integrated but are illustrated separately for conceptual purposes. Motion estimation, performed by motion estimation unit 42, is the process of generating motion vectors, which estimate motion for video blocks. A motion vector may indicate, for example, the displacement of a PU of a video block in a current video frame or picture relative to a predictive block (or other coded unit) in a reference frame relative to a current block (or other coded unit) being coded in the current frame. A predictive block is a block found to closely match a coded block in terms of pixel differences, and the predictive block may be determined by sum of absolute differences (SAD), sum of squared differences (SSD), or other difference metrics. In some examples, video encoder 20 may calculate values ​​for sub-integer pixel locations of a reference picture stored in reference frame memory 64. For example, video encoder 20 may interpolate values ​​for quarter-pixel locations, eighth-pixel locations, or other fractional pixel locations of a reference picture. Thus, motion estimation unit 42 may perform motion searches for full-pixel and fractional-pixel positions and output motion vectors with fractional-pixel accuracy.

[0059] Motion estimation unit 42 calculates a motion vector for a PU of a video block in an inter-coded slice by comparing the location of the PU with the location of a predictive block in a reference picture. The reference picture may be selected from a first reference picture list (List 0) or a second reference picture list (List 1), where the first reference picture list and the second reference picture list each identify one or more reference pictures stored in reference frame memory 64. Motion estimation unit 42 calculates the entropy coding It sends the calculated motion vectors to unit 56 and to motion compensation unit 44 .

[0060] The motion compensation performed by motion compensation unit 44 may involve deriving or generating a predictive block based on the motion vector determined by motion estimation unit 42. Again, in some examples, motion estimation unit 42 and motion compensation unit 44 may be functionally integrated. Upon receiving the motion vector for the PU of the current video block, motion compensation unit 44 may locate the predictive block to which the motion vector points within one of the reference picture lists. Summing adder 50 forms a residual video block by subtracting pixel values ​​of the predictive block from pixel values ​​of the current video block being coded, thereby forming pixel difference values, as described below. Typically, motion estimation unit 42 performs motion estimation with respect to the luma component, and motion compensation unit 44 uses motion vectors calculated based on the luma component for both the chroma and luma components. Mode select unit 40 may also generate syntax elements associated with the video blocks and video slices for use by video decoder 30 in decoding the video blocks of the video slices.

[0061] Intra prediction unit 46 may intra predict the current block, instead of the inter prediction performed by motion estimation unit 42 and motion compensation unit 44, as described above. In particular, intra prediction unit 46 may determine an intra prediction mode to use to encode the current block. In some examples, intra prediction unit 46 may encode the current block using various intra prediction modes, e.g., during separate encoding passes, and intra prediction unit 46 (or, in some examples, mode selection unit 40) can select an appropriate intra prediction mode to use from the modes being tested.

[0062] For example, intra prediction unit 46 may calculate rate-distortion values ​​using a rate-distortion analysis for various tested intra prediction modes and select the intra prediction mode with the best rate-distortion characteristics among the tested modes. The rate-distortion analysis generally determines the bit rate (i.e., number of bits) used to generate the coded block, as well as the amount of distortion (or error) between the block being coded and the original uncoded block previously coded to generate the coded block. Intra prediction unit 46 may calculate a ratio from the distortion and rate for the various coded blocks to determine which intra prediction mode exhibits the best rate-distortion value for the block.

[0063] Additionally, intra prediction unit 46 may be configured to code the depth blocks of the depth map using a depth modeling mode (DMM). Mode selection unit 40 may determine whether an available DMM mode produces better coding results than the intra prediction mode and other DMM modes, for example, using rate-distortion optimization (RDO). Data for texture images corresponding to the depth map may be stored in reference frame memory 64. Motion estimation unit 42 and motion compensation unit 44 may also be configured to inter-predict the depth blocks of the depth map.

[0064] After selecting an intra prediction mode for a block (e.g., a conventional intra prediction mode or one of multiple DMM modes), intra prediction unit 46 may provide information indicating the selected intra prediction mode for the block to entropy coding unit 56. Entropy coding unit 56 may encode the information indicating the selected intra prediction mode. Video encoder 20 may include configuration data in the transmitted bitstream, which may include multiple modified intra prediction mode index tables (also referred to as codeword mapping tables) and multiple intra prediction mode index tables, encoding definitions of multiple contexts for various blocks, and the most likely intra prediction mode to use for each of the multiple contexts, the intra prediction mode index table, and the modified intra prediction mode index table.

[0065] Video encoder 20 forms a residual video block by subtracting the prediction data from mode select unit 40 from the original video block being coded. Summing adder 50 represents one or more components that perform this subtraction operation.

[0066] Transform processing unit 52 applies a transform, such as a discrete cosine transform (DCT) or a conceptually similar transform, to the residual block, resulting in a video block that includes residual transform coefficient values. Transform processing unit 52 may perform other transforms that are conceptually similar to a DCT, and may also use a wavelet transform, an integer transform, a subband transform, or other types of transforms.

[0067] Transform processing unit 52 applies a transform to the residual block, resulting in a block of residual transform coefficients. The transform may convert the residual information from the pixel value domain to a transform domain, such as the frequency domain. Transform processing unit 52 may send the resulting transform coefficients to quantization unit 54. Quantization unit 54 quantizes the transform coefficients to further reduce the bit rate. The quantization process may reduce the bit depth associated with some or all of the coefficients. The degree of quantization may be modified by adjusting a quantization parameter. In some examples, quantization unit 54 may then perform a scan of a matrix containing the transform coefficients being quantized. Alternatively, entropy may be calculated using a quantization parameter. coding Unit 56 may perform the scan.

[0068] Following quantization, entropy coding unit 56 entropy codes the quantized transform coefficients. For example, entropy coding unit 56 may perform context-adaptive variable length coding (CAVLC), context-adaptive binary arithmetic coding (CABAC), syntax-based context-adaptive binary arithmetic coding (SBAC), probability interval partitioned entropy (PIPE) coding, or other entropy coding techniques. In the case of context-based entropy coding, the context may be based on multiple neighboring blocks. Following entropy coding by entropy coding unit 56, the encoded bitstream may be transmitted to another device (e.g., video decoder 30) or archived for later transmission or retrieval.

[0069] Inverse quantization unit 58 and inverse transform unit 60 apply inverse quantization and inverse transformation, respectively, to reconstruct the residual block in the pixel domain, e.g., for subsequent use as a reference block. Motion compensation unit 44 may calculate a reference block by adding the residual block to a predictive block of one of multiple frames in reference frame memory 64. Motion compensation unit 44 may also apply one or more interpolation filters to the reconstructed residual block to calculate sub-integer pixel values ​​for use in motion estimation. Summing adder 62 adds the reconstructed residual block to the motion-compensated predictive block produced by motion compensation unit 44 to generate a reconstructed video block for storage in reference frame memory 64. The reconstructed video block may be used by motion estimation unit 42 and motion compensation unit 44 as a reference block for inter-frame coding of blocks in subsequent video frames.

[0070] 3 is a block diagram illustrating one example of a video decoder 30 capable of implementing video coding techniques. In the example of FIG. 3, video decoder 30 includes an entropy decoding unit 70, a motion compensation unit 72, an intra-frame prediction unit 74, an inverse quantization unit 76, an inverse transform unit 78, a reference frame memory 82, and a summing adder 80. In some examples, video decoder 30 may perform a decoding path that is generally inverse to the encoding path described with respect to video encoder 20 (FIG. 2). Motion compensation unit 72 may generate prediction data based on the motion vectors received from entropy decoding unit 70, while intra-frame prediction unit 74 may generate prediction data based on the intra-frame prediction mode indicator received from entropy decoding unit 70.

[0071] During the decoding process, video decoder 30 receives from video encoder 20 an encoded video bitstream representing video blocks and associated syntax elements of an encoded video slice. Entropy decoding unit 70 of video decoder 30 entropy decodes the bitstream to generate quantized coefficients, motion vectors or intra-frame prediction mode indicators, and other syntax elements. Entropy decoding unit 70 forwards the motion vectors and other syntax elements to motion compensation unit 72. Video decoder 30 may receive syntax elements at the video slice level and / or the video block level.

[0072] When a video slice is coded as an intra-coded (I) slice, intra prediction unit 74 may generate predictive data for video blocks of the current video slice based on the intra prediction mode sent by signaling and data from previously decoded blocks of the current frame or picture. When a video frame is coded as an inter-coded slice (e.g., B, P, or GPB), motion compensation unit 72 generates predictive blocks for video blocks of the current video slice based on motion vectors and other syntax elements received from entropy decoding unit 70. These predictive blocks may be generated from one of multiple reference pictures in one of multiple reference picture lists. Video decoder 30 may construct reference frame lists List0 and List1 using a default construction technique based on reference pictures stored in reference frame memory 82.

[0073] Motion compensation unit 72 determines prediction information for video blocks of the current video slice by analyzing the motion vectors and other syntax elements, and uses the prediction information to generate predictive blocks for the current video block to be decoded. For example, motion compensation unit 72 uses some of the received syntax elements to determine the prediction mode (e.g., intra prediction or inter prediction) to be used to code the video blocks of the video slice, the inter prediction slice type (e.g., B slice, P slice, or GPB slice), construction information for one or more of a plurality of reference picture lists for the slice, motion vectors for each inter coded video block of the slice, inter prediction states for each inter coded video block of the slice, and other information for decoding video blocks in the current video slice.

[0074] Motion compensation unit 72 may also perform interpolation based on interpolation filters. Motion compensation unit 72 may use interpolation filters used by video encoder 20 in encoding the video block to calculate interpolated values ​​for sub-integer pixels of the reference block. In this case, motion compensation unit 72 may determine the interpolation filters used by video encoder 20 from received syntax elements and then use those interpolation filters to generate the predictive block.

[0075] Data for texture images corresponding to the depth maps may be stored in reference frame memory 82. Motion compensation unit 72 may also be configured to inter-frame predict depth blocks of the depth maps.

[0076] In one embodiment, the video decoder 30 includes a user interface (UI) 84. The user interface 84 is configured to receive input from a user of the video decoder 30 (e.g., a network administrator). Through the user interface 84, the user can manage or change settings in the video decoder 30. For example, the user can input or otherwise provide values ​​for parameters (e.g., flags) to control the configuration and / or operation of the video decoder 30 according to the user's preferences. The user interface 84 may be, for example, a graphical user interface (GUI) that allows the user to interact with the video decoder 30 through graphical icons, drop-down menus, check boxes, and the like. In some cases, the user interface 84 may receive information from the user through a keyboard, mouse, or other peripheral device. In one embodiment, the user can access the user interface 84 through a smartphone, tablet device, personal computer, or the like that is located remotely from the video decoder 30. As used herein, the user interface 84 may also be referred to as an external input or external means.

[0077] With the above in mind, video compression techniques perform spatial (intra-picture) prediction and / or temporal (inter-picture) prediction to reduce or remove redundancy inherent in video sequences. For block-based video coding, a video slice (i.e., a video picture or portion of a video picture) may be partitioned into multiple video blocks, which may also be referred to as tree blocks, coding tree blocks (CTBs), coding tree units (CTUs), coding units (CUs), and / or coding nodes. Video blocks in an intra-coded (I) slice of a picture are encoded using spatial prediction with respect to multiple reference samples among multiple neighboring blocks in the same picture. Video blocks in an inter-coded (P or B) slice of a picture may use spatial prediction with respect to multiple reference samples among multiple neighboring blocks in the same picture or temporal prediction with respect to multiple reference samples in other reference pictures. A picture may be referred to as a frame, and a reference picture may be referred to as a reference frame.

[0078] Spatial or temporal prediction produces a predictive block for the block being coded. Residual data represents pixel differences between the original block being coded and the predictive block. Inter-coded blocks are coded according to motion vectors, which point to blocks of reference samples that form the predictive block, and the residual data indicates the difference between the block being coded and the predictive block. Intra-coded blocks are coded according to an intra-coding mode and the residual data. For further compression, the residual data may be transformed from the pixel domain to a transform domain, resulting in residual transform coefficients, which may then be quantized. The quantized transform coefficients may initially be arranged in a two-dimensional array and scanned to generate a one-dimensional vector of transform coefficients, and entropy coding may be applied to achieve even greater compression.

[0079] Image and video compression continues to experience rapid growth, resulting in a variety of coding standards. Such video coding standards include Advanced Video Coding (AVC), also known as ITU-T H.261, International Organization for Standardization / International Electrotechnical Commission (ISO / IEC) MPEG-1 Part 2, ITU-T H.262 or ISO / IEC MPEG-2 Part 2, ITU-T H.263, ISO / IEC MPEG-4 Part 2, ITU-T H.264 or ISO / IEC MPEG-4 Part 10, and High Efficiency Video Coding (HEVC), also known as ITU-T H.265, MPEG-H Part 2. AVC includes extensions such as Scalable Video Coding (SVC), Multiview Video Coding (MVC) and Multiview Video Coding plus Depth (MVC+D), and 3D AVC (3D-AVC). HEVC includes extension standards such as scalable HEVC (SHVC), multi-view HEVC (MV-HEVC), and 3D HEVC (3D-HEVC).

[0080] Additionally, there is a new video coding standard called Versatile Video Coding (VVC) being developed by the Joint Video Experts Team (JVET) of ITU-T and ISO / IEC. The VVC standard has several working drafts, but this specification refers to one working draft (WD) of VVC, specifically B. Bross, J. Chen, and S. Liu, "Versatile Video Coding (Draft 5)," JVET-N1001-v3, 13th JVET Meeting, March 27, 2019 (VVC Draft 5).

[0081] While the description of the techniques disclosed herein is based on Versatile Video Coding (VVC), a video coding standard currently under development by the ITU-T and ISO / IEC Joint Video Experts Team (JVET), the techniques also apply to other video codec standards.

[0082] 4 illustrates a representation 400 of the relationship between an Intra-Frame Random Access Point (IRAP) picture 402 relative to a leading picture 404 and a trailing picture 406 in decoding order 408 and the IRAP picture 402 relative to the leading picture 404 and the trailing picture 406 in presentation order 410. In one embodiment, the IRAP picture 402 is referred to as a Clean Random Access (CRA) picture or an Instantaneous Decoder Refresh (IDR) picture with a Random Access Decodable (RADL) picture. In the case of HEVC, IDR pictures, CRA pictures, and Broken Link Access (BLA) pictures are all considered IRAP pictures 402. For VVC, it was agreed during the 12th JVET meeting in October 2018 to have both IDR and CRA pictures as IRAP pictures. In one embodiment, broken link access (BLA) pictures and gradual decoder refresh (GDR) pictures may also be considered IRAP pictures. The decoding process for a video sequence being coded always starts with an IRAP.

[0083] A CRA picture is an IRAP picture whose respective Video Coding Layer (VCL) Network Abstraction Layer (NAL) unit has nal_unit_type equal to C CRA_NUT. A CRA picture does not reference any pictures other than itself for inter-frame prediction in the decoding process and may be the first picture in the bitstream in decoding order or may appear later in the bitstream. A CRA picture may have associated RADL or random access skip-reading (RASL) pictures. When a CRA picture has NoOutputBeforeRecoveryFlag equal to 1, the associated RASL pictures are not output by the decoder because they may not be decodable because they may contain references to pictures that do not exist in the bitstream.

[0084] 4, leading pictures 404 (e.g., pictures 2 and 3) follow the IRAP picture 402 in decoding order 408 but precede the IRAP picture 402 in presentation order 410. A tail picture 406 follows the IRAP picture 402 in both decoding order 408 and presentation order 410. Although two leading pictures 404 and one tail picture 406 are shown in FIG. 4, those skilled in the art will understand that in actual applications, there may be more or fewer leading pictures 404 and / or tail pictures 406 in decoding order 408 and presentation order 410.

[0085] The leading pictures 404 in FIG. 4 are divided into two types: random access skip leading (RASL) and RADL. When decoding starts from an IRAP picture 402 (such as picture 1), it is possible to properly decode an RADL picture (such as picture 3), but it is not possible to properly decode an RASL picture (such as picture 2). Therefore, the RASL picture is discarded. Considering the distinction between RADL and RASL pictures, the type of the leading picture 404 associated with the IRAP picture 402 needs to be identified as either RADL or RASL for efficient and appropriate coding. In the case of HEVC, when an RASL and an RADL picture exist, for an RASL picture and an RADL picture associated with the same IRAP picture 402, it is constrained that the RASL picture needs to be placed before the RADL picture in the presentation order 410.

[0086] The IRAP picture 402 provides two important features / advantages. First, the presence of the IRAP picture 402 indicates that the decoding process can start from that picture. As long as the IRAP picture 402 is present in that position, this feature enables a random access feature where the decoding process starts at that position in the bitstream, not necessarily at the beginning of the bitstream. Second, the presence of the IRAP picture 402 updates the decoding process so that coded pictures starting at the IRAP picture 402 are coded without reference to previous pictures, except for RASL pictures. The presence of the IRAP picture 402 in the bitstream will prevent errors that may occur during the decoding of coded pictures before the IRAP picture 402 from propagating to the IRAP picture 402 and those pictures that follow it in decoding order 408.

[0087] While IRAP pictures 402 provide important functionality, they also penalize compression efficiency. Their presence causes a sudden increase in bit rate. This penalty to compression efficiency is due to two reasons. First, because an IRAP picture 402 is an intra-frame predicted picture, the IRAP picture 402 itself will require relatively more bits to represent when compared to other pictures that are inter-frame predicted (e.g., leading picture 404, trailing picture 406, etc.). Second, because the presence of the IRAP picture 402 interrupts temporal prediction (the interruption occurs because, in the decoding process, one of the operations of the decoding process for the IRAP picture 402 is to remove the previous reference picture in the picture buffer (DPB) being decoded, which the decoder will update), the IRAP picture 402 causes the coding of pictures that follow the IRAP picture 402 in decoding order 408 to be less efficient (i.e., require more bits to present) because those other pictures have fewer reference pictures for their inter-frame predictive coding.

[0088] Among the picture types considered as IRAP pictures 402, IDR pictures in HEVC have different signaling and derivation when compared to other picture types. Some of the differences are as follows:

[0089] For the signaling and derivation of the Picture Order Count (POC) value of an IDR picture, the most significant bit (MSB) portion of the POC is not derived from the previous key picture, but is simply set equal to 0.

[0090] Regarding the signaling information required for reference picture management, the slice header of an IDR picture does not include information that needs to be sent by signaling to support reference picture management. For other picture types (i.e., CRA pictures, last pictures, temporal partial layer access (TSA) pictures, etc.), the reference picture marking process (i.e., the process of determining the status of reference pictures in the picture buffer (DPB) being decoded, whether they are used for reference or not), requires information such as the reference picture set (RPS) described below or other forms of similar information (e.g., a reference picture list, etc.). On the other hand, for an IDR picture, the presence of an IDR simply indicates that the decoding process needs to mark all of the multiple reference pictures in the DPB as not being used for reference, so there is no need to send such information by signaling.

[0091] In the case of HEVC and VVC, the IRAP picture 402 and the leading picture 404 may each be contained within a single Network Abstraction Layer (NAL) unit. This set of NAL units may be referred to as an access unit. The IRAP picture 402 and the leading picture 404 are given different NAL unit types, allowing system-level applications to easily distinguish between these different NAL unit types. For example, a video splicer needs to understand the picture type being coded without needing to understand the details of the syntax elements in the bitstream being coded, particularly by distinguishing the IRAP picture 402 from non-IRAP pictures and by determining RASL and RADL pictures, without needing to distinguish the leading picture 404 from the tail picture 406. The tail picture 406 is the picture associated with the IRAP picture 402 and following it in presentation order 410. A picture may follow that particular IRAP picture 402 in decoding order 408 and may precede any other IRAP picture 402 in decoding order 408. For this reason, giving the IRAP picture 402 and leading picture 404 their own NAL unit type is useful for such applications.

[0092] In the case of HEVC, the NAL unit types for an IRAP picture include the following NAL unit types:

[0093] BLA with Leading Picture (BLA_W_LP): A NAL unit of a broken link access (BLA) picture that may be followed in decoding order by one or more leading pictures.

[0094] BLA with RADL (BLA_W_RADL): A NAL unit of a BLA picture that may be followed in decoding order by one or more RADL pictures, but no RADL pictures.

[0095] BLA without leading picture (BLA_N_LP): A NAL unit of a BLA picture that is not followed by a leading picture in decoding order.

[0096] IDR with RADL (IDR_W_RADL): A NAL unit of an IDR picture that may be followed in decoding order by one or more RADL pictures, but no RADL pictures.

[0097] IDR without leading picture (IDR_N_LP): A NAL unit that is an IDR picture that is not followed by a leading picture in decoding order.

[0098] CRA: A NAL unit of a clean random access (CRA) picture that may be followed by a leading picture (i.e., either a RASL picture or a RADL picture, or both).

[0099] RADL: NAL unit of a RADL picture.

[0100] RASL: NAL unit of a RASL picture.

[0101] In the case of VVC, the NAL unit types for the IRAP picture 402 and the leading picture 404 are the following NAL unit types:

[0102] IDR with RADL (IDR_W_RADL): A NAL unit of an IDR picture that may be followed in decoding order by one or more RADL pictures, but no RADL pictures.

[0103] IDR without leading picture (IDR_N_LP): A NAL unit of an IDR picture that does not follow a leading picture in decoding order.

[0104] CRA: A NAL unit of a clean random access (CRA) picture that may be followed by a leading picture (either a RASL picture or a RADL picture, or both).

[0105] RADL: NAL unit of a RADL picture.

[0106] RASL: NAL unit of a RASL picture.

[0107] 5 illustrates a video bitstream 550 configured to implement a gradual decoding refresh (GDR) technique 500. As used herein, the video bitstream 550 may also be referred to as a coded video bitstream, a bitstream, or variations thereof. As shown in FIG. 5, the bitstream 550 includes a sequence parameter set (SPS) 552, a picture parameter set (PPS) 554, a slice header 556, and image data 558.

[0108] The SPS 552 contains data that is common to all of the pictures in a sequence of pictures (SOP). In contrast, the PPS 554 contains data that is common to the entire picture. The slice header 556 contains information about the current slice, such as the slice type and which of multiple reference pictures is used. The SPS 552 and PPS 554 may generally be referred to as parameter sets. The SPS 552, PPS 554, and slice header 556 are types of network abstraction layer (NAL) units. An NAL unit is a syntactic structure that contains an indication of the type of data that follows (e.g., the video data being coded). NAL units are classified into video coding layer (VCL) and non-VCL NAL units. VCL NAL units contain data representing values ​​of samples in a video picture, and non-VCL NAL units contain parameter sets (important header data that may apply to a large number of VCL NAL units) and any associated additional information, such as supplemental enhancement information (timing information and other supplemental data that is not necessary to decode values ​​of samples in a video picture but that may increase the usefulness of the video signal being decoded). Those skilled in the art will understand that bitstream 550 may contain other parameters and information in actual applications.

[0109] The image data 558 in Figure 5 includes data associated with the image or video being encoded or decoded. The image data 558 may simply be referred to as the payload or data carried in the bitstream 550. In one embodiment, the image data 558 includes a CVS 508 (or CLVS), which includes a GDR picture 502, one or more tail pictures 504, and a recovery point picture 506. In one embodiment, the GDR picture 502 is referred to as a CVS start (CVSS) picture. The CVS 508 is the coded video sequence for every coded layer video sequence (CLVS) in the video bitstream 550. Notably, when the video bitstream 550 contains a single layer, the CVS and CLVS are the same. The CVS and CLVS differ only when the video bitstream 550 contains multiple layers. In one embodiment, the tail pictures 504 may be considered a form of GDR picture because they precede the recovery point picture 506 in the GDR period.

[0110] In one embodiment, the GDR picture 502, the tail picture 504, and the recovery point picture 506 may define a GDR period in the CVS 508. In one embodiment, the decoding order starts with the GDR picture 502, continues to the tail picture 504, and then Recovery Point Go to picture 506.

[0111] CVS 508 is a series of pictures (or a portion thereof) starting from GDR picture 502 and including all pictures (or a portion thereof) up to, but not including, the next GDR picture or the end of the bitstream. A GDR period is a series of pictures starting from GDR picture 502 and including all pictures up to, and including, recovery point picture 506. The decoding process of CVS 508 always starts at GDR picture 502.

[0112] 5, the GDR technique 500 or principle operates across a series of pictures starting with a GDR picture 502 and ending with a recovery point picture 506. The GDR picture 502 includes an updated / clean region 510 that contains all blocks coded using intra-frame prediction (i.e., intra-predicted blocks) and an unupdated / messy region 512 that contains all blocks coded using inter-frame prediction (i.e., inter-predicted blocks).

[0113] The last picture 504 immediately adjacent to the GDR picture 502 includes an updated / clean region 510 having a first portion 510A coded using intra-frame prediction and a second portion 510B coded using inter-frame prediction. The second portion 510B is coded, for example, by referencing the updated / clean region 510 of a preceding picture in the GDR period of the CVS 508. As shown, the updated / clean region 510 of the last picture 504 expands as the coding process moves or progresses in a consistent direction (e.g., from left to right), causing the unupdated / messy region 512 to correspondingly shrink. Ultimately, a recovery point picture 506 is obtained from the coding process, which includes only the updated / clean region 510. In particular, as described further below, the second portion 510B of the updated / clean region 510, coded as an inter-frame predicted block, may reference only the updated / clean region 510 in the reference picture.

[0114] 5, the GDR picture 502, the tail picture 504, and the recovery point picture 506 in the CVS 508 are each contained in their own VCL NAL unit 530. The set of VCL NAL units 530 in the CVS 508 may be referred to as an access unit.

[0115] In one embodiment, the VCL NAL unit 530 containing the GDR picture 502 in the CVS 508 has a GDR NAL unit type (GDR_NUT). That is, in one embodiment, the VCL NAL unit 530 containing the GDR picture 502 in the CVS 508 has its own unique NAL unit type relative to the tail picture 504 and the recovery point picture 506. In one embodiment, the GDR_NUT allows the bitstream 550 to start with the GDR picture 502 instead of requiring the bitstream 550 to start with an IRAP picture. Designating the VCL NAL unit 530 of the GDR picture 502 as GDR_NUT allows, for example, to indicate to a decoder that an early VCL NAL unit 530 in the CVS 508 contains the GDR picture 502. In one embodiment, the GDR picture 502 is the early picture in the CVS 508. In one embodiment, the GDR picture 502 is an early picture in the GDR period.

[0116] 6 is a schematic diagram illustrating an undesirable motion search 600 when using encoder constraints to support GDR. As shown, the motion search 600 shows a current picture 602 and a reference picture 604. The current picture 602 and the reference picture 604 each include an updated region 606 coded using intra-frame prediction, an updated region 608 coded using inter-frame prediction, and an unupdated region 608. The updated region 604, the updated region 606, and the unupdated region 608 are similar to the first portion 510A of the updated / clean region 510, the second portion 510B of the updated / clean region 510, and the unupdated / messy region 512 of FIG. 5.

[0117] During the motion search process, the encoder suppresses or prevents selecting any motion vector 610 that results in some of the samples of reference block 612 being located outside the region being updated 606. This occurs even when reference block 612 provides the best rate-distortion cost criterion when predicting current block 614 in current picture 602. Thus, Figure 6 illustrates the reason for non-optimality in motion search 600 when using encoder constraints to support GDR.

[0118] 7 illustrates a video bitstream 750 configured to implement a clean random access (CRA) technique 700. As used herein, the video bitstream 750 may also be referred to as a coded video bitstream, a bitstream, or variations thereof. As shown in FIG. 7, the bitstream 750 includes a sequence parameter set (SPS) 752, a picture parameter set (PPS) 754, a slice header 756, and image data 758. The bitstream 750, SPS 752, PPS 754, and slice header 756 in FIG. 7 are similar to the bitstream 550, SPS 552, PPS 554, and slice header 556 in FIG. 5. Therefore, for brevity, the description of these elements will not be repeated.

[0119] 7 includes data associated with an image or video being coded or decoded. Image data 758 may simply be referred to as the payload or data carried in bitstream 750. In one embodiment, image data 758 includes the CRA picture 702, one or more tail pictures 704, and Sequence Picture The CRA picture 702 includes a CVS 708 (or CLVS) that includes the end of the CRA picture 706. In one embodiment, the CRA picture 702 is referred to as a CVSS picture. The decoding process of the CVS 708 always starts with the CRA picture 702.

[0120] 7, the CRA picture 702, the tail picture 704, and the end of sequence picture 706 in the CVS 708 are each contained in their own VCL NAL unit 730. The set of VCL NAL units 730 in the CVS 708 may be referred to as an access unit.

[0121] In the latest draft of the VVC specification, the output of a picture previous to an IRAP picture is defined as follows: A previous picture (e.g., a previously decoded picture) for an IRAP picture refers to a picture that (1) was decoded earlier than the IRAP picture, (2) is indicated for output, (3) is present in the decoded picture buffer (DPB) at the start of decoding of the IRAP picture, and (4) has not been output at the start of decoding of the IRAP picture. As used herein, a previous picture may also be referred to as a previously decoded picture.

[0122] The slice header syntax includes the syntax element no_output_of_prior_pics_flag for IDR and CRA pictures, the semantics of which are as follows:

[0123] The no_output_of_prior_pics_flag affects the output of previously decoded pictures in the decoded picture buffer after decoding of an IDR picture that is not the first picture in the bitstream, as specified in Appendix C of VVC Draft 5.

[0124] Section C.3.2 (Removal of pictures from the DPB before decoding of the current picture) of VVC Draft 5 includes the following statement:

[0125] - When the current picture is an IRAP picture with NoIncorrectPicOutputFlag equal to 1 that is not picture 0, apply the following ordered steps:

[0126] 1. The variable NoOutputOfPriorPicsFlag is derived for the decoder under test as follows:

[0127] - If the current picture is a CRA picture, NoOutputOfPriorPicsFlag is set equal to 1 (regardless of the value of no_output_of_prior_pics_flag).

[0128] - Otherwise, the values ​​of pic_width_in_luma_samples, pic_height_in_luma_samples, chroma_format_idc, separate_colour_plane_flag, bit_depth_luma_minus8, bit_depth_chroma_minus8, or sps_max_dec_pic_buffering_minus1[ HighestTid ] derived from the active SPS are equal to the values ​​of pic_width_in_luma_samples, pic_height_in_luma_samples, chroma_format_idc, separate_colour_plane_flag, bit_depth_luma_minus8, bit_depth_chroma_minus8, or sps_max_dec_pic_buffering_minus1[ HighestTid ] derived from the active SPS for the preceding picture, respectively. ], then NoOutputOfPriorPicsFlag may (but is not required to) be set to 1 by the decoder under test regardless of the value of no_output_of_prior_pics_flag.

[0129] NOTE - Under these conditions, it is preferable to set NoOutputOfPriorPicsFlag to equal no_output_of_prior_pics_flag, but in this case the decoder under test is permitted to set NoOutputOfPriorPicsFlag to 1.

[0130] Otherwise, NoOutputOfPriorPicsFlag is set equal to no_output_of_prior_pics_flag.

[0131] 2. The value of NoOutputOfPriorPicsFlag derived for the decoder under test is applied to a hypothesized reference decoder (HRD) so that when the value of NoOutputOfPriorPicsFlag is equal to 1, all of the picture storage buffers in the DPB are emptied without using the output of the pictures they contain, and DPB fullness is set equal to 0.

[0132] Section C.5.2.2 (Output and deletion of pictures from DPB) of VVC Draft 5 includes the following statement:

[0133] If the current picture is an IRAP picture with NoIncorrectPicOutputFlag equal to 1 that is not picture 0, apply the following ordered steps:

[0134] 1. The variable NoOutputOfPriorPicsFlag is derived for the decoder under test as follows:

[0135] If the current picture is a CRA picture, NoOutputOfPriorPicsFlag is set equal to 1 (regardless of the value of no_output_of_prior_pics_flag).

[0136] - Otherwise, the values ​​of pic_width_in_luma_samples, pic_height_in_luma_samples, chroma_format_idc, separate_colour_plane_flag, bit_depth_luma_minus8, bit_depth_chroma_minus8, or sps_max_dec_pic_buffering_minus1[ HighestTid ] derived from the active SPS are equal to the values ​​of pic_width_in_luma_samples, pic_height_in_luma_samples, chroma_format_idc, separate_colour_plane_flag, bit_depth_luma_minus8, bit_depth_chroma_minus8, or sps_max_dec_pic_buffering_minus1[ HighestTid ] derived from the active SPS for the preceding picture, respectively. ], NoOutputOfPriorPicsFlag may (but is not required to) be set to 1 by the decoder under test regardless of the value of no_output_of_prior_pics_flag.

[0137] NOTE - Under these conditions, it is desirable to set NoOutputOfPriorPicsFlag to equal no_output_of_prior_pics_flag, but in this case the decoder under test is permitted to set NoOutputOfPriorPicsFlag to 1.

[0138] Otherwise, NoOutputOfPriorPicsFlag is set equal to no_output_of_prior_pics_flag.

[0139] 2. The value of NoOutputOfPriorPicsFlag derived for the decoder under test is applied to the HRD as follows:

[0140] - If NoOutputOfPriorPicsFlag is equal to 1, all of the picture storage buffers in the DPB are emptied without using the output of the pictures they contain, and DPB fullness is set equal to 0.

[0141] - Otherwise (when NoOutputOfPriorPicsFlag is equal to 0), all picture storage buffers containing pictures marked as "not needed for output" and "not used for reference" are emptied (without using output), all non-empty picture storage buffers in the DPB are emptied by repeatedly invoking the "bumping" process specified in clause C.5.2.4, and DPB fullness is set equal to 0.

[0142] Several problems with existing designs have been described.

[0143] In the latest draft of the VVC specification, for a CRA picture with NoIncorrectPicOutputFlag equal to 1 (i.e., a CRA picture that starts a new CVS), the value of NoOutputOfPriorPicsFlag is set to 1 regardless of the value of no_output_of_prior_pics_flag, and therefore the value of no_output_of_prior_pics_flag is not used. This means that pictures before each CRA picture that starts a CVS are not output. On the other hand, as in the case of IDR pictures, outputting / displaying previous pictures can provide more continuous playback and therefore a better user experience, as long as the DPB does not overflow when decoding the picture that starts a new CVS and subsequent pictures in decoding order.

[0144] To solve the problems described above, this disclosure provides the following inventive aspects: The value of no_output_of_prior_pics_flag is used to specify the output of the picture before each CRA picture that starts a new CVS and is not the first picture of the bitstream, allowing for more continuous playback and therefore a better user experience.

[0145] This disclosure also applies to other types of pictures that start a new CVS, such as gradual random access (GRA) pictures currently specified in the latest VVC specification draft. In one embodiment, a GRA picture may be referred to as or be synonymous with a GDR picture.

[0146] For example, when decoding a video bitstream, a flag corresponding to a clean random access (CRA) picture is signaled in the bitstream. The flag specifies whether a decoded picture that is in the buffer of pictures being decoded and that has been decoded earlier than a CRA picture is to be output when the CRA picture starts a new coded video sequence. That is, when the value of the flag indicates that the previous picture is to be output (e.g., when the value is equal to 0), the previous picture is output. In one embodiment, the flag is specified as no_output_of_prior_pics_flag.

[0147] As another example, when decoding a video bitstream, a flag corresponding to a gradual random access (GRA) picture is signaled in the bitstream. The flag specifies whether a decoded picture that is in the decoded picture buffer and that is decoded earlier than the GRA picture is to be output when the GRA picture starts a new coded video sequence. That is, when the value of the flag indicates that the previous picture is to be output (e.g., when the value is equal to 0), the previous picture is output. In one embodiment, the flag is specified as no_output_of_prior_pics_flag.

[0148] Disclosed herein are techniques for outputting a previous picture (e.g., a previously decoded picture) in a decoding picture buffer (DPB) when a random access point picture other than an instantaneous decoder refresh (IDR) picture (e.g., a clean random access (CRA) picture, a gradual random access (GRA) picture, or a gradual decoding refresh (GDR) picture, a CVSS picture, etc.) is encountered in decoding order. Emptying previously decoded pictures from the DPB when a random access point picture is reached prevents the DPB from overflowing and promotes more continuous playback. Thus, coders / decoders (also known as "codecs") in video coding are improved compared to current codecs. As a practical matter, the improved video coding process provides a better user experience when video is transmitted, received, and / or viewed.

[0149] 8 illustrates one embodiment of a method 800 for decoding a coded video bitstream implemented by a video decoder (e.g., video decoder 30). Method 800 may be performed after receiving the bitstream being decoded directly or indirectly from a video encoder (e.g., video encoder 20). Method 800 improves the decoding process by emptying the DPB when a random access point picture is encountered and before decoding the current picture. Method 800 prevents the DPB from overflowing and promotes more continuous playback. Therefore, in practice, codec performance is improved, leading to a better user experience.

[0150] In block 802, a video decoder receives a coded video bitstream (e.g., bitstream 750). The coded video bitstream includes a first flag having a first value and a clean random access (CRA) picture. In one embodiment, the CRA picture is not the first picture of the coded video bitstream. In one embodiment, the first flag is specified as no_output_of_prior_pics_flag.

[0151] At block 804, the video decoder sets a second value of a second flag to be equal to the first value of the first flag. In one embodiment, the second flag is specified as NoOutputOfPriorPicsFlag. In one embodiment, the second flag is internal to the decoder.

[0152] In block 806, the video decoder empties any previously decoded pictures from the decoded picture buffer (DPB) based on the second flag having a second value. In one embodiment, after decoding the CRA picture, the previously decoded pictures are emptied from the DPB. That is, the video decoder removes the previously decoded pictures from the picture storage buffer in the DPB. In one embodiment, when a previously decoded picture is removed from the DPB, the previously decoded picture is not output or displayed. In one embodiment, when the first flag is set to the first value, the DPB fullness parameter is set to 0. The DPB fullness parameter indicates how many pictures are stored in the DPB. Setting the DPB fullness parameter to 0 indicates that the DPB is empty.

[0153] In block 808, the video decoder decodes the current picture after the DPB is empty. In one embodiment, the current picture is a picture from the same CVS as the CRA picture, and is obtained or encountered after the CRA in decoding order. In one embodiment, an image generated based on the current picture is displayed for a user of the electronic device (e.g., a smartphone, tablet, laptop, personal computer, etc.).

[0154] 9 illustrates one embodiment of a method 900 for encoding a video bitstream implemented by a video encoder (e.g., video encoder 20). The method 900 may be performed when a picture (e.g., from a video) is encoded into a video bitstream and then transmitted to a video decoder (e.g., video decoder 30). The method 900 improves the encoding process by instructing the video decoder to empty the DPB when a random access point picture is encountered and before decoding the current picture. The method 900 prevents the DPB from overflowing and promotes more continuous playback. Therefore, in practice, codec performance is improved, leading to a better user experience.

[0155] In block 902, a video encoder determines a random access point for a video sequence. In block 904, the video encoder encodes a clean random access (CRA) picture into the video sequence at the random access point. In one embodiment, the CRA picture is not the first picture in the video bitstream.

[0156] In block 906, the video encoder sets a flag to a first value to instruct the video decoder to empty any previously decoded pictures from the decoded picture buffer (DPB). In one embodiment, the video encoder instructs the video decoder to empty any previously decoded pictures from the DPB after decoding the CRA picture. In one embodiment, the flag is specified as no_output_of_prior_pics_flag. In one embodiment, the video encoder instructs the video decoder to set a DPB fullness parameter to 0 when the flag is set to the first value. In one embodiment, the first value of the flag is 1.

[0157] At block 908, the video encoder generates a video bitstream including the video sequence with the CRA pictures at the random access points and the flag. At block 910, the video encoder stores the video bitstream for transmission to a video decoder.

[0158] The following syntax and semantics may be used to implement the embodiments disclosed herein. The following description is relative to the base text, which is the latest draft specification of VVC. In other words, only deltas are listed, while text in the base text that is not mentioned below applies as is. Text that has been added compared to the base text is shown in bold, and text that has been deleted is shown in italics.

[0159] [Table 1]

[0160]

number

[0161] 10 is a schematic diagram of a video coding device 1000 (e.g., video encoder 20 or video encoder 30) according to an embodiment of the present disclosure. The video coding device 1000 is suitable for implementing several disclosed embodiments as described herein. The video coding device 1000 includes an ingress port 1010 and a receiver unit (Rx) 1020 for receiving data, a processor, logic unit, or central processing unit (CPU) 1030 for processing data, a transmitter unit (Tx) 1040 and an egress port 1050 for transmitting data, and a memory 1060 for storing data. The video coding device 1000 may also include optical-electrical (OE) and electro-optical (EO) components coupled to the ingress port 1010, the receiver unit 1020, the transmitter unit 1040, and the egress port 1050 for the egress or ingress of optical or electrical signals.

[0162] The processor 1030 is implemented by hardware and software. The processor 1030 may be implemented as one or more CPU chips, cores (e.g., multi-core processors), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and digital signal processors (DSPs). The processor 1030 communicates with the ingress port 1010, the receiver unit 1020, the transmitter unit 1040, the egress port 1050, and the memory 1060. The processor 1030 includes a coding module 1070. The coding module 1070 implements multiple disclosed embodiments described above. For example, the coding module 1070 implements, processes, prepares, or provides various codec functions. Thus, the inclusion of the coding module 1070 substantially improves the functionality of the video coding device 1000 and provides transformation of the video coding device 1000 into different states. Alternatively, the coding module 1070 is implemented as instructions stored in the memory 1060 and executed by the processor 1030 .

[0163] Video coding device 1000 may also include input and / or output (I / O) devices 1080 for communicating data to and from a user. The I / O devices 1080 may include output devices such as a display for displaying video data, speakers for outputting audio data, etc. The I / O devices 1080 may also include input devices such as a keyboard, mouse, trackball, etc., and / or corresponding interfaces for interacting with such output devices.

[0164] Memory 1060 may include one or more disks, tape drives, and solid state drives, and may be used as an overflow data storage device to store programs when such programs are selected for execution, and to store instructions and data retrieved during the execution of programs. Memory 1060 may be, for example, volatile and / or non-volatile, and may be read-only memory (ROM), random access memory (RAM), ternary content addressable memory (TCAM), and / or static random access memory (SRAM).

[0165] 11 is a schematic diagram of one embodiment of a means for coding 1100. In one embodiment, the means for coding 1100 is implemented by a video coding device 1102 (e.g., video encoder 20 or video decoder 30). The video coding device 1102 includes a means for receiving 1101. The means for receiving 1101 is configured to receive pictures to encode or a bitstream to decode. The video coding device 1102 includes a means for transmitting 1107 coupled to the means for receiving 1101. The means for transmitting 1107 is configured to transmit the bitstream to a decoder or transmit the decoded images to a display means (e.g., one of a plurality of I / O devices 1080).

[0166] The video coding device 1102 includes a storage means 1103. The storage means 1103 is coupled to at least one of the receiving means 1101 or the transmitting means 1107. The storage means 1103 is configured to store instructions. The video coding device 1102 also includes a processing means 1105. The processing means 1105 is coupled to the storage means 1103. The processing means 1105 is configured to execute the instructions stored in the storage means 1103 to perform the methods disclosed herein.

[0167] It should also be understood that the steps of the exemplary methods described herein do not necessarily have to be performed in the order described, and that the order of steps of such methods is merely exemplary. Similarly, additional steps may be included in such methods, and certain steps may be omitted or combined in methods consistent with various embodiments of this disclosure.

[0168] While this disclosure provides several embodiments, it should be understood that the disclosed systems and methods may be embodied in many other specific forms without departing from the spirit or scope of this disclosure. These examples are intended to be illustrative and not limiting, and the intention is not to be limited to the details provided herein. For example, various elements or components may be combined or integrated into other systems, or certain features may be omitted or not implemented.

[0169] Additionally, techniques, systems, subsystems, and methods described and illustrated separately or individually in various embodiments may be combined or integrated with other systems, modules, techniques, or methods without departing from the scope of this disclosure. Other items that are coupled or directly coupled or in communication with each other may also be indirectly coupled or in communication electrically, mechanically, or otherwise, by some interface, device, or intermediate component. Other examples of changes, substitutions, and alterations will be ascertainable by those skilled in the art and could be made without departing from the spirit and scope of the disclosure herein.

Claims

1. 1. A method of encoding performed by a video encoder, comprising: the video encoder determining random access points of a video sequence in a video bitstream; the video encoder encoding a clean random access (CRA) picture into the video sequence at the random access point, the CRA picture not being the first picture of a coded video bitstream, and the CRA picture starting a new coded video sequence (CVS); and the video encoder encoding a first flag into the bitstream, the flag being set to specify a value of a second flag at a decoder side, the first flag being specified as no_output_of_prior_pics_flag and the second flag being specified as NoOutputOfPriorPicsFlag, the second flag being set to indicate whether to empty a previously decoded picture corresponding to the CRA picture from a decoded picture buffer (DPB) or to output a previously decoded picture corresponding to the CRA picture at the decoder side; A method comprising:

2. 2. The method of claim 1, further comprising the step of instructing a video decoder to set a DPB fullness parameter to zero if the flag is set to a particular value.

3. 1. A coding device comprising: a memory containing instructions; a processor coupled to the memory; wherein the processor executes the instructions to cause the encoding device to: determining random access points of a video sequence in the video bitstream; encoding a clean random access (CRA) picture into the video sequence at the random access point, the CRA picture not being the first picture of a coded video bitstream, and the CRA picture starting a new coded video sequence (CVS); encoding a first flag into the bitstream, the flag being set to specify a value of a second flag at a decoder side, the first flag being specified as no_output_of_prior_pics_flag and the second flag being specified as NoOutputOfPriorPicsFlag, the second flag being set to indicate whether to empty a previously decoded picture corresponding to the CRA picture from a decoded picture buffer (DPB) or to output a previously decoded picture corresponding to the CRA picture at the decoder side; a coding device configured to cause

4. 4. The encoding device of claim 3, wherein the memory stores the video bitstream before a transmitter transmits the video stream to a video decoder.

5. 1. A method of decoding implemented by a video decoder, comprising: receiving a coded video bitstream; performing entropy decoding on the coded video bitstream to obtain a coded clean random access (CRA) picture and a first flag, where the coded CRA picture is not a first picture of the coded video bitstream and the coded CRA picture starts a new coded video sequence (CVS); setting a value of a second flag equal to a value of the first flag, the first flag being designated as no_output_of_prior_pics_flag and the second flag being designated as NoOutputOfPriorPicsFlag; emptying a previously decoded picture corresponding to the coded CRA picture from a decoded picture buffer (DPB) based on a value of the second flag, or outputting a previously decoded picture corresponding to the coded CRA picture based on a value of the second flag; A method comprising:

6. 6. The method of claim 5, further comprising the step of setting a decoded picture buffer (DPB) fullness parameter to zero if the value of the second flag indicates that the previously decoded picture is to be emptied from a DPB.

7. 7. The method of claim 5 or 6, wherein the DPB is emptied after the coded CRA picture is decoded.

8. 1. A decoding device comprising: a receiver configured to receive the coded video bitstream; a memory coupled to the receiver, the memory storing instructions; and a processor coupled to the memory; wherein the processor executes the instructions to cause the decoding device to: receiving a coded video bitstream; performing entropy decoding on the coded video bitstream to obtain a coded clean random access (CRA) picture and a first flag, where the coded CRA picture is not a first picture of the coded video bitstream and the coded CRA picture starts a new coded video sequence (CVS); setting a value of a second flag equal to a value of the first flag, the first flag being designated as no_output_of_prior_pics_flag and the second flag being designated as NoOutputOfPriorPicsFlag; emptying a previously decoded picture corresponding to the coded CRA picture from a decoded picture buffer (DPB) based on a value of the second flag, or outputting a previously decoded picture corresponding to the coded CRA picture based on a value of the second flag; A device that is configured to:

9. 9. The device of claim 8, wherein the processor is further configured to set a decoded picture buffer (DPB) fullness parameter to zero if the value of the second flag indicates that the previously decoded picture is to be emptied from a DPB.

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