Semiconductor Devices

Abstract

To prevent a transistor from malfunctioning during a non-selective period by suppressing fluctuations in the threshold voltage of the transistor, in a shift register.SOLUTION: In a pulse output circuit provided on a shift register, electric potential is supplied periodically to a gate electrode of a transistor which is in a floating state such that the gate electrode is turned on during a non-selective period where a pulse is not output. In addition, the electric potential is supplied to the gate electrode of the transistor by periodically turning on or off other transistors.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a pulse output circuit, a shift register, and a display device having the shift register. , semiconductor devices and electronic devices, in particular, single-conductivity thin film transistors (TFTs) Pulse output circuit, shift register, display device, semiconductor device and electronic device do. [Background technology]

[0002] In recent years, thin film transistors have been developed that use semiconductor thin films on insulators, especially glass and plastic substrates. A display device in which a circuit is formed using thin film transistors (hereinafter also referred to as "TFT"), especially an active The development of active matrix display devices is progressing. A matrix display device has hundreds of thousands to millions of pixels arranged in a matrix, The image is displayed by controlling the charge of each pixel using the TFT placed in each pixel. I am doing it.

[0003] In addition to the pixel TFTs that make up the pixels, a more recent technology is the use of TFs in the area surrounding the pixel. The method of simultaneously forming a driving circuit using T has been developed, and the device is becoming lighter, thinner, shorter, and smaller. As a result, the field of application of mobile information technology has expanded significantly in recent years. It has become an indispensable device for the display section of information terminals.

[0004] Generally, the driving circuit of a display device is made up of N-type TFTs and P-type TFTs. The CMOS circuit is a combination of the two. The feature of the CMOS circuit is that the logic changes. (H (High) level to L (Low) level, or L level Current flows only for a moment (from low to high level), and ideally, current flows only when a certain logic is maintained. (Actually, there is a small amount of leakage current), so the power consumption of the entire circuit is extremely low. In addition, the TFTs of each polarity operate in a complementary manner, enabling high-speed operation. Possible points are mentioned.

[0005] However, when considering the manufacturing process, CMOS circuits require complicated ion doping processes. Therefore, the large number of processes directly affects the manufacturing cost. The circuit, which was previously made up of a single-polarity TFT, either N-type or P-type, is now made up of a single-polarity TFT. and has achieved high-speed operation comparable to that of CMOS circuits (for example, patent (See Reference 1).

[0006] The circuit described in Patent Document 1 is electrically connected to the output terminal as shown in FIGS. 7(A) to 7(C). By temporarily setting the gate electrode of the TFT2050 connected to the By using the capacitive coupling between the gate and source of the FT2050, the potential of the gate electrode is As a result, the potential due to the threshold voltage of the TFT2050 can be increased. This allows for an output with no amplitude attenuation without causing a voltage drop. 020, 2030, 2040, and 2060 are TFTs, 2070 is a capacitive element, and 2100 is The first amplitude compensation circuit, 2200, is the second amplitude compensation circuit.

[0007] Such an operation in the TFT2050 is called a bootstrap operation. Operation provides an output pulse without voltage drop due to the TFT threshold. It is possible.

[0008] In addition, the circuits shown in FIGS. 7(A) to 7(C) operate in a period when there is no pulse input or output. The gate electrodes of T2050 and T2060 are both in a floating state, and noise is generated at node α. To solve this problem, T When FT1020 and FT1060 are turned on and left floating, the noise generated at node α is A circuit for reducing noise (see FIGS. 8(A) to 8(C)) has been proposed (for example, Patent Document 2). 1010, 1030, 1040, and 1050 are TFTs, 1070 is a capacitive element, 1100 is a first amplitude compensation circuit, and 1200 is a second amplitude compensation circuit. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-335153 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-226429 Summary of the Invention [Problem to be solved by the invention]

[0010] In Figure 8, if you look at SROut1, after the pulse is output, CK1 will soon become H level. The potential of SROut1 also starts to drop. When K2 becomes H level, the same operation as described above is performed in the second stage, and SR A pulse is output to Out2. This pulse is generated by the As a result, the voltages of the gate electrodes of the TFTs 1020 and 1060 are As a result, the potential of the gate electrode of the TFT 1050 and the SRO The potential of ut1 drops. After that, when the output of SROut2 changes from H level to L level, At this moment, the gate electrodes of the TFTs 1020 and 1060 are turned off. , it will be in a floating state. After that, this state will continue until the next SP is input in the first stage. This will happen.

[0011] In this way, in the circuits of Figures 8(A) and 8(B), node β has no pulse input / output. For example, the circuits shown in Figures 8(A) and 8(B) are used as scan drivers. When using TF as a clock, the potential of node β must be maintained for approximately one frame. The channel widths of T1040 and TFT1060 are relatively large, so the off-current is also high. At this time, the potential of node β drops due to the off current of TFT1040 and TFT1060, The TFT1060 may be turned off, resulting in capacitive coupling to the clock signal. There is a greater possibility of malfunction.

[0012] When a pulse is output from the TFT 1050, the node β is in a floating state. Therefore, when the potential of node γ rises from L level to H level, the The potential of β may increase, which may result in the TFT1020 turning on and causing malfunction. This potential fluctuation is much smaller than the amplitude of a normal pulse, so the potential fluctuation If the voltage fluctuation is smaller than the threshold voltage of the TFT1020, it is not a problem. If it exceeds the threshold of T1020, the potential of node α will drop, causing malfunction. In particular, when amorphous silicon is used for the TFT, the gate insulating film In many cases, nitride films are used for the pulse output circuit, and the threshold voltage may fluctuate. is more likely to malfunction.

[0013] In addition, when amorphous silicon is used as the TFT, the TFT using polysilicon Compared to FT, it has inferior electrical characteristics, making it difficult to obtain sufficient driving capacity, and voltage conditions Therefore, the threshold voltage shifts due to the amorphous silicon TFT. However, the circuit technology for forming a driving circuit for driving pixels has become an issue.

[0014] The invention disclosed in this specification solves one or more of these problems, thereby The pulse output circuit, shift register and The present invention aims to provide a display device for: [Means for solving the problem]

[0015] In the pulse output circuit of the present invention, the gate electrode is turned on during the non-selection period when no pulse is output. By periodically supplying a potential to the gate electrode of the transistor in a floating state, The supply of a potential to the gate electrode of a transistor is different from that of other transistors. This is done by periodically turning the starter on and off.

[0016] Furthermore, the shift register of the present invention is configured to synchronize the pulse output from the m-th pulse output circuit with the pulse output from the m-th pulse output circuit. m+1) pulse output circuit is driven so that the pulses output by the pulse output circuit overlap by half (1 / 2 period). The shift register and pulse output circuit of the present invention are characterized by the following specific features. The configuration will be explained.

[0017] The shift register of the present invention includes an (m-2)th pulse output circuit, an (m-1)th pulse output circuit, the mth pulse output circuit, the (m+1)th pulse output circuit, and the (m+2)th pulse output circuit a plurality of pulse output circuits including at least one pulse output circuit (m≧3) and a clock signal output circuit (m≧3) The pulse output circuit has first to fourth signal lines, and the pulse output circuit has first to sixth input terminals. The m-th pulse output circuit has an input terminal and an output terminal, and the first to third input terminals The input terminal is electrically connected to three different signal lines among the first to fourth signal lines. The fourth input terminal is electrically connected to the output terminal of the (m-2)th pulse output circuit. The fifth input terminal is electrically connected to the output terminal of the (m-1)th pulse output circuit, The input terminal of the (m+2)th pulse output circuit is electrically connected to the output terminal of the (m+2)th pulse output circuit. The sixth input terminal of the (m-2)th pulse output circuit, the sixth input terminal of the (m+1)th pulse output circuit and the fourth input terminal of the (m+2)th pulse output circuit. It is characterized by being

[0018] The pulse output circuit of the present invention includes first to ninth transistors, The transistor has a first electrode electrically connected to the first power supply line and a second electrode electrically connected to the third power supply line. The gate electrode of the transistor is electrically connected to the fourth input terminal. a first electrode of the second transistor electrically connected to the second power supply line; The electrode of the third transistor is electrically connected to the gate electrode of the fourth transistor. a third transistor having a first electrode electrically connected to the gate electrode of the first transistor; a first electrode electrically connected to the input terminal, a second electrode electrically connected to the output terminal, and a fourth transformer The transistor has a first electrode electrically connected to the third power supply line and a second electrode electrically connected to the output terminal. a fifth transistor having a first electrode electrically connected to a fourth power supply line; The second electrode is connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor. a sixth transistor having a gate electrode electrically connected to the fourth input terminal and a gate electrode electrically connected to the fourth input terminal; The first electrode is electrically connected to the fourth power supply line, and the second electrode is connected to the gate of the second transistor. the gate electrode of the fifth transistor and the gate electrode of the fourth transistor are electrically connected to the The seventh transistor is electrically connected to the input terminal, and a first electrode of the seventh transistor is electrically connected to the fifth power supply line. the second electrode is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor. the gate electrode is electrically connected to the sixth input terminal, and the eighth The transistor has a first electrode electrically connected to the fifth power supply line and a second electrode electrically connected to the ninth power supply line. The second electrode of the transistor is electrically connected to the second input terminal. The ninth transistor has a first electrode connected to the gate electrode of the second transistor and The gate electrode of the fourth transistor is electrically connected to the third input terminal. The system is characterized by being dynamically connected.

[0019] The display device of the present invention has pixels and a shift register for driving the pixels. The (m-2)th pulse output circuit, the (m-1)th pulse output circuit, the mth pulse output circuit, the (m+1)th pulse output circuit and the (m+2)th pulse output circuit (m≧3) a plurality of pulse output circuits including at least one clock signal line; and a first signal line through a fourth signal line for outputting a clock signal. The pulse output circuit has first to sixth input terminals and an output terminal. In the m-th pulse output circuit, the first input terminal to the third input terminal receive a first signal The fourth input terminal is electrically connected to one of the (m-2)th to (m-3)th signal lines. The fifth input terminal is electrically connected to the output terminal of the pulse output circuit, and the fifth input terminal is electrically connected to the (m-1)th pulse The sixth input terminal is electrically connected to the output terminal of the pulse output circuit, and the sixth input terminal is electrically connected to the (m+2)th pulse output terminal of the pulse output circuit. and the output terminal of the (m-2)th pulse output circuit is electrically connected to the output terminal of the (m-3)th pulse output circuit. 6 input terminal of the (m+1)th pulse output circuit, the fifth input terminal of the (m+2)th pulse output circuit, The fourth input terminal of the output circuit is electrically connected to the fourth input terminal of the output circuit. [Effects of the Invention]

[0020] The present invention is directed to a transistor that is in a floating state during a non-selection period when no pulses are input or output. By periodically supplying a potential to the gate electrode of the transistor, malfunction of the pulse output circuit can be prevented. can be suppressed.

[0021] In addition, the pulse output from the mth pulse output circuit and the pulse output from the (m+1)th pulse output circuit are By using a driving method in which the pulses output from the It is possible to provide a pulse output circuit that can apply a large load and operate at a high frequency. Cut. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 1 is a diagram showing an example of a shift register and a pulse output circuit of the present invention. [Figure 2] FIG. 4 is a diagram showing an example of the operation of the pulse output circuit of the present invention. [Figure 3] FIG. 4 is a diagram showing an example of the operation of the pulse output circuit of the present invention. [Figure 4] FIG. 4 is a diagram showing an example of the operation of the pulse output circuit of the present invention. [Figure 5] 10A and 10B are diagrams showing a comparison of the operation of the pulse output circuit of the present invention and the operation of a conventional pulse output circuit; [Figure 6] FIG. 1 is a diagram showing an example of a shift register and a pulse output circuit of the present invention. [Figure 7] FIG. 1 is a diagram showing an example of a conventional shift register and pulse output circuit and their operation. [Figure 8] FIG. 1 is a diagram showing an example of a conventional shift register and pulse output circuit and their operation. [Figure 9] FIG. 10 is a diagram showing an example of a display device provided with a shift register of the present invention. [Figure 10] FIG. 10 is a diagram showing an example of a display device provided with a shift register of the present invention. [Figure 11] FIG. 10 is a diagram showing an example of a display device provided with a shift register of the present invention. [Figure 12] FIG. 10 is a diagram showing an example of a display device provided with a shift register of the present invention. [Figure 13] FIG. 10 is a diagram showing an example of a display device provided with a shift register of the present invention. [Figure 14] 1A and 1B are diagrams showing examples of electronic devices provided with a shift register of the present invention. [Figure 15] 1A and 1B are diagrams showing examples of display elements of a display device provided with a shift register of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, embodiments of the present invention will be described with reference to the drawings. and the present invention may be practiced in various different ways without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications can be made to the modes and details of the present invention. However, the present invention should not be construed as being limited to the description of the present embodiment. In the structure of the invention, reference numerals indicating the same objects are common among different drawings.

[0024] (Embodiment 1) In this embodiment, a pulse output circuit of the present invention, a shift register including the pulse output circuit, An example of the controller will be described with reference to the drawings.

[0025] The shift register shown in this embodiment includes a first pulse output circuit 10 _1 ~nth pulse Output circuit 10 _n (n≧3), and the first signal line 11 to the fourth signal line 12 which output clock signals. The first signal line 11 has a first clock signal (CK 1), the second signal line 12 outputs the second clock signal (CK2), and the third signal The line 13 outputs the third clock signal (CK3), and the fourth signal line 14 outputs the fourth clock signal (CK4). Output the number (CK4).

[0026] The clock signal (CK) repeats H (High) and L (Low) signals at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal (CK 4) are delayed by 1 / 2 cycle in order. In this embodiment, the first clock signal (CK 1) The fourth clock signal (CK4) is used to control the driving of the pulse output circuit. .

[0027] First pulse output circuit 10 _1 ~ nth pulse output circuit 10 _n Each of the first input Terminal 21, second input terminal 22, third input terminal 23, fourth input terminal 24, fifth input It has a terminal 25, a sixth input terminal 26, and an output terminal 27 (see FIG. 1(B)).

[0028] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first signal line 1. It is electrically connected to one of the first to fourth signal lines 14. For example, in FIG. 1 pulse output circuit 10 _1 The first input terminal 21 is electrically connected to the first signal line 11. The second input terminal 22 is electrically connected to the second signal line 12, and the third input terminal 23 is electrically connected to the third signal line 13. The second pulse output circuit 10 _2 teeth The first input terminal 21 is electrically connected to the second signal line 12, and the second input terminal 22 is The third input terminal 23 is electrically connected to the third signal line 13, and the third input terminal 23 is electrically connected to the fourth signal line 14. is connected.

[0029] In addition, in the mth pulse output circuit (m≧3) of the shift register shown in this embodiment, The fourth input terminal 24 is connected to the output terminal 27 of the (m-2)th pulse output circuit and the (m-1)th pulse output circuit. The fifth input terminal 25 is electrically connected to the fifth input terminal 25 of the pulse output circuit. The output terminal 27 of the (m-1) pulse output circuit and the fourth input terminal of the (m+1) pulse output circuit The sixth input terminal 26 is electrically connected to the (m+2)th pulse output circuit. The output terminal 27 is electrically connected to the sixth terminal of the (m-2)th pulse output circuit. the fifth input terminal 25 of the (m+1)th pulse output circuit and the fifth input terminal 26 of the (m+2)th pulse output circuit; The fourth input terminal 24 of the pulse output circuit is electrically connected to the OUT(m) terminal. To exert effort.

[0030] For example, the third pulse output circuit 10 _3 In this case, the fourth input terminal 24 receives the first pulse Output circuit 10 _1 output terminal and the second pulse output circuit 10 _2 The fifth input terminal and electrical The fifth input terminal 25 is connected to the second pulse output circuit 10. _2 output terminal and 4 Pulse output circuit 10 _4 The sixth input terminal 26 is electrically connected to the fourth input terminal of the Fifth pulse output circuit 10 _5 and the output terminal is electrically connected to the first pulse Output circuit 10 _1 the sixth input terminal of the fourth pulse output circuit 10 _4 The fifth input terminal and and the fifth pulse output circuit 10 _5 The fourth input terminal is electrically connected to the 3 pulse output circuit 10 _3 In this case, the fourth input terminal 24 is connected to the first pulse output circuit 10 _1 The fifth input terminal 25 receives the signal output from the second output terminal. Circuit 10 _2 The signal output from the output terminal of the fifth signal is input to the sixth input terminal 26. Pulse output circuit 10 _5 The signal output from the output terminal is input and output from output terminal 27. The output signal is sent to the first pulse output circuit 10 _1 the sixth input terminal of the fourth pulse output circuit 1 0 _4 The fifth input terminal and the fifth pulse output circuit 10 _5 The signal is input to the fourth input terminal of do.

[0031] In addition, in the first pulse output circuit, a first start pulse (SP 1) is input to the fifth input terminal 22, and a second start pulse (SP2) is input to the fifth input terminal 25.

[0032] Next, the first pulse output circuit 10 _1 ~ nth pulse output circuit 10 _n Specific configuration of This section explains:

[0033] First pulse output circuit 10 _1 ~ nth pulse output circuit 10 _n Each of the first The first to ninth transistors 101 to 109, the first capacitance element 111, and the second capacitance element 112 (see FIG. 1(C)). In addition, the first input terminal 21 to the sixth input terminal In addition to the input terminal 26 and the output terminal 27, the first power supply line 31 to the sixth power supply line 36 are connected to the first A signal is supplied to the transistor 101 to the ninth transistor 109.

[0034] The first transistor 101 has a first electrode (either a source electrode or a drain electrode) The second electrode (the other of the source electrode and the drain electrode) is electrically connected to the power supply line 31 of the first is electrically connected to the gate electrode of the third transistor 103 and the second electrode of the second capacitor 112. The second transistor is electrically connected to the first input terminal 22 and the gate electrode is electrically connected to the fourth input terminal 24. The transistor 102 has a first electrode electrically connected to the second power supply line 32 and a second electrode The gate electrode of the third transistor 103 is electrically connected to the gate electrode of the fourth transistor 104. The third transistor 103 is electrically connected to the gate electrode of the first transistor 104. The electrode is electrically connected to the first input terminal 21 and the second electrode is electrically connected to the output terminal 27. The fourth transistor 104 has a first electrode electrically connected to the third power supply line 33. and the second electrode is electrically connected to the output terminal 27. 105 has a first electrode electrically connected to the fourth power supply line 34 and a second electrode electrically connected to the second transistor 35. The gate electrode of the fourth transistor 102 and the gate electrode of the fourth transistor 104 are electrically connected to each other. The sixth transistor has a gate electrode electrically connected to the fourth input terminal 24. 106 has a first electrode electrically connected to the fourth power supply line 34 and a second electrode electrically connected to the second transistor The gate electrode of the fourth transistor 102 and the gate electrode of the fourth transistor 104 are electrically connected to each other. The seventh transistor has a gate electrode electrically connected to the fifth input terminal 25. 107 has a first electrode electrically connected to the fifth power line 35 and a second electrode electrically connected to the second transistor The gate electrode of the fourth transistor 102 and the gate electrode of the fourth transistor 104 are electrically connected to each other. The gate electrode of the eighth transistor is electrically connected to the sixth input terminal 26. 108 has a first electrode electrically connected to the fifth power line 35 and a second electrode electrically connected to the ninth transistor The gate electrode is electrically connected to the second electrode of the transistor 109, and the gate electrode is electrically connected to the second input terminal 22. The ninth transistor 109 has a first electrode electrically connected to the second transistor. The gate electrode of the fourth transistor 102 and the gate electrode of the fourth transistor 104 are electrically connected to each other. The first capacitor element 111 has a first terminal connected to a third input terminal 23. The first electrode is electrically connected to the sixth power supply line 36, and the second electrode is connected to the second transistor 10. The gate electrode of the second transistor 102 and the gate electrode of the fourth transistor 104 are electrically connected to each other. The second capacitor element 112 has a first electrode electrically connected to the output terminal 27 and a second electrode A voltage is applied to the second electrode of the first transistor 101 and the gate electrode of the third transistor 103. are electrically connected.

[0035] In FIG. 1C, the second electrode of the first transistor 101 and the second electrode of the second transistor 1 the second electrode of the third transistor 102, the gate electrode of the third transistor 103, the first electrode of the second capacitor 112, The connection point of the electrodes of the second transistor 102 and the second transistor 103 is referred to as node A. The gate electrode of the fourth transistor 104, the second electrode of the fifth transistor 105, the second electrode of the seventh transistor 106, the second electrode of the seventh transistor 107, the second electrode of the ninth transistor 108, The connection point between the first electrode of the transistor 109 and the second electrode of the first capacitor element 111 is called a node. B. The second electrode of the third transistor 103 and the second electrode of the fourth transistor 104 are The connection point between the second electrode, the first electrode of the second capacitor element 112, and the output terminal 27 is referred to as a node C. do.

[0036] Next, the operation of the shift register shown in FIG. 1 will be described with reference to FIGS. Specifically, in the timing chart of FIG. 2, there are a first period 51, a second period 52, a third period 53, and a fourth period 54. The following explanation will be made by dividing the period into a first period 53, a fourth period 54, and a fifth period 55. In the above, the first transistor 101 to the ninth transistor 109 are N-channel thin film transistors. When the gate-source voltage (Vgs) exceeds the threshold voltage (Vth), When this happens, the circuit will be in a conductive state.

[0037] Also, here, the second pulse output circuit 10 _2 The output of the second pulse is explained below. Output circuit 10 _2 The first input terminal 21 supplies a second clock signal (CK2). The second input terminal 22 is electrically connected to the second signal line 12 and receives a third clock signal (CK 3), and the third input terminal 23 is electrically connected to the third signal line 13 that supplies the fourth clock. The clock signal (CK4) is electrically connected to a fourth signal line 14 that supplies the clock signal (CK4).

[0038] The first power supply line 31 and the fifth power supply line 35 are supplied with a potential V1 (VDD). The second power supply line 32 to the fourth power supply line 34 and the sixth power supply line 36 are supplied with the potential V2 (VSS). Here, V1>V2. Also, the first clock signal (CK1) The fourth clock signal (CK4) is a signal that alternates between H level and L level at regular intervals. However, when it is at the H level, it is VDD, and when it is at the L level, it is VSS. For simplicity, VSS=0 is used, but this is not limiting.

[0039] In the first period 51, the second start pulse (SP2) becomes H level and the second pulse Pulse output circuit 10 _2 a first transistor 1 electrically connected to the fourth input terminal 24 of the The third clock signal (CK3) and the fourth transistor 105 are turned on. Since the clock signal (CK4) is also at the H level, the eighth transistor 108 and the ninth transistor The resistor 109 also turns on (see FIG. 3(A)).

[0040] At this time, the potential of the node A rises because the first transistor 101 is on. In addition, a through current flows between the fifth power supply line 35 and the fourth power supply line 34, but the transistor By adjusting the noise, the node For example, the channel width (the width between the source region and the drain region) of the fifth transistor 105 is controlled. The width of the channel in the direction perpendicular to the direction in which carriers flow through the drain region is This is achieved by making the first transistor 108 larger compared to the ninth transistor 109. .

[0041] In the second period 52, the first pulse output circuit 10_1 Output terminal 27 (OUT(1 )) outputs a high-level signal, and the second pulse output circuit 10 _2 5th input terminal 2 The sixth transistor 106 electrically connected to the third clock signal 5 is turned on. The signal (CK3) becomes L level and the eighth transistor 108 is turned off, so that the first period 5 The through current seen in 1 disappears (see Figure 3(B)).

[0042] At this time, the potential of the node A is changed when the second electrode of the first transistor 101 is connected to the source electrode. The potential of the first power supply line 31 is subtracted by the threshold voltage of the first transistor 101. Therefore, V1-Vth101 (Vth101 is the threshold voltage of the first transistor 101) Then, the first transistor 101 turns off, and the node A becomes V1-Vth1. It will become floating while maintaining 01.

[0043] Here, in the third transistor 103, the potential of the gate electrode is V1-Vth101. When the voltage between the gate and source of the third transistor 103 exceeds its threshold, When the voltage is rotating, that is, V1-Vth101-V2>Vth103 (Vth103 is the threshold voltage of the third transistor 103), the third transistor 103 is turned on. do.

[0044] In the third period 53, the second start pulse (SP2) becomes L level and the first The transistor 101 and the fifth transistor 105 are turned off. CK2) becomes H level, and the third transistor electrically connected to the first input terminal 21 An H-level signal is supplied to the first electrode of 103 (see FIG. 3(C)).

[0045] Here, since the third transistor 103 is on, a current flows between the source and the drain. occurs, and the node C (output terminal 27 (OUT(2))), i.e., the third transistor 10 The potential of the second electrode (in this case, the source electrode) of the third transistor 1 begins to rise. Between the gate and source of node C, there is a capacitive coupling due to the second capacitive element 112. As the potential rises, the potential of the gate electrode of the third transistor 103, which is in a floating state, Finally, the gate voltage of the third transistor 103 rises (bootstrap operation). The potential of the electrode becomes higher than V1+Vth103, and the potential of the node C becomes equal to V1.

[0046] This bootstrap operation is performed by connecting the gate electrode of the third transistor 103 and the second This is achieved by providing a second capacitor 112 between the electrode and the second capacitor. 112, the channel capacitance of the third transistor 103 and the This may be achieved by capacitive coupling of the parasitic capacitance between the gate electrode of 103 and the second electrode.

[0047] At this time, the first pulse output circuit 10 _1 Output terminal 27 (OUT(1)) is H Since the sixth transistor 106 is turned on, the node B is maintained at the L level. Therefore, when the potential at node C rises from the L level to the H level, Problems caused by capacitive coupling at node C can be suppressed.

[0048] After that, in the second half of the third period 53, the first pulse output circuit 10 _1 Output terminal 27 (O UT(1)) becomes L level, the sixth transistor 106 turns off, and the node B becomes floating. Also, the third clock signal (CK3) becomes H level, and the eighth transistor Then, the inverter 108 turns on (see FIG. 3(D)).

[0049] In the fourth period 54, the fourth pulse output circuit 10 _4 Output terminal 27 (OUT(4 )) becomes H level, and the fourth pulse output circuit 10 _4 Electrically connected to output terminal 27 The second pulse output circuit 10 connected _2 The input terminal 26 of the 7th transistor becomes H level. The second transistor 107 is turned on, and the node B is also at the H level. 02, the fourth transistor 104 is turned on, the third transistor 103 is turned off, and the output The terminal 27 (OUT(2)) becomes L level. Also, the fourth clock signal (CK4) becomes H. This causes the ninth transistor 109 to turn on (see FIG. 4A).

[0050] Thereafter, in the second half of the fourth period 54, the third clock signal (CK3) becomes L level, The eighth transistor 108 is turned off (see FIG. 4B).

[0051] In the fifth period 55, the fourth pulse output circuit 10 _4 Output terminal 27 (OUT(4 )) becomes L level, the seventh transistor 107 is turned off, and the node B remains H level. As a result, the second transistor 102 and the fourth transistor The inverter 104 is kept on (see FIG. 4(C)).

[0052] After that, during a certain period of the fifth period 55 (the third clock signal (CK3) and the fourth clock signal (CK4) When the clock signals (CK4) are both at H level, the eighth transistor 108 and the 9 is turned on, and a high-level signal is periodically supplied to node B (see FIG. 4(D)).

[0053] In this way, the node B is periodically set to H level while the potential of the output terminal 27 is held at L level. By configuring the signal to be supplied from the bell, malfunction of the pulse output circuit can be suppressed. In addition, the eighth transistor 108 and the ninth transistor 109 can be turned on or off. By periodically performing the flip-flop, it is possible to reduce the threshold shift of the transistor. This becomes:

[0054] During the fifth period 55, a signal of H level is supplied to the node B from the fifth power supply line 35. While the fifth transistor 105 and the sixth transistor 106 are not turned on, the off-state current of the fifth transistor 105 and the sixth transistor 106 However, the potential of the node B may drop due to the first capacitance element 11. By electrically connecting 1, it is possible to mitigate the drop in the potential of node B. .

[0055] In this embodiment, the fifth power supply line 35 is set to the same potential V1 as the first power supply line 31 (V DD), but the fifth power line 35 can also be set lower than the first power line 31 ( V1>V35>V2, where V35 is the potential of the fifth power supply line 35. The potentials of the gate electrodes of the transistor 102 and the fourth transistor 104 can be kept low. The threshold voltages of the second transistor 102 and the fourth transistor 104 can be shifted. This reduces the amount of heat generated and suppresses deterioration.

[0056] In addition, the shift register shown in this embodiment has an m-th pulse as shown in FIG. The pulse output from the (m+1)th pulse output circuit This is a driving method in which the shift registers overlap by half (1 / 2 period). The pulse output from the mth pulse output circuit and the pulse output from the (m+1)th pulse output circuit are Compared with the driving method in which the pulses output from the In this way, the time for which the pulse is output from the m-th pulse output circuit can be approximately doubled. The pulse output from the (m+1)th pulse output circuit overlaps by half (1 / 2 period). By using a new driving method, it is possible to apply a large load and operate at a high frequency. It is also possible to provide a pulse output circuit that operates under a wide range of operating conditions. In particular, thin film transistors using amorphous silicon, which have poor electrical properties, It is very effective to use the driving method shown in FIG. 5(A) for the register.

[0057] The shift register and the pulse output circuit shown in this embodiment mode may be the same as those shown in other embodiments in this specification. The present invention is implemented in combination with the configuration of the shift register and pulse output circuit shown in the embodiment. The present invention can also be applied to semiconductor devices. In this context, the term "semiconductor device" refers to a device that can function by utilizing semiconductor properties.

[0058] (Embodiment 2) In this embodiment mode, a shift register and a pulse output circuit different from those shown in the above embodiment modes are used. The configuration will be described with reference to the drawings.

[0059] The shift register shown in this embodiment includes a first pulse output circuit 10 _1 ~nth pulse Output circuit 10 _n(n≧3), and the first signal line 11 to the fourth signal line 12 which output clock signals. The first pulse output circuit 10 has a line 14 (see FIG. 6(A)). _1 ~nth Pulse output circuit 10 _n Each of the first input terminal 21, the second input terminal 22, and the third input terminal input terminal 23, fourth input terminal 24, fifth input terminal 25, sixth input terminal 26, first output terminal The first output terminal 27 and the second output terminal 28 are provided (see FIG. 6(B)). In the pulse output circuit shown in the first embodiment, a second output terminal 28 is newly added. It is.

[0060] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first signal line 1. It is electrically connected to any one of the first to fourth signal lines 14. In the m-th pulse output circuit (m≧3) of the shift register, the fourth input terminal 24 is The first output terminal 27 of the pulse output circuit (m-2) and the second output terminal 28 of the pulse output circuit (m-1) The fifth input terminal 25 is electrically connected to the (m-1)th pulse output terminal. The first output terminal 27 of the (m+1)th pulse output circuit and the fourth input terminal 24 of the (m+1)th pulse output circuit are connected to each other. The sixth input terminal 26 is electrically connected to the first output terminal of the (m+2)th pulse output circuit. 27, and the first output terminal 27 is electrically connected to the sixth output terminal of the (m-2)th pulse output circuit. input terminal 26, the fifth input terminal 25 of the (m+1)th pulse output circuit and the (m+2)th The second output terminal 28 is electrically connected to the fourth input terminal 24 of the pulse output circuit. A signal is output to (m).

[0061] That is, the shift register shown in this embodiment has a first output terminal 27 and a second output terminal 28 is provided, and an output terminal for outputting a signal to another pulse output circuit and an output terminal for outputting a signal to the outside are provided. The configuration is such that a separate output terminal is provided for this purpose.

[0062] Next, the first pulse output circuit 10 shown in this embodiment _1 ~ nth pulse output circuit 10 _n The specific configuration of the above will be described.

[0063] First pulse output circuit 10 _1 ~ nth pulse output circuit 10 _n Each of the first The transistors 101 to 109, the tenth transistor 201 to 203, The transistor 204, the first capacitance element 111, the second capacitance element 112, and the third capacitance element 21 1 (see FIG. 6C). The pulse output circuit shown in this embodiment has the same structure as the above embodiment. The pulse output circuit shown in the first embodiment includes the tenth transistor 201 to the thirteenth transistor 202. 04 and a third capacitor element 211 are added. The first input terminal 21 to the sixth input terminal 26, the first output terminal 27, and the first power supply line 31 In addition to the sixth power supply line 36, the second output terminal 28, the seventh power supply line 37 to the ninth power supply line 39 A signal is supplied to the transistor from

[0064] The tenth transistor 201 has a first electrode electrically connected to the first input terminal 21. The second electrode is electrically connected to the second output terminal 28, and the gate electrode is connected to the first transistor. The eleventh transistor 202 is electrically connected to the second electrode of the first transistor 101. The first electrode is electrically connected to the eighth power supply line 38, and the second electrode is electrically connected to the second output terminal 28. and the gate electrode of the second transistor 102 and the gate electrode of the fourth transistor The twelfth transistor 203 is electrically connected to the gate electrode of the first transistor 104. The first electrode is electrically connected to the ninth power supply line 39, and the second electrode is connected to the second output terminal 28. The gate electrode of the ninth transistor 109 is electrically connected to the gate electrode of the ninth transistor 109. The thirteenth transistor 204 has a first electrode electrically connected to the seventh power supply line 37. The second electrode is electrically connected to the first output terminal 27, and the gate electrode is connected to the ninth transistor. The third capacitance element 211 is electrically connected to the gate electrode of the transistor 109. , the first electrode is electrically connected to the second output terminal 28, and the second electrode is connected to the first transistor The second electrode of the tenth transistor 101 and the gate electrode of the tenth transistor 201 are electrically connected to each other. are.

[0065] The seventh power line 37 to the ninth power line 39 are connected to the second power line 32 to the fourth power line 33. 4, the sixth power supply line 36 may be configured to be supplied with the potential of V2 (VSS). do.

[0066] The first output terminal 27 and the second output terminal 28 are provided so as to output the same signal. The third transistor 103 corresponds to the tenth transistor 201, and the fourth transistor The eleventh transistor 202 corresponds to the eleventh transistor 104. The first transistor 201 performs the bootstrap operation in the same manner as the third transistor 103. The bootstrap operation of the tenth transistor 201 is performed by By providing a third capacitor element 211 between the gate electrode and the second electrode of the transistor 201, However, the third capacitor element 211 is not provided, and the channel of the tenth transistor 201 is the parasitic capacitance between the gate electrode and the second electrode of the tenth transistor 201; This may be achieved by capacitive coupling.

[0067] The twelfth transistor 203 and the thirteenth transistor 204 are connected to the gate of the scanning line. The twelfth transistor 203 and the thirteenth transistor If the fall time of the potential of the scanning line can be sufficiently shortened by the fourth transistor 104, 04, there is no need to shorten the fall time of the potential of the scan line by the 11th transistor 202. Therefore, the potential of the fifth power supply line 35 can be set lower than the power supply of the first power supply line 31. This is because the fourth transistor 104, the eleventh transistor 202, the second transistor This makes it possible to reduce the threshold shift of the resistor 102.

[0068] The shift register and the pulse output circuit shown in this embodiment mode may be the same as those shown in other embodiments in this specification. The present invention is implemented in combination with the configuration of the shift register and pulse output circuit shown in the embodiment. The present invention can also be applied to semiconductor devices.

[0069] (Embodiment 3) In this embodiment mode, a shift register and a pulse output circuit different from those shown in the above embodiment modes are used. The configuration will be explained below.

[0070] In the configurations shown in the first and second embodiments, all the circuits are N-channel thin-film transistors. Although an example using thin film transistors has been shown, it is possible to use unipolar thin film transistors. In this respect, a similar configuration may be achieved using only P-channel thin film transistors. Although not shown, in the diagrams shown in FIG. 1(C) or FIG. 6(C), the connections of the transistors are the same. In this way, if the potential of the power supply line is reversed from that described in the first and second embodiments, In addition, the H level and L level of the input signal may be reversed. The present invention can also be applied to semiconductor devices.

[0071] (Fourth embodiment) Regarding the structure in which the shift register shown in the above embodiment is provided in the display device, please refer to the drawings. I will explain.

[0072] In FIG. 9A, a plurality of pixels 1101 are arranged in a matrix on a substrate 1107. A pixel portion 1102 is provided with a signal line driver circuit 1103 and a first The first scanning line driver circuit 1104 and the second scanning line driver circuit 1105 are provided. The path is supplied with a signal from the outside via the FPC 1106.

[0073] FIG. 9B shows the first scanning line driver circuit 1104 and the second scanning line driver circuit 1105. The scanning line driving circuits 1104 and 1105 are configured by a shift register 1114 and a buffer 9C shows the configuration of the signal line driver circuit 1103. The line driver circuit 1103 includes a shift register 1111, a first latch circuit 1112, a second latch circuit 1113, and a It has a switching circuit 1113 and a buffer 1117.

[0074] The circuit operating as a shift register shown in this embodiment is the shift register 111 1 and the shift register 1114. By applying a circuit that operates as a shift register, amorphous silicon When a circuit that operates as the shift register is provided using the thin film transistors used, It can also be operated at high frequencies.

[0075] The configuration of the scanning line driver circuit and the signal line driver circuit is not limited to the configuration shown in FIG. For example, a sampling circuit, a level shifter, etc. may be provided. In addition, circuits such as a CPU and a controller may be integrally formed on the substrate 1107. This reduces the number of external circuits (ICs) to be connected, making it possible to further reduce weight and thickness, making it ideal for mobile devices. It is particularly effective at the end.

[0076] The display device shown in this embodiment mode may be a display device having a shift register shown in another embodiment mode in this specification. It is possible to implement the present invention in combination with a resistor, a pulse output circuit, or a display device.

[0077] (Embodiment 5) In this embodiment mode, a structure of a display panel used in the display device shown in Embodiment Mode 4 will be described. This will be explained with reference to the drawings.

[0078] First, a display panel applicable to the display device will be described with reference to FIG. FIG. 10(A) is a top view showing the display panel, and FIG. 10(B) is a cutaway view of FIG. 10(A) along A-A'. 36. A signal line driver circuit 3601, a pixel portion 3602, a second scanning The first scanning line driver circuit 3603 and the second scanning line driver circuit 3606 are also included. The inside surrounded by the sealing material 3605 is a space 3607. There are.

[0079] The wiring 3608 is connected to the second scanning line driver circuit 3603 and the first scanning line driver circuit 3606. and a wiring for transmitting a signal input to the signal line driver circuit 3601, Video signals and clock signals are transmitted from the FPC (Flexible Print Circuit) 3609. It receives signals, start signals, etc. There is an IC chip on the joint between the FPC3609 and the display panel. chip (semiconductor chip with memory circuit, buffer circuit, etc.) 3618 and IC chip The chip 3619 is implemented using COG (Chip On Glass) etc. Although only the FPC is shown in the figure, this FPC is equipped with a printed wiring board (PWB). The display device in this specification does not only refer to the display panel itself, but also to the This also includes the state where an FPC or PWB is attached. This includes those that implement the above.

[0080] Next, the cross-sectional structure will be described with reference to FIG. 602 and its peripheral driving circuits (second scanning line driving circuit 3603, first scanning line driving circuit 36 3606 and a signal line driver circuit 3601) are formed. 01 and pixel portion 3602 are shown.

[0081] The signal line driver circuit 3601 includes an N-channel TFT 3620 and a P-channel TFT 3630. In this embodiment, a CMOS circuit is configured using the 621. Although the display panel shown in FIG. 1 has an integrally formed driving circuit, this is not necessarily required. A part or a portion of the circuit may be formed on an IC chip or the like and mounted using COG or the like.

[0082] The pixel section 3602 includes a switching TFT 3611 and a driving TFT 3612. The source electrode of the driving TFT 3612 is The first electrode 3613 is electrically connected to the first electrode 3613. The end of the first electrode 3613 is covered with the In this example, a positive photosensitive acrylic resin film is used. It is formed by

[0083] In order to improve the coverage, the insulator 3614 is bent at the top or bottom. For example, a positive type material is used as the material for the insulator 3614. When photosensitive acrylic is used, the radius of curvature (0.2 μm to 3 It is preferable to provide a curved surface having a thickness of 1 μm. Negative type that becomes insoluble in etchant when exposed to light, or soluble in etchant when exposed to light Any of the positive type resins can be used.

[0084] A layer 3616 containing an organic compound and a second electrode 3617 are formed on the first electrode 3613. Here, the material used for the first electrode 3613 that functions as an anode is It is desirable to use a material with a large work function. For example, ITO (Indium Tin Oxide) Indium zinc oxide (IZO) film, titanium nitride film, chromium film, titanium In addition to single layer films such as stainless steel, Zn, and Pt films, there are also films with titanium nitride and aluminum as the main components. and a three-layer structure consisting of a titanium nitride film, an aluminum-based film, and a titanium nitride film. In addition, when a laminated structure is used, the resistance as a wiring is low, and a good An ohmic contact can be made and the electrode can further function as an anode.

[0085] The layer 3616 containing an organic compound may be formed by evaporation using an evaporation mask or by inkjet printing. The layer 3616 containing an organic compound contains a metal complex of Group 4 of the periodic table. The body is used as a part of the material, and other materials that can be used in combination are The organic compound may be a low molecular weight material or a high molecular weight material. The materials used are usually organic compounds in a single layer or laminated form. In the above embodiment, a structure in which an inorganic compound is used as part of a film made of an organic compound is also included. Furthermore, known triplet materials can also be used.

[0086] Furthermore, a second electrode (cathode) 3617 formed on the layer 3616 containing an organic compound is The materials used are those with a low work function (Al, Ag, Li, Ca, or a combination of these). Gold (MgAg, MgIn, AlLi, CaF2, or calcium nitride) may be used. When light generated in the layer 3616 containing an organic compound is transmitted through the second electrode 3617, The second electrode (cathode) 3617 is made of a thin metal film and a transparent conductive film (IT O (indium tin oxide), indium oxide zinc oxide alloy (In2O3-ZnO), acid It is preferable to use a laminate with zinc oxide (ZnO, etc.).

[0087] Furthermore, the sealing substrate 3604 is bonded to the substrate 3610 with a sealing material 3605. , into a space 3607 surrounded by the substrate 3610, the sealing substrate 3604, and the sealing material 3605. The space 3607 is filled with an inert gas. In addition to cases where the gas is filled with nitrogen or argon, it also includes a configuration where the gas is filled with a sealing material 3605. It shall be.

[0088] It is preferable to use an epoxy resin for the sealing material 3605. It is desirable that the material be one that is as impermeable to moisture and oxygen as possible. Materials used for 04 include glass substrates, quartz substrates, and FRP (Fiberglass-R reinforced plastics), PVF (polyvinyl fluoride), polyester A plastic substrate made of polyethylene or acrylic can be used.

[0089] In this manner, a display panel can be obtained.

[0090] As shown in FIG. 10, a signal line driver circuit 3601, a pixel portion 3602, a second scanning line driver circuit 3603, and a The first scanning line driver circuit 3603 and the first scanning line driver circuit 3606 are integrally formed, thereby reducing the cost of the display device. It is possible to achieve this.

[0091] The display panel is configured as follows: 1, a pixel portion 3602, a second scanning line driver circuit 3603, and a first scanning line driver circuit 3606 11A corresponding to the signal line driver circuit 3601. The signal line driver circuit 4201 is formed on an IC chip and mounted on the display panel by COG or the like. In addition, the substrate 4200, the pixel portion 4202, the second scanning line driver 4203, and the like shown in FIG. a first scanning line driver circuit 4203, a first scanning line driver circuit 4204, an FPC 4205, and an IC chip 4206 , IC chip 4207, sealing substrate 4208, and sealing material 4209 are the same as those of the substrate 36 in FIG. 10, pixel portion 3602, second scanning line driver circuit 3603, first scanning line driver circuit 3606 , FPC3609, IC chip 3618, IC chip 3619, sealing substrate 3604, Equivalent to material 3605.

[0092] In other words, only the signal line driver circuit, which requires high speed operation, is made of CMOS or the like. It is used to form IC chips and achieve low power consumption. By using a semiconductor chip of this type, it is possible to achieve faster operation and lower power consumption.

[0093] The first scanning line driver circuit 4 provided with the shift register shown in the above embodiment mode 203 and the second scanning line driver circuit 4204 are formed integrally with the pixel portion 4202, It is possible to achieve this.

[0094] In this way, the cost of high-definition display devices can be reduced. 00 and an IC chip with functional circuits (memory and buffers) formed on it. This allows for effective use of the substrate area.

[0095] In addition, the signal line driver circuit 3601, the second scanning line driver circuit 3603, and The signal line driver circuit 4211 in FIG. 11B corresponds to the first scanning line driver circuit 3606, The scanning line driver circuit 4214 and the first scanning line driver circuit 4213 are formed on an IC chip, It may be configured to be mounted on the display panel using COG or the like. In this case, a high-definition display device can be used. Therefore, in order to realize a display device with lower power consumption, Therefore, it is desirable to use polysilicon for the semiconductor layer of the transistor used in the pixel portion. In addition, the substrate 4210, the pixel portion 4212, the FPC 4215, and the IC chip 4216, IC chip 4217, sealing substrate 4218, and sealing material 4219 are the same as those in FIG. 10(A). Substrate 3610, pixel section 3602, FPC 3609, IC chip 3618, IC chip 36 19, a sealing substrate 3604, and a sealing material 3605.

[0096] In addition, amorphous silicon is used for the semiconductor layer of the transistor in the pixel portion 4212. This allows for cost reduction. Furthermore, it is possible to manufacture large display panels. This becomes:

[0097] Further, examples of a display element applicable to the display element 3622 are shown in FIGS. That is, the structure of a display element applicable to the pixel shown in the above embodiment mode is shown in FIG. , (B) will be used to explain.

[0098] The display element of FIG. 15(A) is made up of an anode 4402 and a hole injection material on a substrate 4401. A hole injection layer 4403, a hole transport layer 4404 made of a hole transport material thereon, and a light emitting layer 440 5, an electron transport layer 4406 made of an electron transport material, and an electron injection layer 440 made of an electron injection material 7 and a cathode 4408 are laminated. It may be formed from only one type of luminescent material, but may also be formed from two or more types of materials. The structure of the element of the present invention is not limited to this structure.

[0099] In addition to the laminated structure in which each functional layer is laminated as shown in Figures 15(A) and 15(B), A device using a compound, a high efficiency device using a triplet light-emitting material that emits light from a triplet excited state in the light-emitting layer There are a wide variety of variations, including the use of hole blocking layers to prevent carrier recombination. White display elements obtained by controlling the combined area and dividing the light-emitting area into two areas It can also be applied to

[0100] The method for fabricating an element according to the present invention shown in FIG. 15(A) is to first form a substrate having an anode 4402 (ITO). A hole injection material, a hole transport material, and a light emitting material are deposited in this order on the substrate 4401. Then, a material for the cathode 4408 is vapor-deposited, followed by an electron injection material.

[0101] Next, the materials for the hole injection material, hole transport material, electron transport material, electron injection material, and light emitting material are Suitable materials are listed below.

[0102] As hole injection materials, organic compounds such as porphyrin compounds and phthalocyanines are used. (hereinafter referred to as "H2Pc"), copper phthalocyanine (hereinafter referred to as "CuPc"), etc. In addition, the ionization potential value is smaller than that of the hole transport material used, and Any material that has a hole transport function can also be used as a hole injection material. There are also materials in which the polymer compound is chemically doped, such as polystyrene sulfonate (PSS ") doped polyethylenedioxythiophene (hereinafter referred to as "PEDOT") In addition, insulating polymer compounds are also effective in flattening the anode. Polyimide (hereinafter referred to as "PI") is often used. In addition to thin metal films such as gold and platinum, aluminum oxide (hereinafter referred to as "alumina") is also used. ) ultra-thin films.

[0103] The most widely used hole transport materials are aromatic amines (i.e., benzene The compounds are widely used materials such as 4, 4'-bis(diphenylamino)-biphenyl (hereinafter referred to as "TAD") and its derivatives The compound 4,4'-bis[N-(3-methylphenyl)-N-phenyl-amino]-bis( ... phenyl (hereinafter referred to as "TPD"), 4,4'-bis[N-(1-naphthyl)-N-phenyl] 4,4',4"-[4,4'-(4-amino)-biphenyl] (hereinafter referred to as "α-NPD"). Tris(N,N-diphenyl-amino)-triphenylamine (hereinafter referred to as "TDATA") ), 4,4',4"-tris[N-(3-methylphenyl)-N-phenyl- Starburst type such as [amino]-triphenylamine (hereinafter referred to as "MTDATA") Examples include aromatic amine compounds.

[0104] Metal complexes are often used as electron transport materials, such as Alq, BAlq, and tris(4-methyl-2-methyl-1,3-dichloro-2,4-dichloro-1,3-dichloro-2,4-dichloro-1,4 ... bis(10-hydroxy-8-quinolinolato)aluminum (hereinafter referred to as "Almq"), beryllium (hereinafter referred to as "BeBq") Metal complexes with quinoline or benzoquinoline skeletons are also available. 2-hydroxyphenyl)-benzoxazolato] zinc (hereinafter referred to as "Zn(BOX)2" bis[2-(2-hydroxyphenyl)-benzothiazolato]zinc (hereinafter referred to as "Z Metal complexes with oxazole and thiazole ligands, such as n(BTZ)2 In addition to metal complexes, there are also 2-(4-biphenylyl)-5-(4-tert- butylphenyl)-1,3,4-oxadiazole (hereinafter referred to as "PBD"), OXD -7, oxadiazole derivatives such as TAZ, 3-(4-tert-butylphenyl)- 4-(4-ethylphenyl)-5-(4-biphenylyl)-1,2,4-triazole ( triazole derivatives such as p-EtTAZ), bathophenanthroline ( Phenanthroline derivatives such as BCP (hereinafter referred to as "BPhen") have electron transport properties. do.

[0105] As the electron injection material, the above-mentioned electron transport material can be used. Metal halides such as calcium fluoride, lithium fluoride, and cesium fluoride, and lithium oxide Ultra-thin films of insulating materials such as alkali metal oxides of lithium are often used. Lithium acetylacetonate (hereinafter referred to as "Li(acac)") and 8-quinolinolato- Complexes of alkali metals such as lithium (hereinafter referred to as "Liq") are also effective.

[0106] The luminescent materials are Alq, Almq, BeBq, BAlq, Zn(BOX)2, Zn In addition to metal complexes such as (BTZ)2, various fluorescent dyes are effective. 4,4'-bis(2,2-diphenyl-vinyl)-biphenyl and red-orange 4-( Dicyanomethylene)-2-methyl-6-(p-dimethylaminostyryl)-4H-pyran Triplet luminescent materials are also possible, with platinum or iridium as the central metal. The triplet luminescent material is tris(2-phenylpyridine) yridinium. Umium, bis(2-(4'-tolyl)pyridinato-N,C 2’ ) Acetylacetonate Um (hereinafter referred to as "acacIr(tpy)2"), 2,3,7,8,12,13,1 7,18-octaethyl-21H,23H porphyrin-platinum is known.

[0107] By combining materials with the above-mentioned functions, we can create highly reliable display elements. It can be manufactured.

[0108] In addition, the polarity of the driving transistor in the pixel configuration shown in the above embodiment is changed to an N-channel The potential of the opposing electrode of the display element is set to a potential set to a power supply line. If the above is reversed, a display element having layers formed in the reverse order to that shown in FIG. 15(A) can be used. That is, as shown in FIG. 15(B), a cathode 4408, an electron injection material 4409, and a an electron transport layer 4406 made of an electron transport material thereon; layer 4405, a hole transport layer 4404 made of a hole transport material, and a hole injection layer made of a hole injection material. The element structure is a stack of a layer 4403 and an anode 4402 .

[0109] In addition, the display element requires that at least one of the anode and cathode is transparent in order to extract light. Then, the TFT and the display element are formed on the substrate, and light is emitted from the surface opposite to the substrate. Top emission, bottom emission, and both the substrate side and the opposite side of the substrate. There is a display element with a double-sided emission structure in which light is emitted from both sides, and the pixel structure shown in the above embodiment The composition can be applied to any display element with an emission structure.

[0110] A display element with a top emission structure will be described with reference to FIG.

[0111] A driving TFT 4501 is formed on a substrate 4500 via an undercoat film 4505. A first electrode 4502 is formed in contact with the source electrode of the FT4501, and an organic compound A layer 4503 containing the compound and a second electrode 4504 are formed.

[0112] The first electrode 4502 is an anode of the display element, and the second electrode 4504 is an anode of the display element. That is, the first electrode 4502 and the second electrode 4504 are connected to each other by an organic compound. The area where the layer 4503 containing the organic compound is sandwiched becomes the display element.

[0113] In addition, the material used for the first electrode 4502 functioning as an anode is a material having a work function. It is desirable to use a material with a large number of layers. For example, titanium nitride film, chromium film, tungsten film, In addition to single layer films such as titanium nitride, Zn film, and Pt film, films mainly composed of titanium nitride and aluminum are also available. and a three-layer structure consisting of a titanium nitride film, an aluminum-based film, and a titanium nitride film. In addition, when the laminated structure is used, the resistance as wiring is low and good ohmic properties are obtained. The metal film can be used to make contact with the electrode and also function as an anode. By using the above, it is possible to form an anode that does not transmit light.

[0114] In addition, the material used for the second electrode 4504 that functions as a cathode is a material having a small work function. Materials that are difficult to use (Al, Ag, Li, Ca, or their alloys MgAg, MgIn, AlLi, A metal thin film made of CaF2 or calcium nitride and a transparent conductive film (ITO (indium tin oxide) Lamination with indium tin oxide (IZO), zinc oxide (ZnO, etc.) In this way, by using a thin metal film and a transparent conductive film, It is possible to form a cathode that can transmit light.

[0115] In this way, light from the display element can be extracted to the upper surface as shown by the arrow in FIG. 12(A). That is, when applied to the display panel of FIG. 10, the light is directed to the sealing substrate 3604 side. Therefore, when a display element with a top emission structure is used in a display device, The substrate 3604 is a light-transmitting substrate.

[0116] In addition, when an optical film is provided, the optical film may be provided on the sealing substrate 3604. stomach.

[0117] Next, a display element with a bottom emission structure will be described with reference to FIG. Since the display element has the same structure as that of FIG. 12(A), the same reference numerals will be used in the description.

[0118] Here, the material used for the first electrode 4502 that functions as an anode is a material having a large work function. It is desirable to use a material with a high resistance. For example, ITO (indium tin oxide) film, A transparent conductive film such as an IZO film can be used. By using a transparent conductive film, an anode that can transmit light can be formed.

[0119] In addition, the material used for the second electrode 4504 that functions as a cathode is a material having a small work function. Materials that are difficult to use (Al, Ag, Li, Ca, or their alloys MgAg, MgIn, AlLi, A metal film made of CaF2 or calcium nitride can be used. By using a metal film that reflects light, a cathode that does not transmit light can be formed.

[0120] In this way, light from the display element can be extracted to the bottom surface as shown by the arrow in FIG. 12(B). In other words, when applied to the display panel of FIG. 10, light is incident on the substrate 3610 side. Therefore, when a display element with a bottom emission structure is used in a display device, the substrate 36 The substrate 10 is optically transparent.

[0121] In addition, when an optical film is provided, the optical film may be provided on the substrate 3610 .

[0122] Next, a display element with a dual emission structure will be described with reference to FIG. Since the display element has the same structure as that of FIG. 12(A), the same reference numerals will be used in the description.

[0123] Here, the material used for the first electrode 4502 that functions as an anode is a material having a large work function. It is desirable to use a material with a high resistance. For example, ITO (indium tin oxide) film, A transparent conductive film such as an IZO film can be used. By using a transparent conductive film, an anode that can transmit light can be formed.

[0124] In addition, the material used for the second electrode 4504 that functions as a cathode is a material having a small work function. Materials that are difficult to use (Al, Ag, Li, Ca, or their alloys MgAg, MgIn, AlLi, A metal thin film made of CaF2 or calcium nitride and a transparent conductive film (ITO (indium tin oxide) Indium tin oxide), indium oxide zinc oxide alloy (In2O3-ZnO), zinc oxide (Zn It is preferable to use a laminate of a thin metal film and a transparent conductive film. By using a film, a cathode that can transmit light can be formed.

[0125] In this way, light from the display element can be extracted to both sides as shown by the arrows in FIG. 12(C). In other words, when applied to the display panel of FIG. 10, the substrate 3610 and the sealing substrate Therefore, when a display element with a double-sided emission structure is used in a display device, the light is emitted to the side of the plate 3604. In this case, the substrate 3610 and the sealing substrate 3604 are both optically transparent substrates. There are.

[0126] In addition, when an optical film is provided, it is necessary to form an optical film on both the substrate 3610 and the sealing substrate 3604. An optical film may be provided.

[0127] In addition, a display device that realizes full color display using a white display element and a color filter The present invention can also be applied to

[0128] For example, as shown in FIG. 13, a base film 4602 is formed on a substrate 4600. A driving TFT 4601 is formed, and a first electrode is connected to the source electrode of the driving TFT 4601. A layer 4604 containing an organic compound and a second electrode 4605 are formed on the electrode 4603. It may also be configured as such.

[0129] The first electrode 4603 is an anode of the display element. The first electrode 4603 and the second electrode 4605 are the cathodes of the element. The layer 4604 containing the organic compound is sandwiched between the organic compound layers to form a display element. Then, a red color filter 4606R and a green color filter 4606R are placed on the top of the display element. It is equipped with a blue color filter 4606B and a blue color filter 4606G, allowing for full color display. In addition, the black matrix that separates these color filters (also known as BM) 4607 is provided.

[0130] The above-mentioned configurations of the display element can be used in combination, and the pulse output circuit of the present invention, It can be used appropriately in a display device driven by a shift register. The panel configuration and display element are merely examples, and of course other configurations can also be applied.

[0131] (Embodiment 6) The present invention can be applied to various electronic devices. Such electronic devices include video cameras, digital cameras, etc. cameras, goggle-type displays, navigation systems, sound playback devices (car audio) audio components, computers, game devices, mobile information terminals (mobile computers, computers, mobile phones, portable game consoles, e-books, etc.), image playback devices equipped with recording media Devices (specifically, recording media such as Digital Versatile Discs (DVDs)) and a device equipped with a light-emitting device that can reproduce the image and display the image.

[0132] FIG. 14A shows a light-emitting device, which includes a housing 6001, a support base 6002, a display portion 6003, and a screen. The display device of the present invention includes a display unit 60 The light-emitting device can be used for personal computers, televisions, etc. The shift register of the present invention includes all light-emitting devices for displaying information, such as those for receiving digital broadcasts and for displaying advertisements. By driving the display portion 6003 using a register, it is possible to reduce power consumption. can.

[0133] FIG. 14B shows a camera, which includes a main body 6101, a display unit 6102, an image receiving unit 6103, an operation unit 6104, and an operation panel 6106. The key 6104, the external connection port 6105, the shutter button 6106, etc. The display portion 6102 is driven using a shift register to reduce power consumption. It is possible.

[0134] FIG. 14C shows a computer, which includes a main body 6201, a housing 6202, a display unit 6203, It includes a keyboard 6204, an external connection port 6205, a pointing device 6206, etc. By driving the display portion 6203 using the shift register of the present invention, power consumption can be reduced. It is possible to reduce this.

[0135] FIG. 14D shows a mobile computer, which includes a main body 6301, a display unit 6302, a switch, and a The shift register of the present invention includes a switch 6303, an operation key 6304, an infrared port 6305, etc. By driving the display portion 6302 using a capacitor, power consumption can be reduced. .

[0136] FIG. 14(E) shows a portable image playback device (specifically, a DVD playback device) equipped with a recording medium. The main body 6401, the housing 6402, the display unit A 6403, the display unit B 6404, the recording medium It includes a (DVD, etc.) reading unit 6405, operation keys 6406, a speaker unit 6407, etc. The display unit A6403 mainly displays image information, and the display unit B6404 mainly displays text information. The shift register of the present invention can be used to display the display unit A6403 and the display unit B6 By driving 404, it is possible to reduce power consumption.

[0137] FIG. 14(F) shows a goggle-type display, which includes a main body 6501, a display unit 6502, and an articulated The display unit 6502 is driven by using the shift register of the present invention. Therefore, power consumption can be reduced.

[0138] FIG. 14G shows a video camera, which includes a main body 6601, a display portion 6602, a housing 6603, External connection port 6604, remote control receiver 6605, image receiver 6606, battery 660 7, a voice input unit 6608, operation keys 6609, an eyepiece unit 6610, etc. By driving the display portion 6602 using a register, it is possible to reduce power consumption. can.

[0139] FIG. 14(H) shows a mobile phone, which includes a main body 6701, a housing 6702, a display portion 6703, and a sound A voice input unit 6704, a voice output unit 6705, operation keys 6706, an external connection port 6707, The display portion 6703 is driven using the shift register of the present invention. This makes it possible to reduce power consumption.

[0140] In this way, the present invention can be applied to any electronic device. [Explanation of symbols]

[0141] 10 Pulse output circuit 11 Signal line 12 Signal line 13 Signal line 14 Signal line 21 Input terminal 22 Input terminal 23 Input terminal 24 input terminals 25 Input terminals 26 Input terminals 27 Output terminal 31 Power line 32 Power line 33 Power line 34 Power line 35 Power line 36 Power line 51 period 52 period 53 period 54 period 55 period 101 Transistor 102 transistor 103 Transistor 104 transistors 105 transistors 106 transistors 107 Transistor 108 transistors 109 Transistor 111 Capacitor element 112 Capacitor element

Claims

1. A semiconductor device comprising first to sixth transistors, the first to sixth transistors are P-channel transistors, one of a source and a drain of the first transistor is directly connected to a first wiring; the other of the source and the drain of the first transistor is directly connected to a second wiring; one of the source and the drain of the second transistor is directly connected to the second wiring; one of the source and the drain of the third transistor is directly connected to the gate of the first transistor; the other of the source and the drain of the third transistor is directly connected to a third wiring; a gate of the third transistor is directly connected to a fourth wiring; one of the source and the drain of the fourth transistor is directly connected to a fifth wiring; one of the source and the drain of the fifth transistor is directly connected to the other of the source and the drain of the fourth transistor; the other of the source and the drain of the fifth transistor is directly connected to the gate of the second transistor; one of the source and the drain of the sixth transistor is directly connected to the gate of the second transistor; the same potential is applied to the other of the source or the drain of the second transistor and the other of the source or the drain of the sixth transistor, a gate of the third transistor is not directly connected to a gate of the fourth transistor; a gate of the fourth transistor is not directly connected to a gate of the fifth transistor; one of the source and the drain of the third transistor is not directly connected to the gate of the sixth transistor; a gate of the third transistor is not directly connected to a gate of the sixth transistor; When the first transistor is in an on state, an L-level signal is output from the second wiring; When the second transistor is in an on state, an H-level signal is output from the second wiring; When the first transistor is in an on state, the sixth transistor is in an on state, and has a function of turning the second transistor in an off state; When the third transistor is in an on state, a potential that turns on the first transistor is applied to a gate of the first transistor from the third wiring; a function of allowing a time during which the fourth transistor is off and a time during which the fifth transistor is off to overlap, a function of allowing a time during which the fourth transistor is on and a time during which the fifth transistor is on to overlap; a function of allowing a time during which the fourth transistor is on and a time during which the fifth transistor is off to overlap; a function of allowing a time during which the fourth transistor is off and a time during which the fifth transistor is on to overlap; when the fourth transistor is in an on state and the fifth transistor is in an on state, a potential of the fifth wiring is applied to a gate of the second transistor, the second transistor is turned on, and the H-level signal is output from the second wiring; A semiconductor device in which the sixth transistor is turned on at a time different from the time the fourth transistor and the fifth transistor are turned on.

2. In claim 1, one electrode of a capacitance element is electrically connected to a gate of the second transistor; The semiconductor device in which the other electrode of the capacitor is given the same potential as the other of the source and drain of the second transistor.

Images