Semiconductor device and crystal growth method

Abstract

In one embodiment, a semiconductor device of the present invention comprises at least a semiconductor layer having a corundum structure, and a first electrode and a second electrode each arranged on a first surface side of the semiconductor layer. The semiconductor device is configured such that electrical current flows in a first direction from the first electrode toward the second electrode. The m-axis direction of the semiconductor layer is parallel to the first direction. Additionally, in another embodiment, the semiconductor device is characterized by comprising at least a semiconductor layer having a corundum structure, a first electrode arranged on a first surface side of the semiconductor layer, and a second electrode arranged on a second surface side that faces opposite the first surface side. The first surface is the m surface, the second electrode is longer than the first electrode in at least the first direction, and the first direction is the c-axis direction of the semiconductor layer. As one example of an embodiment of a crystal growth method of the present invention, a crystal growth method includes growing a corundum-structured crystal on a c-surface of a crystal substrate for corundum-structured crystal growth, the crystal substrate being provided with an uneven section such that the displacement accompanying the crystal growth extends in the m-axis direction more than in the a-axis direction. Additionally, one example of an embodiment of the present invention is characterized by being a method for growing a corundum-structured crystal by using a crystal substrate for crystal growth, wherein an uneven section is provided on the crystal growth surface side of the crystal substrate such that displacement that expands in the m-axis direction of the crystal is moved from the direction of crystal growth.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device useful for a power device, etc. The present invention also relates to a crystal growth method by which crystals useful for a power device, etc. can be obtained. [Background technology]

[0002] Conventionally, cracks and lattice defects occur when growing crystals on heterogeneous substrates. To address this issue, methods such as matching the lattice constants and thermal expansion coefficients of the substrate and film have been studied. In addition, when mismatching occurs, film formation techniques such as ELO have also been considered.

[0003] Patent Document 1 describes a method of forming a buffer layer on a heterogeneous substrate and growing a zinc oxide-based semiconductor layer on the buffer layer. Patent Document 2 describes forming a nanodot mask on a heterogeneous substrate and then forming a single-crystal semiconductor material layer. Non-Patent Document 1 describes a method of growing GaN crystals on sapphire via GaN nanocolumns. Non-Patent Document 2 describes a method of growing GaN crystals on Si(111) using a periodic SiN intermediate layer to reduce defects such as pits.

[0004] However, with both techniques, the film formation speed is slow, and cracks, dislocations, warpage, etc. occur in the substrate, and dislocations, cracks, etc. occur in the epitaxial film, making it difficult to obtain a high-quality epitaxial film. These techniques also cause problems when increasing the diameter of the substrate and the thickness of the epitaxial film.

[0005] Furthermore, semiconductor devices using gallium oxide (Ga2O3), which has a large band gap, are attracting attention as next-generation switching elements that can achieve high voltage resistance, low loss, and high heat resistance, and are expected to be applied to power semiconductor devices such as inverters. Furthermore, due to its wide band gap, it is also expected to be applied to light-emitting and receiving devices such as LEDs and sensors. The band gap of gallium oxide can be controlled by mixing indium and aluminum, either individually or in combination, and it constitutes an extremely attractive material family as an InAlGaO-based semiconductor. Here, InAlGaO-based semiconductors refer to In X Al Y Ga Z O3 (0≦X≦2, 0≦Y≦2, 0≦Z≦2, X+Y+Z=1.5~2.5), and can be viewed as the same material family containing gallium oxide.

[0006] However, since the most stable phase of gallium oxide is the β-gallium structure, it is difficult to form a crystalline film with a corundum structure unless a special film formation method is used, and many issues still remain in terms of crystal quality, etc. In response to this, several studies are currently being conducted on the formation of a crystalline semiconductor film with a corundum structure. Patent Document 3 describes a method for producing an oxide crystal thin film by mist CVD using gallium or indium bromide or iodide. Patent Documents 4 to 6 describe multilayer structures in which a semiconductor layer having a corundum crystal structure and an insulating film having a corundum crystal structure are stacked on a base substrate having a corundum crystal structure.

[0007] Recently, studies have been conducted on ELO growth of gallium oxide films with a corundum structure, as described in Patent Documents 7 to 9. According to the methods described in Patent Documents 7 to 9, it is possible to obtain a high-quality gallium oxide film with a corundum structure, but even with the ELO film formation technique utilizing the difference in thermal expansion coefficients described in Patent Document 7, when the crystalline film is actually examined, it tends to grow facets, and there are problems such as dislocations and cracks caused by this facet growth.In addition, as described in Patent Document 10, studies are also being conducted on improving electrical properties by the plane direction. Patent Documents 3 to 10 are all publications relating to patents or patent applications filed by the present applicant. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-232623 [Patent Document 2] Special Publication No. 2010-516599 [Patent Document 3] Patent No. 5397794 [Patent Document 4] Patent No. 5343224 [Patent Document 5] Patent No. 5397795 [Patent Document 6] Japanese Patent Application Laid-Open No. 2014-72533 [Patent Document 7] Japanese Patent Application Laid-Open No. 2016-98166 [Patent Document 8] Japanese Patent Application Laid-Open No. 2016-100592 [Patent Document 9] Japanese Patent Application Laid-Open No. 2016-100593 [Patent Document 10] Japanese Patent Application Publication No. 2018-082144 [Non-patent literature]

[0009] [Non-Patent Document 1] Kazuhide Kusakabe., et al., “Overgrowth of GaN layer on GaN nano-columns by RF-molecular beam epitaxy”, Journal of Crystal Growth 237-239 (2002) 988-992 [Non-patent document 2] KY Zang., et al., “Defect reduction by periodic SiNx interlayers in gallium nitride grown on Si (111)”, Journal of Applied Physics 101, 093502 (2007) Summary of the Invention [Problem to be solved by the invention]

[0010] An object of one embodiment of the present invention is to provide a semiconductor device having excellent semiconductor characteristics.An object of another embodiment of the present invention is to provide a method for industrially advantageously forming crystals with reduced dislocations. [Means for solving the problem]

[0011] As a result of intensive research to achieve at least one of the above-mentioned objects, the present inventors have found that, as one embodiment of a semiconductor device, electrical characteristics are anisotropic in relation to the crystal axis of a gallium oxide crystal having a corundum structure and the direction of current flow. They have succeeded in creating a semiconductor device that includes at least a semiconductor layer, a first electrode and a second electrode each disposed on a first surface side of the semiconductor layer, and is configured so that current flows in the semiconductor layer in a first direction from the first electrode to the second electrode, wherein the semiconductor layer has a corundum structure and the direction of the m-axis of the semiconductor layer is parallel to the first direction.

[0012] Furthermore, the present inventors have discovered that, as another embodiment of a semiconductor device, the electrical characteristics are anisotropic in relation to the crystal axis of a gallium oxide crystal having a corundum structure and the direction of current flow, and have succeeded in creating a semiconductor device having at least a semiconductor layer having a corundum structure, a first electrode arranged on a first surface side of the semiconductor layer, and a second electrode arranged on a second surface side opposite to the first surface side, wherein the second electrode is longer in at least a first direction than the first electrode, the first surface is an m-plane, and the first direction is the c-axis direction of the semiconductor layer.

[0013] It has been found that such a semiconductor device has excellent semiconductor properties, particularly electrical properties, and can solve at least one of the above-mentioned problems of the conventional technology.

[0014] Furthermore, the present inventors have discovered a crystal growth method for growing a crystal included in the above-mentioned semiconductor device, which includes growing a crystal having a corundum structure on the c-plane of a crystal substrate for crystal growth having a corundum structure, the crystal substrate having unevenness such that dislocations accompanying the crystal growth extend in the m-axis direction rather than the a-axis direction, and have found that such a crystal growth method can reduce dislocations by utilizing the anisotropy of dislocations.After obtaining this finding, the present inventors further investigated and completed the present invention.Note that the above-mentioned crystal growth method can grow a crystal as a crystalline film and / or a crystalline oxide semiconductor layer (also referred to as a semiconductor layer), which can be used as the semiconductor layer of the semiconductor device of the present invention.

[0015] That is, the present invention relates to the following inventions. [1] A semiconductor device comprising at least a semiconductor layer, a first electrode and a second electrode each disposed on a first surface side of the semiconductor layer, wherein a current flows in the semiconductor layer in a first direction from the first electrode to the second electrode, wherein the semiconductor layer has a corundum structure, and the direction of the m-axis of the semiconductor layer is parallel to the first direction. [2] A semiconductor device having at least a semiconductor layer having a corundum structure, a first electrode arranged on a first surface side of the semiconductor layer, and a second electrode arranged on a second surface side opposite to the first surface side, wherein the first surface is an m-plane, the second electrode is longer than the first electrode in at least a first direction, and the first direction is a c-axis direction of the semiconductor layer. [3] The semiconductor device according to [1] or [2], wherein the semiconductor layer contains a metal oxide containing at least one metal selected from gallium, indium, rhodium, iridium, and aluminum. [4] The semiconductor device according to [1] or [2], wherein the semiconductor layer is mainly composed of a metal oxide containing at least gallium. [5] The carrier concentration of the semiconductor layer is 1×10 19 / cm 3 The semiconductor device according to [1] above, wherein: [6] The semiconductor device according to [1], wherein the first surface is a c-plane. [7] The semiconductor device according to any one of [1] to [6] above, which is a power device. [8] The semiconductor device according to [7] above, which is a power module, an inverter, or a converter. [9] The semiconductor device according to [7] above, which is a power card.

[10] The semiconductor device according to [8], further comprising a cooler and an insulating member, the cooler being provided on both sides of the semiconductor layer with at least the insulating member interposed therebetween.

[11] The semiconductor device according to [9], wherein a heat dissipation layer is provided on each side of the semiconductor layer, and the cooler is provided on the outside of the heat dissipation layer via at least the insulating member.

[12] A semiconductor system including a semiconductor device, wherein the semiconductor device is the semiconductor device according to any one of [1] to

[10] above.

[13] A crystal growth method comprising growing a crystal having a corundum structure on the c-plane of a crystal substrate for crystal growth having a corundum structure, the crystal substrate having unevenness such that dislocations accompanying the crystal growth extend in the m-axis direction rather than the a-axis direction.

[14] A method for growing a crystal having a corundum structure using a crystal substrate for crystal growth, characterized in that the crystal growth surface side of the crystal substrate is provided with uneven portions that move dislocations extending in the m-axis direction of the crystal away from the direction of crystal growth.

[15] The method according to

[13] or

[14] above, wherein the convex portions of the concave-convex portion are a mask containing TiO2.

[16] The method according to

[14] above, wherein the main surface of the crystal substrate on which the uneven portion is provided is a c-plane.

[17] The method according to any one of

[13] to

[16] above, wherein the crystal contains a metal oxide containing at least one metal selected from gallium, indium, rhodium, iridium, and aluminum.

[18] The method according to any one of

[13] to

[17] above, wherein the crystals are mainly composed of a metal oxide containing at least gallium.

[19] The method according to any one of

[13] to

[18] above, wherein the crystal growth is carried out by at least one method selected from the group consisting of CVD, MOCVD, MOVPE, mist CVD, mist epitaxy, MBE, HVPE, pulse growth, and ALD.

[20] The method according to any one of

[13] to

[19] above, wherein the uneven portion includes at least two or more slopes of adjacent m planes. [twenty one] The method according to any one of

[13] to

[20] above, wherein the concave-convex portion includes at least two or more m-plane slopes facing each other. [twenty two] The method according to any one of

[13] to

[21] above, wherein the crystal growth direction includes the c-axis direction, the a-axis direction, and the m-axis direction. [twenty three] The method according to any one of

[13] to

[22] above, wherein the crystalline substrate comprises a c-plane sapphire substrate and gallium oxide disposed on the c-plane sapphire substrate. [twenty four] The method according to any one of

[13] to

[23] above, wherein the convex portions of the concave-convex portion are a mask layer, and the concave portions are a plurality of openings that penetrate the mask layer. [twenty five] The method according to

[24] , wherein the centers of the plurality of openings are located at the vertices of a triangular lattice, and one side of the triangular lattice is arranged parallel to the a-axis direction.

[26] The method according to

[24] , wherein the centers of the plurality of openings are located at the vertices of a triangular lattice, and one side of the triangular lattice is arranged parallel to the m-axis direction.

[27] The method according to any one of

[13] to

[26] above, wherein the crystal is a crystal film. [Effects of the Invention]

[0016] The crystal growth method according to the present invention makes it possible to industrially advantageously form crystals, crystal films, and / or semiconductor layers with reduced dislocations. Furthermore, the semiconductor device according to the present invention has excellent semiconductor properties, particularly excellent electrical properties. [Brief explanation of the drawings]

[0017] [Figure 1] As an example of a film forming apparatus that can be suitably used in an embodiment of the present invention, a schematic configuration diagram of the film forming apparatus is shown. [Figure 2] FIG. 2 shows a schematic configuration diagram of a film forming apparatus (mist CVD) of another embodiment different from that shown in FIG. 1 that is preferably used in an embodiment of the present invention. [Figure 3]FIG. 1 is a diagram schematically illustrating a preferred example of a power supply system. [Figure 4] FIG. 1 is a diagram schematically illustrating a preferred example of a system device. [Figure 5] FIG. 1 is a diagram schematically illustrating a preferred example of a power supply circuit diagram of a power supply device. [Figure 6] FIG. 1 is a diagram schematically illustrating an example of a metal oxide semiconductor field effect transistor (MOSFET) as one aspect of a semiconductor device according to an embodiment of the present invention. [Figure 7] 1 is a schematic partial top view showing one mode of a semiconductor device according to an embodiment of the present invention. [Figure 8] As one aspect of a semiconductor device according to an embodiment of the present invention, a schematic partial cross-sectional view is shown, for example, as an example of the AA cross section in FIG. [Figure 9] 7 is a partial cross-sectional view showing a specific example as one aspect of a semiconductor device in an embodiment of the present invention, and shows a schematic view as an example of a specific cross section taken along line AA in FIG. [Figure 10] FIG. 1 is a diagram schematically illustrating a preferred example of a Schottky barrier diode (SBD) using a rectangular semiconductor layer, showing a longitudinal cross section. [Figure 11] FIG. 1 is a diagram showing a schematic longitudinal cross section of a preferred example of a metal oxide semiconductor field effect transistor (MOSFET) using a rectangular semiconductor layer. [Figure 12] FIG. 1 is a diagram schematically illustrating a preferred example of an insulated gate bipolar transistor (IGBT) using a rectangular semiconductor layer, showing a longitudinal cross section. [Figure 13] FIG. 1 is a diagram schematically illustrating a preferred example of a junction barrier Schottky diode (JBS) using a rectangular semiconductor layer, showing a longitudinal cross section. [Figure 14] FIG. 1 is a diagram schematically illustrating a preferred example of a junction barrier Schottky diode (JBS) using a rectangular semiconductor layer, showing a longitudinal cross section. [Figure 15] FIG. 1 is a diagram schematically illustrating a preferred example of a power card. [Figure 16] FIG. 1 shows the results of Example 1. [Figure 17] FIG. 17 shows an enlarged view of the central part of FIG. [Figure 18] FIG. 1 is a diagram illustrating a halide vapor phase epitaxy (HVPE) apparatus preferably used in an embodiment of the present invention. [Figure 19] 1 is a diagram schematically showing the surface of a concave-convex portion formed on the surface of a substrate that is preferably used in one embodiment of the present invention. [Figure 20] 1 is a schematic diagram showing the surface of a concave-convex portion formed on the surface of a substrate preferably used in one embodiment of the present invention. [Figure 21] 1 is a top perspective view schematically showing the surface of a concave-convex portion formed on the surface of a substrate preferably used in one embodiment of the present invention. [Figure 22] FIG. 22 is an explanatory diagram of the convex portions of the concave-convex portion of the substrate shown in FIG. 21, showing a partial cross-sectional view cut across the concave-convex portion of the substrate. [Figure 23] FIG. 22 is an explanatory diagram of the recesses in the uneven portion of the substrate shown in FIG. 21, showing a partial cross section cut across the uneven portion of the substrate. [Figure 24-a] FIG. 10 is a perspective view schematically showing a substrate and a mask used in Example 2 of the present invention. [Figure 24-b] FIG. 24-a is a plan view showing a schematic diagram illustrating that the centers of a plurality of openings penetrating from the upper surface to the lower surface of the mask are located at the vertices of a triangular lattice. [Figure 24-c] 1 is an AFM (atomic force microscope) image showing the results of Example 2. [Figure 24-d] FIG. 24-c is a schematic explanatory diagram showing the positions of the openings in the mask in plan view by dotted lines in the AFM image shown in FIG. [Figure 25-a] FIG. 10 is a perspective view schematically showing a substrate and a mask used in Example 3 of the present invention. [Figure 25-b] FIG. 25-a is a plan view showing a schematic diagram illustrating that the centers of a plurality of openings penetrating from the upper surface to the lower surface of the mask are located at the vertices of a triangular lattice. [Figure 25-c]1 is an AFM (atomic force microscope) image showing the results of Example 2. [Figure 25-d] FIG. 25-c is a schematic explanatory diagram showing the positions of the openings in the mask in plan view by dotted lines in the AFM image shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0018] A semiconductor device in one embodiment of the present invention has at least a semiconductor layer, a first electrode and a second electrode respectively arranged on a first surface side of the semiconductor layer, and is configured so that a current flows in the semiconductor layer in a first direction from the first electrode to the second electrode, characterized in that the semiconductor layer has a corundum structure and the direction of the m-axis of the semiconductor layer is parallel to the first direction.

[0019] In another embodiment of the present invention, a semiconductor device includes at least a semiconductor layer having a corundum structure, a first electrode arranged on a first surface side of the semiconductor layer, and a second electrode arranged on a second surface side opposite the first surface side, wherein the first surface is an m-plane, the second electrode is longer than the first electrode in at least a first direction, and the first direction is a c-axis direction of the semiconductor layer.

[0020] In an embodiment of the present invention, the semiconductor layer contains a metal oxide containing at least one metal selected from gallium, indium, rhodium, iridium, and aluminum. Furthermore, in an embodiment of the present invention, the semiconductor layer may contain a metal oxide containing at least gallium as a main component, which can provide superior semiconductor characteristics, such as high breakdown voltage. The term "main component" means that the metal oxide accounts for 50% or more, preferably 70% or more, more preferably 90% or more, of the total components in the semiconductor layer, and may be 100% in some embodiments. Preferably, the metal oxide contains at least gallium and further contains indium, rhodium, or iridium. It is also preferred that the metal oxide contains at least gallium and further contains indium and / or aluminum. It is more preferred that the metal oxide contains at least gallium, since this can improve power device characteristics, such as switching characteristics. Furthermore, in an embodiment of the present invention, it is preferred that the first surface is a c-plane, since this can improve electrical characteristics.

[0021] Furthermore, an example of an embodiment of the crystal growth method of the present invention is a crystal growth method comprising growing a crystal having a corundum structure on the c-plane of a crystal substrate for crystal growth having a corundum structure, the crystal substrate having a concave-convex portion formed thereon so that dislocations accompanying the crystal growth extend in the m-axis direction rather than the a-axis direction. Another example of an embodiment of the present invention is a method for growing a crystal having a corundum structure using a crystal substrate for crystal growth, characterized in that the crystal growth surface of the crystal substrate has a concave-convex portion formed thereon to shift dislocations extending in the m-axis direction of the crystal away from the direction of crystal growth. In an embodiment of the present invention, the convex portions of the concave-convex portion are preferably masks. Furthermore, the mask is preferably a mask containing TiO. Furthermore, the main surface of the crystal substrate on which the concave-convex portion is formed is preferably a c-plane. As an example of an embodiment, the crystal preferably contains a metal oxide containing at least one metal selected from gallium, indium, rhodium, chromium, iridium, and aluminum, and more preferably contains a metal oxide containing at least one metal selected from gallium, indium, rhodium, iridium, and aluminum. In an embodiment of the present invention, it is more preferable that the crystal is primarily composed of a metal oxide containing at least gallium. Furthermore, it is preferable that the crystal growth be performed by at least one method selected from the group consisting of CVD, MOCVD, MOVPE, mist CVD, mist epitaxy, MBE, HVPE, pulsed growth, and ALD. As another example of an embodiment of the present invention, it is also preferable that the uneven portion includes at least two adjacent m-plane slopes. In this embodiment, it is preferable that the uneven portion includes at least two opposing m-plane slopes. By growing a crystal having a corundum structure in the crystal growth direction, including the c-axis direction, the a-axis direction, and the m-axis direction, it is possible to easily obtain a crystal with reduced dislocations in the a-axis direction.

[0022] The crystal growth method according to a preferred embodiment of the present invention is advantageous for obtaining crystals with excellent semiconductor properties, and the crystals can be suitably used as semiconductor layers in semiconductor devices.

[0023] The semiconductor layer is preferably a crystalline oxide semiconductor layer and contains a crystalline oxide semiconductor. The crystalline oxide semiconductor contains the metal oxide, and as described above, preferably contains at least gallium, more preferably gallium oxide or a mixed crystal thereof as a main component. The crystalline oxide semiconductor is not particularly limited in terms of crystal structure, but in the present invention, the crystalline oxide semiconductor preferably contains a metal oxide having a corundum structure as a main component. The metal oxide is not particularly limited, but preferably contains at least one or more metals from periods 4 to 6 of the periodic table, more preferably contains at least gallium, indium, rhodium, or iridium, and most preferably contains gallium. In the present invention, the metal oxide also preferably contains gallium and indium and / or aluminum. Examples of the metal oxide containing gallium include α-Ga2O3 or a mixed crystal thereof. A semiconductor layer containing such a preferred metal oxide as a main component can exhibit improved crystallinity and heat dissipation properties, and can also exhibit even better semiconductor properties. For example, when the metal oxide is α-Ga2O3, the atomic ratio of gallium contained in the semiconductor layer may be 50% or more relative to the total metal components in the semiconductor layer. In the present invention, the atomic ratio of gallium in the metal components of the semiconductor layer is preferably 70% or more, more preferably 80% or more, relative to the total metal components in the semiconductor layer. The semiconductor layer may be either single crystal or polycrystalline. The semiconductor layer is usually in the form of a film, but is not particularly limited as long as it does not impede the object of the present invention, and may be in the form of a plate or a sheet.

[0024] The semiconductor layer may contain a dopant. The dopant is not particularly limited as long as it does not impede the object of the present invention. It may be an n-type dopant or a p-type dopant. Examples of the n-dopant include tin, germanium, silicon, titanium, zirconium, vanadium, and niobium. The carrier concentration may be appropriately set, and specifically, for example, about 1×10 16 / cm 3 ~1×10 22 / cm 3 Alternatively, the carrier concentration may be, for example, about 1×10 17 / cm 3 Furthermore, as an example of an embodiment, the carrier concentration of the semiconductor layer may be set to about 1×10 20 / cm 3 Although the above-mentioned high concentration may be contained, in the embodiment of the present invention, a lower carrier concentration in the semiconductor layer makes the anisotropy more effective and improves the semiconductor characteristics. Therefore, for example, 1×10 19 / cm 3 It is preferable to set it to 5×10 or less. 18 / cm 3 It is more preferable to set it to 1×10 or less. 18 / cm 3 Most preferably, the following:

[0025] The semiconductor layer can be obtained by, for example, the following suitable film formation method: For example, a crystal substrate having a second side shorter than a first side is used, and the m-axis direction is defined as a first direction, and the semiconductor layer is formed by epitaxial crystal growth by a mist CVD method or a mist epitaxy method so that a current flows in the first direction from the first electrode to the second electrode, thereby fabricating a semiconductor device.

[0026] <Crystal substrate> The crystal substrate is not particularly limited as long as it does not impede the objectives of the present invention, and may be a known substrate. It may be an insulating substrate, a conductive substrate, or a semiconductor substrate. It may be a single crystal substrate or a polycrystalline substrate. Examples of the crystal substrate include a substrate containing a crystalline material having a corundum structure as a main component. The term "main component" refers to a substrate containing 50% or more of the crystalline material, preferably 70% or more, and more preferably 90% or more, in terms of composition ratio in the substrate. Examples of the crystal substrate having a corundum structure include a sapphire substrate, an α-type gallium oxide substrate, and an α-type mixed crystal substrate containing Ga2O3 and Al2O3, with Al2O3 being more than 0 wt% and 60 wt% or less.

[0027] In the present invention, the crystal substrate is preferably a sapphire substrate. Examples of the sapphire substrate include a c-plane sapphire substrate, an m-plane sapphire substrate, an a-plane sapphire substrate, and an r-plane sapphire substrate. In embodiments of the present invention, a c-plane sapphire substrate or a c-plane α-Ga2O3 substrate is preferably used. The sapphire substrate may have an off-angle. The off-angle is not particularly limited and may be, for example, 0.01° or more, preferably 0.2° or more, and more preferably 0.2° to 12°. The sapphire substrate is also preferably a c-plane sapphire substrate with an off-angle of 0.2° or more. The thickness of the crystal substrate is not particularly limited, but is usually 10 μm to 20 mm, and more preferably 10 to 1000 μm.

[0028] Furthermore, in the present invention, an ELO mask may be used to control the direction of crystal growth, etc., in the semiconductor layer so that the second side is shorter than the first side, the linear thermal expansion coefficient in the first crystal axis direction is smaller than the linear thermal expansion coefficient in the second crystal axis direction, the first side direction is parallel or approximately parallel to the first crystal axis direction, and the second side direction is likely to be parallel or approximately parallel to the second crystal axis direction. Suitable shapes of the crystal substrate include, for example, a triangle, a quadrangle (for example, a rectangle or a trapezoid), a polygonal shape such as a pentagon or a hexagon, a U-shape, an inverted U-shape, an L-shape, or a C-shape.

[0029] In the present invention, other layers such as a buffer layer or a stress relaxation layer may be provided on the crystal substrate. Examples of the buffer layer include a layer made of a metal oxide having the same crystal structure as the crystal substrate or the semiconductor layer. Examples of the stress relaxation layer include an ELO mask layer.

[0030] Preferred embodiments of the crystal substrate that can be suitably used in the present invention will be described below with reference to the drawings. FIG. 19 shows one embodiment of a concave-convex portion formed on the crystal growth surface of a crystal substrate according to the present invention. The concave-convex portion in FIG. 19 is composed of a crystal substrate 401 and a mask layer 404. FIG. 20 shows the surface of the concave-convex portion shown in FIG. 19 as viewed from the zenith direction. As can be seen from FIGS. 19 and 20, the mask layer 404 is formed on the crystal growth surface of the crystal substrate 401 as convex portions 402a, and dot-shaped concave portions 402b represent openings formed in the mask layer. The dot-shaped concave portions 402b in the mask layer 404 are openings through which the crystal substrate 401 is exposed, and the centers of the dot-shaped concave portions 402b are formed to be located at the vertices of a triangular lattice. The dot circles are spaced at regular intervals 400a. The period 400a is not particularly limited, but in the present invention, it is preferably 1 μm to 1 mm, and more preferably 5 μm to 300 μm. Here, the period 400a refers to the distance between the ends of adjacent dot circles. The mask layer 404 can be formed by depositing a material for the mask layer 404 and then processing it into a predetermined shape using known techniques such as photolithography. Examples of materials for the mask layer 404 include oxides, nitrides, or carbides of Si, Ge, Ti, Zr, Hf, Ta, Sn, Al, etc., carbon, diamond, metals, and mixtures thereof. In the present invention, the mask layer 404 preferably contains a transition metal oxide, preferably a Group 4 metal of the periodic table, and most preferably titanium oxide. By using such a preferred material for the mask layer 404, the crystallinity of the crystalline oxide layer can be improved. The method for depositing the mask layer 404 is not particularly limited and may be any known method. Examples of methods for depositing the mask layer 404 include vacuum deposition, CVD, and sputtering. In the present invention, when the mask layer 404 contains titanium oxide, it is preferable to use a sputtering method, since this method can more effectively form a polycrystalline oxide on the mask layer 404. It is more preferable to use a reactive sputtering method, and it is most preferable to use a reactive sputtering method under an O2 gas supply.

[0031] FIG. 21 is a top perspective view schematically illustrating the surface of a concave-convex portion formed on the surface of a substrate used in one embodiment of the crystal growth method of the present invention. FIG. 22 is an explanatory diagram of the convex portions of the concave-convex portion of the substrate shown in FIG. 21 , showing a partial cross-sectional view taken across the concave-convex portion of the substrate. In this embodiment, the substrate 401 may be a sapphire substrate (PSS) having concave-convex portions arranged parallel to each other on the surface 401a of the substrate 401. Unlike the concave-convex portions shown in FIGS. 19 and 20 , in this embodiment, the concave-convex portion may include at least one adjacent slope 405 and / or one facing slope 405, and in this embodiment, the slope 405 is preferably an m-plane. Note that the substrate shown in FIG. 21 has a triangular cross-sectional shape of the convex portions 402a and / or the concave portions 402b with an apex angle of 60°. As shown in Fig. 21, by forming the cross section of the convex portion 402a into a triangular ridge shape, dislocations accompanying crystal growth are extended in the direction perpendicular to the slope 405 (m-axis direction) as shown by arrow B in Fig. 22, thereby preventing dislocations from extending in the crystal growth direction as shown by arrow A. Furthermore, in the concave portion 402b of the uneven portion of the substrate, dislocations accompanying the crystal growth are extended in the direction perpendicular to the slope 405 facing the concave portion 402b (m-axis direction) as shown by arrow B in Fig. 23, bringing the dislocations closer to each other and promoting dislocation annihilation, thereby reducing the dislocation density and dislocation region extending in the a-axis direction. In this way, a wide range of crystals with reduced dislocations can be obtained in the crystal growth direction.

[0032] The epitaxial crystal growth method is not particularly limited and may be any known method as long as it does not impede the object of the present invention. Examples of the epitaxial crystal growth method include CVD, MOCVD, MOVPE, mist CVD, mist epitaxy, MBE, HVPE, pulse growth, and ALD. In the present invention, the epitaxial crystal growth method is preferably mist CVD or mist epitaxy.

[0033] In the mist CVD method or mist epitaxy method, a raw material solution containing a metal is atomized (atomization process), the droplets are suspended, the resulting atomized droplets are transported to the vicinity of the crystal substrate by a carrier gas (transportation process), and then the atomized droplets are thermally reacted (film formation process).

[0034] (Raw material solution) The raw material solution contains a metal as a film-forming raw material, and is not particularly limited as long as it can be atomized, and may contain an inorganic material or an organic material. The metal may be a simple metal or a metal compound, and is not particularly limited as long as it does not impede the object of the present invention. Examples of the metal include gallium (Ga), iridium (Ir), indium (In), rhodium (Rh), aluminum (Al), gold (Au), silver (Ag), platinum (Pt), copper (Cu), iron (Fe), manganese (Mn), nickel (Ni), palladium (Pd), cobalt (Co), ruthenium (Ru), chromium (Cr), molybdenum (Mo), tungsten (Tb), and the like. Examples of suitable metals include one or more metals selected from the group consisting of W, tantalum (Ta), zinc (Zn), lead (Pb), rhenium (Re), titanium (Ti), tin (Sn), magnesium (Mg), calcium (Ca), and zirconium (Zr). In the present invention, the metal preferably includes at least one or more metals from periods 4 to 6 of the periodic table, and more preferably includes at least gallium, indium, rhodium, or iridium. In the present invention, the metal preferably includes gallium and indium and / or aluminum. By using such preferred metals, the semiconductor layer can be formed, which is more suitable for use in semiconductor devices and the like.

[0035] In the present invention, the raw material solution can be suitably prepared by dissolving or dispersing the metal in the form of a complex or salt in an organic solvent or water. Examples of the complex include acetylacetonate complexes, carbonyl complexes, ammine complexes, and hydride complexes. Examples of the salt include organic metal salts (e.g., metal acetates, metal oxalates, and metal citrates), metal sulfides, metal nitrates, metal phosphates, and metal halides (e.g., metal chlorides, metal bromides, and metal iodides).

[0036] The solvent for the raw material solution is not particularly limited as long as it does not impair the object of the present invention, and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. In the present invention, the solvent preferably contains water.

[0037] The raw material solution may also contain additives such as hydrohalic acids and oxidizing agents. Examples of hydrohalic acids include hydrobromic acid, hydrochloric acid, and hydroiodic acid. Examples of oxidizing agents include peroxides such as hydrogen peroxide (HO), sodium peroxide (NaO), barium peroxide (BaO), and benzoyl peroxide (CHCO)O, as well as hypochlorous acid (HClO), perchloric acid, nitric acid, ozone water, and organic peroxides such as peracetic acid and nitrobenzene.

[0038] The raw material solution may contain a dopant. The dopant is not particularly limited as long as it does not impede the object of the present invention. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium, or p-type dopants. The dopant concentration is usually about 1×10 16 / cm 3 ~1×10 22 / cm 3 Alternatively, the dopant concentration may be, for example, about 1×10 17 / cm 3 Furthermore, according to the present invention, the dopant may be present in a concentration as low as about 1×1020 / cm 3 It may be contained in a concentration higher than this.

[0039] (Atomization process) The atomization step involves preparing a raw material solution containing a metal, atomizing the raw material solution, suspending the droplets, and generating atomized droplets. The blending ratio of the metal is not particularly limited, but is preferably 0.0001 mol / L to 20 mol / L relative to the total raw material solution. The atomization means is not particularly limited as long as it can atomize the raw material solution, and may be any known atomization means. However, in the present invention, an atomization means using ultrasonic vibration is preferred. The mist used in the present invention is airborne, and is preferably a mist that floats in space with an initial velocity of zero and can be transported as a gas, rather than being sprayed like a spray. The droplet size of the mist is not particularly limited, and may be droplets of about several mm, but is preferably 50 μm or less, more preferably 1 to 10 μm.

[0040] (Transportation process) In the transport step, the atomized droplets are transported to the substrate by the carrier gas. The type of carrier gas is not particularly limited as long as it does not impede the object of the present invention, and suitable examples include oxygen, ozone, an inert gas (e.g., nitrogen, argon, etc.), or a reducing gas (e.g., hydrogen gas, forming gas, etc.). The type of carrier gas may be one type, or two or more types. A dilution gas with a different carrier gas concentration (e.g., a 10-fold dilution gas, etc.) may also be used as a second carrier gas. The number of carrier gas supply locations may be one or more. The flow rate of the carrier gas is not particularly limited, but is preferably 1 LPM or less, and more preferably 0.1 to 1 LPM.

[0041] (Film forming process) In the film-forming step, the atomized droplets are reacted to form a film on the crystal substrate. The reaction is not particularly limited as long as it forms a film from the atomized droplets, but a thermal reaction is preferred in the present invention. The thermal reaction may be any reaction that heats the atomized droplets to react, and the reaction conditions are not particularly limited as long as they do not impede the objectives of the present invention. In this step, the thermal reaction is typically carried out at a temperature equal to or higher than the evaporation temperature of the solvent in the raw material solution, but is preferably not too high, more preferably 650°C or lower. The thermal reaction may be carried out under any of the following conditions: vacuum, oxygen-free, reducing gas, and oxygen, as long as it does not impede the objectives of the present invention. Furthermore, the thermal reaction may be carried out under any of the following conditions: atmospheric pressure, pressurized, and reduced pressure. However, in the present invention, atmospheric pressure is preferred because it simplifies the calculation of the evaporation temperature and simplifies the equipment. The film thickness can be set by adjusting the film-forming time.

[0042] A film formation apparatus 19 suitable for use in the present invention will be described below with reference to the drawings. The film formation apparatus 19 shown in Fig. 1 includes a carrier gas source 22a for supplying a carrier gas, a flow rate control valve 23a for adjusting the flow rate of the carrier gas delivered from the carrier gas source 22a, a carrier gas (dilution) source 22b for supplying a carrier gas (dilution), a flow rate control valve 23b for adjusting the flow rate of the carrier gas (dilution) delivered from the carrier gas (dilution) source 22b, a mist generation source 24 for containing a raw material solution 24a, a container 25 for containing water 25a, an ultrasonic vibrator 26 attached to the bottom of the container 25, a film formation chamber 30, a quartz supply pipe 27 connecting the mist generation source 24 to the film formation chamber 30, and a hot plate (heater) 28 installed in the film formation chamber 30. A substrate 20 is placed on the hot plate 28.

[0043] As shown in FIG. 1, the raw material solution 24a is placed in the mist source 24. Next, the substrate 20 is placed on the hot plate 28, and the hot plate 28 is operated to raise the temperature inside the film formation chamber 30. Next, the flow rate control valves 23 (23a, 23b) are opened to supply carrier gas from the carrier gas source 22 (22a, 22b) into the film formation chamber 30. After the atmosphere in the film formation chamber 30 is sufficiently replaced with the carrier gas, the flow rates of the carrier gas and the carrier gas (dilution) are adjusted. Next, the ultrasonic vibrator 26 is vibrated, and the vibrations are propagated to the raw material solution 24a through the water 25a, thereby atomizing the raw material solution 24a and generating atomized droplets 24b. The atomized droplets 24b are introduced into the film-forming chamber 30 by the carrier gas and transported to the substrate 20, and then, under atmospheric pressure, the atomized droplets 24b undergo a thermal reaction in the film-forming chamber 30 to form a film (semiconductor layer) on the substrate 20.

[0044] It is also preferable to use a mist CVD apparatus 19 as the film formation apparatus shown in Fig. 2. The mist CVD apparatus 19 in Fig. 2 includes a susceptor 21 on which a substrate 20 is placed, a carrier gas supply means 22a for supplying a carrier gas, a flow rate control valve 23a for adjusting the flow rate of the carrier gas delivered from the carrier gas supply means 22a, a carrier gas (dilution) supply means 22b for supplying a carrier gas (dilution), a flow rate control valve 23b for adjusting the flow rate of the carrier gas delivered from the carrier gas (dilution) supply means 22b, a mist generating source 24 that contains a raw material solution 24a, a container 25 that contains water 25a, an ultrasonic vibrator 26 attached to the bottom of the container 25, a supply pipe 27 made of a quartz tube with an inner diameter of 40 mm, a heater 28 installed around the supply pipe 27, and an exhaust port 29 for discharging mist, droplets, and exhaust gas after the thermal reaction. The susceptor 21 is made of quartz, and the surface on which the substrate 20 is placed is inclined from the horizontal. By making both the supply pipe 27, which serves as the film formation chamber, and the susceptor 21 out of quartz, impurities originating from the apparatus are prevented from being mixed into the film formed on the substrate 20. This mist CVD apparatus 19 can be used in the same manner as the above-mentioned film formation apparatus 19.

[0045] By using the above-described suitable film-forming apparatus, the semiconductor layer can be more easily formed on the crystal growth surface of the crystal substrate. The semiconductor layer is usually formed by epitaxial crystal growth.

[0046] The semiconductor layer is useful for semiconductor devices, particularly power devices. Examples of semiconductor devices formed using the semiconductor layer include transistors such as MIS and HEMT, TFTs, Schottky barrier diodes using semiconductor-metal junctions, JBS, PN or PIN diodes combined with other P layers, and light-emitting / receiving elements. In the present invention, the crystalline oxide semiconductor is grown to form a semiconductor layer, which can be peeled off from the crystalline substrate as desired and used as a semiconductor layer (film) in a semiconductor device. The semiconductor layer can also be disposed on a substrate with higher thermal conductivity than the crystalline substrate.

[0047] The semiconductor device is preferably used as a lateral element (lateral device) in which an electrode is formed on one side of a semiconductor layer. Suitable examples of the semiconductor device include a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), a metal semiconductor field effect transistor (MESFET), a high electron mobility transistor (HEMT), a metal oxide semiconductor field effect transistor (MOSFET), a static induction transistor (SIT), a junction field effect transistor (JFET), an insulated gate bipolar transistor (IGBT), and a light emitting diode (LED).

[0048] Hereinafter, preferred examples of the semiconductor device in the case where the semiconductor layer in the embodiment of the present invention is applied to an n-type semiconductor layer (an n+ type semiconductor layer, an n- type semiconductor layer, etc.) will be described with reference to the drawings, but the present invention is not limited to these examples.

[0049] FIG. 6 shows an example of a semiconductor device according to an embodiment of the present invention, in which the semiconductor device is a lateral MOSFET. A semiconductor device 100 according to an embodiment of the present invention includes at least one semiconductor layer (e.g., 131a) and a first electrode (e.g., 135b) and a second electrode (e.g., 135c) disposed on a first surface 100a of the semiconductor device 100, i.e., on the first surface side of the semiconductor layer. The semiconductor layer is configured so that a current flows in a first direction from the first electrode to the second electrode. The semiconductor layer has a corundum structure, and the direction of the m-axis of the semiconductor layer is parallel to the first direction. Here, "the m-axis direction of the semiconductor layer is parallel to the first direction" means that the first direction from the first electrode to the second electrode is parallel to the m-axis direction of the semiconductor layer, and also includes directions within an angle range of 5° or less with respect to the m-axis direction. Furthermore, since the direction of current flow from the first electrode 135b to the second electrode 135c can be made parallel to the m-axis direction, a semiconductor device can be obtained in which current flow is less likely to be impeded even when dislocations extending in the m-axis direction are present. In an embodiment of the present invention, the first surface of the semiconductor layer is preferably a c-plane. This preferred embodiment improves the electrical characteristics of the semiconductor device 100. Specifically, the MOSFET of FIG. 6 includes an n-type semiconductor layer 131a, a first n+-type semiconductor layer 131b, a second n+-type semiconductor layer 131c, a gate insulating film 134, a gate electrode 135a, a source electrode 135b, a drain electrode 135c, a buffer layer 138, and a semi-insulating layer 139. For example, by burying the n+-type semiconductor layer in the n-type semiconductor layer, as shown in FIG. 6, current can flow more efficiently than in other lateral MOSFETs.

[0050] The electrode material may be a known electrode material, and examples of the electrode material include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, rhenium oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole; and mixtures and laminates thereof.

[0051] The electrode can be formed by known means such as vacuum deposition or sputtering. More specifically, for example, when forming an electrode using two types of metals, a first metal and a second metal, the electrode can be formed by stacking a layer made of the first metal and a layer made of the second metal, and then patterning the layer made of the first metal and the layer made of the second metal using a photolithography technique.

[0052] FIG. 7 shows a schematic partial top view to explain the main parts of an example of a semiconductor device in an embodiment of the present invention, but the number, shape, and arrangement of electrodes of the semiconductor device can be selected as appropriate.

[0053] FIG. 8 is a partial cross-sectional view illustrating a main portion of an example of a semiconductor device according to an embodiment of the present invention, showing, for example, the cross section AA of FIG. 7. A semiconductor device 200 according to an embodiment of the present invention includes at least one semiconductor layer (e.g., 2) and a first electrode (e.g., 5b) and a second electrode (e.g., 5c) disposed on a first surface 200a of the semiconductor device 200, i.e., on the first surface side of the semiconductor layer 2. The semiconductor layer is configured so that a current flows in a first direction from the first electrode to the second electrode. The semiconductor layer has a corundum structure, and the direction of the m-axis of the semiconductor layer is the first direction. In an embodiment of the present invention, the first surface of the semiconductor layer is preferably a c-plane. This preferred embodiment improves the electrical characteristics of the semiconductor device. The semiconductor device 200 includes, as the semiconductor layer 2, an oxide semiconductor film including a crystal containing at least gallium oxide. The semiconductor layer 2 includes an inversion channel region 2a. The crystal may contain gallium oxide as a main component and may be a mixed crystal. The semiconductor device 200 has an oxide film 2b at a position in contact with the inversion channel region 2a.

[0054] FIG. 9 is a schematic cross-sectional view illustrating a specific example of a semiconductor device according to an embodiment of the present invention, showing, for example, an example of a specific cross section taken along line AA in FIG. 7. A semiconductor device 300 according to an embodiment of the present invention includes at least one semiconductor layer (e.g., 2), a first electrode (e.g., 5b) and a second electrode (e.g., 5c), each disposed on a first surface side of the semiconductor layer 2. The semiconductor layer is configured so that a current flows in a first direction from the first electrode to the second electrode. The semiconductor layer has a corundum structure, and the direction of the m-axis of the semiconductor layer is parallel to the first direction. In an embodiment of the present invention, the first surface of the semiconductor layer is preferably a c-plane. According to this preferred embodiment, the electrical characteristics of the semiconductor device can be improved. The semiconductor device 300 has a semiconductor layer 2 made of an oxide semiconductor film including crystals containing at least gallium oxide, and the semiconductor layer 2 includes an inversion channel region 2a. The crystals have a corundum structure. The semiconductor device 300 also has a first semiconductor region 1a and a second semiconductor region 1b. In this embodiment, as shown in FIG. 9, the inversion channel region 2a is located between the first semiconductor region 1a and the second semiconductor region 1b in a planar view. When a voltage is applied to the semiconductor device 300, the inversion channel region of the semiconductor layer 2 is inverted, thereby causing current to flow between the first semiconductor region 1a and the second semiconductor region 1b. In this embodiment, the first semiconductor region 1a and the second semiconductor region 1b are located within the semiconductor layer 2, and are arranged within the semiconductor layer 2 so that the top surfaces of the first semiconductor region 1a, the second semiconductor region 1b, and the inversion channel region 2a are flush with each other. On the first surface side 300a of the semiconductor device 300, i.e., the first surface side (top surface side in the figure) of the semiconductor layer 2, the semiconductor layer 2, which is an oxide semiconductor film including a first semiconductor region 1a and an inversion channel region 2a, and the second semiconductor region 1b, form a flat surface. This facilitates design, including the arrangement of electrodes, and also leads to a thinner semiconductor device. As described below, the case where the semiconductor layer 2 includes an oxide semiconductor film having an oxide film 2b in contact with the inversion channel region 2a2 is included in the case where the first semiconductor region 1a, the oxide semiconductor film including the inversion channel region 2a, and the second semiconductor region 1b form a flat surface. The first semiconductor region 1a and the second semiconductor region 1b may be embedded in the semiconductor layer 2 or may be disposed within the semiconductor layer 2 by ion implantation. In this embodiment, the semiconductor layer 2 is a p-type semiconductor film, and the first semiconductor region 1a and the second semiconductor region 1b are n-type. The semiconductor layer 2 may contain a p-type dopant. Furthermore, the semiconductor device 300 may have an oxide film 2b disposed on the inversion channel region 2a. In an embodiment of the present invention, the oxide film 2b preferably has a crystal structure belonging to the trigonal system to which the corundum structure belongs. The oxide film 2b contains at least one element of Group 15 of the periodic table, and preferably contains phosphorus.In another embodiment, the oxide film 2b may further contain at least one element from Group 13 of the periodic table, and the semiconductor device 300 has a first electrode 5b electrically connected to the first semiconductor region 1a and a second electrode 5c electrically connected to the second semiconductor region 1b. The semiconductor device 300 further has a third electrode 5a between the first electrode 5b and the second electrode 5c, separated from the inversion channel region 2a by an insulating film 4a. As shown in the drawing, the first electrode 5b, the second electrode 5c, and the third electrode 5a are disposed on the first surface 300a of the semiconductor device 300, i.e., on the first surface side of the semiconductor layer 2. Specifically, the semiconductor device 300 has an insulating film 4a disposed on the oxide film 2b above the inversion channel region 2a, and the third electrode 5a is disposed on the insulating film 4a. In the semiconductor device 300, the first electrode 5b and the first semiconductor region 1a are electrically connected, but an insulating film 4b may be provided partially between the first electrode 5b and the first semiconductor region 1a. The second electrode 5c and the second semiconductor region 1b are electrically connected, but an insulating film 4b may be provided partially between the second electrode 5c and the second semiconductor region 1b. The semiconductor device 300 may further include another layer on the second surface 300b of the semiconductor device 300, i.e., the second surface side (the lower surface side in the figure) of the semiconductor layer 2, and may include a substrate 9 as shown in FIG. 9. As shown in FIG. 7, the first semiconductor region 1a has a portion overlapping the first electrode 5b and a portion overlapping the third electrode 5a in a plan view. The second semiconductor region 1b has a portion overlapping the second electrode 5c and a portion overlapping the third electrode 5a in a plan view. In this embodiment, when a positive voltage is applied to the third electrode 5a relative to the first electrode 5b, the inversion channel region 2a of the semiconductor layer 2 is inverted from p-type to n-type, forming an n-type channel layer, establishing electrical continuity between the first semiconductor region 1a and the second semiconductor region 1b, and electrons flow from the source electrode to the drain electrode. Furthermore, by setting the voltage of the third electrode 5a to zero, no channel layer is formed in the inversion channel region 2a, resulting in turn-off.In this embodiment, for example, the first electrode 5b may be a source electrode, the second electrode 5c may be a drain electrode, and the third electrode 5a may be a gate electrode. In this case, the insulating film 4a is a gate insulating film, and the insulating film 4b is a field insulating film.

[0055] FIG. 10 illustrates an example of a Schottky barrier diode (SBD) as a semiconductor device 120 according to an embodiment of the present invention. The semiconductor device 120 includes a first electrode 125a disposed on a first surface 120a of a semiconductor layer 121 and a second electrode 125b disposed on a second surface 120b opposite the first surface 120a. In this embodiment, the semiconductor layer 121 includes an n-type semiconductor layer as the first semiconductor layer 121a and an n+-type semiconductor layer as the second semiconductor layer 121b disposed in contact with the first semiconductor layer 121a. The first electrode 121a disposed on the first semiconductor layer 121a is a Schottky electrode 125a. The second electrode disposed on the second semiconductor layer 121b is an ohmic electrode 125b. In this embodiment, the first surface is an m-plane, the second electrode is longer than the first electrode in at least a first direction, and the first direction is the c-axis direction of the semiconductor layer. Furthermore, since the direction of current flow from the first electrode 121a to the second electrode 125b can be made parallel to the m-axis direction, a semiconductor device can be obtained in which the flow of current is less likely to be obstructed even when dislocations extending in the m-axis direction are present.

[0056] The materials for the Schottky electrode and the ohmic electrode may be known electrode materials, and examples of the electrode materials include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, rhenium oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole; and mixtures and laminates thereof.

[0057] The Schottky electrode and the ohmic electrode can be formed by known means such as vacuum deposition or sputtering. More specifically, when forming a Schottky electrode using two types of metals, a first metal and a second metal, the Schottky electrode can be formed by stacking a layer made of the first metal and a layer made of the second metal, and then patterning the layer made of the first metal and the layer made of the second metal using a photolithography technique.

[0058] 10, a depletion layer (not shown) expands into the n-type semiconductor layer 121a, resulting in a high breakdown voltage SBD. Furthermore, when a forward bias is applied, electrons flow from the ohmic electrode 125b to the Schottky electrode 125a. Thus, an SBD using this semiconductor structure is excellent for high breakdown voltage and large current applications, has fast switching speed, and excels in breakdown voltage and reliability.

[0059] (MOSFET) FIG. 11 shows a MOSFET as a semiconductor device 140 according to an embodiment of the present invention. The semiconductor device 140 has a second electrode 145c arranged on a second surface 140b opposite to a first surface 140a of a semiconductor layer (also referred to as a semiconductor film) 141. The MOSFET in FIG. 11 is a trench MOSFET. In this embodiment, the semiconductor layer 141 has multiple stacked layers. The semiconductor device 140 has a source electrode as the first electrode 145b, a drain electrode as the second electrode 145c, and a gate electrode as the third electrode 145a.

[0060] 11, an n+ type semiconductor layer 141b having a thickness of, for example, 100 nm to 100 μm is formed on the drain electrode 145c, and an n- type semiconductor layer 141a having a thickness of, for example, 100 nm to 100 μm is formed on the n+ type semiconductor layer 141b. Furthermore, an n+ type semiconductor layer 141c is formed on the n- type semiconductor layer 141a, and a source electrode 145b is formed on the n+ type semiconductor layer 141c.

[0061] The semiconductor layer 141 has at least one trench 143, and the depth direction of the at least one trench 143 is parallel to the m-axis of the semiconductor layer. In an embodiment of the present invention, the semiconductor layer 141 has a plurality of semiconductor layers, and a plurality of the trenches 143 are arranged. The semiconductor layer 141 has the n-type semiconductor layer as a first semiconductor layer 141a, the n+ type semiconductor layer as a second semiconductor layer 141b arranged in contact with the second surface side of the first semiconductor layer 141a, and the n+ type semiconductor layer as a third semiconductor layer 141c arranged in contact with the first surface of the first semiconductor layer 141a. In this embodiment, the trenches 143 penetrate the third semiconductor layer (n+ semiconductor layer) 141c, and a plurality of trenches 143 are formed to a depth that reaches partway through the first semiconductor layer (n-type semiconductor layer) 141a. A gate electrode 145a is buried in the trench 143 via a gate insulating film 144 having a thickness of, for example, 10 nm to 1 μm.

[0062] 11, when a voltage is applied between the source electrode 145b and the drain electrode 145c and a positive voltage with respect to the source electrode 145b is applied to the gate electrode 145a, a channel layer is formed on the side surface of the n-type semiconductor layer 141a, electrons are injected into the n-type semiconductor layer 141a, and the MOSFET is turned on. When the voltage of the gate electrode is set to 0V, no channel layer is formed, and the n-type semiconductor layer 141a becomes filled with a depletion layer, resulting in the MOSFET being turned off.

[0063] (IGBT) FIG. 12 shows a preferred example of an insulated gate bipolar transistor (IGBT) as a semiconductor device 150 according to an embodiment of the present invention. The semiconductor device 150 includes a semiconductor layer 153 (also referred to as a semiconductor film). The semiconductor device 150 includes a first electrode 155b and a third electrode 155a disposed on a first surface 150a of the semiconductor layer (also referred to as a semiconductor film) 153, and a second electrode 155c disposed on a second surface 150b opposite the first surface 150a. The semiconductor layer 153 includes at least one trench 156, and the depth direction of the at least one trench 156 is parallel to the m-axis of the semiconductor layer. In an embodiment of the present invention, the semiconductor layer 153 includes multiple semiconductor layers, and multiple trenches 156 are disposed. The first semiconductor layer 151a is an n-type semiconductor layer, and a trench 156 is arranged having a depth extending from the first surface side of the first semiconductor layer (in this embodiment, an n-type semiconductor layer) 151a to the middle of the second surface side, a p-type semiconductor region 152a is arranged in the trench 156, and an n+ type semiconductor region 151b is arranged in the p-type semiconductor region 152a. The semiconductor device 150 further includes, on the second surface side of the first semiconductor layer 151a, a second semiconductor layer 151 (in this embodiment, an n-type semiconductor layer 151) arranged in contact with the first semiconductor layer 151a, and a third semiconductor layer 152b (in this embodiment, a p-type semiconductor layer) arranged in contact with the second surface of the second semiconductor layer 151. In this embodiment, a gate insulating film 154 is arranged on the first surface side 150a of the semiconductor layer 153, a gate electrode 155a is arranged on the gate insulating film 154, and the first surface side 150a of the semiconductor layer 153 has an emitter electrode 155b arranged on the p-type semiconductor region 152 and a collector electrode as a second electrode 155c arranged in contact with the p-type semiconductor layer 152b located on the second surface side 150b of the semiconductor layer 153.

[0064] FIG. 13 shows a junction barrier Schottky diode (JBS) as a semiconductor device 160 according to an embodiment of the present invention. The semiconductor device 160 includes a semiconductor layer 163 (also referred to as a semiconductor film). The semiconductor device 160 includes a first electrode 162 disposed on a first surface 160a of the semiconductor layer 163 and a second electrode 164 disposed on a second surface 160b of the semiconductor layer 163 opposite the first surface 160a. The semiconductor layer 163 includes at least one trench 166, and the depth direction of the at least one trench 166 is parallel to the m-axis of the semiconductor layer. In an embodiment of the present invention, the semiconductor layer 163 may include multiple semiconductor layers. Furthermore, multiple trenches 166 may be disposed. 13 , which is one preferred embodiment of the present invention, includes a semiconductor layer 163, a barrier electrode 162 provided on the semiconductor layer 163 and capable of forming a Schottky barrier between the barrier electrode 162 (first electrode) and the semiconductor layer 163, and a barrier height adjusting region 161 provided between the barrier electrode 162 (first electrode) and the semiconductor layer 163 and capable of forming a Schottky barrier between the barrier electrode 162 and the semiconductor layer 163, the barrier height adjusting region 161 having a barrier height greater than that of the Schottky barrier of the barrier electrode 162. The barrier height adjusting region 161 is embedded in a trench 166 formed in the semiconductor layer 163. In this embodiment, the barrier height adjusting regions 161 are preferably provided at regular intervals, and more preferably, the barrier height adjusting regions 161 are provided between both ends of the barrier electrode 162 and the semiconductor layer 163. This preferred embodiment provides a JBS with superior thermal stability and adhesion, reduced leakage current, and superior semiconductor properties such as breakdown voltage. The semiconductor device of FIG. 13 includes an ohmic electrode 164 (second electrode) disposed on the semiconductor layer 163.

[0065] 13 may be formed by any known method as long as it does not impede the object of the present invention, such as forming a film by vacuum deposition, CVD, sputtering, or various coating techniques, followed by patterning by photolithography, or directly patterning by printing technology.

[0066] FIG. 14 illustrates a junction barrier Schottky diode (JBS) as a semiconductor device 167 according to an embodiment of the present invention. The semiconductor device 167 includes a semiconductor layer 163 (also referred to as a semiconductor film). The semiconductor device 167 includes a first electrode 162 disposed on a first surface 160a of the semiconductor layer 163 and a second electrode 164 disposed on a second surface 160b of the semiconductor layer 163 opposite the first surface 160a. The semiconductor layer 163 includes at least one trench 161, and the depth direction of the at least one trench 161 is parallel to the m-axis of the semiconductor layer 163. In an embodiment of the present invention, the semiconductor layer 163 may include multiple semiconductor layers. Alternatively, multiple trenches 161 may be disposed. The semiconductor device of FIG. 14 differs from the semiconductor device of FIG. 13 in that a guard ring 165 is provided around the outer periphery of the barrier electrode. This configuration allows for a semiconductor device with superior semiconductor characteristics, such as breakdown voltage. In the present invention, the breakdown voltage can be improved more effectively by burying a portion of the guard ring 165 in the first surface of the semiconductor layer 163. Furthermore, by using a metal with a high barrier height for the guard ring, the guard ring can be provided industrially advantageously together with the formation of the barrier electrode, and can be formed without significantly affecting the semiconductor region or deteriorating the on-resistance.

[0067] The guard rings are typically made of a material with a high barrier height. Examples of materials used for the guard rings include conductive materials with a barrier height of 1 eV or more, which may be the same as the electrode material. In the present invention, the material used for the guard rings is preferably a metal, as this provides a high degree of freedom in designing the voltage-resistant structure, allows for the provision of multiple guard rings, and flexibly improves the voltage resistance. The shape of the guard rings is not particularly limited, and examples include a square shape, a circle, a U-shape, an L-shape, and a strip shape. The number of guard rings is also not particularly limited, but is preferably three or more, more preferably six or more.

[0068] An oxide semiconductor film containing crystals containing gallium oxide and / or an oxide semiconductor film containing crystals having a corundum structure can be obtained by epitaxial crystal growth. The epitaxial crystal growth method is not particularly limited and may be any known method as long as it does not impede the objectives of the present invention. Examples of the epitaxial crystal growth method include CVD, MOCVD (Metal Organic Chemical Vapor), MOVPE (Metal Organic Vapor-phase epitaxy), mist CVD, mist epitaxy, MBE (Molecular Beam Epitaxy), HVPE (Hydride Vapor Phase Epitaxy), and pulse growth. In an embodiment of the present invention, when forming an oxide semiconductor film by epitaxial crystal growth, it is preferable to use mist CVD or mist epitaxy.

[0069] Examples of materials for the first electrode, second electrode, and / or third electrode include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, rhenium oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole; and mixtures thereof. The method for forming the electrodes is not particularly limited, and they can be formed on the substrate by a method appropriately selected from wet methods such as printing, spraying, and coating; physical methods such as vacuum deposition, sputtering, and ion plating; and chemical methods such as CVD and plasma CVD, taking into consideration their suitability for the materials.

[0070] In addition to the above features, the semiconductor device according to the embodiment of the present invention can be suitably used as a power module, inverter, or converter using a known method, and further suitably used in, for example, a semiconductor system using a power supply device. The power supply device can be fabricated from or as the semiconductor device by connecting to a wiring pattern or the like using a conventional method. FIG. 3 shows a power supply system 170 configured using multiple power supply devices 171, 172 and a control circuit 173. As shown in FIG. 4, the power supply system can be used in a system device 180 by combining an electronic circuit 181 and a power supply system 182. FIG. 5 shows an example of a power supply circuit diagram for a power supply device. FIG. 5 shows the power supply circuit of the power supply device, which is composed of a power circuit and a control circuit. DC voltage is switched at high frequency by an inverter 192 (comprising MOSFETs A to D) to convert it to AC, which is then insulated and transformed by a transformer 193. The rectifier MOSFET 194 rectifies the voltage, smooths it using a DCL 195 (smoothing coils L1, L2) and a capacitor, and outputs a DC voltage. At this time, a voltage comparator 197 compares the output voltage with a reference voltage, and a PWM control circuit 196 controls the inverter 192 and rectifying MOSFET 194 so as to obtain a desired output voltage.

[0071] In the present invention, the semiconductor device is preferably a power card, including a cooler and an insulating member. More preferably, the cooler is provided on both sides of the semiconductor layer, with at least the insulating member interposed between the cooler and the semiconductor layer. Most preferably, a heat dissipation layer is provided on both sides of the semiconductor layer, with the cooler provided on the outside of the heat dissipation layer, with at least the insulating member interposed between the cooler and the semiconductor layer. Figure 15 shows a power card according to a preferred embodiment of the present invention. The power card shown in Figure 15 is a double-sided cooled power card 201, and includes a refrigerant tube 202, a spacer 203, an insulating plate (insulating spacer) 208, a sealing resin portion 209, a semiconductor chip 301a, a metal heat transfer plate (protruding terminal portion) 302b, a heat sink and electrode 303, a metal heat transfer plate (protruding terminal portion) 303b, a solder layer 304, a control electrode terminal 305, and a bonding wire 308. The thickness-direction cross section of the refrigerant tube 202 has a number of flow paths 222 separated by a number of partition walls 221 extending in the flow path direction at predetermined intervals. Such a suitable power card can achieve higher heat dissipation and satisfy higher reliability.

[0072] The semiconductor chip 301a is bonded to the inner main surface of the metal heat transfer plate 302b with a solder layer 104, and the metal heat transfer plate (protruding terminal portion) 302b is bonded to the remaining main surface of the semiconductor chip 301a with a solder layer 304, thereby connecting the collector electrode surface and emitter electrode surface of the IGBT with the anode electrode surface and cathode electrode surface of the flywheel diode in a so-called anti-parallel configuration. Examples of materials for the metal heat transfer plates (protruding terminal portions) 302b and 303b include Mo or W. The metal heat transfer plates (protruding terminal portions) 302b and 303b have a thickness difference that compensates for the difference in thickness between the semiconductor chips 101a and 101b, thereby making the outer surface of the metal heat transfer plate 102 flat.

[0073] Resin sealing portion 209 is made of, for example, epoxy resin and is molded to cover the side surfaces of metal heat transfer plates 302b and 303b, and semiconductor chip 301a is molded in resin sealing portion 209. However, the outer main surfaces, i.e., the contact heat-receiving surfaces, of metal heat transfer plates 302b and 303b are completely exposed. Metal heat transfer plates (protruding terminal portions) 302b and 303b protrude from resin sealing portion 209 to the right in Fig. 15, and control electrode terminal 305, which is a so-called lead frame terminal, connects the gate (control) electrode surface of semiconductor chip 301a on which, for example, an IGBT is formed, to control electrode terminal 305.

[0074] The insulating spacer, insulating plate 208, is made of, for example, aluminum nitride film, but may be made of other insulating films. Insulating plate 208 completely covers and adheres to metal heat transfer plates 302b and 303b. However, insulating plate 208 and metal heat transfer plates 302b and 303b may simply be in contact with each other, or may be coated with a good heat transfer material such as silicone grease, or may be joined by various methods. Alternatively, an insulating layer may be formed by ceramic spraying, or insulating plate 208 may be joined to the metal heat transfer plate, or may be joined or formed on the refrigerant tube.

[0075] The refrigerant tubes 202 are fabricated by cutting aluminum alloy plates formed by pultrusion or extrusion to the required length. The cross section of the refrigerant tubes 202 in the thickness direction has numerous flow paths 222 separated by numerous partition walls 221 extending at predetermined intervals in the flow path direction. The spacers 203 may be soft metal plates such as solder alloys, or may be films formed by coating on the contact surfaces of the metal heat transfer plates 302b and 303b. The surface of this soft spacer 3 easily deforms to conform to the minute irregularities and warping of the insulating plate 208 and the refrigerant tubes 202, thereby reducing thermal resistance. The surfaces of the spacers 203 may be coated with a known high-thermal-conductivity grease, or the spacers 203 may be omitted.

[0076] Example 1 1. Formation of ELO mask A sapphire substrate (c-plane, off-angle 0.25°) with an α-GaO layer formed on its surface was used as the substrate. A titanium oxide mask layer was formed on the substrate by sputtering, and then the formed mask layer was processed into a mask of a predetermined shape by photolithography. Specifically, a titanium oxide (TiO) mask layer (50 nm thick) was formed by sputtering while flowing O and Ar gases. Furthermore, multiple openings (dot-shaped openings) (diameter: 3 μm) were formed by photolithography. The multiple openings were processed so that the distance from the center of each opening to the center of the nearest opening was 25 μm, and the centers of the openings were arranged on the substrate so that they were located at the vertices of a triangular lattice (in this example, an equilateral triangular lattice).

[0077] 2. Crystal formation 2-1.HVPE equipment The halide vapor phase epitaxy (HVPE) apparatus 50 used in this example will be described with reference to FIG. 18. The HVPE apparatus 50 includes a reaction chamber 51, a heater 52a for heating a metal source 57, and a heater 52b for heating a substrate fixed to a substrate holder 56. The reaction chamber 51 also includes an oxygen-containing source gas supply pipe 55b, a reactive gas supply pipe 54b, and a substrate holder 56 for placing a substrate thereon. The reactive gas supply pipe 54b includes a metal-containing source gas (metal halide gas) supply pipe 53b, forming a double-pipe structure. The oxygen-containing source gas supply pipe 55b is connected to an oxygen-containing source gas supply source 55a, forming an oxygen-containing source gas flow path so that the oxygen-containing source gas can be supplied from the oxygen-containing source gas supply source 55a through the oxygen-containing source gas supply pipe 55b to the substrate fixed to the substrate holder 56. Furthermore, reactive gas supply pipe 54b is connected to reactive gas supply source 54a, and forms a reactive gas flow path so that reactive gas can be supplied from reactive gas supply source 54a via reactive gas supply pipe 54b to a substrate fixed to substrate holder 56. Metal-containing source gas supply pipe 53b is connected to halogen-containing source gas supply source 53a, and the halogen-containing source gas is supplied to the metal source to become a metal-containing source gas, which is then supplied to the substrate fixed to substrate holder 56. Reaction chamber 51 is provided with a gas exhaust unit 59 that exhausts used gas, and further, a protective sheet 58 is attached to the inner wall of reaction chamber 51 to prevent precipitation of reactants.

[0078] 2-2. Preparation for film deposition A gallium (Ga) metal source 57 (with a purity of 99.99999% or more) was placed inside metal-containing source gas supply pipe 53b, and the sapphire substrate with the mask layer obtained in 1 above was placed as a substrate on substrate holder 56 inside reaction chamber 51. Thereafter, heaters 52a and 52b were operated to raise the temperature inside reaction chamber 51 to 570°C (near the Ga metal source) and 540°C (near the substrate holder).

[0079] 2-3. Film formation Hydrogen chloride (HCl) gas (purity 99.999% or higher) was supplied from a halogen-containing source gas supply source 53a to gallium (Ga) metal 57 disposed inside a metal source-containing gas supply pipe 53b. Gallium chloride (GaCl / GaCl) was generated by a chemical reaction between the Ga metal and the hydrogen chloride (HCl) gas. The resulting gallium chloride (GaCl / GaCl) and O gas (purity 99.99995% or higher) supplied from an oxygen-containing source gas supply source 55a were supplied onto the substrate through a reactive gas supply pipe 54b. Then, under the flow of HCl gas, the gallium chloride (GaCl / GaCl) and O gas were reacted on the substrate at atmospheric pressure and 540°C, forming a film on the substrate. Here, the flow rate of HCl gas supplied from the halogen-containing source gas supply source 53a was maintained at 10 sccm, the flow rate of HCl gas supplied from the reactive gas supply source 54a was maintained at 10 sccm, and the flow rate of O gas supplied from the oxygen-containing source gas supply source 55a was maintained at 100 sccm.

[0080] 2-4.Evaluation The laminated structure obtained in 2-3 above was subjected to AFM (Atomic Force Microscope) observation after surface polishing and cleaning. The results are shown in Figure 16. A partially enlarged view of the central part of Figure 16 is shown in Figure 17. As is clear from Figures 16 and 17, anisotropy was confirmed, with dislocations not extending in the a-axis direction but extending in the m-axis direction. Furthermore, it was found that dislocations in the c-axis direction were also reduced because dislocations extended in the m-axis direction.

[0081] Example 2 1. Formation of ELO mask A sapphire substrate (c-plane, off-angle 0.25°) with an α-Ga2O3 layer formed on its surface was used as the substrate, and a mask layer (thickness 50 nm) was formed in the same manner as in Example 1. In Example 2, a plurality of openings (dot-shaped openings) (diameter: 3 μm) were formed. The mask layer was processed so that the distance from the center of each opening to the center of the nearest opening was 10 μm, and the centers of the openings were arranged on the substrate so that they were located at the vertices of a triangular lattice (in this example, a triangular lattice of equilateral triangles). As shown in Fig. 24-b, in this example, the centers of the multiple openings provided in the mask layer were located at the vertices of a triangular lattice (in this example, a triangular lattice of equilateral triangles), and the triangles of the triangular lattice were arranged so that one side of the triangles was parallel to the a-axis direction, as shown in Fig. 24-b. By locating the centers of the openings in the mask at the vertices of the equilateral triangular lattice as described above and arranging one side of the triangles of the triangular lattice parallel to the axial direction, it was possible to control the shape and size of the region with reduced dislocations.

[0082] 2. Crystal formation Crystals were grown and associated in the same manner as in 2-1 to 2-3 of Example 1 above, to obtain a laminated structure. 2-4.Evaluation The resulting laminated structure was subjected to AFM (Atomic Force Microscope) observation after surface polishing and cleaning. The results are shown in Figure 24-c. Figure 24-d shows an explanatory diagram of the AFM image shown in Figure 24-c, with the mask openings indicated by dotted lines in a plan view. As is clear from Figures 24-c and 24-d, anisotropy was confirmed, with dislocations not extending in the a-axis direction but extending in the m-axis direction. As shown in Figure 24-d, it can be seen that dislocations are reduced in the inner region of the rhombus compared to the region near the vertex of the rhombus. The long side of the diagonal of the rhombus coincides with the a-axis direction. Furthermore, because dislocations extend in the m-axis direction, it was found that dislocations in the c-axis direction are also reduced as the crystal grows.

[0083] Example 3 1. Formation of ELO mask A sapphire substrate (c-plane, off-angle 0.25°) with an α-GaO layer formed on its surface was used as the substrate. A mask layer (50 nm thick) was formed on the substrate by sputtering, as in Examples 1 and 2. In Example 3, multiple openings (dot-shaped openings) (diameter: 3 μm) were formed. The multiple openings were processed so that the distance from the center of each opening to the center of the nearest opening was 10 μm, and the centers of the openings were positioned at the vertices of a triangular lattice (in this example, equilateral triangular lattice) and arranged on the substrate. In this example, the centers of the multiple openings provided in the mask layer were positioned at the vertices of the triangular lattice, and as shown in Figure 25-b, the openings were arranged so that one side of the triangle in the triangular lattice was parallel to the m-axis direction.

[0084] 2. Crystal formation Crystals were grown and associated in the same manner as in 2-1 to 2-3 of Example 1 above, to obtain a laminated structure. 2-4.Evaluation The resulting laminated structure was subjected to AFM (Atomic Force Microscope) observation after surface polishing and cleaning. The results are shown in Figure 25-c. Figure 20-d shows an explanatory diagram of the AFM image shown in Figure 25-c, with the mask openings indicated by dotted lines in a plan view. As is clear from Figures 25-c and 25-d, anisotropy was confirmed, with dislocations extending in the m-axis direction but not in the a-axis direction. As shown in Figure 25-d, triangular areas with reduced dislocations were obtained. The vertices of the triangles overlap with the centers of the mask layer openings in a plan view, indicating that dislocations are reduced in the inner areas of the triangles compared to the areas near the vertices. Furthermore, because dislocations extend in the m-axis direction, dislocations in the c-axis direction are also reduced. As described above, by arranging the mask dot-shaped openings at the vertices of equilateral triangles in a triangular lattice or by aligning one side of the equilateral triangle parallel to the axial direction, the shape and size of the regions with reduced crystal dislocations were controllable.

[0085] According to an embodiment of the present invention, a gallium oxide semiconductor crystal can be obtained that has a region with reduced dislocations centered in the a-axis direction, thereby obtaining a semiconductor crystal with reduced dislocations over a wide range. [Industrial Applicability]

[0086] The semiconductor device according to the embodiment of the present invention can be used in a wide range of fields, including semiconductors (e.g., compound semiconductor electronic devices), electronic components, electrical equipment components, optical and electrophotographic related devices, and industrial materials, but is particularly useful as a power device. [Explanation of symbols]

[0087] 1a First semiconductor region 1b Second semiconductor region 2. Semiconductor layer 2a Inversion channel region 2b Oxide film 4a Insulating film 4b Insulating film 5a Third electrode 5b First electrode 5c Second electrode 9 Substrate 19 Film deposition equipment 20 PCB 21 Susceptor 22a Carrier gas supply source 22b Carrier gas (dilution) supply source 23a Carrier gas flow control valve 23b Carrier gas (dilution) flow control valve 24 Mist source 24a Raw material solution 24b Atomized droplets 25 Container 25a water 26 Ultrasonic vibrator 27 Supply pipe 28 Hot plate (heater) 29 Exhaust port 30 Deposition chamber 50 Halide Vapor Phase Epitaxy (HVPE) Equipment 51 Reaction chamber 52a Heater 52b Heater 53a Halogen-containing raw gas supply source 53b Metal-containing raw material gas (metal halide gas) supply pipe 54a Reactive gas supply source 54b Reactive gas supply pipe 55a Oxygen-containing raw gas supply source 55b Oxygen-containing raw gas supply pipe 56 PCB holder 57 Metal sources 58 Protective Sheet 59 Gas exhaust section 70 Substrate (Crystalline Substrate) 71 Sapphire substrate 72 Gallium oxide layer 73 Mask Layer 74 Opening through the mask layer 100 Semiconductor device 100a 1st side 120 Semiconductor device 120a 1st side 120b 2nd side 121 Semiconductor layer 121a First semiconductor layer 121b Second semiconductor layer 125a Schottky electrode 125b Ohmic electrode 131a n-type semiconductor layer 131b First n+ type semiconductor layer 131c second n+ type semiconductor layer 132 p-type semiconductor layer 132a p+ type semiconductor layer 134 Gate insulating film 135a gate electrode 135b Source electrode 135c Drain electrode 139 Circuit Board 140 Semiconductor devices 140a: First surface side of semiconductor layer 140b: second surface side of semiconductor layer 141 Semiconductor layer 141a first semiconductor layer 141b Second semiconductor layer 141c Third semiconductor layer 143 Trench 145a Third electrode 145b first electrode 145c second electrode 150 Semiconductor devices 150a: First surface side of semiconductor layer 150b: second surface side of semiconductor layer 151a first semiconductor layer 151 Second semiconductor layer 152a p-type semiconductor region 152b third semiconductor layer 153 Semiconductor layer 154 Gate insulating film 155a Gate electrode 160 Semiconductor devices 161 Barrier Height Adjustment Area 162 First electrode 163 Semiconductor layer 164 Second Electrode 165 Guard Ring 166 Trench 170 Power System 171 Power supply 172 Power supply 173 Control Circuit 180 System Unit 181 Electronic circuit 182 Power System 192 inverter 193 Trans 194 Rectifier MOSFET 195 DCL 196 PWM control circuit 197 Voltage Comparator 200 Semiconductor device 200a 1st side 200b 2nd side 201 Double-sided cooled power card 202 Refrigerant tube 203 Spacer 208 Insulating plate (insulating spacer) 209 Sealing resin part 221 Bulkhead 222 Channel 300 Semiconductor device 300a 1st side 300b 2nd side 301a Semiconductor chip 302b Metal heat transfer plate (protruding terminal part) 303 Heat sink and electrode 303b Metal heat transfer plate (protruding terminal part) 304 solder layer 305 Control electrode terminal 308 Bonding Wire 400a period 401 Substrate (Crystalline Substrate) 401a Surface of the substrate 402a Convex part 402b Recess 404 Mask Layer 405 Slope

Claims

1. A semiconductor device comprising at least a semiconductor layer, and a first electrode and a second electrode respectively arranged on a first surface side of the semiconductor layer, wherein a current flows in the semiconductor layer in a first direction from the first electrode to the second electrode, wherein the semiconductor layer has a corundum structure, the direction of an m-axis of the semiconductor layer is parallel to the first direction, and dislocations due to crystal growth in the semiconductor layer extend more in the m-axis direction than in the a-axis direction.

2. 2. The semiconductor device according to claim 1, wherein the semiconductor layer contains a metal oxide containing at least one metal selected from the group consisting of gallium, indium, rhodium, iridium, and aluminum.

3. 2. The semiconductor device according to claim 1, wherein the semiconductor layer is mainly composed of a metal oxide containing at least gallium.

4. The carrier concentration of the semiconductor layer is 1×10 １９ / cm ３ The semiconductor device according to any one of claims 1 to 3, wherein:

5. 5. The semiconductor device according to claim 1, wherein the first surface is a c-plane.

6. 6. The semiconductor device according to claim 1, which is a power device.

7. 7. The semiconductor device according to claim 6, which is a power module, an inverter, or a converter.

8. 7. The semiconductor device according to claim 6, which is a power card.

9. 8. The semiconductor device according to claim 7, further comprising a cooler and an insulating member, the cooler being provided on both sides of the semiconductor layer with at least the insulating member interposed therebetween.

10. 10. The semiconductor device according to claim 9, wherein a heat dissipation layer is provided on each side of the semiconductor layer, and the cooler is provided outside the heat dissipation layer with at least the insulating member interposed therebetween.

11. A semiconductor system comprising a semiconductor device, wherein the semiconductor device is the semiconductor device according to any one of claims 1 to 10.

Images