Indication device

Abstract

To provide a display device capable of suppressing a short circuit between an ion trap electrode and a shield layer.SOLUTION: A display device includes, around at least one curved line portion, a first ion trap electrode, a second ion trap electrode, and a bifurcating electrode. The first ion trap electrode is disposed between the shield layer and a gate driver circuit, provided in a linear shape along the gate driver circuit, and supplied with a constant potential. The second ion trap electrode is disposed between the shield layer and the first ion trap electrode, provided in a linear shape along an edge of the shield layer, and supplied with the same potential as the first ion trap electrode. The bifurcating electrode bifurcates the second ion trap electrode from halfway through the first ion trap electrode in a linear shape.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present disclosure relates to a display device. [Background technology]

[0002] In the display device of Patent Document 1, the display area has a curved shape other than a rectangular shape. The display device of Patent Document 1 is also called an irregular-shaped display.

[0003] Patent Document 2 describes an ion trap electrode for trapping ionic impurities outside the display area, and also describes a shield layer provided in the peripheral area to cover the drive circuit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2013 / 0328051 [Patent Document 2] Patent Publication No. 2021-113960 Summary of the Invention [Problem to be solved by the invention]

[0005] A display device has an array substrate and an opposing substrate overlaid on the array substrate, and a reference potential is sometimes supplied from the array substrate to the edge of the opposing substrate using silver paste. In harsh environments, compounds resulting from the components of the silver paste may precipitate between the ion trap electrode and the shield layer, potentially causing a short circuit between the ion trap electrode and the shield layer.

[0006] An object of the present disclosure is to provide a display device that can suppress short circuits between an ion trap electrode and a shield layer. [Means for solving the problem]

[0007] A display device according to one aspect of the present disclosure includes a first region in which an array substrate, a plurality of scanning lines extending in a first direction, a plurality of signal lines extending in a second direction, and a plurality of pixels are provided on the array substrate, the first region having a first side, a second side, a third side, a fourth side, and a plurality of curved portions, and a second region located between an end of the array substrate and the first region, the display device including: a signal line connection circuit disposed in the second region and connected to the plurality of signal lines; a shielding layer disposed in the second region and covering at least a portion of the signal line connection circuit around at least one of the curved portions; the first ion trap electrode is arranged between the shield layer and the gate driver circuit, linearly arranged along the edge of the shield layer, and supplied with a constant potential; the second ion trap electrode is arranged between the shield layer and the first ion trap electrode, linearly arranged along the edge of the shield layer, and supplied with the same potential as the first ion trap electrode; and a branch electrode that branches off the second ion trap electrode from the middle of the linear first ion trap electrode. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view schematically showing a display device according to an embodiment. [Figure 2A] FIG. 2A is a cross-sectional view taken along line IIA-IIA' in FIG. [Figure 2B] FIG. 2B is a cross-sectional view taken along line IIB-IIB' in FIG. [Figure 3] FIG. 3 is an enlarged cross-sectional view of region A in FIG. 2A. [Figure 4] FIG. 4 is a circuit diagram showing the pixel arrangement in the display area. [Figure 5] FIG. 5 is a plan view schematically showing the array substrate of the embodiment. [Figure 6] FIG. 6 is a cross-sectional view taken along the line VI-VI' in FIG. [Figure 7] FIG. 7 is a plan view showing an example of a light-shielding layer according to an embodiment. [Figure 8] FIG. 8 is a plan view showing a shield layer and an ion trap electrode according to an embodiment, which are positioned adjacent to a display area with a curved corner. [Figure 9] FIG. 9 is an enlarged plan view showing the first shield layer and the second shield layer. [Figure 10] FIG. 10 is a cross-sectional view taken along the line XX' in FIG. [Figure 11] FIG. 11 is a partial enlarged view of the Q11 portion of FIG. [Figure 12] FIG. 12 is a cross-sectional view taken along the line XII-XII' in FIG. [Figure 13] FIG. 13 is a plan view showing a shield layer and an ion-trap electrode according to a comparative example, which are arranged adjacent to a display area of ​​a curved corner. DETAILED DESCRIPTION OF THE INVENTION

[0009] Modes (embodiments) for carrying out the present disclosure will be described in detail with reference to the drawings. The present disclosure is not limited to the contents described in the following embodiments. Furthermore, the components described below include those that can be easily imagined by a person skilled in the art and those that are substantially identical. Furthermore, the components described below can be combined as appropriate. Note that the disclosure is merely an example, and any appropriate modifications that a person skilled in the art can easily conceive while maintaining the gist of the invention are naturally included within the scope of the present disclosure. Furthermore, for clarity of explanation, the drawings may schematically depict the width, thickness, shape, etc. of each part compared to the actual embodiment. However, these are merely examples and are not intended to limit the interpretation of the present disclosure. Furthermore, in this specification and each figure, elements similar to those previously described with reference to the preceding figures may be designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0010] (Embodiment) FIG. 1 is a plan view schematically illustrating a display device according to an embodiment. FIG. 2A is a cross-sectional view taken along line IIA-IIA′ in FIG. 1. FIG. 2B is a cross-sectional view taken along line IIB-IIB′ in FIG. 1. FIG. 3 is a cross-sectional view showing an enlarged view of region A in FIG. 2A. As shown in FIG. 1, the display device 1 includes an array substrate SUB1 and a counter-substrate SUB2. In the display device 1, a peripheral region BE (second region) is provided outside a display region DA (first region). In the display device 1, the display region DA is formed in a substantially rectangular shape with curved corners, but the outer shape of the display region DA is not limited thereto. For example, the display region DA may have a notch, or may be formed in another polygonal shape, or may be formed in another shape such as a circle or an ellipse.

[0011] In this embodiment, the first direction Dx is a direction along the short side of the display area DA. The second direction Dy is a direction intersecting (or perpendicular to) the first direction Dx. However, the second direction Dy may intersect with the first direction Dx at an angle other than 90°. The plane defined by the first direction Dx and the second direction Dy is parallel to the surface of the array substrate SUB1. Furthermore, the third direction Dz, which is perpendicular to the first direction Dx and the second direction Dy, is the thickness direction of the array substrate SUB1.

[0012] The display area DA is an area for displaying an image and overlaps with multiple pixels PX. The peripheral area BE is an area inside the outer periphery of the array substrate SUB1 and outside the display area DA. The peripheral area BE may be a frame-like area surrounding the display area DA, in which case the peripheral area BE can also be called a frame area.

[0013] The first insulating substrate 10 of the array substrate SUB1 has a first side 10s1, a second side 10s2, a third side 10s3, and a fourth side 10s4. The first side 10s1 extends along a first direction Dx in a plan view. The second side 10s2 faces the first side 10s1. The third side 10s3 extends along a second direction Dy. The fourth side 10s4 faces the third side 10s3.

[0014] The peripheral region BE includes a first partial peripheral region sBE1, a second partial peripheral region sBE2, a third partial peripheral region sBE3, and a fourth partial peripheral region sBE4. In this embodiment, the first partial peripheral region sBE1 is the region between the first side 10s1 and a virtual line (shown by a two-dot chain line) extending from a straight portion of a short side of the display region DA. The second partial peripheral region sBE2 is the region between the second side 10s2 and a virtual line extending from a straight portion of a short side of the display region DA. The third partial peripheral region sBE3 and the fourth partial peripheral region sBE4 are regions between the first partial peripheral region sBE1 and the second partial peripheral region sBE2, and are provided along the third side 10s3 and the fourth side 10s4, respectively.

[0015] 1 and 2A, the length of the array substrate SUB1 in the second direction Dy is longer than the length of the counter substrate SUB2 in the second direction Dy. As shown in Fig. 1, the first insulating substrate 10 has a protruding portion 10A. The protruding portion 10A is a portion that protrudes outward beyond the first side 20s1 of the second insulating substrate 20 in a plan view.

[0016] A plurality of terminals T1 are provided on the protruding portion 10A. The plurality of terminals T1 are arranged in the first direction Dx along the first side 10s1 in the first partial peripheral area sBE1. A wiring board 101 is also provided on the protruding portion 10A. The wiring board 101 is configured by, for example, a flexible wiring board (FPC: Flexible Printed Circuits). The wiring board 101 is connected to the plurality of terminals T1 of the first insulating substrate 10 by, for example, FOG (Film On Glass) using an anisotropic conductive film (ACF: Anisotropic Conductive Film) (hereinafter referred to as "FOG mounting"). This electrically connects each of the wirings of the first insulating substrate 10 to each of the wirings of the wiring board 101.

[0017] The driver IC (Integrated Circuit) 110 is provided on the wiring substrate 101. The driver IC 110 includes a control circuit for controlling the display of the display device 1, a detection circuit, an analog front end, and the like. The driver IC 110 is mounted on the wiring substrate 101 by COF (Chip On Film) using ACF, for example (hereinafter referred to as "COF mounting"). Furthermore, without being limited to this example, the driver IC 110 may be mounted on the first insulating substrate 10 by COG (Chip On Glass). In this case, the driver IC 110 is provided between the terminal T1 to which the wiring substrate 101 is connected and the signal line connecting circuit 30 (see FIG. 5). The arrangement of the driver IC 110 is not limited thereto, and the driver IC 110 may be provided on, for example, a control substrate or a flexible substrate outside the module.

[0018] 2A and 3, the counter substrate SUB2 is disposed opposite to the surface of the array substrate SUB1 in a direction perpendicular to the surface of the array substrate SUB1, and a liquid crystal layer LC is provided between the array substrate SUB1 and the counter substrate SUB2.

[0019] 1, a pad electrode 10S serving as a reference potential is provided on the protruding portion 10A of the array substrate SUB1, to the side of the terminal T1. As shown in FIG. 2B, a conductive pillar 10P made of silver paste is laminated on the pad electrode 10S, and the conductive pillar 10P is provided along a first side 20s1 of the second insulating substrate 20, with a portion of the silver paste extending over the second insulating substrate 20. The conductive pillar 10P is electrically connected to a conductive layer 21, which will be described later.

[0020] 3, the array substrate SUB1 has as its base a first insulating substrate 10 having light-transmitting properties, such as a glass substrate or a resin substrate. The array substrate SUB1 includes a first insulating film 11, a second insulating film 12, a third insulating film 13, a fourth insulating film 14, a fifth insulating film 15, a sixth insulating film 16, signal lines SL, pixel electrodes PE, detection electrodes DE, a first alignment film AL1, etc. on the side of the first insulating substrate 10 facing the counter substrate SUB2.

[0021] In this specification, the direction from the first insulating substrate 10 to the second insulating substrate 20 in a direction perpendicular to the first insulating substrate 10 is referred to as the "upper side" or simply "upper". The direction from the second insulating substrate 20 to the first insulating substrate 10 is referred to as the "lower side" or simply "lower". Furthermore, "planar view" refers to a view from a direction perpendicular to the first insulating substrate 10. The detection electrode DE is also referred to as the first electrode, and the pixel electrode PE is also referred to as the second electrode.

[0022] The first insulating film 11 is located on the first insulating substrate 10. The second insulating film 12 is located on the first insulating film 11. The third insulating film 13 is located on the second insulating film 12. The signal line SL is located on the third insulating film 13. The fourth insulating film 14 is located on the third insulating film 13 and covers the signal line SL.

[0023] The sensor wiring 51 is located on the fourth insulating film 14. The sensor wiring 51 faces the signal line SL via the fourth insulating film 14. That is, the sensor wiring 51 overlaps the signal line SL. The sensor wiring 51 is covered by the fifth insulating film 15. The first insulating film 11, the second insulating film 12, the third insulating film 13, and the sixth insulating film 16 are formed of a light-transmitting inorganic material such as silicon oxide or silicon nitride. The fourth insulating film 14 and the fifth insulating film 15 are formed of a light-transmitting resin material and have a thickness greater than that of other insulating films formed of inorganic materials. In other words, the signal line SL is covered by the fourth insulating film 14 and the fifth insulating film 15, which are organic insulating films. However, the fifth insulating film 15 may be formed of an inorganic material.

[0024] The detection electrode DE is located on the fifth insulating film 15. The detection electrode DE faces the sensor wiring 51 via the fifth insulating film 15. The slit SPA of the detection electrode DE is located directly above the sensor wiring 51. The detection electrode DE is covered with the sixth insulating film 16.

[0025] The pixel electrode PE is located on the sixth insulating film 16 and faces the detection electrode DE via the sixth insulating film 16. The pixel electrode PE and the detection electrode DE are formed of a light-transmitting conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The pixel electrode PE is covered with a first alignment film AL1. The first alignment film AL1 also covers the sixth insulating film 16.

[0026] The counter substrate SUB2 is based on a second insulating substrate 20 having light transparency, such as a glass substrate or a resin substrate. The counter substrate SUB2 is provided with a light-shielding layer BM, color filters CFR, CFG, CFB, an overcoat layer OC, a second alignment film AL2, etc. on the side of the second insulating substrate 20 facing the array substrate SUB1. The counter substrate SUB2 is provided with a conductive layer 21 on the side of the second insulating substrate 20 opposite to the array substrate SUB1.

[0027] The light-shielding layer BM is located on the side of the second insulating substrate 20 facing the array substrate SUB1. The light-shielding layer BM defines openings facing the pixel electrodes PE. The pixel electrodes PE are partitioned into pixel openings. The light-shielding layer BM is made of a black resin material or a light-shielding metal material.

[0028] The color filters CFR, CFG, and CFB are located on the side of the second insulating substrate 20 facing the array substrate SUB1, and their ends overlap the light-shielding layer BM. In one example, the color filters CFR, CFG, and CFB are formed from resin materials colored red, green, and blue, respectively.

[0029] The overcoat layer OC covers the color filters CFR, CFG, and CFB. The overcoat layer OC is made of a light-transmitting resin material. The second alignment film AL2 covers the overcoat layer OC. The first alignment film AL1 and the second alignment film AL2 are made of, for example, a material that exhibits horizontal alignment.

[0030] The array substrate SUB1 and the counter substrate SUB2 are arranged so that the first alignment film AL1 and the second alignment film AL2 face each other. A liquid crystal layer LC is sealed between the first alignment film AL1 and the second alignment film AL2. The liquid crystal layer LC is made of a negative-type liquid crystal material with negative dielectric anisotropy or a positive-type liquid crystal material with positive dielectric anisotropy.

[0031] The array substrate SUB1 faces the backlight unit IL, and the counter substrate SUB2 faces the display surface. Various types of backlight unit IL are applicable, but detailed explanation of their structures will be omitted.

[0032] The conductive layer 21 is provided on the second insulating substrate 20. The conductive layer 21 is made of a translucent conductive material such as ITO. The conductive layer 21 is electrically connected to the pad electrode 10S via the conductive pillars 10P (see FIG. 2B). Therefore, static electricity applied from the outside and static electricity charged on the polarizer PL2 flow through the conductive layer 21. The display device 1 can remove static electricity in a short time, thereby reducing static electricity applied to the liquid crystal layer LC, which is the display layer. This allows the display device 1 to improve its ESD resistance. The conductive layer 21 is particularly useful in display devices that utilize a lateral electric field in which an electric field is generated between the pixel electrodes PE and a common electrode (detection electrode DE) provided on the array substrate SUB1.

[0033] The optical element including the polarizing plate PL1 is disposed on the outer surface of the first insulating substrate 10 or on the surface facing the backlight unit IL. The optical element including the polarizing plate PL2 is disposed on the outer surface of the second insulating substrate 20 or on the surface on the viewing position side. The first polarization axis of the polarizing plate PL1 and the second polarization axis of the polarizing plate PL2 are in a crossed Nicol positional relationship in the XY plane, for example. The polarizing plate PL2 and the optical element including the polarizing plate PL2 may include other optically functional elements such as a retardation plate.

[0034] For example, if the liquid crystal layer LC is made of a negative liquid crystal material, when no voltage is applied to the liquid crystal layer LC, the liquid crystal molecules LM are initially aligned in the XY plane with their long axes aligned along the first direction Dx. On the other hand, when a voltage is applied to the liquid crystal layer LC, that is, when an electric field is formed between the pixel electrode PE and the detection electrode DE in the on state, the alignment state of the liquid crystal molecules LM changes under the influence of the electric field. When the polarization state of incident linearly polarized light passes through the liquid crystal layer LC, it changes depending on the alignment state of the liquid crystal molecules LM.

[0035] Fig. 4 is a circuit diagram showing the pixel arrangement in the display area. On the array substrate SUB1, switching elements Tr, signal lines SL, scanning lines GL, etc. of each sub-pixel SPX shown in Fig. 4 are formed. In the display area DA, the signal lines SL extend in the second direction Dy. The signal lines SL are wiring for supplying pixel signals to each pixel electrode PE (see Fig. 3). In the display area DA, the scanning lines GL extend in the first direction Dx. The scanning lines GL are wiring for supplying gate signals (scanning signals) that drive each switching element Tr.

[0036] The pixel PX includes a plurality of sub-pixels SPX. Each sub-pixel SPX has a switching element Tr and a capacitance of a liquid crystal layer LC. The switching element Tr is configured by a thin-film transistor, and in this example, is configured by an n-channel MOS (Metal Oxide Semiconductor) TFT. A sixth insulating film 16 is provided between the pixel electrode PE and the detection electrode DE shown in FIG. 3, and these form a storage capacitance Cs shown in FIG. 4.

[0037] The color filters CFR, CFG, and CFB shown in FIG. 3 have color regions colored in three colors, for example, red (R), green (G), and blue (B), arranged periodically. Each sub-pixel SPX is associated with a set of color regions of R, G, and B. A pixel PX is formed by a set of sub-pixels SPX corresponding to the three color regions. Note that the color filter may include color regions of four or more colors. In this case, the pixel PX may include four or more sub-pixels SPX.

[0038] FIG. 5 is a plan view schematically illustrating an array substrate. FIG. 6 is a cross-sectional view taken along line VI-VI′ of FIG. 5. FIG. 6 also schematically illustrates the stacked structure of the switching element Tr of the subpixel SPX. The display area DA, which displays an image, includes a sensor area included in a detection device that detects capacitance. As shown in FIG. 5, the detection electrodes DE are arranged in a matrix in the first direction Dx and the second direction Dy in the display area DA. The multiple detection electrodes DE are divided into the first direction Dx and the second direction Dy by slits SPA. Each detection electrode DE is schematically illustrated as having a rectangular or square shape in a plan view, but is not limited thereto and may have a polygonal shape, a parallelogram shape, or an irregular shape having a notch or the like. The detection electrodes DE are made of a light-transmitting conductive material, such as ITO.

[0039] The display device 1 further includes a signal line connection circuit 30, a wiring area LA including multiple wirings 53, and a gate driver circuit 18. The signal line connection circuit 30 includes multiple analog switch elements and is also called a multiplexer. The signal line connection circuit 30 and the wiring area LA are provided in the first partial peripheral area sBE1 of the first insulating substrate 10. From the first side 10s1 toward the display area DA, multiple terminals T1, the wiring area LA (wirings 53), the signal line connection circuit 30, and the signal lines SL are connected in this order. Two gate driver circuits 18 are provided in the third partial peripheral area sBE3 and the fourth partial peripheral area sBE4, respectively. In other words, the two gate driver circuits 18 are arranged along the third side sDA3 and the fourth side sDA4 of the display area DA, respectively. The gate driver circuit 18 is arranged outside the signal line connection circuit 30. The gate driver circuit 18 may be provided in only one of the third partial peripheral area sBE3 and the fourth partial peripheral area sBE4.

[0040] Each of the plurality of sensor wirings 51 is electrically connected to a corresponding one of the plurality of detection electrodes DE and extends to the peripheral region BE. Each of the plurality of sensor wirings 51 extends along the second direction Dy, and the plurality of sensor wirings 51 are arranged side by side in the first direction Dx. One end of each of the plurality of sensor wirings 51 is connected to the detection electrode DE, and the other end is electrically connected to the signal line connection circuit 30. The other end of each of the plurality of sensor wirings 51 is connected to the terminal T1 via wiring 53. In this manner, the detection electrodes DE are electrically connected to the driver IC 110 (see FIG. 1).

[0041] During display, the driver IC 110 supplies a display drive signal to the sensor wire 51 via the wire 53. The detection electrode DE receives the display drive signal during display and functions as a common electrode for the plurality of pixel electrodes PE. During the display period, all of the detection electrodes DE are at a common potential. During touch detection, the driver IC 110 supplies a touch drive signal for detection to the detection electrode DE via the sensor wire 51. As a result, a detection signal corresponding to a change in capacitance of the detection electrode DE is supplied to the detection circuit of the driver IC 110 via the wire 53. This allows the display device 1 to detect an object in contact with or in proximity to each of the plurality of detection electrodes DE.

[0042] Furthermore, the pixel electrodes PE (see FIG. 3) are electrically connected to the driver IC 110 via signal lines SL and a signal line connection circuit 30. Each of the signal lines SL is electrically connected to a corresponding one of the pixel electrodes PE arranged in the first direction Dx, and is drawn out to the peripheral region BE. Each of the signal lines SL extends along the second direction Dy, and the signal lines SL are arranged side by side in the first direction Dx. Note that, for ease of understanding, FIG. 5 shows only some of the signal lines SL and sensor wirings 51.

[0043] As shown in Figure 5, the display area DA is a rectangle having a first side sDA1, a second side sDA2, a third side sDA3, and a fourth side sDA4. The first side sDA1, the second side sDA2, the third side sDA3, and the fourth side sDA4 are continuously connected by a curved portion DAc. Here, the third side sDA3 faces the fourth side sDA4, and the second side sDA2 faces the first side sDA1.

[0044] The ion trapping electrode ITL1 is disposed in the second partial peripheral region sBE2, the third partial peripheral region sBE3, and the fourth partial peripheral region sBE4 along the second side sDA2, the third side sDA3, and the fourth side sDA4. The ion trapping electrode ITL1 extends continuously along the second side sDA2, the third side sDA3, and the fourth side sDA4. This defines the display region DA inside the ion trapping electrode ITL1.

[0045] The ion trapping electrode ITL1 is disposed in the third partial peripheral region sBE3 between one of the gate driver circuits 18 and the third side sDA3. The ion trapping electrode ITL1 is disposed in the fourth partial peripheral region sBE4 between the other of the gate driver circuits 18 and the fourth side sDA4.

[0046] The signal line connection circuit 30 is provided along the boundary between the display area DA and the first partial peripheral area sBE1 and is provided along the curved portion DAc of the display area DA. The end of the gate driver circuit 18 on the first partial peripheral area sBE1 side is provided adjacent to the curved portion DAc in the first direction Dx. The portion of the signal line connection circuit 30 along the curved portion DAc is provided between the gate driver circuit 18 and the curved portion DAc in the first direction Dx. A plurality of signal lines SL are connected to the signal line connection circuit 30. The signal line connection circuit 30 is also electrically connected to the wiring substrate 101 (see FIG. 1 ) via a plurality of wirings 53 and terminals T1 provided in the wiring area LA. The signal line connection circuit 30 is a circuit that switches between connection and disconnection between the signal lines SL and the wirings 53.

[0047] The liquid crystal layer LC is typically sealed between the array substrate SUB1 and the counter substrate SUB2 with a seal. If external impurities such as metal ions, inorganic anions, or organic acids infiltrate the liquid crystal layer LC in the display area DA, these impurities may prevent the proper electric field from being maintained, potentially causing display defects such as display spots and burn-in. To prevent display defects, a constant potential is supplied to the ion trapping electrode ITL1. This constant potential is fixed, for example, to the VGL potential, a low voltage among the signals (voltages) used for control signals. In this way, the ion trapping electrode ITL1 keeps ionic impurities in the peripheral area BE, preventing them from infiltrating into the liquid crystal layer LC in the display area DA.

[0048] 5, adjacent to the curved portion DAc, the ion trapping electrode ITL1 is disposed between the gate driver circuit 18 and the plurality of wirings 53 provided in the wiring region LA. This allows the ion trapping electrode ITL1 to prevent ionic impurities that gather around the curved portion DAc from penetrating into the liquid crystal layer LC in the display region DA.

[0049] 6, the switching element Tr includes a semiconductor 61, a source electrode 62, a drain electrode 63, and a gate electrode 64. The semiconductor 61 is provided on a first insulating substrate 10 with a first insulating film 11 interposed therebetween. A light-shielding layer 67 is provided between the first insulating substrate 10 and the semiconductor 61 in a direction perpendicular to the first insulating substrate 10.

[0050] The second insulating film 12 is provided on the first insulating film 11, covering the semiconductor 61. The gate electrode 64 is provided on the second insulating film 12. The gate electrode 64 is a portion of the scanning line GL that overlaps with the semiconductor 61. The third insulating film 13 is provided on the second insulating film 12, covering the semiconductor 61 and the gate electrode 64. A channel region is formed in the portion of the semiconductor 61 that overlaps with the gate electrode 64.

[0051] 6, the switching element Tr has a so-called top-gate structure. However, the switching element Tr may have a bottom-gate structure in which a gate electrode 64 is provided below the semiconductor 61. Alternatively, the switching element Tr may have a dual-gate structure in which the gate electrodes 64 are provided on either side of the semiconductor 61 in a direction perpendicular to the first insulating substrate 10.

[0052] The source electrode 62 and the drain electrode 63 are provided on the third insulating film 13. In this embodiment, the source electrode 62 is electrically connected to the semiconductor 61 through a contact hole H2. The drain electrode 63 is electrically connected to the semiconductor 61 through a contact hole H3. The source electrode 62 is a portion of the signal line SL that overlaps with the semiconductor 61.

[0053] The fourth insulating film 14 and the fifth insulating film 15 are provided on the third insulating film 13, covering the source electrode 62 and the drain electrode 63. A relay electrode 65 and a sensor wiring 51 are provided on the fourth insulating film 14. The relay electrode 65 is electrically connected to the drain electrode 63 through a contact hole H4. The sensor wiring 51 is provided above the signal line SL. In a plan view, the sensor wiring 51 overlaps with the signal line SL and extends parallel to the signal line SL. In addition, a detection electrode DE is provided on the fifth insulating film 15. The detection electrode DE is electrically connected to the sensor wiring 51 through a contact hole H1.

[0054] The pixel electrode PE is electrically connected to the relay electrode 65 via a contact hole H5 provided in the sixth insulating film 16 and the fifth insulating film 15. The contact hole H5 is formed at a position overlapping with the opening DEa of the detection electrode DE. With this configuration, the pixel electrode PE is connected to the switching element Tr.

[0055] As described above, in the display area DA, a plurality of scanning lines GL, a plurality of signal lines SL, a plurality of sensor wirings 51, a plurality of detection electrodes DE (first electrodes), and a plurality of pixel electrodes PE (second electrodes) are stacked in order, each with an insulating film interposed therebetween.

[0056] 7 is a plan view showing an example of a light-shielding layer according to an embodiment. In this embodiment, a boundary BL of a curved portion DAc is formed between the display area DA and the peripheral area BE by providing a difference in aperture ratio per unit area of ​​the light-shielding layer BM.

[0057] For example, the display area DA has, as the pixels PX, a first pixel PX1, a second pixel PX2, a third pixel PX3, a fourth pixel PX4, and a fifth pixel PX5. The first pixel PX1, the second pixel PX2, the third pixel PX3, the fourth pixel PX4, and the fifth pixel PX5 each have a different aperture ratio per unit area of ​​the light-shielding layer BM.

[0058] The light-shielding layer BM at a position overlapping with the first pixel PX1 has three first openings AP1. The light-shielding layer BM at a position overlapping with the second pixel PX2 has three second openings AP2. The light-shielding layer BM at a position overlapping with the third pixel PX3 has three third openings AP3. The light-shielding layer BM at a position overlapping with the fourth pixel PX4 has three fourth openings AP4. The light-shielding layer BM at a position overlapping with the fifth pixel PX5 has three fifth openings AP5.

[0059] The area of ​​each opening (i.e., aperture ratio) decreases in the order of first opening AP1, second opening AP2, third opening AP3, fourth opening AP4, and fifth opening AP5. The first opening AP1 has the largest aperture area, and the fifth opening AP5 has the smallest aperture area. As a result, the light transmittance decreases in the order of the first pixel PX1, second pixel PX2, third pixel PX3, fourth pixel PX4, and fifth pixel PX5.

[0060] In this embodiment, the first opening AP1, the second opening AP2, the third opening AP3, the fourth opening AP4, and the fifth opening AP5 are arranged so that the light transmittance decreases from the display area DA toward the peripheral area BE in the first direction Dx and the second direction Dy, whereby the light-shielding layer BM defines the boundary BL of the curved portion DAc.

[0061] Next, the configurations of the shield layer CES and ion trap electrodes ITL1 and ITL2 of this embodiment will be described in detail. Fig. 8 is a plan view showing the shield layer and ion trap electrodes according to this embodiment, which are arranged adjacent to the display area of ​​the curved corner. Although not shown in Fig. 5, as shown in Fig. 8, in region Q1, outside the boundary BL of curved portion DAc, there is a wiring region TA including multiple signal lines SL and sensor wiring 51 (see Fig. 5).

[0062] Outside the wiring area TA is an area where the signal line connection circuit 30 is arranged. Outside the area where the signal line connection circuit 30 is arranged is a wiring area LA. In this embodiment, a plurality of pixel electrodes PE (pixels PX) are provided between the boundary BL and the wiring area TA. This makes it possible to prevent the wiring and peripheral circuits in the peripheral area BE from being visible even when a viewer views from an oblique direction.

[0063] A shield layer CES is provided around the curved portion DAc. The shield layer CES includes a first shield layer CES1 and a second shield layer CES2. The first shield layer CES1 covers the signal line connection circuit 30 and at least a portion of the wiring area TA and the wiring area LA. The second shield layer CES2 is disposed so as to overlap the first shield layer CES1. The second shield layer CES2 includes a plurality of rectangular shield portions 55 each having an area smaller than that of the first shield layer CES1, and the shield portions 55 are arranged in the first direction Dx and the second direction Dy. As the distance between the gate driver circuit 18 and the boundary BL decreases, the width of the first shield layer CES1 in the first direction Dx decreases. The width of the second shield layer CES2 (the number of shield portions 55) is also arranged differently depending on the width of the first shield layer CES1 in the first direction Dx.

[0064] The first shield layer CES1 and the second shield layer CES2 are connected to connection wiring CL that supplies the same reference potential. The connection wiring CL is connected to lower-layer connection wiring CLs at predetermined intervals via through holes. The connection wiring CL is formed in the same layer as the pixel electrodes PE and made of the same material. The lower-layer connection wiring CLs is formed in the same layer as the signal lines SL and made of the same material. The reference potential is, for example, a signal having the same potential as the common potential applied to the detection electrodes DE during display. In other words, the second shield layer CES2 is supplied with the same potential as that of the first shield layer CES1. This allows the first shield layer CES1 and the second shield layer CES2 to shield against electric fields generated due to the operation of the signal line connection circuit 30. Furthermore, the first shield layer CES1 and the second shield layer CES2 can shield against electric fields generated due to pixel signals supplied to the signal lines SL and the wiring 53.

[0065] 8 shows only a portion of the shield layer CES for clarity, but in reality, the first shield layer CES1 is provided along the extension direction of the signal line connecting circuit 30, and the multiple shield portions 55 of the second shield layer CES2 are arranged from one end side to the other end side of the extension direction of the first shield layer CES1. The detailed configurations of the first shield layer CES1 and the second shield layer CES2 will be described later.

[0066] The distance between the gate driver circuit 18 and the wiring region LA increases as the distance increases in the second direction Dy. The two ion trapping electrodes ITL1 and ITL2 are provided between the gate driver circuit 18 and the wiring region LA. That is, the ion trapping electrodes ITL1 and ITL2 are disposed adjacent to the first shield layer CES1 and the second shield layer CES2 in the first direction Dx, but do not overlap in plan view.

[0067] The ion trap electrode ITL1 is routed so as to run parallel to the connection wiring CL without contacting it. The ion trap electrode ITL1 is provided in a curved line along the gate driver circuit 18. The ion trap electrode ITL2 extends closer to the display area DA than the ion trap electrode ITL1, more specifically, along the wiring area LA, and is disposed between the ion trap electrode ITL1 and the wiring area LA. One end of the ion trap electrode ITL2 branches off from the ion trap electrode ITL1 at a portion where the distance between the gate driver circuit 18 and the wiring area LA narrows. One end of the ion trap electrode ITL2 branches off from the ion trap electrode ITL1 via a branch electrode ITL3. The other end of the ion trap electrode ITL2 is disposed apart from the ion trap electrode ITL1. However, the ion trap electrode ITL2 is connected to the ion trap electrode ITL1 via the branch electrode ITL3 and is formed of a single continuous, light-transmitting conductive material.

[0068] The gate driver circuit 18 curves along the outer periphery 10s and the curved portion DAc of the first insulating substrate. A scanning signal wiring region 18L is formed between the gate driver circuit 18 and the outer periphery 10s. In the scanning signal wiring region 18L, a plurality of scanning signal wirings for supplying gate signals (scanning signals) are provided along the outer periphery 10s.

[0069] The third shield layer CES3 includes a curved portion covering the gate driver circuit 18 and a portion extending in the first direction Dx and covering the wiring area LA (see FIG. 5) between the display area DA and the terminal T1. The third shield layer CES3 is electrically connected to the first shield layer CES1 and is supplied with a reference potential having the same potential as that of the first shield layer CES1. This enables the third shield layer CES3 to shield the electric field generated in the wiring area LA near the gate driver circuit 18 and the terminal T1.

[0070] As described above, in the display device 1, the wiring area TA (signal lines SL), signal line connecting circuit 30, wiring area LA (wiring 53), ion trapping electrode ITL2, ion trapping electrode ITL1, and gate driver circuit 18 are arranged in this order from the boundary BL of curved portion DAc toward the outer periphery 10s of the first insulating substrate. That is, the shield layer CES (first shield layer CES1 and second shield layer CES2), ion trapping electrode ITL2, ion trapping electrode ITL1, and third shield layer CES3 are arranged in this order from the boundary BL of curved portion DAc toward the outer periphery 10s of the first insulating substrate.

[0071] In this way, the display device 1 has a region around the curved portion DAc where the distance in the first direction Dx between the gate driver circuit 18 and the boundary BL increases. By providing the first shield layer CES1 and the second shield layer CES2, it is possible to shield the electric field caused by the signal line connecting circuit 30, the wiring region TA (signal lines SL), and the wiring region LA (wiring 53) around the curved portion DAc. Around the curved portion DAc, the greater the distance between the gate driver circuit 18 and the shield layer CES, the greater the distance between the first ion trapping electrode ITL1 and the second ion trapping electrode ITL2. In addition, because the ion trapping electrodes ITL1 and ITL2 are sandwiched between the shield layer CES (the first shield layer CES1 and the second shield layer CES2) and the third shield layer CES3 that covers the gate driver circuit 18 in a plan view, ionic impurities can be confined to the peripheral region BE (second region) outside the display region DA (first region).

[0072] Fig. 9 is an enlarged plan view showing the first shield layer and the second shield layer. As shown in Fig. 9, the first shield layer CES1 has a plurality of openings OP. Each of the plurality of openings OP is rectangular and arranged in a matrix. The second shield layer CES2 has a plurality of shield portions 55 and a plurality of connection portions CN (connection portions CNx and connection portions CNy). The shield portions 55 are arranged in a matrix, covering the plurality of openings OP, respectively.

[0073] Specifically, in the second shield layer CES2, the multiple shield parts 55 are arranged at intervals SPx in the first direction Dx, and adjacent shield parts 55 in the first direction Dx are connected by narrow connecting parts CNx. Furthermore, the multiple shield parts 55 are arranged at intervals SPy in the second direction Dy, and adjacent shield parts 55 in the second direction Dy are connected by narrow connecting parts CNy. This electrically connects the multiple shield parts 55 arranged in the first direction Dx and the second direction Dy. Furthermore, the multiple shield parts 55 are each provided to cover the entire area of ​​the opening OP.

[0074] The width of the opening OP in the first direction Dx is defined as a first opening width Wopx, and the width of the opening OP in the second direction Dy is defined as a second opening width Wopy. The first opening width Wopx of the opening OP is larger than the second opening width Wopy.

[0075] Furthermore, the width of each shield part 55 of the second shield layer CES2 in the first direction Dx is defined as a first width Wx, and the width of each shield part 55 in the second direction Dy is defined as a second width Wy. The first width Wx of the shield part 55 is larger than the second width Wy. The area of ​​the shield part 55 in plan view is larger than the area of ​​the opening OP. That is, the first width Wx of the shield part 55 is larger than the first opening width Wopx of the opening OP, and the second width Wy of the shield part 55 is larger than the second opening width Wopy of the opening OP.

[0076] The arrangement pitch of the shield parts 55 is equal to the arrangement pitch of the openings OP. The arrangement pitch of the shield parts 55 is also equal to the arrangement pitch of the pixels PX. Alternatively, the arrangement pitch of the shield parts 55 can be n times the arrangement pitch of the pixels PX or 1 / n (n is an integer).

[0077] The first shield layer CES1 and the second shield layer CES2 are electrically connected at any location. In this embodiment, multiple shield parts 55 are connected via connection parts CNx and CNY. Therefore, it is sufficient that the first shield layer CES1 and the second shield layer CES2 are electrically connected at at least one location, and there is no need to form a connection structure such as a contact hole for each of the multiple shield parts 55.

[0078] 9 are merely examples and may be modified as appropriate. The opening OP and the shield part 55 may have an irregular shape, such as a square, polygonal, parallelogram, circle, ellipse, or a notch. The shape of the opening OP and the shape of the shield part 55 may be different from each other.

[0079] Fig. 10 is a cross-sectional view taken along the line X-X' in Fig. 8. Note that Fig. 10 schematically shows the stacked structure of the signal lines SL and the scanning lines GL, and omits transistors and the like that constitute the signal line connecting circuit 30 and the gate driver circuit 18.

[0080] 10, the first shield layer CES1 is formed in the same layer as the detection electrode DE and from the same material. The second shield layer CES2 (shield portion 55 and connection portion CN) is formed in the same layer as the pixel electrode PE and from the same material. A sixth insulating film 16 is provided between the first shield layer CES1 and the second shield layer CES2 in a direction perpendicular to the first insulating substrate 10. The ion trapping electrodes ITL1 and ITL2, the branch electrode ITL3, and the third shield layer CES3 are also formed in the same layer as the second shield layer CES2 and the pixel electrode PE and from the same material. In other words, the first shield layer CES1, the second shield layer CES2, the ion trapping electrodes ITL1 and ITL2, and the third shield layer CES3 are made of a light-transmitting conductive material such as ITO.

[0081] The insulating film 17 is provided to cover the second shield layer CES2, the ion trapping electrode ITL1, the ion trapping electrode ITL2, and the third shield layer CES3. The insulating film 17 is formed as the first alignment film AL1 in the display area DA. The sealing portion 58 is provided on the periphery of the first insulating substrate 10 and overlaps with a portion of the third shield layer CES3.

[0082] Below the ion trap electrode ITL1, a lower-layer connection wiring ITL1s is routed so as to run parallel to the ion trap electrode ITL1 on the third insulating film 13. Between the ion trap electrode ITL1 and the ion trap electrode ITL2, a lower-layer connection wiring CLs is routed on the third insulating film 13. A reference potential that is the same as the common potential applied to the detection electrode DE during display is applied to the lower-layer connection wiring CLs.

[0083] The first shield layer CES1 and the second shield layer CES2 are provided to overlap the signal lines SL connected to the signal line connecting circuit 30 and the scanning lines GL connected to the gate driver circuit 18. Furthermore, a plurality of openings OP are provided in the first shield layer CES1, and the second shield layer CES2 is provided above the openings OP with a sixth insulating film 16 interposed therebetween.

[0084] As a result, even if an opening OP is provided in the first shield layer CES1, the first shield layer CES1 and the second shield layer CES2 can effectively shield the electric field generated in the signal line connecting circuit 30 and various wirings.

[0085] Furthermore, moisture may enter the fourth insulating film 14 made of an organic material from the outside (for example, from the outer periphery of the first insulating substrate 10). Because the first shield layer CES1 has openings OP, moisture that enters the fourth insulating film 14 escapes to the outside through the openings OP. Furthermore, because the multiple shield parts 55 of the second shield layer CES2 are arranged at intervals SPx and SPy, moisture that passes through the openings OP escapes to the outside through the intervals SPx and SPy.

[0086] As a result, even if moisture penetrates the fourth insulating film 14, the opening OP and the gaps SPx and SPy form a path for the moisture to pass through, and the first shield layer CES1 and the second shield layer CES2 can efficiently release the moisture to the outside. As a result, moisture can be prevented from accumulating between the first shield layer CES1 and the second shield layer CES2 and each insulating film. As a result, the display device 1 can prevent film peeling of the first shield layer CES1 and the second shield layer CES2 caused by moisture in the fourth insulating film 14.

[0087] Fig. 11 is a partial enlarged view of portion Q11 in Fig. 8. In Fig. 11, to make the drawing easier to see, the outer shape of the first shield layer CES1 is shown by a two-dot chain line, and the opening OP and the second shield layer CES2 are omitted.

[0088] As shown in FIG. 11, the signal line connection circuit 30 includes a plurality of switching circuit sections 30S. The plurality of switching circuit sections 30S are provided corresponding to the pixels PX arranged in the first direction Dx, respectively, and are arranged along the curved portion DAc. The plurality of switching circuit sections 30S are configured with a plurality of transistors. The plurality of switching circuit sections 30S may be arranged so that they have different inclination angles. Furthermore, the plurality of switching circuit sections 30S may be arranged so that they are spaced apart at different intervals.

[0089] As the distance between the gate driver circuit 18 and the boundary BL of the curved portion DAc decreases, the width in the first direction Dx occupied by the wiring area LA, the signal line connection circuit 30, and the wiring area TA decreases. Accordingly, the shape and orientation of the switching circuit section 30S on the end side of the signal line connection circuit 30 may be changed.

[0090] For example, the switching circuit unit 30S at the end of the curved portion DAc (the position farthest from the terminal T1 (see FIG. 5)) may be oriented in a different direction from the other switching circuit units 30S, and may be provided so that its long side is aligned with the second direction Dy. This makes it possible to reduce the size of the curved portion DAc.

[0091] The gate driver circuit 18 includes a plurality of transfer circuits 18S. The plurality of transfer circuits 18S are arranged along the outer periphery 10s of the first insulating substrate 10 so as to form a curved shape as a whole. The plurality of transfer circuits 18S are arranged with different inclination angles. The plurality of transfer circuits 18S may also be arranged at different intervals.

[0092] The scanning lines GL connected to the transfer circuits 18S respectively extend in the second direction Dy, intersecting with the ion trapping electrodes ITL1 and ITL2. Furthermore, the scanning lines GL intersect with the wiring area LA (wiring 53), pass between adjacent switching circuit units 30S, and intersect with the wiring area TA (signal lines SL) to be connected to the pixels PX.

[0093] 12 is a cross-sectional view taken along line XII-XII' in FIG. 11. The lower-layer connection wiring ITL1s is provided on the third insulating film 13. The lower-layer connection wiring ITL1s is a conductive layer that supplies the VGL potential. The lower-layer connection wiring ITL1s is formed in the same layer and from the same material as the signal line SL.

[0094] The lower layer connection wiring ITL1s is covered with a fourth insulating film 14.

[0095] The relay conductive layer ITM is provided on the fourth insulating film 14. The relay conductive layer ITM is formed in the same layer and from the same material as the relay electrode 65 and the sensor wiring TL shown in FIG.

[0096] In this way, the ion trapping electrode ITL1 is connected to the lower layer connection wiring ITL1s via contact holes H13 at predetermined intervals. The lower layer connection wiring ITL1s is, for example, a metal wiring provided in the same layer as the signal line SL. The VGL potential is applied to the ion trapping electrodes ITL1 and ITL2 via the lower layer connection wiring ITL1s.

[0097] In this way, the first shield layer CES1 and the second shield layer CES2 overlap the wiring area LA (wiring 53), the switching circuit section 30S, the wiring area TA (signal lines SL), and the area where the scanning lines GL are provided, thereby enabling the first shield layer CES1 and the second shield layer CES2 to effectively shield the electric field around the curved portion DAc.

[0098] 13 is a plan view showing a shield layer and ion trap electrodes according to a comparative example, which are arranged adjacent to a display area at a curved corner. As shown in FIG. 13, ion trap electrodes ITL1 and ITL2 according to the comparative example are folded back at a connection portion ITLx to form a U-shape. Because connection portion ITLx is close to pad electrode 10S, portions of ion trap electrodes ITL1 and ITL2 fall within a range of a predetermined distance Lag from first edge 20s1 of second insulating substrate 20.

[0099] For example, if saltwater were to remain in the protruding portion 10A for a long period of time in a harsh environment, the saltwater could react with the silver of the conductive pillar 10P shown in FIG. 2B, potentially causing compounds resulting from the components of the silver paste to precipitate within a predetermined distance Lag. The predetermined distance Lag is, for example, 1.4 mm. The precipitates are often conductive, and could cause unintended currents to flow between the third shield layer CES3 and the ion trapping electrode ITL1, or between the shield layer CES (the first shield layer CES1 and the second shield layer CES2) and the ion trapping electrode ITL2, which are at different potentials, potentially impairing the functionality of the gate driver circuit 18 and the signal line connection circuit 30.

[0100] In contrast, the display device 1 of the embodiment includes an ion trap electrode ITL1, an ion trap electrode ITL2, and a branch electrode ITL3. The ion trap electrode ITL1 is disposed between the shield layer CES and the gate driver circuit 18, linearly arranged along the gate driver circuit 18, and supplied with a constant potential. The second ion trap electrode ITL2 is disposed between the shield layer CES and the first ion trap electrode ITL1, linearly arranged along the edge of the shield layer CES. The second ion trap electrode ITL2 is supplied with the same potential as the ion trap electrode ITL1. The branch electrode ITL3 is a branch portion where the linear second ion trap electrode ITL2 branches off from the linear first ion trap electrode ITL1. This eliminates the need to connect the first ion trap electrode ITL1 and the second ion trap electrode ITL2 in a U-shape. As shown in FIG. 8, it is possible to prevent a portion of the ion trapping electrodes ITL1 and ITL2 from being within a range of a predetermined distance Lag from the first side 20s1 of the second insulating substrate 20.

[0101] The other ends of the ion trap electrodes ITL1 and ITL2 are located at a predetermined distance Lag from the first edge 20s1 of the second insulating substrate 20. If the predetermined distance Lag is 1.4 mm, the first ion trap electrode ITL1 and the second ion trap electrode ITL2 are not located within a distance of 1.4 mm from the first edge 20s1 of the counter substrate SUB2 adjacent to the protruding portion 10A of the array substrate SUB1. This prevents unintended current from flowing between the third shield layer CES3 and the ion trap electrode ITL1, which have different potentials, or between the shield layer CES and the ion trap electrode ITL2, which have different potentials, within the area where compounds resulting from the components of the silver paste are deposited. This reduces the possibility of impairing the functions of the gate driver circuit 18 and the signal line connection circuit 30, improving the reliability of the display device 1.

[0102] As described above, the larger the distance between the gate driver circuit 18 and the shield layer CES around the curved portion DAc, the larger the distance between the first ion trapping electrode ITL1 and the second ion trapping electrode ITL2. The second ion trapping electrode ITL2 is provided along the edge of the shield layer CES, and the edge of the shield layer CES is gradually larger than the edge of the third shield layer CES3, so the length from the branch electrode ITL3 to the other end of the second ion trapping electrode ITL2 is longer than the length from the branch electrode ITL3 to the other end of the first ion trapping electrode ITL1.

[0103] Each pixel of the display device 1 has a plurality of detection electrodes DE (first electrodes) and a plurality of pixel electrodes PE (second electrodes) stacked in this order with insulating films interposed therebetween. Therefore, the conductive layer 21 can reduce static electricity applied to the liquid crystal layer LC in a display device that utilizes a lateral electric field formed between the pixel electrodes PE and a common electrode (detection electrode DE) provided on the array substrate SUB1. To use the conductive layer 21 as a reference potential, the display device 1 has a pad electrode 10S on the protruding portion 10A of the array substrate SUB1 exposed from the counter substrate SUB2, and a conductive pillar OP provided on the pad electrode 10S is electrically connected to the conductive layer 21.

[0104] The shield layer CES has a connection wiring CL that supplies a potential, and the connection wiring CL does not intersect with the second ion trapping electrode ITL2 or the branch electrode ITL3, so that the connection wiring CL does not short-circuit with the second ion trapping electrode ITL2 or the branch electrode ITL3.

[0105] Although preferred embodiments of the present disclosure have been described above, the present disclosure is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible within the scope of the present disclosure. Appropriate modifications made within the scope of the present disclosure naturally fall within the technical scope of the present disclosure. At least one of various omissions, substitutions, and modifications of components can be made within the scope of the gist of each of the above-described embodiments and modifications.

[0106] For example, the wiring area LA may be provided with the ion trap electrode of Patent Document 2 on the first side sDA1 described above. The above-described embodiment includes the ion trap electrode of Patent Document 2, and thus includes an aspect in which ion trap electrodes are arranged on the first side sDA1, the second side sDA2, the third side sDA3, the fourth side sDA4, and the curved portion DAc.

[0107] The plane defined by the first direction Dx and the second direction Dy is parallel to the surface of the array substrate SUB1, but the surface of the array substrate SUB1 may be curved. In this case, when viewed from the direction in which the display device 1 is viewed at its maximum area, a predetermined direction becomes the first direction, and a direction intersecting the first direction becomes the second direction. The direction in which the display device 1 is viewed at its maximum area may be defined as a third direction perpendicular to the first and second directions. [Explanation of symbols]

[0108] 1 Display device 10 First insulating substrate 18 Gate Drivers 20 Second insulating substrate 30 Signal line connection circuit 53 Wiring 51 Sensor wiring 101 wiring board 110 Driver IC BE peripheral area (second area) CES shielding layer CES1 1st shield layer CES2 Second Shield Layer CES3 3rd shield layer DA display area (1st area) CL connecting electrode DAc curved section DE detection electrode ITL1, ITL2 ion trap electrodes LA, TA wiring area OP Opening PE pixel electrode SUB1 array board SUB2 opposing substrate T1 terminal

Claims

1. an array substrate; a first region provided on the array substrate; a second region provided on the array substrate and positioned between an end of the array substrate and the first region; the first region includes a plurality of scanning lines extending in a first direction, a plurality of signal lines extending in a second direction, and a plurality of pixels; the first region has a first side, a second side, a third side, a fourth side, and a plurality of curved portions; a signal line connection circuit disposed in the second region and connected to the plurality of signal lines; a shielding layer disposed in the second region and covering at least a portion of the signal line connecting circuit around at least one of the curved portions; a gate driver circuit disposed in the second region outside the signal line connection circuit and connected to the plurality of scanning lines; a first ion trap electrode disposed between the shield layer and the gate driver circuit, linearly provided along the gate driver circuit, and supplied with a constant potential; a second ion trap electrode disposed between the shield layer and the first ion trap electrode, provided linearly along an edge of the shield layer, and supplied with the same potential as the first ion trap electrode; a branch electrode that branches off the second ion trap electrode from the middle of the linear first ion trap electrode, a length from the branch electrode to an end of the second ion trap electrode is longer than a length from the branch electrode to an end of the first ion trap electrode; Display device.

2. the greater the distance between the gate driver circuit and the shield layer, the greater the distance between the first ion trapping electrode and the second ion trapping electrode; The display device according to claim 1 .

3. the pixel has a first electrode, an insulating film on the first electrode, and a second electrode on the insulating film; a counter substrate superimposed on the array substrate, a conductive layer covers a surface of the counter substrate opposite to the array substrate; a pad electrode is provided on a protruding portion of the array substrate exposed from the opposing substrate; a conductive pillar provided on the pad electrode is electrically connected to the conductive layer; The display device according to claim 1 .

4. the first ion trapping electrode and the second ion trapping electrode are not present within a distance of 1.4 mm from the side of the opposing substrate adjacent to the protruding portion of the array substrate; The display device according to claim 3 .

5. a potential different from the potentials applied to the first ion trap electrode and the second ion trap electrode is supplied to the shield layer; The display device according to claim 1 .

6. the first ion trap electrode and the second ion trap electrode are in the same layer as at least a part of the shield layer and do not overlap with the shield layer in a plan view; The display device according to claim 1 .

7. The display device according to claim 1 , further comprising a connection wiring for supplying a potential to the shield layer, the connection wiring not intersecting the second ion trap electrode and the branch electrode.

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