Method for driving an electro-optic display

Abstract

The present invention provides a method and associated apparatus for driving an electro-optic display having an electrophoretic display medium electrically coupled between a common electrode and a display pixel associated with a display pixel electrode, and n-type transistors electrically coupled to a display controller circuit capable of applying a waveform comprising a frame to the display pixel by applying a voltage to the common electrode and the display pixel electrode via the n-type transistor. The method includes applying one or more waveforms to the display pixel to drive the electrophoretic display medium adjacent to the display pixel to a first optical state, and utilizing a leakage conduction effect of the n-type transistor to release residual voltage from the electrophoretic display medium.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Patent Application No. 63 / 275,515, filed November 4, 2021, the entire contents of which are incorporated herein. Additionally, the entire contents of any patents, published applications, or other published works referenced herein are incorporated herein by reference in their entirety.

[0002] FIELD OF THE INVENTION This invention relates to reflective electro-optic displays and materials for use in such displays. More particularly, this invention relates to displays with reduced remnant voltage and to driving methods that reduce remnant voltage in electro-optic displays. [Background technology]

[0003] Electro-optic displays driven by direct current (DC) imbalanced waveforms can develop remnant voltages, which can be identified by measuring the open-circuit electrochemical potential of the display pixels. Remnant voltages have been found to be a more common phenomenon in electrophoretic and other impulse-driven electro-optic displays, both in cause and effect. It has also been found that DC imbalances can cause long-term lifetime degradation of some electrophoretic displays.

[0004] The term "residual voltage" is also sometimes used as a convenient term to refer to the overall phenomenon. However, the basis for the switching behavior of impulse-driven electro-optic displays is the application of a voltage impulse (the integral of voltage over time) across the electro-optic medium. The remnant voltage may reach a peak value shortly after application of the drive pulse and then decay substantially exponentially. The persistence of the remnant voltage for a significant period of time applies a "residual impulse" to the electro-optic medium, and it is this remnant impulse, not strictly speaking a remnant voltage, that may be responsible for the effects on the optical state of the electro-optic display that are typically thought to be caused by the remnant voltage.

[0005] In theory, the effect of the remnant voltage should directly correspond to the remnant impulse. However, in practice, the impulse switching model can lose accuracy at low voltages. Some electro-optic media have a threshold such that a remnant voltage of approximately 1 V may not cause a noticeable change in the optical state of the medium after the drive pulse is terminated. However, for other electro-optic media, including the preferred electrophoretic medium used in the experiments described herein, a remnant voltage of approximately 0.5 V can cause a noticeable change in the optical state. Therefore, the two equivalent remnant impulses may differ in actual results, and it may be useful to increase the threshold of the electro-optic medium to reduce the effect of the remnant voltage. E Ink Corporation has produced electrophoretic media with an appropriate "low threshold" to prevent the remnant voltage experienced in some situations after the drive pulse is terminated from immediately changing the display image. If the threshold is incorrect or the remnant voltage is too high, the display may exhibit kickback / self-erase or self-improvement phenomena. The term "optical kickback" is used herein to describe the change in the optical state of a pixel that is caused, at least in part, in response to the release of the pixel's remnant voltage.

[0006] Even when remnant voltages fall below a small threshold, they can have a significant effect on image switching if they still exist when the next image update occurs. For example, assume that during an image update of an electrophoretic display, a + / -15V drive voltage is applied to move electrophoretic particles. If a +1V remnant voltage is present from the previous update, the drive voltage will effectively shift from +15V / -15V to +16V / -14V. As a result, the pixel will be biased toward a dark or white state, depending on whether it has a positive or negative remnant voltage. Furthermore, this effect varies over time due to the decay rate of the remnant voltage. The electro-optic material in a pixel that is switched to white using a 15V, 300ms drive pulse immediately after the previous image update may actually experience a waveform closer to 16V for 300ms, while the material in a pixel that is switched to white one minute later using the exact same drive pulse (15V, 300ms) may actually experience a waveform closer to 15.2V for 300ms. As a result, the pixel may exhibit significantly different shades of white.

[0007] If a remnant voltage field is generated across multiple pixels due to a previous image (e.g., a dark line on a white background), the remnant voltage may also be aligned across the display in a similar pattern. As a practical matter, the most noticeable effect of remnant voltage on display performance may be image retention. This problem, in addition to the problem described previously, i.e., DC imbalance (e.g., 16V / 14V instead of 15V / 15V), may be the cause of slow lifetime degradation of the electro-optic medium.

[0008] If the remnant voltage decays slowly and is nearly constant, its effect in shifting the waveform will not vary with each image update and may in fact not produce as much afterimage as a quickly decaying remnant voltage. Thus, the afterimage experienced by updating one pixel after 10 minutes and another after 11 minutes will be much less than the afterimage experienced by updating one pixel immediately and another after 1 minute. Conversely, a remnant voltage that decays quickly to near zero before the next update occurs may in fact not cause a detectable afterimage.

[0009] There are several potential sources of remnant voltage: One major source of remnant voltage is believed to be ionic polarization within the materials of the various layers that form the display (although some embodiments are not limited in any way by this notion).

[0010] In summary, remnant voltage as a phenomenon can manifest itself at various points as image retention or visual artifacts, with some sensitivity varying with the elapsed time during image update. Remnant voltage can also create DC imbalances and shorten the final display life. The effects of remnant voltage are therefore detrimental to the quality of electrophoretic or other electro-optical devices, and it can be desirable to minimize both the remnant voltage itself and the sensitivity of the device's optical state to the effects of remnant voltage.

[0011] Thus, releasing the remnant voltage in an electro-optic display can improve the quality of the displayed image, even in situations where the remnant voltage is already low. The inventors recognize and understand that conventional techniques for releasing the remnant voltage in an electro-optic display may not completely release the remnant voltage. That is, conventional techniques for releasing the remnant voltage may result in the electro-optic display retaining at least a low remnant voltage. Therefore, techniques are needed to better completely release the remnant voltage from an electro-optic display. Summary of the Invention [Means for solving the problem]

[0012] The present invention provides a method of driving a display pixel of an electro-optic display, the method comprising applying a negative bias voltage to the gate-source of a pixel transistor to induce leakage conduction in the transistor, thereby creating a conduction path for draining residual voltage.

[0013] In one aspect, the invention features an electro-optic display including an electrophoretic display medium electrically coupled between a common electrode and a display pixel electrode associated with a display pixel. The electro-optic display also includes a display controller circuit in electrical communication with the common electrode and n-type transistors associated with the display pixel electrode. The display controller circuit is capable of applying waveforms to the display pixel by applying one or more time-dependent voltages between the common electrode and the display pixel electrode, the one or more time-dependent voltages being applied to the display pixel electrode via the n-type transistor. The display controller circuit is configured to apply the one or more waveforms to the display pixel to drive the electrophoretic display medium adjacent to the display pixel to a first optical state and maintain the display pixel in the first optical state for a hold period. The display controller circuit is also configured to place the display pixel in a floating state, applying substantially zero volts to the common electrode and the display pixel electrode. The display controller circuit is also configured to apply a low gate voltage rail voltage to the gate electrode of the n-type transistor, the low gate voltage rail voltage being a negative voltage of sufficient magnitude to induce a leakage conduction path in the n-type transistor to release residual voltage from the electrophoretic display medium, the low gate voltage rail voltage having a magnitude greater than the gate-off voltage of the n-type transistor.

[0014] In some embodiments, the electro-optic display includes an active matrix of display pixels, and the display pixel is one of the display pixels of the active matrix of display pixels. In some embodiments, each of the one or more waveforms comprises one or more frames. In some embodiments, the hold period comprises one or more frames.

[0015] In some embodiments, a leakage conduction path is formed between the drain electrode of the n-type transistor and the source electrode of the n-type transistor.

[0016] In some embodiments, placing the first display pixel in a floating state includes applying a gate-off voltage to the gate electrode of the n-type transistor, the gate-off voltage being a negative voltage sufficient to prevent formation of a conduction path through the drain electrode of the n-type transistor and the source electrode of the n-type transistor. In some embodiments, placing the first display pixel in a floating state includes disconnecting an electrical connection between the common electrode and a voltage source.

[0017] In some embodiments, maintaining the display pixel in the first optical state for the hold period includes applying substantially equal voltages to the common electrode and the display pixel electrode, and applying a gate-on voltage to the gate electrode of the n-type transistor, the gate-on voltage being a positive voltage sufficient to create a conduction path through the n-type transistor.

[0018] In another aspect, the invention features a method of driving an electro-optic display that includes an electrophoretic display medium electrically coupled between a common electrode and display pixels associated with a display pixel electrode and an n-type transistor electrically coupled to a display controller circuit capable of applying waveforms to the display pixel by applying one or more time-dependent voltages between the common electrode and the display pixel electrode through the n-type transistor, the one or more time-dependent voltages being applied to the display pixel electrode. The method includes, in the following order: (1) applying one or more waveforms to a display pixel to drive an electrophoretic display medium adjacent to the display pixel to a first optical state; (2) maintaining the display pixel in the first optical state for a hold period; (3) placing the display pixel in a floating state; (4) applying substantially zero volts to the common electrode and the display pixel electrode; and (5) applying a low gate voltage rail voltage to the gate electrode of an n-type transistor, the low gate voltage rail voltage being a negative voltage sufficient to induce a leakage conduction path in the n-type transistor to release residual voltage from the electrophoretic display medium, the low gate voltage rail voltage having a magnitude greater than the gate-off voltage of the n-type transistor.

[0019] In some embodiments, the method includes an active matrix of display pixels, and the display pixel is one of the display pixels of the active matrix of display pixels. In some embodiments, each of the one or more waveforms comprises one or more frames. In some embodiments, the hold period comprises one or more frames. In some embodiments, a leakage conduction path is formed between a drain electrode of the n-type transistor and a source electrode of the n-type transistor.

[0020] In some embodiments, placing the first display pixel in a floating state includes applying a gate-off voltage to the gate electrode of the n-type transistor, the gate-off voltage being a negative voltage sufficient to prevent formation of a conduction path through the drain electrode of the n-type transistor and the source electrode of the n-type transistor. In some embodiments, placing the first display pixel in a floating state includes disconnecting an electrical connection between the common electrode and a voltage source.

[0021] In some embodiments, maintaining the display pixel in the first optical state for the hold period includes applying substantially equal voltages to the common electrode and the display pixel electrode, and applying a gate-on voltage to the gate electrode of the n-type transistor, the gate-on voltage being a positive voltage sufficient to create a conduction path through the n-type transistor.

[0022] In another aspect, the invention features an electro-optic display including an electrophoretic display medium electrically coupled between a common electrode and a display pixel electrode associated with a display pixel. The electro-optic display includes a display controller circuit in electrical communication with the common electrode and n-type transistors associated with the display pixel electrodes. The display controller circuit is capable of applying waveforms to the display pixels by applying one or more time-dependent voltages between the common electrode and the display pixel electrodes via the n-type transistors, the one or more time-dependent voltages being applied to the display pixel electrodes. The display controller circuit is configured to apply the one or more waveforms to the display pixels to drive electrophoretic display media adjacent to the display pixels to a first optical state. The display controller circuit is also configured to apply substantially zero volts to the common electrode and the display pixel electrodes and to apply a low gate voltage rail voltage to the gate electrodes of the n-type transistors, the low gate voltage rail voltage being a negative voltage sufficient to induce a leakage conduction path in the n-type transistor to release residual voltage from the electrophoretic display medium, the low gate voltage rail voltage having a magnitude greater than a gate-off voltage of the n-type transistor.

[0023] In some embodiments, the electro-optic display includes an active matrix of display pixels, and the display pixel is one of the display pixels of the active matrix of display pixels. In some embodiments, each of the one or more waveforms includes one or more frames. In some embodiments, the hold period includes one or more frames.

[0024] In some embodiments, a leakage conduction path is formed between the drain electrode of the n-type transistor and the source electrode of the n-type transistor.

[0025] In another aspect, the invention features a method of driving an electro-optic display that includes an electrophoretic display medium electrically coupled between a common electrode and a display pixel, the display pixel associated with a display pixel electrode and an n-type transistor electrically coupled to a display controller circuit capable of applying waveforms to the display pixel by applying one or more time-dependent voltages between the common electrode and the display pixel electrode via the n-type transistor, the one or more time-dependent voltages being applied to the display pixel electrode. The method includes, in the following order: (1) applying one or more waveforms to a display pixel to drive an electrophoretic display medium adjacent to the display pixel to a first optical state; (2) applying substantially zero volts to a common electrode and a display pixel electrode; and (3) applying a low gate voltage rail voltage to a gate electrode of an n-type transistor, the low gate voltage rail voltage being a negative voltage of sufficient magnitude to induce a leakage conduction path in the n-type transistor to release residual voltage from the electrophoretic display medium, the low gate voltage rail voltage having a magnitude greater than a gate-off voltage of the n-type transistor.

[0026] In some embodiments, the electro-optic display includes an active matrix of display pixels, and the display pixel is one of the display pixels of the active matrix of display pixels.

[0027] In some embodiments, each of the one or more waveforms includes one or more frames. In some embodiments, the hold period consists of one or more frames. In some embodiments, a leakage conduction path is formed between the drain electrode of the n-type transistor and the source electrode of the n-type transistor. The present specification also provides, for example, the following: (Item 1) 1. An electro-optic display, comprising: an electrophoretic display medium electrically coupled between a common electrode and a display pixel electrode associated with the display pixel; a display controller circuit in electrical communication with the common electrode and the n-type transistor associated with the display pixel electrode; Equipped with the display controller circuit is capable of applying waveforms to the display pixels by applying one or more time-dependent voltages between the common electrode and the display pixel electrodes, the one or more time-dependent voltages being applied to the display pixel electrodes via the n-type transistors; The display controller circuit applying one or more waveforms to the display pixels to drive the electrophoretic display media adjacent to the display pixels to a first optical state; maintaining the display pixel in the first optical state for a hold period; placing the display pixel in a floating state; applying substantially zero volts to the common electrode and the display pixel electrode; applying a low gate voltage rail voltage to the gate electrode of said n-type transistor; configured to: An electro-optic display, wherein the low gate voltage rail voltage is a negative voltage of sufficient magnitude to induce a leakage conduction path in the n-type transistor to release residual voltage from the electrophoretic display medium, and the low gate voltage rail voltage has a magnitude greater than the gate-off voltage of the n-type transistor. (Item 2) Item 10. An electro-optic display as described in item 1, further comprising an active matrix of display pixels, the display pixel being one of the display pixels of the active matrix of display pixels. (Item 3) Item 3. An electro-optic display as described in item 2, wherein each of the one or more waveforms comprises one or more frames. (Item 4) Item 4. An electro-optic display as described in item 3, wherein the hold period comprises one or more frames. (Item 5) Item 2. An electro-optic display as described in item 1, wherein the leakage conduction path is formed between the drain electrode of the n-type transistor and the source electrode of the n-type transistor. (Item 6) 2. The electro-optic display of claim 1, wherein placing the first display pixel in a floating state includes applying a gate-off voltage to the gate electrode of the n-type transistor, the gate-off voltage being a negative voltage sufficient to prevent the formation of a conduction path through the drain electrode of the n-type transistor and the source electrode of the n-type transistor. (Item 7) Item 10. The electro-optic display of item 1, wherein placing the first display pixel in a floating state comprises disconnecting an electrical connection between the common electrode and a voltage source. (Item 8) maintaining the display pixel in the first optical state for the hold period; applying substantially equal voltages to the common electrode and the display pixel electrode; applying a gate-on voltage to the gate electrode of the n-type transistor; Including, Item 2. An electro-optic display as described in item 1, wherein the gate-on voltage is a positive voltage sufficient to create a conduction path through the n-type transistor. (Item 9) 1. A method of driving an electro-optic display, the electro-optic display comprising an electrophoretic display medium electrically coupled between a common electrode and a display pixel associated with a display pixel electrode, the display pixel associated with an n-type transistor electrically coupled to the display pixel electrode and to a display controller circuit, the display controller circuit being capable of applying waveforms to the display pixels by applying one or more time-dependent voltages between the common electrode and the display pixel electrode via the n-type transistor, the one or more time-dependent voltages being applied to the display pixel electrode; The method comprises, in order: applying one or more waveforms to the display pixels to drive the electrophoretic display media adjacent to the display pixels to a first optical state; maintaining the display pixel in the first optical state for a hold period; placing the display pixels in a floating state; applying substantially zero volts to the common electrode and the display pixel electrode; applying a low gate voltage rail voltage to the gate electrode of said n-type transistor; Including, The method wherein the low gate voltage rail voltage is a negative voltage of sufficient magnitude to induce a leakage conduction path in the n-type transistor to release residual voltage from the electrophoretic display medium, and the low gate voltage rail voltage has a magnitude greater than a gate-off voltage of the n-type transistor. (Item 10) 10. The method of claim 9, further comprising an active matrix of display pixels, the display pixel being one of the display pixels of the active matrix of display pixels. (Item 11) Item 11. The method of item 10, wherein each of the one or more waveforms comprises one or more frames. (Item 12) Item 12. The method of item 11, wherein the retention period comprises one or more frames. (Item 13) Item 10. The method of item 9, wherein the leakage conduction path is formed between a drain electrode of the n-type transistor and a source electrode of the n-type transistor. (Item 14) 10. The method of claim 9, wherein placing the first display pixel in a floating state comprises applying a gate-off voltage to a gate electrode of the n-type transistor, the gate-off voltage being a negative voltage sufficient to prevent formation of a conduction path through a drain electrode of the n-type transistor and a source electrode of the n-type transistor. (Item 15) Item 10. The method of item 9, wherein placing the first display pixel in a floating state includes disconnecting an electrical connection between the common electrode and a voltage source. (Item 16) maintaining the display pixel in the first optical state for the hold period; applying substantially equal voltages to the common electrode and the display pixel electrode; applying a gate-on voltage to the gate electrode of the n-type transistor; Including, Item 10. The method of item 9, wherein the gate-on voltage is a positive voltage sufficient to create a conduction path through the n-type transistor. (Item 17) 1. An electro-optic display, comprising: an electrophoretic display medium electrically coupled between a common electrode and a display pixel electrode associated with the display pixel; a display controller circuit in electrical communication with the common electrode and the n-type transistor associated with the display pixel electrode; Equipped with the display controller circuit is capable of applying waveforms to the display pixels by applying one or more time-dependent voltages between the common electrode and the display pixel electrodes via n-type transistors, the one or more time-dependent voltages being applied to the display pixel electrodes; The display controller circuit applying one or more waveforms to the display pixels to drive the electrophoretic display media adjacent to the display pixels to a first optical state; applying substantially zero volts to the common electrode and the display pixel electrode; applying a low gate voltage rail voltage to the gate electrode of said n-type transistor; configured to: An electro-optic display, wherein the low gate voltage rail voltage is a negative voltage of sufficient magnitude to induce a leakage conduction path in the n-type transistor to release residual voltage from the electrophoretic display medium, and the low gate voltage rail voltage has a magnitude greater than the gate-off voltage of the n-type transistor. (Item 18) Item 18. An electro-optic display according to item 17, further comprising an active matrix of display pixels, the display pixel being one of the display pixels of the active matrix of display pixels. (Item 19) Item 19. An electro-optic display as described in item 18, wherein each of the one or more waveforms comprises one or more frames. (Item 20) 20. An electro-optic display as described in item 19, wherein the hold period comprises one or more frames. (Item 21) Item 18. An electro-optic display as described in item 17, wherein a conductive path is formed between the drain electrode of the n-type transistor and the source electrode of the n-type transistor. (Item 22) 1. A method of driving an electro-optic display, the electro-optic display comprising an electrophoretic display medium electrically coupled between a common electrode and a display pixel associated with a display pixel electrode, the display pixel associated with an n-type transistor electrically coupled to the display pixel electrode and to a display controller circuit, the display controller circuit being capable of applying waveforms to the display pixels by applying one or more time-dependent voltages between the common electrode and the display pixel electrode via the n-type transistor, the one or more time-dependent voltages being applied to the display pixel electrode; The method comprises, in order: applying one or more waveforms to the display pixels to drive the electrophoretic display media adjacent to the display pixels to a first optical state; applying substantially zero volts to the common electrode and the display pixel electrode; applying a low gate voltage rail voltage to the gate electrode of said n-type transistor; Including, The method wherein the low gate voltage rail voltage is a negative voltage of sufficient magnitude to induce a leakage conduction path in the n-type transistor to release residual voltage from the electrophoretic display medium, and the low gate voltage rail voltage has a magnitude greater than a gate-off voltage of the n-type transistor. (Item 23) Item 23. The method of item 22, further comprising an active matrix of display pixels, the display pixel being one of the display pixels of the active matrix of display pixels. (Item 24) 24. The method of claim 23, wherein each of the one or more waveforms comprises one or more frames. (Item 25) Item 25. The method of item 24, wherein the retention period comprises one or more frames. (Item 26) Item 23. The method of item 22, wherein the leakage conduction path is formed between a drain electrode of the n-type transistor and a source electrode of the n-type transistor. [Brief explanation of the drawings]

[0028] [Figure 1] FIG. 1 is a circuit diagram illustrating an electrophoretic display in accordance with the presently disclosed subject matter.

[0029] [Figure 2] FIG. 2 illustrates a circuit model of an electro-optic imaging layer in accordance with the subject matter disclosed herein.

[0030] [Figure 3] FIG. 3 illustrates the conduction map of a transistor in response to an applied gate voltage.

[0031] [Figure 4] FIG. 4 illustrates one embodiment of a drive sequence in accordance with the subject matter disclosed herein.

[0032] [Figure 5] FIG. 5 illustrates another embodiment of a drive sequence in accordance with the subject matter disclosed herein.

[0033] [Figure 6] FIG. 6 illustrates a comparison of residual voltage release effectiveness using different gate voltages. DETAILED DESCRIPTION OF THE INVENTION

[0034] The term "electro-optic," as applied to a material or display, is used in its conventional sense in the imaging arts and is used herein to refer to a material having first and second display states that differ in at least one optical property, the material being changed from its first to its second display state by the application of an electric field to the material. The optical property is typically color perceptible to the human eye, but may be another optical property such as optical transmittance, reflectance, luminescence, or, in the case of displays intended for machine-reading, pseudocolor in the sense of a change in reflection of electromagnetic wavelengths outside the visible range.

[0035] The term “gray state” is used herein in its conventional sense in the imaging arts to refer to a state intermediate between two extreme pixel optical states, and does not necessarily imply a transition between these two extreme states of black and white. For example, several electrophoretic ink patents and published applications referenced below describe electrophoretic displays whose extreme states are white and dark blue, whereby the intermediate “gray state” is actually light blue. In fact, as noted above, a change in optical state may not be a change in color at all. The terms “black” and “white” may be used hereinafter to refer to the two extreme optical states of a display and should be understood to generally include extreme optical states that are not strictly black and white, such as the aforementioned white and dark blue states. The term “monochrome” may hereinafter be used to refer to a display drive scheme that drives pixels exclusively to their two extreme optical states, with no intervening gray states.

[0036] Much of the following discussion will focus on methods for driving one or more pixels of an electro-optic display through a transition from an initial gray level to a final gray level (which may or may not differ from the initial gray level). The term "waveform" will be used to refer to the overall voltage versus time curve used to effect a transition from a particular initial gray level to a particular final gray level. Typically, such a waveform will comprise multiple waveform elements: if these elements are essentially rectangular (i.e., if a given element comprises the application of a constant voltage for a period of time), the element may be referred to as a "pulse" or "drive pulse." The term "drive scheme" refers to a set of waveforms sufficient to effect all possible transitions between gray levels for a particular display. A display may utilize more than one drive scheme: for example, the aforementioned U.S. Patent No. 7,012,600 teaches that a drive scheme may need to be modified depending on parameters such as the temperature of the display or the amount of time it has been in operation during its lifetime, and thus a display may have multiple different drive schemes for use at different temperatures, etc. A set of drive schemes used in this manner may be referred to as a "set of related drive schemes." As described in some of the aforementioned MEDEOD applications, it is also possible to use two or more drive schemes simultaneously in different areas of the same display, and a set of drive schemes used in this way may be referred to as a "set of simultaneous drive schemes."

[0037] Some electro-optic materials are solid, in the sense that the material has a solid exterior surface, but the material can, and often does, have an interior liquid- or gas-filled space. Such displays using solid electro-optic materials may hereinafter be referred to for convenience as "solid electro-optic displays." Thus, the term "solid electro-optic display" includes rotating dichroic member displays, encapsulated electrophoretic displays, microcell electrophoretic displays, and encapsulated liquid crystal displays.

[0038] The terms "bistable" and "bistable" are used herein in their conventional sense in the art to refer to displays comprising display elements having first and second display states that differ in at least one optical property, where a given element is driven with a finite-duration address pulse to exhibit either the first or second display state, and after the address pulse terminates, that state persists for at least several times, e.g., at least four times, the minimum duration of the address pulse required to change the state of the display element. U.S. Patent No. 7,170,670 shows that some grayscale-capable particle-based electrophoretic displays are stable not only in their extreme black and white states but also in their intermediate gray states, and the same is true for several other types of electro-optic displays. Displays of this type are properly referred to as "multistable" rather than bistable, although for convenience, the term "bistable" may be used herein to encompass both bistable and multistable displays.

[0039] Several types of electro-optic displays are known. One type of electro-optic display is the rotating dichroic member type, as described in, for example, U.S. Patent Nos. 5,808,783, 5,777,782, 5,760,761, 6,054,071, 6,055,091, 6,097,531, 6,128,124, 6,137,467, and 6,147,791. (This type of display is often referred to as a "rotating dichroic ball" display, but in some of the aforementioned patents, the term "rotating dichroic member" is preferred as it is more accurate because the rotating member is not spherical.) Such displays use a large number of small bodies (typically spherical or cylindrical) that have two or more segments with different optical properties and an internal dipole. These bodies are suspended within liquid-filled vacuoles in a matrix, and the vacuoles are filled with liquid so that the bodies are free to rotate. The appearance of the display is changed by applying an electric field to the display, thus rotating the bodies to various positions and varying the positions of segments of the bodies seen through the viewing surface. This type of electro-optic medium is typically bistable.

[0040] One type of electro-optic display that has been the subject of research and development for many years is the particle-based electrophoretic display, in which a plurality of charged particles move through a fluid under the influence of an electric field. Electrophoretic displays can have attributes of good brightness and contrast, wide viewing angles, state bistability, and low power consumption when compared to liquid crystal displays. Nevertheless, issues with the long-term image quality of these displays have prevented their widespread use. For example, the particles that make up electrophoretic displays tend to settle, resulting in inadequate useful life for these displays.

[0041] As mentioned above, electrophoretic media require the presence of a fluid. In most prior art electrophoretic media, the fluid is a liquid, but electrophoretic media can also be generated using gaseous fluids (see, for example, Kitamura, T., et al., "Electrical toner movement for electronic paper-like display," IDW Japan, 2001, Paper HCS1-1, and Yamaguchi, Y., et al., "Toner display using insulative particles charged triboelectrically," IDW Japan, 2001, Paper AMD4-4). See also U.S. Patent Nos. 7,321,459 and 7,236,291. Such gas-based electrophoretic media are believed to be susceptible to the same types of problems as liquid-based electrophoretic media due to particle settling when used in an orientation that allows such settling, such as, for example, in a sign where the medium is placed on a vertical surface. In fact, particle settling is believed to be a more serious problem in gas-based electrophoretic media than in liquid-based electrophoretic media because the lower viscosity of the gaseous suspending fluid compared to the viscosity of the fluid allows for faster settling of the electrophoretic particles.

[0042] Numerous patents and applications assigned to or in the name of the Massachusetts Institute of Technology (MIT) and E Ink Corporation describe various techniques used in encapsulated electrophoretic and other electro-optic media. Such encapsulated media comprise a number of small capsules, each of which itself comprises an internal phase containing electrophoretically mobile particles in a fluid medium and a capsule wall surrounding the internal phase. Typically, the capsules themselves are held in a polymer adhesive, forming a coherent layer positioned between two electrodes. Techniques described in these patents and applications include the following:

[0043] (a) electrophoretic particles, fluids, and fluid additives (see, e.g., U.S. Patent Nos. 7,002,728 and 7,679,814);

[0044] (b) capsules, binders, and encapsulation processes (see, e.g., U.S. Patent Nos. 6,922,276 and 7,411,719);

[0045] (c) microcell structures, wall materials, and methods of forming the microcells (see, e.g., U.S. Patent Nos. 7,072,095 and 9,279,906);

[0046] (d) methods of filling and sealing microcells (see, e.g., U.S. Patent Nos. 7,144,942 and 7,715,088);

[0047] (e) films and subassemblies containing electro-optical materials (see, e.g., U.S. Patent Nos. 6,982,178 and 7,839,564);

[0048] (f) backplanes, adhesive layers, and other auxiliary layers and methods used in displays (see, e.g., U.S. Patent Nos. 7,116,318 and 7,535,624);

[0049] (g) color formation and color control (see, e.g., U.S. Patent Nos. 7,075,502 and 7,839,564);

[0050] (h) display applications (see, e.g., U.S. Patent Nos. 7,312,784 and 8,009,348);

[0051] (i) non-electrophoretic display (see, e.g., U.S. Patent No. 6,241,921 and U.S. Patent Application Publication No. 2015 / 0,277,160) and non-display applications of encapsulation and microcell technology (see, e.g., U.S. Patent Application Publication Nos. 2015 / 0,005,720 and 2016 / 0,012,710); and

[0052] Methods of driving displays: (e.g., U.S. Patent Nos. 5,930,026, 6,445,489, 6,504,524, 6,512,354, 6,531,997, 6,753,999, 6,825,970, 6,900,851, 6,995,550, 7,012,600, 7,023,420, 7,034,783, 7,061,166, 7,061,662, 7,116,466, 7,119,772, 7,177,066, 7,193,625, 7,202,847 No. 7,242,514, No. 7,259,744, No. 7,304,787, No. 7,312,794, No. 7,327,511, No. 7,408,699, No. 7,453,445, No. 7,492,339, No. 7,528,822, No. 7,545,358, No. 7, No. 583,251, No. 7,602,374, No. 7,612,760, No. 7,679,599, No. 7,679,813, No. 7,68 No. 3,606, No. 7,688,297, No. 7,729,039, No. 7,733,311, No. 7,733,335, No. 7,787,1 No. 69, No. 7,859,742, No. 7,952,557, No. 7,956,841, No. 7,982,479, No. 7,999,787 No. 8,077,141, No. 8,125,501, No. 8,139,050, No. 8,174,490, No. 8,243,013, No. 8,274,472, No. 8,289,250, No. 8,300,006, No. 8,305,341, No. 8,314,784, No. 8 ,373,649, No.8,384,658, No.8,456,414, No.8,462,102, No.8,537,105, No.8,55 No. 8,783, No. 8,558,785, No. 8,558,786, No. 8,558,855, No. 8,576,164, No. 8,576, No. 259, No. 8,593,396, No. 8,605,032, No. 8,643,595, No. 8,665,206, No. 8,681,191 No. 8,730,153, No. 8,810,525, No. 8,928,562, No. 8,928,641, No. 8,976,444, No. 9,013,394, No. 9,019,197, No. 9,019,198, No. 9,019,318, No. 9,082,352, No. 9,Nos. 171,508, 9,218,773, 9,224,338, 9,224,342, 9,224,344, 9,230,492, 9,251,736, 9,262,973, 9,269,311, 9,299,294, 9,373,289, 9,390,066, 9,390,661, and 9,412,314, and U.S. Patent Application Publication Nos. 2,003 / 0,102,858, 2,004 / 0,246,562, 2,005 / 0,253,777, and 2,007 / 0,070,032 No. 2,007 / 0,076,289, No. 2,007 / 0,091,418, No. 2,007 / 0,103,427, No. 2,007 / 0,176,912, No. 2,007 / 0,296,452, No. 2,008 / 0,024,429, No. 2,008 / 0,024,4 No. 82, No. 2,008 / 0,136,774, No. 2,008 / 0,169,821, No. 2,008 / 0,218,471, No. 2,0 08 / 0,291,129, 2,008 / 0,303,780, 2,009 / 0,174,651, 2,009 / 0,195, No. 568, No. 2,009 / 0,322,721, No. 20,100,194,733, No. 20,100,194,789, No. 20,1 No. 00,220,121, No. 20,100,265,561, No. 20,100,283,804, No. 2,011 / 0,063,314 No. 2,011 / 0,175,875, No. 2,011 / 0,193,840, No. 2,011 / 0,193,841, No. 2,011 / 0,199,671, No. 2,011 / 0,221,740, No. 2,012 / 0,001,957, No. 2,012 / 0,098,74 No. 0, No. 2,013 / 0,063,333, No. 2,013 / 0,194,250, No. 2,013 / 0,249,782, No. 2,01 3 / 0,321,278, 2,014 / 0,009,817, 2,014 / 0,085,355, 2,014 / 0,204,0 No. 12, No. 2,014 / 0,218,277, No. 2,014 / 0,240,210, No. 2,014 / 0,240,373, No. 2,0 14 / 0,253,425, 2,014 / 0,292,830, 2,014 / 0,293,398, 2,014 / 0,333,(See Nos. 685, 2,014 / 0,340,734, 2,015 / 0,070,744, 2,015 / 0,097,877, 2,015 / 0,109,283, 2,015 / 0,213,749, 2,015 / 0,213,765, 2,015 / 0,221,257, 2,015 / 0,262,255, 2,016 / 0,071,465, 2,016 / 0,078,820, 2,016 / 0,093,253, 2,016 / 0,140,910, and 2,016 / 0,180,777).

[0053] Many of the aforementioned patents and applications recognize that the walls surrounding the separate microcapsules in an encapsulated electrophoretic medium may be replaced with a continuous phase, thus producing a so-called polymer-dispersed electrophoretic display, in which the electrophoretic medium comprises a plurality of separate droplets of electrophoretic fluid and a continuous phase of polymer material, and that the separate droplets of electrophoretic fluid in such a polymer-dispersed electrophoretic display may be considered capsules or microcapsules even though a separate capsule membrane is not associated with each individual droplet. See, e.g., aforementioned US Pat. No. 2,002 / 0,131,147. Therefore, for purposes of this application, such polymer-dispersed electrophoretic media are considered a subspecies of encapsulated electrophoretic media.

[0054] A related type of electrophoretic display is the so-called "microcell electrophoretic display." In a microcell electrophoretic display, the charged particles and suspending fluid are not encapsulated in microcapsules, but instead are held within a plurality of cavities formed in a carrier medium, e.g., a polymer film. See, e.g., International Application Publication No. WO 02 / 01,281 and Published U.S. Application No. 2,002 / 0,075,556 (both assigned to Sipix Imaging, Inc.).

[0055] Many of the aforementioned EINK and MIT patents and applications also discuss microcell electrophoretic displays and polymer-dispersed electrophoretic displays. The term "encapsulated electrophoretic displays" can refer to any such display type, which may also be collectively described as "microcavity electrophoretic displays" to generalize across wall configurations.

[0056] Another type of electro-optic display is the electrowetting display developed by Philips and described in Hayes, R.A., et al., "Video-Speed ​​Electronic Paper Based on Electrowetting," Nature, 425, 383-385 (2003). In co-pending application Ser. No. 10 / 711,802, filed Oct. 6, 2004, it is shown that such electrowetting displays can be made bistable.

[0057] Other types of electro-optic materials may also be used, most notably bistable ferroelectric liquid crystal displays (FLCs), which exhibit remnant voltage behavior.

[0058] Although electrophoretic media can be opaque (e.g., in many electrophoretic media, the particles substantially block the transmission of visible light through the display) and operate in a reflective mode, some electrophoretic displays can be made so that one display state is substantially opaque and one display state is light-transmitting, operating in a so-called "shutter mode." See, e.g., U.S. Pat. Nos. 6,130,774 and 6,172,798 and U.S. Pat. Nos. 5,872,552, 6,144,361, 6,271,823, 6,225,971, and 6,184,856. Dielectrophoretic displays, which are similar to electrophoretic displays but rely on variations in electric field strength, can operate in a similar mode. See U.S. Pat. No. 4,418,346. Other types of electro-optic displays may also be capable of operating in a shutter mode.

[0059] High-resolution displays can include individual pixels that are addressable without interference from neighboring pixels. One way to achieve such pixels is to provide an array of nonlinear elements, such as transistors or diodes, with at least one nonlinear element associated with each pixel, resulting in an "active matrix" display. The address or pixel electrode that addresses a pixel is connected to an appropriate voltage source through the associated nonlinear element. When the nonlinear element is a transistor, the pixel electrode can be connected to the drain of the transistor; this arrangement will be assumed in the following description, but is essentially arbitrary; the pixel electrode can also be connected to the source of the transistor. In high-resolution arrays, pixels can be arranged in a two-dimensional array of rows and columns, such that any particular pixel is uniquely defined by the intersection of one defined row and one defined column. The sources of all transistors in each column can be connected to a single column electrode, while the gates of all transistors in each row can be connected to a single row electrode. Again, the assignment of sources to rows and gates to columns can be reversed, as desired.

[0060] The display can be written in a row-by-row manner. The row electrodes are connected to row drivers, which apply voltages to the selected row electrodes to ensure that all transistors in the selected row are conducting, while voltages can be applied to all other rows to ensure that all transistors in these unselected rows remain non-conducting. The column electrodes are connected to column drivers, which apply voltages to the various column electrodes selected to drive the pixels in the selected row to their desired optical states. (These voltages are relative to a common front electrode provided on the opposite side from the nonlinear array of electro-optic medium and which may span the entire display. As known in the art, voltages are relative and are a measure of the charge difference between two points. One voltage value is relative to another voltage value. For example, zero voltage (“0V”) refers to having no voltage difference relative to another voltage.) After a preselected interval known as the “line address time,” the selected row is deselected, another row is selected, and the voltages on the column drivers are changed so that the next line of the display is written.

[0061] However, in use, certain waveforms can cause remnant voltages to appear in the pixels of an electro-optic display, and as is evident from the above discussion, this remnant voltage can give rise to several undesirable optical effects and is generally undesirable.

[0062] As presented herein, a "shift" in optical state associated with an address pulse refers to the situation where the initial application of a particular address pulse to an electro-optic display results in a first optical state (e.g., a first shade of gray), and a subsequent application of the same address pulse to the electro-optic display results in a second optical state (e.g., a second shade of gray). A remnant voltage can result in a shift in optical state because the voltage applied to a pixel of an electro-optic display during application of an address pulse comprises the sum of the remnant voltage and the voltage of the address pulse.

[0063] "Drift" over time in the optical state of a display refers to the situation in which the optical state of an electro-optic display changes while the display is stationary (e.g., during periods when no address pulses are applied to the display). Residual voltages can result in drift in the optical state because the optical state of a pixel can depend on the remnant voltage of the pixel, and the remnant voltage of a pixel can decay over time.

[0064] As discussed above, "image persistence" refers to the situation where a trace of a previous image is still visible after an electro-optic display has been rewritten. Residual voltage can result in "edge image persistence," a type of image persistence in which the contours (edges) of parts of the previous image remain visible.

[0065] The term "optical kickback" is used herein to describe the change in the optical state of a pixel that occurs at least in part in response to the release of a remnant voltage on the pixel.

[0066] 1 shows a schematic of a pixel 100 of an electro-optic display in accordance with the presently presented subject matter. Pixel 100 may include an imaging film 110. In some embodiments, imaging film 110 may be bistable. In some embodiments, imaging film 110 may include, but is not limited to, an encapsulated electrophoretic imaging film, which may include, for example, charged pigment particles.

[0067] The imaging film 110 may be disposed between the front electrode 102 and the back electrode 104. The front electrode 102 may be formed between the imaging film and the front surface of the display. In some embodiments, the front electrode 102 may be transparent. In some embodiments, the front electrode 102 may be formed from any suitable transparent material, including, but not limited to, indium tin oxide (ITO). The back electrode 104 may be formed opposite the front electrode 102. In some embodiments, a parasitic capacitance (not shown) may form between the front electrode 102 and the back electrode 104.

[0068] The pixel 100 may be one of a plurality of pixels. The plurality of pixels may be arranged in a two-dimensional array of rows and columns to form a matrix, whereby any particular pixel is uniquely defined by the intersection of one defined row and one defined column. In some embodiments, the matrix of pixels may be an "active matrix," with each pixel associated with at least one nonlinear circuit element 120. The nonlinear circuit element 120 may be coupled between the back electrode 104 and the address electrode 108. In some embodiments, the nonlinear element 120 may include a diode and / or a transistor, including, but not limited to, a MOSFET. The drain (or source) of the MOSFET may be coupled to the back electrode 104, the source (or drain) of the MOSFET may be coupled to the address electrode 108, and the gate 106 of the MOSFET may be coupled to a driver configured to control activation and deactivation of the MOSFET. (For convenience, the end of the MOSFET coupled to the back electrode 104 will be referred to as the drain of the MOSFET, and the end of the MOSFET coupled to the address electrode 108 will be referred to as the source of the MOSFET. However, those skilled in the art will recognize that in some embodiments, the source and drain of a MOSFET may be interchanged.)

[0069] In some embodiments of an active matrix, the address electrodes 108 of all pixels in each column may be connected to the same column electrode, and the gates 106 of all transistors associated with all pixels in each row may be connected to the same row electrode. The row electrodes may be connected to a row driver, which may select one or more rows of pixels by applying a voltage to the selected row electrode sufficient to activate the nonlinear elements 120 of all pixels 100 in the selected row. The column electrodes may be connected to a column driver, which may apply a suitable voltage to the transistor gates 106 of the selected (activated) pixels to drive the pixels to a desired optical state. The voltage applied to the address electrodes 108 may be relative to the voltage applied to the front electrodes 102 of the pixels (e.g., a voltage of about zero volts). In some embodiments, the front electrodes 102 of all pixels in the active matrix may be coupled to a common electrode.

[0070] In some embodiments, the pixels 100 of the active matrix may be written in a row-by-row manner. For example, a row of pixels may be selected by a row driver, and voltages corresponding to the desired optical state for the row of pixels may be applied to the pixels by a column driver. After a preselected interval known as a "line address time," the selected row may be deselected, another row may be selected, and the voltages on the column drivers may be changed so that another line of the display is written.

[0071] An electro-optic display may receive power from external electronics, such as a display controller, and may provide voltages from "power management" circuitry. The power management circuitry may provide multiple voltages, including "gate-on voltages," which are applied to gate lines (also referred to herein as "select lines") to place transistors on selected lines into a conductive state. The power management circuitry may be separate components or an integrated circuit (e.g., a power management integrated circuit ("PMIC"). Additional circuitry may include pull-down resistors and / or pull-down capacitors.

[0072] An electro-optic display can include display controller circuitry, including power management circuitry, for applying voltage waveforms to display pixels sufficient to change the optical state of electrophoretic display media adjacent to the display pixels. Those skilled in the art will appreciate that the display controller circuitry of the present invention can be implemented in several different physical forms and can utilize a variety of analog and digital components. For example, the display controller circuitry can include a general-purpose microprocessor along with appropriate peripheral components (e.g., one or more digital-to-analog converters (“DACs”)) capable of converting digital outputs from the microprocessor into appropriate voltages for application to the pixels. Alternatively, the display controller circuitry can be implemented in an application-specific integrated circuit (“ASIC”) or field-programmable gate array (“FPGA”). Those skilled in the art will appreciate that the display controller circuitry can include both processing components and power management circuitry, such as the PMIC described above.

[0073] In some embodiments, the display controller circuitry includes a timing controller integrated circuit (“IC”) that receives incoming image data and outputs control signals to a data collection and selection driver IC to produce appropriate voltages at the pixels to display the desired image. In some embodiments, a host controller in communication with the display controller circuit requests updates to the display and provides image data for updates to the display controller circuit. In some embodiments, the display controller circuitry receives image data through access to a memory buffer containing the image data, or receives a signal from which the image data is extracted. In some embodiments, the memory buffer has a structure such as that described in the above-referenced U.S. Pat. No. 9,721,495. In some embodiments, the display controller circuitry receives a serial signal containing information needed to perform the calculations necessary to generate drive impulses (e.g., drive waveforms) for application to an electrophoretic medium during scanning of a pixel array.

[0074] 2 shows a circuit model of an electro-optic imaging layer 110 disposed between a front electrode 102 and a back electrode 104 in accordance with the subject matter presented herein. Resistor 202 and capacitor 204 may represent the resistance and capacitance of the electro-optic imaging layer 110, front electrode 102, and back electrode 104, including any adhesive layers. Resistor 212 and capacitor 214 may represent the resistance and capacitance of a lamination adhesive layer. Capacitor 216 may represent capacitance that may arise at an interlayer interface contact area between the front electrode 102 and back electrode 104, e.g., the interface between the imaging layer and a lamination adhesive layer and / or the lamination adhesive layer and a back electrode. The voltage Vi across the imaging film 110 of a pixel may include the residual voltage of the pixel.

[0075] In some embodiments, remnant voltage release can be achieved by utilizing the leakage conduction effect of the transistor associated with each display pixel. For example, referring now to plot 300 of FIG. 3, transistor leakage current is shown here as the drain / source current, or Ids, that increases as the voltage bias, or Vgs, across the transistor gate / source becomes increasingly negative. In practice, as Vgs becomes increasingly negative, the transistor becomes conductive, and this conduction can be used to drain remnant voltage not only from the display pixel, but also from the display.

[0076] In use, the release of the residual voltage of the pixel using the leakage conduction effect of the pixel transistor may be initiated and / or controlled by applying any suitable set of signals to the pixel (including, but not limited to, the set of signals as illustrated in more detail in Figures 4 and 5 below).

[0077] 4 illustrates one embodiment of a drive pulse configuration for driving a single display pixel with an n-type field effect transistor and a reservoir capacitor in accordance with the subject matter disclosed herein. The example in FIG. 4 illustrates a gate voltage 402 (e.g., a voltage applied to the gate of the pixel transistor), a reference voltage 404 (e.g., zero volts), and a common voltage 406 (typically V), which is the voltage applied to the front electrode 102 (FIG. 1). COM ), the source voltage 408, and the voltage Vi 410, which is the voltage experienced by the electro-optic layer.

[0078] 4, one or more waveforms are applied to a display pixel during an address phase 420 to drive an electrophoretic display medium adjacent to the display pixel to a desired optical state. A hold period 430, lasting for the duration of one or more frames, follows the address phase 420. During the hold period 430, substantially equal voltages are applied to the common voltage 406 and the display pixel electrode via a source voltage 408, while a gate-on voltage is applied to the gate electrode of the n-type transistor via a gate voltage 402. The gate-on voltage is a sufficiently positive voltage to create a conduction path through the n-type transistor. In some embodiments, the hold period 430 is part of the address phase 420.

[0079] After the hold period 430, the gate voltage 402 is set to zero volts, placing the display pixel in a floating, hold state 440. In some embodiments, placing the display pixel in the floating, hold state 440 includes applying a gate-off voltage to the gate electrode of the n-type transistor via the gate voltage 402. The gate-off voltage can be a sufficiently negative voltage to prevent the formation of a conduction path through the drain electrode of the n-type transistor and the source electrode of the n-type transistor. In some embodiments, placing the display pixel in the floating, hold state 440 includes disconnecting the electrical connection between the common electrode and the voltage source that provides the common voltage 406.

[0080] Following the floating hold state 440, the display pixel enters the discharge state 450. During the discharge state 450, the low gate voltage rail voltage 460 (V EEd 460) can be applied to the gate electrode of the n-type transistor via gate voltage 402. EEd460 is large enough to induce a leakage conduction path in the n-type transistor to release the residual voltage from the electrophoretic display media. In some embodiments, the low gate voltage rail voltage has a magnitude greater than the gate off voltage of the n-type transistor. Upon completion of the discharge of the residual voltage, the gate voltage 402 can return to zero volts.

[0081] Alternatively, and referring now to Figure 5, the low gate voltage rail voltage V EEd 560 may be applied to the gate electrode of the n-type transistor via gate voltage 502 immediately after the end of the address phase 520, without any intervening hold period or floating state, to place the display pixel in the discharged state 550.

[0082] FIG. 6 shows that V is 0.01 V compared to setting the gate voltage to a +28 volt level (VDDH=+28V (610) as is done for conventional techniques). EEd (V EEd =-10V(620), V EEd =-20V(630), V EEd =-25V(640), V EEd = -28V(650). As shown, comparable discharge is achievable using the leakage conduction effect compared to that of a positive gate voltage. Additionally, with this amount of leakage conduction, the display can still be used for normal or standard refresh operations.

[0083] Furthermore, using the driving sequences presented in Figures 4 and 5, specialized circuitry is no longer needed to provide high gate voltages to pixel transistors to mitigate transistor performance instability, and no additional positive stress bias is introduced to the transistors due to draining residual voltages using positive gate voltages, as in conventional techniques.

[0084] Thus, the techniques disclosed herein provide a simpler method of releasing remnant voltage than conventional techniques. Furthermore, because the techniques described herein release remnant voltage during a period that is separate from the addressing phase, display pixels can be driven using DC unbalanced waveforms, which are typically shorter in duration than DC balanced waveforms. This improves the user experience by reducing the overall update time of the display.

[0085] It will be apparent to those skilled in the art that numerous changes and modifications can be made to the specific embodiments of the invention described above without departing from the scope of the invention. Accordingly, the whole of the foregoing description is to be interpreted in an illustrative sense, rather than a restrictive sense.

Claims

1. 1. An electro-optic display, comprising: an electrophoretic display medium electrically coupled between a common electrode and a display pixel electrode associated with the display pixel; a display controller circuit in electrical communication with the common electrode and the n-type transistor associated with the display pixel electrode; Equipped with the display controller circuit is capable of applying waveforms to the display pixels by applying one or more time-dependent voltages between the common electrode and the display pixel electrodes, the one or more time-dependent voltages being applied to the display pixel electrodes via the n-type transistors; The display controller circuit, in turn, applying one or more waveforms to the display pixels to drive the electrophoretic display media adjacent to the display pixels to a first optical state; applying substantially equal voltages to the common electrode and the display pixel electrode during a hold period; applying a gate-on voltage to a gate electrode of the n-type transistor while the substantially equal voltages are applied to the common electrode and the display pixel electrode, the gate-on voltage being a sufficiently positive voltage to create a conduction path through the n-type transistor; maintaining the display pixel in the first optical state for the hold period by placing the display pixel in a floating state by removing the gate-on voltage from the gate electrode of the n-type transistor and removing voltages from the common electrode and the display pixel electrode; applying a low gate voltage to the gate electrode of the n-type transistor; configured to: An electro-optic display, wherein the low gate voltage is a negative voltage of sufficient magnitude to induce a leakage conduction path in the n-type transistor to release residual voltage from the electrophoretic display medium, and the low gate voltage has a magnitude that is more negative than a gate-off voltage of the n-type transistor.

2. 10. An electro-optic display according to claim 1, further comprising an active matrix of display pixels, said display pixel being one of said display pixels of said active matrix of display pixels.

3. 3. An electro-optic display as claimed in claim 2, wherein each of the one or more waveforms comprises one or more frames.

4. 4. An electro-optic display as claimed in claim 3, wherein the hold period comprises one or more frames.

5. 2. An electro-optic display according to claim 1, wherein the leakage conduction path is formed between a drain electrode of the n-type transistor and a source electrode of the n-type transistor.

6. 2. The electro-optic display of claim 1, wherein placing the display pixel in a floating state comprises applying the gate-off voltage to the gate electrode of the n-type transistor, the gate-off voltage being a negative voltage sufficient to prevent formation of a conduction path through the drain electrode of the n-type transistor and the source electrode of the n-type transistor.

7. 10. An electro-optic display according to claim 1, wherein placing the display pixel in a floating state further comprises disconnecting an electrical connection between the common electrode and a voltage source.

8. 1. A method of driving an electro-optic display, the electro-optic display comprising an electrophoretic display medium electrically coupled between a common electrode and display pixels, the display pixels having associated n-type transistors electrically coupled to display pixel electrodes and to a display controller circuit, the display controller circuit being capable of applying waveforms to the display pixels by applying one or more time-dependent voltages between the common electrode and the display pixel electrodes via the n-type transistors, the one or more time-dependent voltages being applied to the display pixel electrodes; The method comprises, in order: applying one or more waveforms to the display pixels to drive the electrophoretic display media adjacent to the display pixels to a first optical state; applying substantially equal voltages to the common electrode and the display pixel electrode during a hold period; applying a gate-on voltage to a gate electrode of the n-type transistor while the substantially equal voltages are applied to the common electrode and the display pixel electrode, the gate-on voltage being a sufficiently positive voltage to create a conduction path through the n-type transistor; maintaining the display pixel in the first optical state for the hold period by placing the display pixel in a floating state by removing the gate-on voltage from the gate electrode of the n-type transistor and removing voltages from the common electrode and the display pixel electrode; applying a low gate voltage to the gate electrode of the n-type transistor; Including, The method wherein the low gate voltage is a negative voltage of sufficient magnitude to induce a leakage conduction path in the n-type transistor to release residual voltage from the electrophoretic display medium, and the low gate voltage has a magnitude that is more negative than a gate-off voltage of the n-type transistor.

9. The method of claim 8 , further comprising an active matrix of display pixels, the display pixel being one of the display pixels of the active matrix of display pixels.

10. The method of claim 9 , wherein each of the one or more waveforms comprises one or more frames.

11. The method of claim 10 , wherein the hold period comprises one or more frames.

12. 9. The method of claim 8, wherein the leakage conduction path is formed between a drain electrode of the n-type transistor and a source electrode of the n-type transistor.

13. 9. The method of claim 8, wherein leaving the display pixel floating further comprises applying the gate-off voltage to the gate electrode of the n-type transistor, the gate-off voltage being a negative voltage sufficient to prevent formation of a conduction path through the drain electrode of the n-type transistor and the source electrode of the n-type transistor.

14. 9. The method of claim 8, wherein placing the display pixel in a floating state further comprises disconnecting an electrical connection between the common electrode and a voltage source.

15. 1. An electro-optic display, comprising: an electrophoretic display medium electrically coupled between a common electrode and a display pixel electrode associated with the display pixel; a display controller circuit in electrical communication with the common electrode and the n-type transistor associated with the display pixel electrode; Equipped with the display controller circuit is capable of applying waveforms to the display pixels by applying one or more time-dependent voltages between the common electrode and the display pixel electrodes via the n-type transistors, the one or more time-dependent voltages being applied to the display pixel electrodes; The display controller circuit, in turn, applying one or more waveforms to the display pixels to drive the electrophoretic display media adjacent to the display pixels to a first optical state; placing the display pixel in a floating state by removing the gate-on voltage from the gate electrode of the n-type transistor and removing the voltages from the common electrode and the display pixel electrode; applying a low gate voltage to the gate electrode of the n-type transistor; configured to: An electro-optic display, wherein the low gate voltage is a negative voltage of sufficient magnitude to induce a leakage conduction path in the n-type transistor to release residual voltage from the electrophoretic display medium, and the low gate voltage has a magnitude that is more negative than a gate-off voltage of the n-type transistor.

16. 16. An electro-optic display according to claim 15, further comprising an active matrix of display pixels, said display pixel being one of said display pixels of said active matrix of display pixels.

17. 17. An electro-optic display according to claim 16, wherein each of the one or more waveforms comprises one or more frames.

18. 16. An electro-optic display according to claim 15, wherein the leakage conduction path is formed between a drain electrode of the n-type transistor and a source electrode of the n-type transistor.

19. 1. A method of driving an electro-optic display, the electro-optic display comprising an electrophoretic display medium electrically coupled between a common electrode and display pixels, the display pixels having associated n-type transistors electrically coupled to display pixel electrodes and to a display controller circuit, the display controller circuit being capable of applying waveforms to the display pixels by applying one or more time-dependent voltages between the common electrode and the display pixel electrodes via the n-type transistors, the one or more time-dependent voltages being applied to the display pixel electrodes; The method comprises, in order: applying one or more waveforms to the display pixels to drive the electrophoretic display media adjacent to the display pixels to a first optical state; placing the display pixel in a floating state by removing the gate-on voltage from the gate electrode of the n-type transistor and removing the voltages from the common electrode and the display pixel electrode; applying a low gate voltage to the gate electrode of the n-type transistor; Including, The method wherein the low gate voltage is a negative voltage of sufficient magnitude to induce a leakage conduction path in the n-type transistor to release residual voltage from the electrophoretic display medium, and the low gate voltage has a magnitude that is more negative than a gate-off voltage of the n-type transistor.

20. 20. The method of claim 19, further comprising an active matrix of display pixels, wherein the display pixel is one of the display pixels of the active matrix of display pixels.

21. 21. The method of claim 20, wherein each of the one or more waveforms comprises one or more frames.

22. 20. The method of claim 19, wherein the leakage conduction path is formed between a drain electrode of the n-type transistor and a source electrode of the n-type transistor.

Images