Gate drive circuit

Abstract

To provide a gate drive circuit capable of suppressing malfunctions even when high-speed switching is performed.SOLUTION: A gate drive circuit has a first circuit, a second circuit, and a signal insulator for insulating and transmitting a signal from the first circuit to the second circuit. The first circuit has: a reference generator that generates a reference value; a first buffer for holding the reference value; and a synchronization signal generator that generates a synchronization signal for making the first and second circuits synchronize with each other. The second circuit has: a second buffer for holding the reference value transmitted from the first buffer in the first circuit via the signal insulator; a carrier generator that generates a carrier signal synchronized with the synchronization signal transmitted from the first circuit via the signal insulator; and a comparator that compares the reference signal outputted from the second buffer and the carrier signal outputted from the carrier signal generator with each other, and outputs a gate drive signal.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a gate drive circuit used in a power conversion circuit such as an inverter, a rectifier, or a DC / DC converter. [Background technology]

[0002] Power devices using wide bandgap semiconductors, such as SiC MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) and GaN HEMTs (High Electron Mobility Transistors), are capable of high-speed switching, i.e., a large voltage change rate (dv / dt). Utilizing this feature in power conversion circuits makes it possible to reduce switching losses and increase the carrier frequency, thereby reducing the volume of ripple suppression filters. However, as the voltage change rate (dv / dt) increases, common-mode noise on the transmission line that transmits control signals also increases, which can cause malfunctions in gate drive circuits.

[0003] A typical countermeasure to this problem is to use optical isolators in the signal isolation section to minimize the stray capacitance of the transmission path that transmits the control signal and suppress common-mode noise. However, optical isolators have large jitter in signal transmission, making it difficult to achieve switching operations of several hundred kHz to several MHz, which are expected of wide bandgap devices. In response to this problem, magnetically or capacitively coupled signal isolators can be used to reduce jitter, but they also increase the stray capacitance of the transmission path that transmits the control signal compared to when optical isolators are used, resulting in increased common-mode noise superimposed on the transmission path during high-speed switching, which can cause noise in the gate drive signal.

[0004] FIG. 1 shows an example of a conventional gate drive circuit that generates a gate drive signal. In this example, a signal processor that generates and outputs the gate drive signal is insulated from the gate driver, gate resistor, MOSFET, and other components by a signal isolator. This signal processor includes a synchronization signal generator that generates a synchronization signal (e.g., a peak signal indicating the timing of a counter's maximum value and a bottom signal indicating the timing of its minimum value) from a clock CLK, a reference generator that generates a reference value in response to the synchronization signal, a buffer for holding the reference value, a carrier generator that generates a carrier signal, e.g., a triangular wave, in response to the clock CLK, and a comparator that compares the reference value output by the buffer with the carrier signal output by the carrier generator. The signal processor is implemented using a microprocessor, a programmable logic device such as an FPGA (Field Programmable Gate Array) or a CPLD (Complex Programmable Logic Device), or a logic circuit such as a CMOS (Complementary Metal Oxide Semiconductor) or a TTL (Transistor-Transistor Logic), or a combination of these.

[0005] The operation of the gate drive circuit shown in Figure 1 will be explained using Figure 2. The reference value is assumed to be a value between 0 and 1, and the carrier signal, which is a triangular wave, also has a value between 0 and 1. The reference value output by the buffer is updated at the times when the carrier signal reaches its maximum and minimum. Specifically, the reference generator begins calculating the reference value at time t1, when the carrier signal reaches its minimum, and completes the calculation at time t2. The calculated reference value is temporarily stored in the buffer, and at time t3, when the carrier signal reaches its maximum, the buffer outputs the held reference value to the comparator. At time t3, the reference generator begins calculating the next reference value, and completes the calculation at time t4. The calculated reference value is temporarily stored in the buffer, and at time t5, when the carrier signal reaches its minimum, the buffer outputs the held reference value to the comparator. This process continues in the same manner. The reference value compared to the carrier signal by the comparator is a discrete value and is delayed by half a cycle of the carrier signal. The comparator compares the magnitude of the carrier signal with a reference value, and if the carrier signal is greater, the gate drive signal maintains an off signal (L), and if the reference value is greater, the gate drive signal maintains an on signal (H).The signal processor of such a conventional gate drive circuit always transmits the gate drive signal via a signal isolator.

[0006] Figure 3 shows an example of a configuration in which such a conventional gate drive circuit is applied to a step-down chopper. In the example in Figure 3, the step-down inductance is assumed to be sufficiently large, and the load is represented as a constant current source I. In the example in Figure 3, the reference potential on the primary side of the gate drive circuit is GND1. On the other hand, on the secondary side, the source terminal voltage of the MOSFET is set to reference potential GND2. Generally, a stray capacitance C of several pF to several hundred pF exists between different isolated reference potentials (here, between GND1 and GND2).

[0007] The operation of such a gate drive circuit is explained using Figure 4. This shows the gate signal being switched from OFF (L) to ON (H) at time t6. After a turn-on delay, the MOSFET drain-source voltage v1 drops at time t7. At this time, according to Kirchhoff's voltage law, the diode voltage v2 begins to rise. Meanwhile, considering that the voltage applied to the stray capacitance C of the signal isolator is equal to the diode voltage v2, as the diode voltage v2 rises from time t7 to time t8, a common-mode current of C(dv2 / dt) flows from GND2 to GND1.

[0008] Magnetically coupled and capacitively coupled signal isolators can malfunction due to the flow of such common mode currents. For example, if an off signal (L) is mistakenly output due to a malfunction caused by a common mode current even though an on signal (H) is input to the signal isolator, the MOSFET will mistakenly turn off. In particular, when high-speed switching is performed using wide bandgap devices, malfunctions in signal isolators become more pronounced because the common mode current is proportional to the voltage change rate (dv / dt). [Prior art documents] [Patent documents]

[0009] [Patent Document 1] U.S. Patent No. 6,111,454 [Non-patent literature]

[0010] [Non-Patent Document 1] J. Wang, S. Mocevic, R. Burgos and D. Boroyevich, “High-Scalability Enhanced Gate Drivers for SiC MOSFET Modules With Transient Immunity Beyond 100 V / ns,” in IEEE Transactions on Power Electronics, vol. 35, no. 10, pp. 10180-10199, Oct. 2020. Summary of the Invention [Problem to be solved by the invention]

[0011] SUMMARY OF THE INVENTION Therefore, one object of the present invention is to provide a gate drive circuit that can suppress malfunctions even when high-speed switching is performed. [Means for solving the problem]

[0012] A gate drive circuit according to one aspect of the present invention includes a first circuit, a second circuit, and a signal isolator for isolating and transmitting a signal from the first circuit to the second circuit. The first circuit includes a reference generator for generating a reference value, a first buffer for holding the reference value, and a synchronization signal generator for generating a synchronization signal for synchronizing the first circuit and the second circuit. The second circuit includes a second buffer for holding the reference value transmitted from the first buffer in the first circuit via the signal isolator, a carrier generator for generating a carrier signal synchronized with the synchronization signal transmitted from the first circuit via the signal isolator, and a carrier generator for synchronizing the reference signal and the carrier signal output by the second buffer. Departure and a comparator that compares the carrier signal output by the generator with the gate drive signal and outputs the gate drive signal. [Effects of the Invention]

[0013] According to one aspect, it is possible to provide a gate drive circuit that can suppress malfunction even when high-speed switching is performed. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a diagram showing an example of a circuit according to the prior art. [Figure 2] FIG. 2 is a diagram for explaining the operation of a circuit according to the prior art. [Figure 3] FIG. 3 is a diagram showing an application example of a circuit of the prior art. [Figure 4] FIG. 4 shows waveforms of voltage, current and gate drive signals in an application of the prior art circuit. [Figure 5] FIG. 5 is a diagram showing a gate drive circuit according to the first embodiment. [Figure 6] FIG. 6 is a diagram for explaining the operation of the gate drive circuit according to the first embodiment. [Figure 7] FIG. 7 is a diagram for explaining the operation of the gate drive circuit according to the first embodiment. [Figure 8] FIG. 8 is a diagram for explaining the operation of the gate drive circuit according to the first embodiment. [Figure 9] FIG. 9 is a diagram showing a gate drive circuit according to the second embodiment. [Figure 10] FIG. 10 is a diagram for explaining the operation of the gate drive circuit according to the second embodiment. [Figure 11] FIG. 11 is a diagram for explaining the operation of the gate drive circuit according to the second embodiment. [Figure 12] FIG. 12 is a diagram showing a gate drive circuit according to the second embodiment. [Figure 13] FIG. 13 is a diagram showing an example of a circuit for generating a plurality of gate drive signals. [Figure 14] FIG. 14 is a diagram showing an example of an experimental circuit. [Figure 15] FIG. 15 is a diagram showing various voltage, current and signal waveforms when a gate drive signal generated by a circuit of the prior art is used. [Figure 16]FIG. 16 is a diagram showing various voltage, current and signal waveforms when the gate drive signal generated by the gate drive circuit according to the first embodiment is used. DETAILED DESCRIPTION OF THE INVENTION

[0015] [Embodiment 1] An example of the configuration of a gate drive circuit according to this embodiment is shown in Fig. 5. As shown in Fig. 5, in this embodiment, a circuit 1 that generates a reference value (also called a command value) and a circuit 2 that generates a gate drive signal based on the reference value are connected and insulated by signal isolators 1 and 2, and the gate of a MOSFET or the like is driven by the gate drive signal via a gate driver and gate resistor.

[0016] The circuit 1 is provided with a signal processor 1, which includes a synchronization signal generator 1, a reference generator, and a buffer 1. The synchronization signal generator 1 counts up, for example, from 0 to 1 in response to a clock signal clk1 on the circuit 1 side, and outputs a synchronization signal Peak1 when the count value reaches 1. When the count value reaches 1, the synchronization signal generator 1 counts down to 0 and outputs a synchronization signal Bottom1 when the count value reaches 0. The synchronization signals Peak1 and Bottom1 are output to the reference generator and buffer 1, and are also output to the circuit 2 side via a signal isolator 2. The reference generator starts calculating a reference value using each of the synchronization signals Peak1 and Bottom1, and outputs the calculated reference value to buffer 1. Buffer 1 measures timing using the clock signal clk1 and the synchronization signals Peak1 and Bottom1, holds the reference value output from the reference generator, and outputs it to the circuit 2 side via the signal isolator 1.

[0017] Signal isolators 1 and 2 are, for example, magnetically coupled or capacitively coupled signal isolators based on their responsiveness, and signal processors 1 and 2 are, as in the past, realized by a microprocessor, a programmable logic device such as an FPGA or CPLD, or a logic circuit such as a CMOS or TTL, or a combination of these.

[0018] The circuit 2 is provided with a signal processor 2, which includes a buffer 2, a synchronization signal generator 2, a carrier generator, and a comparator. The synchronization signal generator 2 counts up, for example, from 0 to 1 in response to a clock signal clk2 on the circuit 2 side, and outputs a synchronization signal Peak2 when the count value reaches 1. Conversely, when the count value reaches 1, the synchronization signal generator 2 counts down to 0 and outputs a synchronization signal Bottom2 when the count value reaches 0. However, because the clock signals clk1 and clk2 are not synchronized, the synchronization signal generator 2 adjusts the timing at which the count value reaches 1 or 0 in response to at least one of the synchronization signals Peak1 and Bottom1 transmitted via the signal isolator 2. The buffer 2 holds the reference value transmitted via the signal isolator 1 and switches the reference value to be output to the next reference value in response to at least one of the synchronization signals Peak2 and Bottom2 from the synchronization signal generator 2. The carrier generator outputs a count value, for example, counting up from 0 to 1 in response to clock signal clk2, and when the count value reaches 1, it counts back down to 0, thereby outputting a triangular wave carrier signal. Note that because clock signals clk1 and clk2 are not synchronized, the carrier generator also adjusts the timing at which the count value becomes 1 and 0 in response to synchronization signals peak1 and bottom1 transmitted via signal isolator 2. The comparator compares the carrier signal with a reference value, and if the carrier signal is greater than the reference value, the gate drive signal becomes an off signal (L), and if the reference value is equal to or greater than the carrier signal, the gate drive signal becomes an on signal (H).

[0019] FIG. 6 shows a timing chart of the processing of signal processors 1 and 2 shown in FIG. 5. In FIG. 6, as shown in the second row, the period during which the counter value of synchronization signal generator 1 first counts up is denoted by n, followed by the period during which it counts down is denoted by n+1, and the count increases by 1 thereafter. As shown in the first row of FIG. 6, when period n begins at time t9, the reference generator starts calculating the reference value. After completing calculation of the reference value at time t10, the buffer 1 outputs the reference value to buffer 1, as indicated by the arrow in FIG. 6. The buffer 1 transmits the reference value to circuit 2 via signal isolator 1, as indicated by the arrows in the third and fourth rows of FIG. 6. Here, buffer 1 transmits the reference value from time t10 to time t11. During period n+1, the reference value is calculated by the reference generator from time t12 to time t13, and the reference value is output to buffer 1 at time t13. The buffer 1 outputs the reference value to circuit 2 via signal isolator 1 from time t13 to time t15.

[0020] As shown in the fifth row of FIG. 6, if circuits 1 and 2 are synchronized, buffer 2 receives and holds the reference value transmitted via signal isolator 1 during period n. During period n (times t9 to t12), buffer 2 outputs the reference value it received and held during period n-1. Therefore, when period n+1 begins at time t12, buffer 2 outputs the reference value it received and held during period n. Therefore, as shown in the sixth row of FIG. 6, the reference value changes with each period. Meanwhile, as shown in the seventh row of FIG. 6, if circuits 1 and 2 are synchronized, the carrier generator outputs a carrier signal that increases from time t9 and decreases from time t12. As shown in the eighth row of FIG. 6, the comparator compares the reference value with the carrier signal. If the carrier signal is greater than the reference value, the comparator turns off the gate drive signal. If the carrier signal is equal to or less than the reference value, the comparator turns on the gate drive signal. The comparator operates in the same way during other periods.

[0021] By transmitting the reference value through the signal isolator in this way, communication is completed in a shorter time than with conventional technology, which always transmits gate drive signals through the signal isolator, making it less susceptible to malfunctions in the signal isolator. For example, if the reference value is transmitted from Buffer 1 to Buffer 2 using 32-bit, 100 MHz serial communication, the time required to transmit the reference value (t11 - t10) is 0.32 μs (= 32 / 100 MHz). Therefore, during one cycle of the carrier signal, a significant signal passes through Signal Isolator 1 for only 2 × 0.32 = 0.64 μs.

[0022] Even if the period during which a significant signal is transmitted is shortened in this way, depending on the reference value, the gate drive signal may change during communication from Buffer 1 to Buffer 2. In the example of Figure 6, there is no change in the gate drive signal from time t10 to time t11 in period n, but a change occurs in the gate drive signal at time t14 between time t13 and time t15 in period n+1. In such a case, there is a risk of signal isolator 1 malfunctioning, so buffer 1 adjusts the output timing of the reference value.

[0023] Specifically, as shown in Figure 7, Buffer 1 delays the timing of outputting the reference value. In Figure 7, period n+1 starts at time t16, but even if Buffer 1 receives the reference value from the reference generator at time t17, it delays outputting the reference value until time t17 to t19. As a result, even if the gate drive signal changes at time t18 between times t17 and t19, Buffer 1 can start outputting the reference value from time t19, allowing the reference value to be transmitted through Signal Isolator 1 without being affected by the change in the gate drive signal.

[0024] In any period i to i+1 (iεn, n±1, n±2...), the buffer 1 delays the output of the reference value only when the following formula is satisfied. T C <t sw,i ≦T C +T t (1) In addition, T Cis the time required to calculate the reference value, which can be obtained from simulations of microprocessors and programmable logic. t is the time required to transmit the reference value, calculated as above. In FIG. 7, for period n, T C and T t In addition, the period from the beginning of period n is t sw As can be seen, condition (1) is not satisfied in period n.

[0025] On the other hand, t sw,i is the switching time in period i, and the point at which calculation of the reference value starts is expressed as t = 0. The switching time is calculated from the intersection of the carrier signal and the reference value (or the intersection of the counter value of the synchronization signal generator 2 and the reference value) as follows: t sw,i =(1-D i-1 ) / 2f sw (2) In addition, f sw is the carrier frequency, D i-1 is the reference value for period i-1. That is, the reference value to be compared with the carrier signal is the reference value calculated one period before, so D i-1 This becomes:

[0026] Therefore, the buffer 1 determines whether or not the formula (1) is satisfied, and if it is determined that it is not satisfied, it outputs the reference value as soon as it receives it from the reference generator. On the other hand, if it is determined that the formula (1) is satisfied, it outputs the reference value as soon as it receives it from the beginning of the period i, which is expressed by the formula (2). sw,i The reference value is output after the elapse of the predetermined period. The transfer of the reference value is completed before the calculation of the next reference value is started, i.e., before the start of the next period.

[0027] Next, the synchronization between circuit 1 and circuit 2 will be described with reference to FIG. 8. Synchronization signal generator 1 counts up and down as shown in the first row of FIG. 8, generates synchronization signals peak1 and bottom1 as shown in the second and third rows of FIG. 8, and transmits them to circuit 2 via signal isolator 2 as shown in the fourth row of FIG. 8. Synchronization signal generator 2 and carrier generator count up and down like the carrier signal shown in the fifth row of FIG. 8, but change their own count value to a maximum value (e.g., 1) upon receiving synchronization signal peak1 and to a minimum value (e.g., 0) upon receiving synchronization signal bottom1. That is, synchronization signal generator 2 outputs synchronization signal peak2 upon receiving synchronization signal peak1 and outputs synchronization signal bottom2 upon receiving synchronization signal bottom1. Furthermore, the carrier generator changes the count value that becomes the carrier signal to a maximum value upon receiving synchronization signal peak1 and to a minimum value upon receiving synchronization signal bottom1. In the example of Figure 8, at time t21, the count value is adjusted to the minimum value of 0 in accordance with the synchronization signal bottom1, at time t22, the count value is adjusted to the maximum value of 1 in accordance with the synchronization signal peak1, at time t23, the count value is adjusted to the minimum value of 0 in accordance with the synchronization signal bottom1, and at time t24, the count value is adjusted to the maximum value 1 in accordance with the synchronization signal peak1.

[0028] In this way, synchronization can be achieved even in a configuration in which signal processors 1 and 2 are isolated by signal isolators 1 and 2. Strictly speaking, the period on the circuit 1 side and the period on the circuit 2 side are not simultaneous, but the above configuration allows a correspondence between period n on the circuit 1 side and period n on the circuit 2 side, and for convenience of explanation, they are shown in the figure as being simultaneous.

[0029] In the above example, the synchronization signals peak1 and bottom1 are transmitted from circuit 1 to circuit 2, but it is also possible to transmit only one of them. In this case, circuit 2 adjusts the count value at the reception timing of either one of them.

[0030] Furthermore, the synchronization signal generator 2 and the carrier generator may be integrated because some of their functions overlap.

[0031] [Embodiment 2] In the first embodiment, the influence of the gate drive signal on the signal isolator 2 was not taken into consideration. However, there may be an influence if the timing of the synchronization signals peak1 and bottom1 transmitted from the circuit 1 side via the signal isolator 2 overlaps with the timing of the signal change in the gate drive signal. Specifically, when the reference value is small (close to 0 in the above example), the timing at which the synchronization signal bottom1 is output may overlap with the timing of the signal change in the gate drive signal, and when the reference value is large (close to 1 in the above example), the timing at which the synchronization signal peak1 is output may overlap. Therefore, in this embodiment, such a problem is addressed by adopting the configuration described below.

[0032] The configuration of the gate drive circuit according to this embodiment is shown in FIG. 9. Circuit 1 is the same as in the first embodiment, but signal processor 2 of circuit 2 has been modified. Specifically, buffer 2 immediately outputs the reference value to synchronization signal generator 2 and carrier generator within the same period in which it received the reference value. Based on the received reference value, synchronization signal generator 2 and carrier generator determine whether either synchronization signal peak1 or bottom1 will be affected by a change in the gate drive signal during the next period. If affected, synchronization signal generator 2 and carrier generator do not adjust the synchronization signal peak1 or bottom1 accordingly, but instead adjust the synchronization signal peak1 or bottom1 accordingly. For example, if the count value is between 0 and 1, and the reference value received during a certain period is less than 0.1, synchronization signal bottom1 may be affected. Therefore, during the next period, adjustment based on synchronization signal bottom1 is not performed, but adjustment is made in response to the reception of synchronization signal peak1. Furthermore, if the reference value received in a certain period exceeds 0.9, there is a possibility that it may affect the synchronization signal peak1, so in the next period, adjustments are not made based on the synchronization signal peak1, but are made in response to the reception of the synchronization signal bottom1. In all other cases, regardless of whether the synchronization signal peak1 or bottom1 arrives in the next period, adjustments are made based on that synchronization signal.

[0033] FIG. 10 shows an example in which only synchronization signal peak1 is used. In the example of FIG. 10, because the reference value received in period n-1 is less than 0.1, the gate drive signal is turned on only for a short period when the carrier signal value is also small. Therefore, times t25 to t26, when synchronization signal bottom1 is transmitted via signal isolator 2, fall within the time period in which the gate drive signal is on. Therefore, if the reference value received in period n-1 is less than 0.1, the count value is not adjusted based on synchronization signal bottom1 in the next period n. On the other hand, because the reference value received in period n does not exceed 0.9, the count value is adjusted based on synchronization signal peak1 at time t27 in period n+1. Similarly, because the reference value received in period n+1 is less than 0.1, the time periods t28 to t29, when synchronization signal bottom1 is transmitted via signal isolator 2, fall within the time period in which the gate drive signal is on. Therefore, if the reference value received in period n+1 is less than 0.1, the count value is not adjusted based on synchronization signal bottom1 in the next period n+2. On the other hand, since the reference value in period n+2 does not exceed 0.9, the count value is adjusted based on the synchronization signal peak1 at time t30 in period n+3.

[0034] FIG. 11 shows an example in which only synchronization signal bottom1 is used. In the example of FIG. 11, the reference value received in period n-1 exceeds, for example, 0.9, so the count value is adjusted based on synchronization signal bottom1 at time t31 in period n. Meanwhile, the reference value received in period n exceeds 0.9, and the gate drive signal is turned off for only a short time when the carrier signal value is also large. Times t32 to t33, when synchronization signal peak1 is transmitted via signal isolator 2, are included in the time period in which the gate drive signal is off. Therefore, if the reference value received in period n exceeds 0.9, the count value is not adjusted based on synchronization signal peak1 in the next period n+1. Similarly, since the reference value received in period n+1 exceeds 0.9, the count value is adjusted based on synchronization signal bottom1 at time t34 in period n+2. Furthermore, the reference value received in period n+2 exceeds, for example, 0.9, so times t35 to t36, when synchronization signal peak1 is transmitted via signal isolator 2, are included in the time period in which the gate drive signal is off. Therefore, if the reference value received in period n+2 exceeds 0.9, the count value will not be adjusted based on the synchronization signal peak1 in the next period n+3.

[0035] Note that adjusting the count value of synchronization signal generator 2 may result in successive maximum or minimum count values. Therefore, if the same type of synchronization signal is input multiple times, buffer 2 operates to ignore the second and subsequent synchronization signals. For example, if synchronization signal peak1 is received after the count value of synchronization signal generator 2 has exceeded its maximum value, synchronization signal generator 2 will again set the count value to its maximum value. In this case, synchronization signal generator 2 will output synchronization signal peak2 twice in succession, but buffer 2 will ignore the second synchronization signal peak2.

[0036] [Modification of the second embodiment] In the second embodiment, the buffer 2 outputs a reference value to the synchronization signal generator 2 and the carrier generator, and each determines whether or not to receive the synchronization signals peak1 and bottom1 based on the reference value, but the buffer 2 may determine whether or not to receive the synchronization signals peak1 and bottom1 based on the reference value, and output a synchronization signal selection signal EN to the synchronization signal generator 2 and the carrier generator. For example, an example of a gate drive circuit configured in this way is shown in Figure 12.

[0037] 13, a synchronization signal selection signal EN is output from buffer 2 to synchronization signal generator 2 and carrier generator 3. When buffer 2 receives a reference value via signal isolator 2, it immediately determines whether the reference value is less than 0.1 or greater than 0.9, and if the reference value is less than 0.1, it outputs a selection signal EN that selects only synchronization signal peak1, and if the reference value exceeds 0.9, it outputs a selection signal EN that selects only synchronization signal bottom1, and otherwise it outputs a selection signal EN that selects both synchronization signals peak1 and bottom1.

[0038] When the synchronization signal generator 2 and the carrier generator receive a selection signal EN that selects only the synchronization signal peak1, they adjust their own count values ​​using only the synchronization signal peak1; when they receive a selection signal EN that selects only the synchronization signal bottom1, they adjust their own count values ​​using only the synchronization signal bottom1; and when they receive a selection signal EN that selects both the synchronization signals peak1 and bottom1, they adjust their own count values ​​using the synchronization signals peak1 and bottom1.

[0039] [When generating multiple gate drive signals] Fig. 13 shows an example of the configuration of a gate drive circuit that generates two gate drive signals for two MOSFETs or the like. In Fig. 13, signal processor 2 that generates gate drive signal 1 is the signal processor 2 in the embodiment described above, and signal processor 3 that generates gate drive signal 2 has the same configuration as signal processor 2 in the embodiment described above. Meanwhile, signal processor 1 has buffer 3 for signal processor 3 added to buffer 1 for signal processor 2, and the reference generator generates reference value 1 that is accumulated in buffer 2 and transmitted to signal processor 2 via signal isolator 1, and reference value 2 that is accumulated in buffer 3 and transmitted to signal processor 3 via signal isolator 3. Note that synchronization signal generator 1 outputs synchronization signals peak1 and bottom1 (peak and bottom in Fig. 13) in the same way as in the embodiment described above.

[0040] In this way, the signal processor 1 is provided with buffers for the number of gate drive signals to be generated, and the reference generator generates reference values ​​for the number of gate drive signals to be generated. Also, the secondary side signal processors 2 are provided for the number of gate drive signals to be generated.

[0041] [About the effects] An experiment was conducted using a step-down chopper as shown in FIG. 14. Specifically, the gate drive signal 1 for the upper arm was always an off signal (L), and the gate drive signal 2 for the lower arm was generated using either the conventional circuit shown in FIG. 1 or a circuit according to this embodiment (e.g., FIG. 5) and had a double-pulse waveform. The voltage vsig represents the voltage of the gate drive signal, the voltage vg represents the output voltage of the gate driver, and the voltage vds represents the drain-source voltage. The DC power supply was set to 500 V. As a result, the drain-source voltage vds is 0 V when on and 500 V when off. Furthermore, when the gate drive signal is an on (H) signal, vsig = 5 V, and when it is an off (L) signal, vsig = 0 V. The output voltage of the gate driver is vg = 19 V when on and vg = -5 V when off. Rg represents the gate resistance, Rg = 3.3 Ω.

[0042] Figure 15 shows experimental results when gate drive signal 2 was generated using the conventional circuit shown in Figure 1 and output to the circuit shown in Figure 15. More specifically, the results of measurements of vds, vsig, and vg for a double-pulse waveform were overlaid 200 times. The turn-off trigger was generated by changing the gate drive signal vsig from 5V to 0V. Then, after the drain-source voltage vds increased, ringing occurred in the gate drive signal vsig. Focusing on the gate driver output voltage vg, although it should have remained at -5V after the turn-off trigger, it temporarily increased. This is believed to be due to common-mode noise causing the signal isolator to malfunction, resulting in ringing in the gate drive signal, which in turn generated an erroneous on signal and turned on the gate driver erroneously. As a result, the drain-source voltage temporarily dropped, causing the MOSFET to turn on erroneously.

[0043] Meanwhile, FIG. 16 shows experimental results when gate drive signal 2 is generated using the circuit according to this embodiment shown in FIG. 5 and output to the circuit shown in FIG. 14. More specifically, it shows the results of 200 overlapping measurements of double-pulse waveforms for vds, vsig, and vg. The gate drive signal vsig was changed from 5V to 0V to trigger turn-off. This significantly reduced the ringing that occurred in the gate drive signal vsig after turn-off. Therefore, the gate driver output voltage remained in the off state. In other words, the gate driver did not erroneously turn on. As a result, the drain-source voltage did not erroneously turn on. In other words, common-mode noise was successfully addressed.

[0044] Although the embodiments of the present invention have been described above, the present invention is not limited to these. For example, it is possible to delete any technical feature of each embodiment, or to combine any technical feature of any embodiment.

[0045] The above-described embodiment can be summarized as follows.

[0046] A gate drive circuit according to a first aspect of this embodiment includes a first circuit, a second circuit, and a signal isolator for isolating and transmitting a signal from the first circuit to the second circuit. The first circuit includes a reference generator for generating a reference value, a first buffer for holding the reference value, and a synchronization signal generator for generating a synchronization signal for synchronizing the first circuit and the second circuit. The second circuit includes a second buffer for holding the reference value transmitted from the first buffer in the first circuit via the signal isolator, a carrier generator for generating a carrier signal synchronized with the synchronization signal transmitted from the first circuit via the signal isolator, and a carrier generator for synchronizing the reference signal and the carrier signal output by the second buffer. Departure and a comparator that compares the carrier signal output by the generator with the gate drive signal and outputs the gate drive signal.

[0047] In this way, the signal that passes through the signal isolator becomes a reference value and a synchronization signal, and the reference value can be transmitted in a shorter time than when transmitting a gate drive signal, making it possible to suppress the adverse effects that the gate drive signal generated on the second circuit side has on the signal that passes through the signal isolator (i.e., the reference value).

[0048] The first buffer described above may hold the reference value generated by the reference generator for a certain period and transmit it to the second circuit via a signal isolator, and the second buffer may hold the reference value transmitted from the first buffer in the first circuit via the signal isolator for a period corresponding to the certain period and output the reference value transmitted during the certain period and held during the period following the period corresponding to the certain period. This double-buffer configuration makes it possible to transmit the reference value at the appropriate timing.

[0049] Furthermore, the first buffer may be configured to output a reference value after receiving the reference value from the reference generator during the certain period, avoiding the time when the gate drive signal changes. This reduces the adverse effects of the gate drive signal on signals passing through the signal isolator. Note that since the time when the gate drive signal changes can be predicted from the reference value in the previous period, if the time when the reference value is output overlaps with the time when the gate drive signal changes, the reference value may be delayed until after the time when the gate drive signal changes.

[0050] Furthermore, the synchronization signal may be at least one of a first signal representing the timing of the maximum value of the carrier signal and a second signal representing the timing of the minimum value of the carrier signal, which shortens the time it takes to pass through the signal isolator and is less susceptible to the influence of the gate drive signal.

[0051] In addition, when the synchronization signal described above includes a first signal and a second signal, the carrier generator described above may be configured to adjust the carrier signal based on the received signals by switching between receiving only the first signal, receiving only the second signal, and receiving both the first and second signals in a period following the period based on a reference value received by the second buffer during the period, thereby achieving synchronization between the first circuit and the second circuit in a manner that avoids adverse effects of the gate drive signal.

[0052] Furthermore, when the synchronization signal described above includes a first signal and a second signal, the second buffer described above may determine, based on a reference value received during a certain period, whether reception of only the first signal, only the second signal, or both the first and second signals is appropriate during a period following the certain period, and output a selection signal representing the appropriate signal to the carrier generator. In this case, the carrier generator may switch between reception of only the first signal, only the second signal, or both the first and second signals based on the selection signal from the second buffer, and adjust the carrier signal based on the received signal. Even with this configuration, synchronization between the first circuit and the second circuit can be achieved in a manner that avoids adverse effects of the gate drive signal.

[0053] Furthermore, the above-mentioned carrier generator may be configured to adjust the value of the carrier signal to a maximum value when a first signal is received, and to adjust the value of the carrier signal to a minimum value when a second signal is received.

[0054] Furthermore, the second circuit may further include a second synchronization signal generator that generates a second synchronization signal synchronized with the synchronization signal transmitted from the first circuit via the signal isolator. In this case, the second buffer is configured to output a reference value to the comparator in response to the second synchronization signal from the second synchronization signal generator.

[0055] A gate drive circuit according to a second aspect of the present embodiment includes a first circuit, a second circuit, and a signal isolator for isolating and transmitting a signal from the first circuit to the second circuit. The first circuit includes a reference generator for generating a reference value and a first buffer for holding the reference value, and the second circuit includes a second buffer for holding the reference value transmitted from the first buffer in the first circuit via the signal isolator, a carrier generator for generating a carrier signal, and a comparator for comparing the reference signal output by the second buffer with the carrier signal output by the carrier generator and outputting a gate drive signal.

[0056] In this way, the reference value transmitted through the signal isolator can be transmitted in a shorter time than when transmitting the gate drive signal, thereby making it possible to suppress the adverse effects that the gate drive signal generated on the second circuit side has on the signal passing through the signal isolator (i.e., the reference value).

[0057] It should be noted that various methods are possible for synchronizing the first circuit and the second circuit, and the method is not limited to the above-described embodiment.

Claims

1. a first circuit; a second circuit; and a signal isolator for isolating and transmitting a signal from the first circuit to the second circuit; and The first circuit comprises: a reference generator for generating a reference value; a first buffer for holding the reference value; a synchronization signal generator that generates a synchronization signal for synchronizing the first circuit and the second circuit; and The second circuit includes: a second buffer for holding the reference value transmitted from the first buffer in the first circuit through the signal isolator; a carrier generator that generates a carrier signal synchronized with the synchronization signal transmitted from the first circuit through the signal isolator; a comparator that compares the reference signal output by the second buffer with the carrier signal output by the carrier generator and outputs a gate drive signal; A gate drive circuit having:

2. the first buffer holds the reference value generated by the reference generator for a certain period of time and transmits the reference value to the second circuit via the signal isolator; The second buffer holds the reference value transmitted from the first buffer in the first circuit via the signal isolator during a period corresponding to the certain period, and outputs the reference value transmitted during the certain period and held during the period next to the period corresponding to the certain period.

2. The gate drive circuit according to claim 1.

3. The first buffer outputs the reference value in the certain period after receiving the reference value from the reference generator so as to avoid a time when the gate drive signal changes.

3. The gate drive circuit according to claim 2.

4. The synchronization signal is at least one of a first signal representing the timing of the maximum value of the carrier signal and a second signal representing the timing of the minimum value of the carrier signal.

2. The gate drive circuit according to claim 1.

5. When the synchronization signal includes the first signal and the second signal, The carrier generator includes: The second buffer switches between receiving only the first signal, receiving only the second signal, and receiving both the first and second signals in a period following the certain period based on the reference value received in the certain period, and adjusts the carrier signal based on the received signal.

5. The gate drive circuit according to claim 4.

6. When the synchronization signal includes the first signal and the second signal, The second buffer comprises: determining whether reception of only the first signal, reception of only the second signal, or reception of both the first and second signals is appropriate in a period following the certain period based on the reference value received in the certain period, and outputting a selection signal representing the appropriate signal to the carrier generator; The carrier generator includes: Based on the selection signal from the second buffer, the receiver switches between receiving only the first signal, receiving only the second signal, and receiving both the first and second signals, and adjusts the carrier signal based on the received signal.

5. The gate drive circuit according to claim 4.

7. The carrier generator includes: adjusting the value of the carrier signal to a maximum value when the first signal is received; When the second signal is received, the value of the carrier signal is adjusted to a minimum value.

5. The gate drive circuit according to claim 4.

8. The second circuit includes: a second synchronization signal generator that generates a second synchronization signal synchronized with the synchronization signal transmitted from the first circuit through the signal isolator; The second buffer outputs the reference value to the comparator in response to a second synchronization signal from the second synchronization signal generator.

3. The gate drive circuit according to claim 2.

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