Processing device, processing method, and program

Abstract

To provide a processor capable of specifying a pseudo error without manual processing.SOLUTION: Preparing a plurality of pieces of data each including a set of input data and output data, the input data associating a net list of a circuit, a layout of the circuit, and an electrical rule for physically realizing the circuit generated based on the layout with each other, the output data indicating a true error or a pseudo error that is a result for the input data; And a neural network in which weighting is adjusted such that a true error or a pseudo error which is output data of the same set as input data is output in a case where each piece of input data of the plurality of sets of prepared data is input, and a true error or a pseudo error which is an error corresponding to new input data is output in a case where the new input data is input.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present disclosure relates to a processing device, a processing method, and a program. [Background technology]

[0002] In the field of circuit design, whether a physically manufactured circuit satisfies electrical requirements is verified in a simulation stage before manufacturing. Patent Document 1 discloses a related technology for detecting pseudo errors in the inspection process of mask patterns used in the manufacture of semiconductor devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-227407 Summary of the Invention [Problem to be solved by the invention]

[0004] One of the above-mentioned verifications is the Electrical Rule Check (ERC). ERC is a set of electrical rules that are uniquely defined based on worst-case scenarios according to the process used to physically realize a designed circuit. When verifying a circuit using such uniquely defined rules, depending on the specifications of the circuit being designed, the rules may be over-specified for the designed circuit. Therefore, it is not necessary to follow all electrical rules. Errors identified in verification using the electrical rules may be considered pseudo-errors, which are not actually problems. However, pseudo-errors are generally determined visually by humans. Therefore, in the field of circuit design related to Patent Document 1, there is a demand for technology that can identify pseudo-errors without manual processing.

[0005] One of the objectives of each aspect of the present disclosure is to provide a processing device, a processing method, and a program that can solve the above-mentioned problems. [Means for solving the problem]

[0006] According to one aspect of the present disclosure, a processing device includes: a neural network that prepares a plurality of sets of data, each set consisting of input data associating a netlist of a circuit, a layout of the circuit, and electrical rules for physically realizing connections of the circuit generated based on the layout, and output data indicating true errors or pseudo errors that are actual results for the input data; adjusts weighting so that when input data of the plurality of sets of prepared data is input, it outputs true errors or pseudo errors that are output data of the same set as the input input data; and when new input data is input, it outputs true errors or pseudo errors that are errors corresponding to the new input data. .

[0007] According to another aspect of the present disclosure, a processing method includes: The method includes: preparing a plurality of sets of data each consisting of input data associating a netlist of a circuit, a layout of the circuit, and electrical rules for physically realizing connections of the circuit generated based on the layout, and output data indicating true errors or pseudo errors that are actual results for the input data; adjusting weights of a neural network so that when inputting each of the plurality of sets of prepared input data, the neural network outputs true errors or pseudo errors that are output data of the same set as the input data; and when new input data is input to the neural network, outputting true errors or pseudo errors that are errors corresponding to the new input data. .

[0008] According to another aspect of the present disclosure, a program includes: The computer is caused to prepare a plurality of sets of data, each set being made up of input data associating a netlist of a circuit, a layout of the circuit, and electrical rules for physically realizing connections of the circuit generated based on the layout, and output data indicating true errors or pseudo errors that are actual results for the input data, and adjust weighting of a neural network so that when inputting each of the plurality of sets of prepared input data, the neural network outputs true errors or pseudo errors that are output data of the same set as the inputted input data, and when new input data is input to the neural network, outputs true errors or pseudo errors that are errors corresponding to the new input data. . [Effects of the Invention]

[0009] According to each aspect of the present disclosure, pseudo errors can be identified without manual processing. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 illustrates an example of a configuration of a processing system according to some embodiments of the present disclosure. [Figure 2] FIG. 1 illustrates an example of a netlist used in a past ERC according to some embodiments of the present disclosure. [Figure 3] FIG. 10 is a diagram illustrating an example of layout information used in a past ERC according to some embodiments of the present disclosure. [Figure 4] FIG. 10 is a diagram illustrating an example of ERC rule information used in a past ERC according to some embodiments of the present disclosure. [Figure 5] FIG. 10 illustrates an example of an execution report according to some embodiments of the present disclosure. [Figure 6] FIG. 10 is a diagram illustrating an example of past ERC results stored in a DB according to some embodiments of the present disclosure. [Figure 7] FIG. 1 is a diagram illustrating an example of a processing flow of a processing system according to some embodiments of the present disclosure. [Figure 8]FIG. 10 is a diagram illustrating an example of a configuration of a processing system according to modified examples of some embodiments of the present disclosure. [Figure 9] FIG. 1 illustrates an example of a configuration of a processing system according to some embodiments of the present disclosure. [Figure 10] FIG. 1 is a diagram illustrating an example of a processing flow of a processing system according to some embodiments of the present disclosure. [Figure 11] FIG. 1 is a schematic block diagram illustrating the configuration of a computer according to at least one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, the embodiments will be described in detail with reference to the drawings. <Embodiment> A processing system 1 according to an embodiment of the present disclosure will be described with reference to the drawings. The processing system 1 is a system that identifies pseudo errors in an Electrical Rule Check (hereinafter referred to as "ERC") when designing an electric circuit.

[0012] (Processing system configuration) FIG. 1 is a diagram illustrating an example of a configuration of a processing system 1 according to some embodiments of the present disclosure. As illustrated in FIG. 1 , the processing system 1 according to one embodiment of the present disclosure includes a CAD (Computer Aided Design) system 10, a database (hereinafter referred to as “DB”) 20, an artificial intelligence (hereinafter referred to as “AI”) 30, and a notification device 40. FIG. 1 also illustrates files (i.e., a netlist F1, layout information F2, ERC rule information F3, and execution report F4, which will be described later) used or generated by the CAD system 10 when executing a tool, as well as processes performed by a user. The ERC rules indicate rules for checking the reliability of electrical characteristics in a process of circuit elements used in the design of an electrical circuit using a layout indicated by layout information F2.

[0013] The CAD system 10 is a system capable of executing various tools for designing electrical circuits. Examples of tools that the CAD system 10 can execute include a tool that defines the connections between circuit elements in an electrical circuit, a tool that performs simulations to confirm the functionality of an electrical circuit with defined connections, a layout tool that physically generates an electrical circuit that has been confirmed to have the desired functionality, and an ERC that checks whether the layout is electrically problem-free (i.e., whether it is within a range defined by rules). Details of the processing performed by the CAD system 10 will be described later.

[0014] The DB20 stores the results of past ERCs. The results of past ERCs stored in the DB20 include a netlist F1 used in the past ERC, layout information F2 used in the past ERC, ERC rule information F3 used in the past ERC, and an execution report F4 of the past ERC. FIG. 2 is a diagram illustrating an example of the netlist F1 used in the past ERC according to some embodiments of the present disclosure. FIG. 3 is a diagram illustrating an example of layout information F2 used in the past ERC according to some embodiments of the present disclosure. FIG. 4 is a diagram illustrating an example of ERC rule information F3 used in the past ERC according to some embodiments of the present disclosure. FIG. 5 is a diagram illustrating an example of an execution report F4 according to some embodiments of the present disclosure. FIG. 6 is a diagram illustrating an example of the results of past ERCs stored in the DB20 according to some embodiments of the present disclosure.

[0015] As shown in Fig. 2, each of netlists #1 to #10000 in netlist F1 includes a netlist of an overall circuit, given the netlist name of the overall circuit, and netlists of subcircuits included in the overall circuit, given the netlist names of the subcircuits. For example, as shown in Fig. 2, netlist #1 includes a netlist of an overall circuit, given the netlist name of overall circuit A1, and netlists of three subcircuits, given the netlist names of subcircuits A1_a1, A1_a2, and A1_a3. Also, as shown in Fig. 2, netlist #2 includes a netlist of an overall circuit, given the netlist name of overall circuit A1, and netlists of four subcircuits, given the netlist names of subcircuits A2_a1, A2_a2, A2_a3, and A2_a4. Also, for example, as shown in FIG. 2, netlist #10000 includes a netlist of an overall circuit with the netlist name overall circuit A10000, and netlists of three subcircuits with the netlist names subcircuits A10000_a1, A10000_a2, and 10000_a3.

[0016] 3, each of layouts #1 to #10000 in layout information F2 includes a layout with an overall circuit layout name and a subcircuit layout included in the overall circuit layout with a subcircuit netlist name. For example, as shown in FIG. 3, layout #1 includes a layout with an overall circuit layout name of layout A1 and three subcircuit layout names of layouts A1_a1, A1_a2, and A1_a3. For example, as shown in FIG. 3, layout #2 includes a layout with an overall circuit layout name of layout A2 and four subcircuit layout names of A2_a1, A2_a2, A2_a3, and A2_a4. Also, for example, as shown in FIG. 3, layout #10000 includes a layout whose overall circuit layout name is layout A10000, and three subcircuit layouts whose subcircuit layout names are A10000_a1, A10000_a2, and 10000_a3.

[0017] 4, each of ERC#1 to #10000 in the ERC rule information F3 includes an ERC rule with an ERC rule name. For example, as shown in FIG. 4, ERC#1 includes an ERC rule with an ERC rule name ERC rule A1. For example, ERC#2 includes an ERC rule with an ERC rule name ERC rule A2. For example, ERC#10000 includes an ERC rule with an ERC rule name ERC rule A10000.

[0018] 5, each of the judgment results #1 to #10000 in the execution report F4 includes information indicating whether or not there is an error in the overall circuit, and if it is determined that there is an error in the overall circuit, whether the layout of the subcircuit in which the error occurred is a true error or a pseudo-error. For example, as shown in FIG. 5, judgment result #1 includes information indicating that there is no error in the overall circuit. For example, as shown in FIG. 5, judgment result #2 includes information indicating that there is an error in the overall circuit, information indicating that subcircuit layouts A2_a2 and A2_a3 are true errors, and information indicating that subcircuit layout A2_a4 is a pseudo-error. For example, as shown in FIG. 5, judgment result #10000 includes information indicating that there is an error in the overall circuit, and information indicating that subcircuit layouts A10000_a1 and A10000_a3 are pseudo-errors.

[0019] Then, the DB20 associates and stores the corresponding netlist, layout, ERC rule, and judgment result. For example, as shown in Fig. 6, the DB20 associates and stores the netlist #1 shown in Fig. 2, the layout #1 shown in Fig. 3, the ERC #1 shown in Fig. 4, and the judgment result #1 shown in Fig. 5. Also, as shown in Fig. 6, the DB20 associates and stores the netlist #2 shown in Fig. 2, the layout #2 shown in Fig. 3, the ERC #2 shown in Fig. 4, and the judgment result #2 shown in Fig. 5. Also, as shown in Fig. 6, the DB20 associates and stores the netlist #10000 shown in Fig. 2, the layout #10000 shown in Fig. 3, the ERC #10000 shown in Fig. 4, and the judgment result #10000 shown in Fig. 5.

[0020] The AI30 is, for example, a neural network using deep learning technology. For example, the AI30 determines weights (i.e., coefficients) in the neural network by performing supervised learning using past ERC results stored in the DB20 as training data. Specifically, for example, the netlist, layout, and ERC rules in each of the past ERC results stored in the DB20 (for example, DB#1 to #10000 shown in FIG. 6) are used as inputs, and the weights of the neural network included in the AI30 are determined so that the corresponding judgment results are output.

[0021] If the results of the ERC performed on the netlist of the new overall circuit and the layout of the overall circuit contain an error, the trained AI 30 determines whether the error is a true error or a pseudo-error. For example, the trained AI 30 is input with the netlist of the new overall circuit, the netlist of the subcircuits included in the overall circuit, the layout of the overall circuit, the layout of the subcircuits included in the layout of the overall circuit, and the ERC rule used for the ERC. As a result, the trained AI 30 outputs a determination result corresponding to the input. Note that the determination result output by the trained AI 30 includes the presence or absence of an error in the overall circuit, and, if it is determined that there is an error in the overall circuit, includes information indicating whether the layout of the subcircuit in which the error occurred is a true error or a pseudo-error.

[0022] The notification device 40 notifies the determination result output by the AI ​​30.

[0023] The above-described processing performed by the processing system 1 according to the embodiment of the present disclosure is merely an example, and the processing system 1 is not limited to the above-described processing. For example, the processing system 1 may perform the processing described below.

[0024] (Processing performed by the processing system) 7 is a diagram illustrating an example of a processing flow of the processing system 1 according to some embodiments of the present disclosure. Here, a description will be given of the processing performed by the processing system 1. Note that the AI ​​30 is a neural network that uses deep learning technology, and is assumed to be a learned AI in which the weighting (i.e., coefficients) of the neural network is determined by performing supervised learning using the results of past ERCs stored in the DB 20 as training data.

[0025] The user performs an operation to store information indicating the connections between the circuit elements in the electric circuit in a tool that defines the connections between the circuit elements in the electric circuit of the CAD system 10. In response to this operation by the user, the CAD system 10 defines the connections between the circuit elements in the electric circuit (step S1). The definition of the connections between the circuit elements in step S1 is realized by the CAD system 10 generating a netlist F1 that indicates the netlist of the electric circuit.

[0026] The user also sets simulation conditions for a tool that executes a simulation to confirm the function of the electrical circuit whose connections have been specified, and performs an operation to execute the simulation under the set conditions. In response to this operation by the user, the CAD system 10 executes a simulation to confirm the function of the electrical circuit (step S2). If it is confirmed that there are no problems with the simulation results in step S2, the netlist of the electrical circuit is finalized. Note that this netlist of the electrical circuit includes a netlist of the entire electrical circuit and netlists of subcircuits included in the entire electrical circuit.

[0027] The user then performs an operation to lay out the electrical circuit using a layout tool for physically generating the electrical circuit that has been confirmed to have the desired functionality, and saves layout information F2 indicating the layout that has been executed. In response to this operation by the user, the CAD system 10 draws the layout and stores layout information F2 indicating the layout (step S3). Note that this electrical circuit layout includes the layout of the entire electrical circuit and the layout of each subcircuit included in the entire electrical circuit.

[0028] The user also performs an operation to set ERC rule information F3, which indicates ERC rules, in a tool for executing ERC. Then, the user performs an operation to have the CAD system 10 execute ERC. In response to the user's operation, the CAD system 10 executes ERC on the layout indicated by the layout information F2 using the ERC rule information F3 (step S4). Then, the CAD system 10 outputs an execution report F4, which is the result of executing the ERC (step S5). The CAD system 10 also outputs a netlist F1 (step S6). The CAD system 10 also outputs the layout information F2 (step S7).

[0029] The trained AI 30 is input with a netlist of the entire electrical circuit, a netlist of the subcircuits included in the entire electrical circuit, a layout of the entire electrical circuit, a layout of the subcircuits included in the layout of the entire electrical circuit, and the ERC rule used for the ERC. As a result, the trained AI 30 outputs a determination result corresponding to the input to the alarm device 40 (step S8). The determination result output by the trained AI 30 includes the presence or absence of an error in the entire electrical circuit, and, if it is determined that an error exists in the entire electrical circuit, includes information indicating whether the layout of the subcircuit in which the error occurred is a true error or a pseudo error.

[0030] Furthermore, if the AI ​​30 after learning determines that the error is a pseudo error, it deletes the error determined to be a pseudo error from the execution report F4 (step S9). Note that the AI ​​30 after learning may input the netlist of the entire electric circuit, the netlist of the subcircuits included in the entire electric circuit, the layout of the entire electric circuit, the layout of the subcircuits included in the layout of the entire electric circuit, and the ERC rule used for the ERC, associate these with the judgment result obtained as an output, and add them as new information to the information stored in the DB 20.

[0031] The notification device 40 notifies the determination result output by the AI ​​30 after learning (step S10).

[0032] (advantage) The processing system 1 according to an embodiment of the present disclosure has been described above. In the processing system 1 (an example of a processing device), the AI ​​30 (an example of a neural network) prepares a plurality of sets of input data, each of which associates a netlist of a circuit, a layout of the circuit, and an ERC rule (an example of an electrical rule) for physically realizing the circuit generated based on the layout, and adjusts weighting so that when each of the prepared sets of input data is input, a true error or a pseudo error corresponding to the input data is output, and when new input data is input, a true error or a pseudo error corresponding to the new input data is output.

[0033] This processing system 1 makes it possible to identify pseudo errors without manual processing.

[0034] In addition, in the processing system 1 according to a modified example of the embodiment of the present disclosure, the user may confirm the content processed by the AI ​​30. Fig. 8 is a diagram showing an example of the configuration of the processing system 1 according to a modified example of the embodiment of the present disclosure. As shown in Fig. 8, the user may confirm the content of the execution report F4 processed by the AI ​​30, and the confirmed content may be reflected in the CAD system 10 and the DB 20.

[0035] Next, a processing system 1 according to some embodiments of the present disclosure will be described. Fig. 9 is a diagram illustrating an example of the configuration of the processing system 1 according to some embodiments of the present disclosure. As shown in Fig. 9, the processing system 1 includes a neural network 301.

[0036] The neural network 301 prepares multiple sets of data, each set consisting of input data that associates a circuit netlist, a layout of the circuit, and electrical rules for physically realizing the circuit generated based on the layout, and output data that indicates true errors or pseudo-errors that are actual results for the input data.The weighting is adjusted so that when each of the multiple sets of input data prepared is input, a true error or pseudo-error that is the output data of the same set as the input data is output, and when new input data is input, a true error or pseudo-error that is an error corresponding to the new input data is output.

[0037] The neural network 301 can be realized, for example, by using the functions of the AI ​​30 illustrated in FIG. 1 or FIG.

[0038] Next, processing performed by the processing system 1 according to some embodiments of the present disclosure will be described. Fig. 10 is a diagram showing an example of a processing flow of the processing system 1 according to some embodiments of the present disclosure. Here, the processing of the processing system 1 will be described with reference to Fig. 10.

[0039] The neural network 301 prepares multiple sets of data, each set consisting of input data that associates a circuit netlist, a layout of the circuit, and electrical rules for physically realizing the circuit generated based on the layout, and output data that indicates true errors or pseudo-errors that are actual results for the input data.The weighting is adjusted so that when each of the multiple sets of input data prepared is input, a true error or pseudo-error that is the output data of the same set as the input data is output, and when new input data is input, a true error or pseudo-error that is an error corresponding to the new input data is output (step S101).

[0040] The processing system 1 according to some embodiments of the present disclosure has been described above. This processing system 1 makes it possible to identify pseudo errors without manual processing.

[0041] The order of the processes in each embodiment of the present disclosure may be changed as long as the processes are performed appropriately.

[0042] Each embodiment of the present disclosure has been described, but the processing system 1, CAD system 10, database 20, AI 30, notification device 40, and other control devices may have a computer system built therein. The above-described processing steps are stored in the form of a program on a computer-readable recording medium, and the computer reads and executes this program to perform the above processing. Specific examples of computers are shown below.

[0043] 11 is a schematic block diagram showing the configuration of a computer according to at least one embodiment. As shown in FIG. 11, the computer 5 includes a CPU (Central Processing Unit) 6, a main memory 7, a storage 8, and an interface 9.

[0044] For example, the above-described processing system 1, CAD system 10, database 20, AI 30, notification device 40, and other control devices are each implemented in a computer 5. The operations of the above-described processing units are stored in the form of a program in storage 8. CPU 6 reads the program from storage 8, loads it into main memory 7, and executes the above-described processing in accordance with the program. Furthermore, CPU 6 allocates storage areas in main memory 7 corresponding to the above-described storage units in accordance with the program.

[0045] Examples of storage 8 include a hard disk drive (HDD), a solid state drive (SSD), a magnetic disk, a magneto-optical disk, a compact disc read-only memory (CD-ROM), a digital versatile disc read-only memory (DVD-ROM), and a semiconductor memory. Storage 8 may be an internal medium directly connected to the bus of computer 5, or an external medium connected to computer 5 via interface 9 or a communication line. In addition, when this program is distributed to computer 5 via a communication line, computer 5 that receives the program may load the program into main memory 7 and execute the above-mentioned processing. In at least one embodiment, storage 8 is a non-transitory tangible storage medium.

[0046] The program may also implement some of the functions described above. Furthermore, the program may be a file that can implement the functions described above in combination with a program already recorded in the computer system, a so-called differential file (differential program).

[0047] Although several embodiments of the present disclosure have been described, these embodiments are merely examples and do not limit the scope of the disclosure. Various additions, omissions, substitutions, and modifications may be made to these embodiments without departing from the spirit of the disclosure.

[0048] Note that part or all of the above-described embodiments can be described as, but are not limited to, the following supplementary notes.

[0049] (Appendix 1) a neural network that prepares a plurality of sets of data each consisting of input data associating a netlist of a circuit, a layout of the circuit, and electrical rules for physically realizing the circuit generated based on the layout, and output data indicating true errors or pseudo errors that are actual results for the input data, and that adjusts weighting so that when input data of the plurality of sets of prepared data is input, it outputs true errors or pseudo errors that are the same set of output data as the input input data, and when new input data is input, it outputs true errors or pseudo errors that are errors corresponding to the new input data; A processing device comprising:

[0050] (Appendix 2) a notification device that notifies the true error or the pseudo error output by the neural network; 2. The processing device of claim 1, comprising:

[0051] (Appendix 3) a storage means for storing the plurality of sets of data consisting of the input data and the output data indicating true errors or pseudo errors that are actual results for the input data; 2. The processing device of claim 1, comprising:

[0052] (Appendix 4) The storage means storing the new input data and the true error or the pseudo error output by the neural network for the new input data as a new set of data; 4. The processing device of claim 3.

[0053] (Appendix 5) preparing a plurality of sets of data each consisting of input data associating a netlist of a circuit, a layout of the circuit, and electrical rules for physically realizing the circuit generated based on the layout, and output data indicating true errors or pseudo errors that are actual results for the input data, and adjusting weighting of the neural network so that when each of the prepared sets of input data is input, true errors or pseudo errors that are the same set of output data as the input input data are output; When new input data is input to the neural network, a true error or a pseudo error corresponding to the new input data is output; A processing method comprising:

[0054] (Appendix 6) notifying the true error or the pseudo error; Attachment 5, a processing method comprising:

[0055] (Appendix 7) storing the plurality of sets of data consisting of the input data and the output data indicating actual true errors or pseudo errors for the input data; 6. The method of claim 5, further comprising:

[0056] (Appendix 8) storing the new input data and the true error or the pseudo error output by the neural network for the new input data as a new set of data; 9. The processing method according to any one of appendices 5 to 8, including:

[0057] (Appendix 9) On the computer, preparing a plurality of sets of data each consisting of input data associating a netlist of a circuit, a layout of the circuit, and electrical rules for physically realizing the circuit generated based on the layout, and output data indicating true errors or pseudo errors that are actual results for the input data, and adjusting weighting of the neural network so that when each of the prepared sets of input data is input, true errors or pseudo errors that are the same set of output data as the input input data are output; When new input data is input to the neural network, a true error or a pseudo error corresponding to the new input data is output; A program that executes the following.

[0058] (Appendix 10) notifying the true error or the pseudo error; 10. The program according to claim 9, which causes the computer to execute the above steps.

[0059] (Appendix 11) storing the plurality of sets of data consisting of the input data and the output data indicating actual true errors or pseudo errors for the input data; 11. The program according to claim 9 or 10, which causes the computer to execute the above.

[0060] (Appendix 12) storing the new input data and the true error or the pseudo error output by the neural network for the new input data as a new set of data; 12. The program according to any one of claims 9 to 11, which causes the computer to execute the above. [Explanation of symbols]

[0061] 1. Processing System 5. Computer 6 CPU 7. Main memory 8. Storage 9. Interface 10. CAD system 20···DB 30···AI 40 Alarm device 301 Neural Networks

Claims

1. a neural network that prepares a plurality of sets of data each consisting of input data associating a netlist of a circuit, a layout of the circuit, and electrical rules for physically realizing connections of the circuit generated based on the layout, and output data indicating true errors or pseudo errors that are actual results for the input data, and that adjusts weighting so that when input data of the plurality of sets of prepared data is input, it outputs true errors or pseudo errors that are output data of the same set as the input data, and when new input data is input, it outputs true errors or pseudo errors that are errors corresponding to the new input data; A processing device comprising:

2. a notification device that notifies the true error or the pseudo error output by the neural network; The processing device of claim 1 , comprising:

3. a storage means for storing the plurality of sets of data consisting of the input data and the output data indicating true errors or pseudo errors that are actual results for the input data; The processing device of claim 1 , comprising:

4. The storage means storing the new input data and the true error or the pseudo error output by the neural network for the new input data as a new set of data; The processing device according to claim 3 .

5. preparing a plurality of sets of data each consisting of input data associating a netlist of a circuit, a layout of the circuit, and electrical rules for physically realizing connections of the circuit generated based on the layout, and output data indicating true errors or pseudo errors that are actual results for the input data, and adjusting weighting of the neural network so that when each of the prepared sets of input data is input, true errors or pseudo errors that are the same set of output data as the input input data are output; When new input data is input to the neural network, a true error or a pseudo error corresponding to the new input data is output; A processing method comprising:

6. On the computer, preparing a plurality of sets of data each consisting of input data associating a netlist of a circuit, a layout of the circuit, and electrical rules for physically realizing connections of the circuit generated based on the layout, and output data indicating true errors or pseudo errors that are actual results for the input data, and adjusting weighting of the neural network so that when each of the prepared sets of input data is input, true errors or pseudo errors that are the same set of output data as the input input data are output; When new input data is input to the neural network, a true error or a pseudo error corresponding to the new input data is output; A program that executes the following.

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