Localized stress regions for three-dimensional chiplet formation.

Abstract

An aspect of the present disclosure provides a method of forming chiplets on a semiconductor structure. The method may include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side of the first semiconductor structure, and attaching the first side to a carrier substrate. The method may further include forming a composite of a first stress film and a second stress film on a second side of the first semiconductor structure, and separating the carrier substrate from the first semiconductor structure. The method may further include cutting the composite of the first stress film and the second stress film and the first semiconductor structure to define at least one chiplet, and coupling the at least one chiplet to a second semiconductor structure having a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.

Description

[Technical Field]

[0001] Incorporation by Reference This disclosure claims the benefit of U.S. Provisional Patent Application No. 63 / 141,552, entitled "Method of Making Localized Stress Regions for Advanced 3D Chiplet Formation," filed January 26, 2021, and U.S. Provisional Patent Application No. 63 / 141,553, entitled "Method of Making Localized Stress Regions for Advanced 3D Chiplet Formation," filed January 26, 2021, the contents of which are incorporated by reference herein in their entireties.

[0002] The present disclosure relates generally to microelectronic devices, including semiconductor devices, transistors, and integrated circuits, including methods of microfabrication. [Background technology]

[0003] The fabrication of semiconductor devices (especially on a microscopic scale) involves various fabrication processes, such as film formation deposition, etch mask creation, patterning, material etching and removal, and doping processes. These processes are performed repeatedly to form desired semiconductor device elements on a substrate. Historically, in microfabrication, transistors have been created in a single plane, with wiring / metallization formed above the active device plane, and are therefore characterized as two-dimensional (2D) circuits or 2D fabrication. While scaling efforts have significantly increased the number of transistors per unit area in 2D circuits, scaling efforts face greater challenges as scaling enters single-digit nanometer semiconductor device fabrication nodes. Semiconductor device manufacturers have expressed a desire for three-dimensional (3D) semiconductor circuits in which transistors are stacked on top of each other. Summary of the Invention [Means for solving the problem]

[0004] Aspects of the present disclosure provide a method for forming chiplets on a semiconductor structure. For example, the method may include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side of the first semiconductor structure, and attaching the first side of the first semiconductor structure to a carrier substrate. The method may further include forming a stress film on a second side of the first semiconductor structure and separating the carrier substrate from the first semiconductor structure. The method may further include cutting the stress film and the first semiconductor structure to define at least one chiplet, and bonding the at least one chiplet to a second semiconductor structure having a second circuit and a second wiring structure, such that the second wiring structure is connected to the first wiring structure. In one embodiment, the method may further include removing the stress film after the at least one chiplet is bonded to the second semiconductor structure.

[0005] In one embodiment, the method may further include patterning the stress film to form a patterned stress film, and cutting the stress film and the first semiconductor structure to define the at least one chiplet may include cutting the patterned stress film and the first semiconductor structure to define the at least one chiplet. In one embodiment, the patterned stress film may be formed via a mask-based lithography tool, ultraviolet (UV) crosslinking, or a direct-write lithography tool. For example, the patterned stress film may be formed via a direct-write lithography tool using a digital light processing (DLP) chip, a grating light valve, or a laser galvanometer. In one embodiment, the method may further include removing the patterned stress film after the at least one chiplet is bonded to the second semiconductor structure.

[0006] In one embodiment, the first semiconductor structure may further include a first dielectric layer formed on the second surface thereof, and forming the stress film on the second surface of the first semiconductor structure may include forming the stress film on the first dielectric layer of the first semiconductor structure. For example, the first semiconductor structure may further include a first substrate formed on the first dielectric layer, and the method may further include removing the first substrate to expose the first dielectric layer before forming the stress film on the first dielectric layer of the first semiconductor structure.

[0007] In an embodiment, the first surface of the first semiconductor structure can be attached to a carrier substrate using an attachment material, and separating the carrier substrate from the first semiconductor structure can include heating the attachment material such that the carrier substrate is separated from the first semiconductor structure.

[0008] Aspects of the present disclosure further provide another method for forming chiplets on a semiconductor structure. For example, the method may include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side of the first semiconductor structure and attaching the first side of the first semiconductor structure to a carrier substrate. The method may further include forming a stress film on a second side of the first semiconductor structure and cutting the stress film and the first semiconductor structure to define at least one chiplet. The method may further include separating the carrier substrate from the at least one chiplet and coupling the at least one chiplet to a second semiconductor structure having a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.

[0009] In one embodiment, the method can further include patterning the stress film to form a patterned stress film, and cutting the stress film and the first semiconductor structure to define the at least one chiplet can include cutting the patterned stress film and the first semiconductor structure to define the at least one chiplet. In one embodiment, the patterned stress film can be formed via a mask-based lithography tool, UV crosslinking, or a direct-write lithography tool. For example, the patterned stress film can be formed via a direct-write lithography tool using a DLP tip, a grating light valve, or a laser galvanometer.

[0010] In one embodiment, the first semiconductor structure may further include a first dielectric layer formed on the second surface thereof, and forming the stress film on the second surface of the first semiconductor structure may include forming the stress film on the first dielectric layer of the first semiconductor structure. For example, the first semiconductor structure may further include a first substrate formed on the first dielectric layer, and the method may further include removing the first substrate to expose the first dielectric layer before forming the stress film on the first dielectric layer of the first semiconductor structure.

[0011] In one embodiment, the first surface of the first semiconductor structure can be attached to a carrier substrate using an attachment material, and cutting the stress film and the first semiconductor structure to define the at least one chiplet can include cutting the stress film, the first semiconductor structure, and the attachment material to define the at least one chiplet. For example, cutting the stress film, the first semiconductor structure, and the attachment material to define the at least one chiplet can include cutting the stress film, the first semiconductor structure, the attachment material, and a portion of the carrier substrate to define the at least one chiplet.

[0012] In an embodiment, the first surface of the first semiconductor structure can be attached to a carrier substrate using an attachment material, and separating the carrier substrate from the at least one chiplet can include heating the attachment material such that the carrier substrate is separated from the at least one chiplet.

[0013] In one embodiment, the method may further include forming a chiplet support on the stress film of the at least one chiplet before separating the carrier substrate from the at least one chiplet. For example, the method may further include removing the chiplet support and the stress film after the at least one chiplet is bonded to the second semiconductor structure.

[0014] This "Summary of the Invention" section does not specify every embodiment and / or inherently novel aspect of the invention described in this disclosure or claimed herein. Rather, this summary merely provides a preliminary description of various embodiments and corresponding novelties over the prior art. For additional details and / or anticipated aspects of the invention and embodiments, the reader is directed to the "Detailed Description of the Invention" section of this disclosure and corresponding drawings, as further discussed below.

[0015] Aspects of the present disclosure provide a method for forming chiplets on a semiconductor structure. For example, the method may include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side of the first semiconductor structure and attaching the first side of the first semiconductor structure to a carrier substrate. The method may further include forming a composite of a first stress film and a second stress film on a second side of the first semiconductor structure and separating the carrier substrate from the first semiconductor structure. The method may further include cutting the composite of the first stress film and the second stress film and the first semiconductor structure to define at least one chiplet and bonding the at least one chiplet to a second semiconductor structure having a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure. In an embodiment, the method may further include removing the composite of the first stress film and the second stress film after the at least one chiplet is bonded to the second semiconductor structure.

[0016] In one embodiment, the first semiconductor structure may further include a first dielectric layer formed on the second side of the first semiconductor structure, and forming the composite of the first stress film and the second stress film on the second side of the first semiconductor structure may include forming the composite of the first stress film and the second stress film on the first dielectric layer of the first semiconductor structure. For example, the first semiconductor structure may further include a first substrate formed on the first dielectric layer, and the method may further include removing the first substrate to expose the first dielectric layer before forming the composite of the first stress film and the second stress film on the first dielectric layer of the first semiconductor structure.

[0017] In an embodiment, the first surface of the first semiconductor structure can be attached to a carrier substrate using an attachment material, and separating the carrier substrate from the first semiconductor structure can include heating the attachment material such that the carrier substrate is separated from the first semiconductor structure.

[0018] In one embodiment, the method may further include patterning the first stress film to form a first patterned stress film, and cutting the composite of the first stress film and the second stress film and the first semiconductor structure to define at least one chiplet may include cutting the composite of the first patterned stress film and the second stress film and the first semiconductor structure to define at least one chiplet. For example, the first patterned stress film may be formed with at least one stress region, and the second stress film may be formed within the at least one stress region. As another example, the second stress film may be further formed on the first patterned stress film. In one embodiment, the first patterned stress film may be formed via a mask-based lithography tool, ultraviolet (UV) crosslinking, or a direct-write lithography tool. For example, the first patterned stress film may be formed via a direct-write lithography tool using a digital light processing (DLP) chip, a grating light valve, or a laser galvanometer. In an embodiment, the method may further include removing the composite of the first patterned stress film and the second stress film after the at least one chiplet is bonded to the second semiconductor structure.

[0019] Aspects of the present disclosure further provide another method for forming chiplets on a semiconductor structure. For example, the method may include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side of the first semiconductor structure and attaching the first side of the first semiconductor structure to a carrier substrate. The method may further include forming a composite of a first stress film and a second stress film on a second side of the first semiconductor structure and cutting the composite of the first stress film and the second stress film and the first semiconductor structure to define at least one chiplet. The method may further include separating the carrier substrate from the at least one chiplet and coupling the at least one chiplet to a second semiconductor structure having a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.

[0020] In one embodiment, the method may further include patterning the first stress film to form a first patterned stress film, and cutting the composite of the first stress film and the second stress film and the first semiconductor structure to define at least one chiplet may include cutting the composite of the first patterned stress film and the second stress film and the first semiconductor structure to define at least one chiplet. For example, the first patterned stress film may be formed with at least one stress region, and the second stress film may be formed within the at least one stress region. As another example, the second stress film may be further formed on the first patterned stress film. In one embodiment, the first patterned stress film may be formed via a mask-based lithography tool, UV crosslinking, or a direct-write lithography tool.

[0021] In one embodiment, the first semiconductor structure may further include a first dielectric layer formed on the second side of the first semiconductor structure, and forming the composite of the first stress film and the second stress film on the second side of the first semiconductor structure may include forming the composite of the first stress film and the second stress film on the first dielectric layer of the first semiconductor structure. For example, the first semiconductor structure may further include a first substrate formed on the first dielectric layer, and the method may further include removing the first substrate to expose the first dielectric layer before forming the composite of the first stress film and the second stress film on the first dielectric layer of the first semiconductor structure.

[0022] In one embodiment, the first surface of the first semiconductor structure can be attached to a carrier substrate using an attachment material, and cutting the stress film and the first semiconductor structure to define the at least one chiplet can include cutting the stress film, the first semiconductor structure, and the attachment material to define the at least one chiplet. For example, cutting the stress film, the first semiconductor structure, and the attachment material to define the at least one chiplet can include cutting the stress film, the first semiconductor structure, the attachment material, and a portion of the carrier substrate to define the at least one chiplet.

[0023] This "Summary of the Invention" section does not specify every embodiment and / or inherently novel aspect of the invention described in this disclosure or claimed herein. Rather, this summary merely provides a preliminary description of various embodiments and corresponding novelties over the prior art. For additional details and / or anticipated aspects of the invention and embodiments, the reader is directed to the "Detailed Description of the Invention" section of this disclosure and corresponding drawings, as further discussed below.

[0024] Various embodiments of the present disclosure, proposed by way of example, will now be described in detail with reference to the following figures, in which like numbers refer to like elements, and in which: [Brief explanation of the drawings]

[0025] [Figure 1-10] 1A-1C are cross-sectional views illustrating a first exemplary method of forming chiplets on a semiconductor structure according to some embodiments of the present disclosure. [Figure 11-16] 10A-10C are cross-sectional views illustrating a second exemplary method of forming chiplets on a semiconductor structure according to some embodiments of the present disclosure. [Figure 17-20] 10A-10C are cross-sectional views illustrating a third exemplary method of forming chiplets on a semiconductor structure according to some embodiments of the present disclosure. [Figure 21] 10 is a flowchart illustrating a fourth exemplary method for forming chiplets on a semiconductor structure, according to some embodiments of the present disclosure. [Figure 22] 10 is a flowchart illustrating a fifth exemplary method for forming chiplets on a semiconductor structure, according to some embodiments of the present disclosure. [Figure 23-31] 1A-1C are cross-sectional views illustrating a first exemplary method of forming chiplets on a semiconductor structure according to some embodiments of the present disclosure. [Figure 32-36] 10A-10C are cross-sectional views illustrating a second exemplary method of forming chiplets on a semiconductor structure according to some embodiments of the present disclosure. [Figure 37-39] 10A-10C are cross-sectional views illustrating a third exemplary method of forming chiplets on a semiconductor structure according to some embodiments of the present disclosure. [Figure 40-44] 10A-10C are cross-sectional views illustrating a fourth exemplary method of forming chiplets on a semiconductor structure according to some embodiments of the present disclosure. [Figure 45] 10 is a flowchart illustrating a fifth exemplary method for forming chiplets on a semiconductor structure, according to some embodiments of the present disclosure. [Figure 46] 10 is a flowchart illustrating a sixth exemplary method for forming chiplets on a semiconductor structure, according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0026] 3D integration, or the vertical stacking of multiple devices, aims to overcome the scaling limitations experienced in planar devices by increasing transistor density in volume rather than area. While device stacking has been successfully demonstrated and implemented by the flash memory industry through the adoption of 3D NAND, its application to random logic designs is much more difficult in practice. 3D integration for logic chips (CPUs (Central Processing Units), GPUs (Graphics Processing Units), FPGAs (Field Programmable Gate Arrays), and SoCs (System on Chip)) is being promoted.

[0027] As microelectronic devices are fabricated on a wafer, the wafer itself is subjected to various stresses from various materials being added or removed, as well as processing steps such as annealing. Such stresses can cause overlay problems from wafer warping, distortion, and curvature. These problems can be exacerbated by stacking wafer-on-wafer. Technology herein includes systems and methods that alleviate troublesome issues related to wafer stress from stacked wafers and chiplets.

[0028] The techniques herein may include selective stress (or stressor) film techniques and the construction of relatively thin chiplets for attachment or bonding to semiconductor structures, such as wafers or dies. One or more layers of stress film may be deposited on a surface of the chiplet (e.g., the second or inactive surface of the backside, or the surface opposite the first active or functional surface of the frontside). In one embodiment, a direct-write lithography exposure tool may be used to write a compensated stress pattern on the backside of the chiplet before the chiplet is cut and placed on or bonded to a wafer. The chiplet may receive the same or different stress film and the same or different stress compensation pattern for localized stress regions. This allows for higher density stacking of 3D chiplets, as the thickness of the chiplet may be significantly reduced. These techniques enable higher die yields per wafer, as the wafer has less bow or curvature, enabling more precise photolithography.

[0029] The order of description of the various steps described herein is presented for clarity. In general, these steps can be performed in any suitable order. In addition, although each of the various features, techniques, configurations, etc. herein may be discussed in different parts of this disclosure, it is intended that each of these concepts can be implemented independently of each other or in combination with each other. Thus, the present invention can be embodied and viewed in many different ways.

[0030] 1-10 are cross-sectional views illustrating a first exemplary method for forming chiplets on a semiconductor structure according to some embodiments of the present disclosure. As shown in FIG. 1 , a first semiconductor structure 100 may be provided. In one embodiment, the first semiconductor structure 100 may have a first circuit (or first active circuit) 110 and a first wiring structure 120 formed on a first side 100A (or front active or functional side) of the first semiconductor structure 100. For example, the first circuit 110 may be formed within the bulk silicon 105 of the first semiconductor structure 100. As another example, the first wiring structure 120 may include vias and a copper layer. In one embodiment, the first circuit 110 and the first wiring structure 120 may be used as a chiplet. A chiplet, as used herein, may be a component device, an integrated circuit, or a component of a larger module, assembly, package, or integrated circuit. The chiplet may be cut from a larger device or wafer, such as the first semiconductor structure 100. The dotted lines shown in FIG. 1 may identify example chiplets.

[0031] In one embodiment, the first semiconductor structure 100 may further include a first dielectric layer 130 and a first substrate 140 formed on a second side (or backside or inactive side) 100B of the first semiconductor structure 100. For example, the first substrate 140 may be a silicon substrate. In fabricating the first semiconductor structure 100, a silicon-on-insulator (SOI) substrate composed of the first substrate 140, the first dielectric layer 130, and bulk silicon 105 may be provided, the first circuit 110 may be formed in the bulk silicon 105 via photolithography, and the first wiring structure 120 may be formed to connect to the first circuit 110.

[0032] 1 further shows a carrier substrate 150 for the first semiconductor structure 100 that is attached to the first semiconductor structure 100. For example, the carrier substrate 150 can be a silicon wafer.

[0033] 2, the first side 100A of the first semiconductor structure 100 may be attached to the carrier wafer 150 using an attachment material 210. For example, the attachment material 210 may be identified as an adhesion layer, a bonding layer, a method for joining wafers that can be subsequently removed, a semiconductor-to-semiconductor with a native oxide at a dielectric interface, a metal-metal, a metal with an oxide coating, a metal with a SiC coating, a metal with a SiCN coating, a metal with an attached film that includes a semiconductor with a coating of one or more elements, or a combination thereof.

[0034] 3, the first substrate 140 can be removed to expose the first dielectric layer 130. For example, the first semiconductor structure 100 can be planarized via chemical mechanical planarization (also called chemical mechanical polishing) (CMP), where the CMP stops at the first dielectric layer 130 and the first substrate 140 is removed to expose the first dielectric layer 130.

[0035] 4, a stress film 410 may be formed on the first dielectric layer 130. By depositing or forming the stress film 410 on the dielectric layer 130, any type of stress (i.e., compressive or tensile) can be induced in the bulk silicon 105. For example, a photoresist layer may be applied to the first dielectric layer 130 via spin coating or deposited on the first dielectric layer 130 to serve as the stress film 410. As another example, the stress film 410 may be made of silicon nitride, silicon oxide, etc., such as Si3N4, SiO x N y , Si, and SiO2. The stress film 410 can be an ultraviolet (UV) crosslinkable stress film including spin-on materials, such as benzocyclobutene (BCB) and other materials with crosslinking properties. For example, the spin-on material can be exposed by direct write exposure and then baked to complete the process and establish the desired stress pattern and can be used for any one of the exemplary methods.

[0036] As shown in FIG. 5 , the stress film 410 may optionally be patterned to form a patterned stress film 510. In one embodiment, the stress film 410 may be patterned, exposed, and developed to remove the reacted (e.g., positive) photoresist layer and form the patterned stress film 510. For example, a photomask may be used to form the patterned stress film 510. As another example, the stress film 410, e.g., a photoresist layer, may be patterned using a direct-write (or maskless) lithography tool, which simultaneously projects or uses a scanning motion to project a stress-altering pattern onto the photoresist layer or a layer having a photoreactive agent. The patterned photoresist layer may then be developed to create a relief pattern. This relief pattern may function as the stress film or may be transferred to an underlying layer to form the patterned stress film 510. For example, a digital light processing chip (DLP) may be used. As another example, a grating light valve or a laser galvanometer may be used. The direct write system can use a processing engine to control the amount / intensity of light at any given point on the substrate or film being exposed. Depending on the photo-reactive agent of the corresponding film, any of a variety of conventional light wavelengths can be used (or the film composition can be selected based on the available light wavelengths). For stress relaxation, exposure at a lower resolution is sufficient to create the desired stress modification (or patterned stress film 510). The stress modification pattern (or patterned stress film 510) herein can form regions with stress induced by the stress film (or patterned stress film) and regions with reduced or no stress where the first write tool has removed the stress film, resulting in a flatter substrate and optimizing photolithography accuracy.

[0037] 6, the deposition material 210 can be removed to separate the first semiconductor structure 100 from the carrier substrate 150. For example, the deposition material 210 can be an adhesive or bonding layer, which can be heated and evaporated so that the first semiconductor structure 100 can be separated from the carrier substrate 150.

[0038] As shown in FIG. 7 , the first semiconductor structure 100, together with the patterned stress film 510 (or stress film 410), can be cut, for example, via etching, to define multiple chiplets 750. Because the patterned stress film 510 (or stress film 410) is formed on the first semiconductor structure 100, the first semiconductor structure 100 (and chiplets 750) can receive the same or different stress films and the same or different stress compensation patterns for localized stress regions, allowing for less complex wafer stress, the first semiconductor structure 100 (and chiplets 750) to have reduced thickness, and higher density 3D chiplets to be stacked. One or more of the chiplets 750 can be bonded to another semiconductor structure. For example, the chiplets 750 can be bonded to a second semiconductor structure 700 having a second circuit 710 and a second wiring structure 720 corresponding to the first wiring structure 120 of the first semiconductor structure 100.

[0039] As shown in FIG. 8, a chiplet 750 may be coupled to a second semiconductor structure 700 with the first wiring structure 120 of the chiplet 750 connected to the second wiring structure 720 of the second semiconductor structure 700 .

[0040] 9, the patterned stress film 510 (or the stress film 410) can be removed to expose the first dielectric layer 130. For example, the patterned stress film 510 (or the stress film 410) can be removed via CMP, where the CMP stops at the first dielectric layer 130 to expose the first dielectric layer 130.

[0041] 10, the first dielectric layer 130 may be removed. For example, the first dielectric layer 130 may be removed via CMP. In one embodiment, the patterned stress film 510 (or stress film 410) and the first dielectric layer 130 may be removed in a single CMP process. Thus, the chiplet 750 bonded to the second semiconductor structure 700 can be very thin.

[0042] 11-16 are cross-sectional views illustrating a second exemplary method for forming chiplets on a semiconductor structure according to some embodiments of the present disclosure. The second exemplary method differs from the first exemplary method in that, prior to forming the stress film 410, both the first substrate 140 and the first dielectric layer 130 are removed, which may enable optimal stress transfer. As shown in FIG. 11 , which follows FIG. 2 , the first substrate 140 and the first dielectric layer 130 are removed. For example, the first substrate 140 and the first dielectric layer 130 may be removed in a single CMP process or in two corresponding CMP processes to expose the second side (or backside or inactive side) 100B of the first semiconductor structure 100.

[0043] 12, a stress film 410 can be formed on the second side 100B of the first semiconductor structure 100 and can be in direct contact with the bulk silicon 105 of the first semiconductor structure 100. For example, a photoresist layer can be deposited on the second side 100B to act as the stress film 410.

[0044] As shown in FIG. 13 , the stress film 410 may optionally be patterned to form a patterned stress film 510. In one embodiment, the stress film 410 may be patterned, exposed, and developed to remove the reacted (e.g., positive) resist layer and form the patterned stress film 510. For example, a photomask may be used to form the patterned stress film 510. As another example, the stress film 410, e.g., a photoresist layer, may be patterned using a direct-write technique. For example, a DLP chip may be used. As another example, a grating light valve or a laser galvanometer may be used. Depending on the photo-reactive agent of the corresponding film, any of a variety of conventional light wavelengths may be used (or the film composition may be selected based on the available light wavelength). For stress relaxation, exposure at a lower resolution may be sufficient to create the desired stress modification (or patterned stress film 510). The stress-altering pattern (or patterned stress film 510) herein can form regions with stress induced by the stress film (or patterned stress film) and regions with reduced or no stress where the first writing tool has removed at least a portion of the stress film, resulting in a more planar substrate and optimizing photolithography accuracy. While the pattern is shown extending only partially through the stress film 410 / patterned stress film 510, it should be understood that the pattern may extend completely therethrough to further modify the stress characteristics.

[0045] 14, the deposition material 210 can be removed to separate the first semiconductor structure 100 from the carrier substrate 150. For example, the deposition material 210 can be heated and evaporated such that the first semiconductor structure 100 can be separated from the carrier substrate 150.

[0046] 15 , the first semiconductor structure 100, together with the patterned stress film 510 (or stress film 410), can be cut, for example, via etching, to define a plurality of chiplets 1550. One or more of the chiplets 1550 can be coupled to another semiconductor structure. For example, the chiplet 1550 can be coupled to a second semiconductor structure 700 having a second circuit 710 and a second wiring structure 720, where the second wiring structure 720 corresponds to the first wiring structure 120 of the first semiconductor structure 100.

[0047] 16, the chiplet 1550 may be coupled to the second semiconductor structure 700, with the first wiring structure 120 of the chiplet 1550 connected to the second wiring structure 720 of the second semiconductor structure 700. The patterned stress film 510 (or stress film 410) may then be removed to provide the structure shown in FIG. 10. For example, the patterned stress film 510 (or stress film 410) may be removed via CMP.

[0048] 17-20 are cross-sectional views illustrating a third exemplary method for forming chiplets on a semiconductor structure according to some embodiments of the present disclosure. The third exemplary method differs from the first and second exemplary methods in that the first semiconductor structure 100, along with the first patterned stress film 510 (or stress film 410), is cut to define the chiplets 750 / 1550, while the carrier substrate 150 and deposition material 210 remain in place, and the chiplets 750 / 1550 are separated from the carrier substrate 150 at the chiplet level in a subsequent step. The third exemplary method may allow for control over cutting chiplets with a thicker underlying substrate. As shown in FIG. 17 , which follows FIG. 5 , the first semiconductor structure 100, including the patterned stress film 510 (or stress film 410), the first dielectric layer 130, the first circuit 110, the first wiring structure 120, and the adhesion material 210, can be sequentially cut, for example via etching, to define chiplets 750. In one embodiment, as shown in FIG. 17 , the cutting process can stop at the carrier substrate 150. In another embodiment, the carrier substrate 150 can be partially etched in the cutting process. In yet another embodiment, the cutting process can stop at the adhesion layer 210. FIG. 17 can also follow FIG. 13 , where the first semiconductor structure 100, including the patterned stress film 510 (or stress film 410), the first circuit 110, and the first wiring structure 120 (and, optionally, the top of the adhesion material 210 and / or the carrier substrate 150) can be sequentially etched to define chiplets 1550.

[0049] As shown in FIG. 18 , chiplet supports 1810 can optionally be formed on the patterned stress film 510 (or stress film 410) for each of the chiplets 750 (or chiplets 1550), and the attachment material 210 can be removed, for example, via heating, to separate the carrier substrate 150 from the chiplets 750 (or chiplets 1550). In one embodiment, the chiplet supports 1810 can be used to hold the chiplets 750 (or chiplets 1550) in place during a subsequent process step, such as a cutting process step. For example, the chiplet supports 1810 can be adhesive. As another example, the chiplet supports 1810 can be formed at random locations on the surface of the patterned stress film 510 for each of the chiplets 750 (or chiplets 1550). The chiplet supports 1810 can be formed in any shape, for example, in blocks as shown in FIG.

[0050] 19, one or more of the chiplets 750 (or chiplets 1550) can be coupled to another semiconductor structure. For example, the chiplets 750 (or chiplets 1550) can be coupled to a second semiconductor structure 700 having a second circuit 710 and a second wiring structure 720, where the second wiring structure 720 corresponds to the first wiring structure 120 of the first semiconductor structure 100.

[0051] 20 , the chiplet 750 (or chiplet 1550) may be coupled to the second semiconductor structure 700, with the first wiring structure 120 of the chiplet 750 (or chiplet 1550) connected to the second wiring structure 720 of the second semiconductor structure 700. The chiplet support 1810, the patterned stress film 510 (or stress film 410), and the first dielectric layer 130 may then be removed to provide the structure shown in FIG. 10 . For example, the chiplet support 1810, the patterned stress film 510, and the first dielectric layer 130 may be removed via CMP in a single process or multiple processes.

[0052] 21 is a flowchart illustrating a fourth exemplary method 2100 for forming chiplets on a semiconductor structure, according to some embodiments of the present disclosure. In one embodiment, some steps of the illustrated fourth exemplary method 2100 may be performed simultaneously or in a different order than those illustrated, may be replaced by other method steps, or may be omitted. Additional method steps may also be performed as desired. In another embodiment, the fourth exemplary method 2100 may correspond to the first and second exemplary methods shown in FIGS. 1-16.

[0053] In step S2110, a first semiconductor structure may be provided. In one embodiment, the first semiconductor structure (e.g., first semiconductor structure 100) may include a first circuit (e.g., first circuit 110) and a first wiring structure (e.g., first wiring structure 120) formed on a first side (e.g., first side 100A) of the first semiconductor structure, and a first dielectric layer (e.g., first dielectric layer 130) and a first substrate (e.g., first substrate 140) formed on a second side (e.g., second side 100B) of the first semiconductor structure.

[0054] In step S2120, the first side of the first semiconductor structure may be attached to a carrier substrate. For example, the first side 100A of the first semiconductor structure 100 may be attached to the carrier substrate 150 using the attachment material 210.

[0055] In step S2130, the first substrate (and the first dielectric layer) may be removed. For example, the first substrate 140 (and the first dielectric layer 130) may be removed via CMP.

[0056] In step S2140, a stress film may be formed on the second surface (or the first dielectric layer) of the first semiconductor structure. For example, as shown in FIG. 4, a stress film 410 may be formed on the first dielectric layer 130. As another example, as shown in FIG. 12, a stress film 410 may be formed on the second surface 100B of the first semiconductor structure 100.

[0057] In step S2150, the stress film may optionally be patterned to form a patterned stress film. For example, the stress film 410 may be patterned using direct writing to form the patterned stress film 510.

[0058] In step S2160, the first semiconductor structure may be separated from the carrier substrate. For example, the adhesion layer 210 may be heated and evaporated so that the first semiconductor structure 100 may be separated from the carrier substrate 150.

[0059] In step S2170, the first semiconductor structure may be cut together with the patterned stress film (or stress film) to define a plurality of chiplets. For example, the first semiconductor structure 100 may be cut together with the patterned stress film 510 (or stress film 410), for example, via etching, to define a plurality of chiplets 750 / 1550.

[0060] In step S2180, one or more of the chiplets may be coupled to another semiconductor structure. For example, chiplet 750 / 1550 may be coupled to a second semiconductor structure 700 having a second circuit 710 and a second wiring structure 720, with the first wiring structure 120 of chiplet 750 / 1550 connected to the second wiring structure 720 of the second semiconductor structure 700.

[0061] In step S2190, the patterned stress film (or the stress film) (and the first dielectric layer) may be removed. For example, the patterned stress film 510 (or the stress film 410) (and the first dielectric layer 130) may be removed via CMP.

[0062] 22 is a flowchart illustrating a fifth exemplary method 2200 for forming chiplets on a semiconductor structure according to some embodiments of the present disclosure. In one embodiment, some steps of the illustrated fifth exemplary method 2200 may be performed simultaneously or in a different order than those illustrated, may be replaced by other method steps, or may be omitted. Additional method steps may also be performed as desired. In another embodiment, the fifth exemplary method 2200 may correspond to the third exemplary method shown in FIGS. 17-20. The fifth exemplary method 2200 may also include steps S2110-S2150.

[0063] In step S2260, the first semiconductor structure may be cut together with the patterned stress film (or stress film) to define a plurality of chiplets. For example, the first semiconductor structure 100 may be cut together with the patterned stress film 510 (or stress film 410), e.g., via etching, to form chiplets 750 / 1550, with the carrier substrate 150 and deposition material 210 held in place, and the chiplets 750 / 1550 separated from the carrier substrate 150 at the chiplet level in a subsequent step.

[0064] In step S2265, optionally, a chiplet support may be formed on the patterned stress film (or stress film) for each of the chiplets. For example, chiplet support 1810 may be formed on the patterned stress film 510 (or stress film 410) for each of the chiplets 750 (or chiplets 1550).

[0065] In step S2270, the chiplets may be separated from the carrier substrate. For example, adhesion layer 210 may be heated and evaporated so that chiplets 750 / 1550 may be separated from carrier substrate 150.

[0066] In step S2280, one or more of the chiplets may be coupled to another semiconductor structure. For example, chiplet 750 / 1550 may be coupled to a second semiconductor structure 700 having a second circuit 710 and a second wiring structure 720, with the first wiring structure 120 of chiplet 750 / 1550 connected to the second wiring structure 720 of the second semiconductor structure 700.

[0067] In step S2290, the chiplet support and the patterned stress film (or stress film) (and the first dielectric layer) may be removed. For example, the chiplet support 1810 and the patterned stress film 510 (or stress film) (and the first dielectric layer 130) may be removed via CMP.

[0068] In the foregoing description, specific details have been set forth, such as the particular configuration of the processing system and descriptions of the various components and processes used therein. However, it should be understood that the technology of the present invention may be practiced in other embodiments that deviate from these specific details, and that such details are for illustrative purposes only and are not intended to limit the present invention. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for explanatory purposes, specific numbers, materials, and configurations have been set forth to provide a thorough understanding. Nevertheless, multiple embodiments can be practiced without such specific details. Components having substantially the same functional structure are designated by similar reference numerals, and therefore, any redundant description may be omitted.

[0069] To facilitate understanding of various embodiments, various techniques have been described as multiple discrete operations. The order of description should not be construed as to imply that these operations are necessarily order dependent. In fact, these operations need not be performed in the order presented. The described operations may also be performed in a different order than in the described embodiments. In additional embodiments, various additional operations may be performed and / or described operations may be omitted.

[0070] As used herein, "substrate" or "target substrate" refers generally to an object to be processed in accordance with the present invention. A substrate may include any material portion or structure of a device, particularly a semiconductor device or other electronic device, and may be, for example, a base substrate structure such as a semiconductor wafer, a reticle, or a layer on or overlying the base substrate structure, e.g., a thin film. Thus, substrate is not limited to any particular base structure, underlying layer, or overlying layer, whether patterned or not, but rather is intended to include any such layer or base structure, and any combination of layers and / or base structures. While the description may refer to particular types of substrates, this is for illustrative purposes only.

[0071] Those skilled in the art will also appreciate that many variations can be made to the operation of the techniques described above and still achieve the same objectives of the present invention. Such variations are intended to be encompassed within the scope of the present disclosure. Accordingly, the above description of embodiments of the present invention is not intended to be limiting. Rather, any limitations to embodiments of the present invention are presented in the following claims.

[0072] 3D integration, or the vertical stacking of multiple devices, aims to overcome the scaling limitations experienced in planar devices by increasing transistor density in volume rather than area. While device stacking has been successfully demonstrated and implemented by the flash memory industry through the adoption of 3D NAND, its application to random logic designs is much more difficult in practice. 3D integration for logic chips (CPUs (Central Processing Units), GPUs (Graphics Processing Units), FPGAs (Field Programmable Gate Arrays), and SoCs (System on Chip)) is being promoted.

[0073] As microelectronic devices are fabricated on a wafer, the wafer itself is subjected to various stresses from various materials being added or removed, as well as processing steps such as annealing. Such stresses can cause overlay problems from wafer warping, distortion, and curvature. These problems can be exacerbated by stacking wafer-on-wafer. Technology herein includes systems and methods that alleviate troublesome issues related to wafer stress from stacked wafers and chiplets.

[0074] The techniques herein may include selective stress (or stressor) film techniques and the construction of relatively thin chiplets for attachment or bonding to semiconductor structures, such as wafers or dies. One or more layers of stress film may be deposited on a surface of the chiplet (e.g., the second or inactive surface of the backside, or the surface opposite the second active or functional surface of the frontside). In one embodiment, a direct-write lithography exposure tool may be used to write a compensated stress pattern on the backside of the chiplet before the chiplet is cut and placed on or bonded to a wafer. The chiplet may receive the same or different stress film and the same or different stress compensation pattern for localized stress regions. This allows for a greater density of 3D chiplets to be stacked, as the thickness of the chiplet may be significantly reduced. These techniques enable a higher die yield per wafer, as the wafer has less bow or curvature, enabling more precise photolithography.

[0075] The order of description of the various steps described herein is presented for clarity. In general, these steps can be performed in any suitable order. In addition, although each of the various features, techniques, configurations, etc. herein may be discussed in different parts of this disclosure, it is intended that each of these concepts can be implemented independently of each other or in combination with each other. Thus, the present invention can be embodied and viewed in many different ways.

[0076] 23-31 are cross-sectional views illustrating a first exemplary method for forming chiplets on a semiconductor structure according to some embodiments of the present disclosure. As shown in FIG. 23 , a first semiconductor structure 100 may be provided. In one embodiment, the first semiconductor structure 100 may have a first circuit (or first active circuit) 110 and a first wiring structure 120 formed on a first surface 100A (or front active or functional surface) of the first semiconductor structure 100. For example, the first circuit 110 may be formed in the bulk silicon 105 of the first semiconductor structure 100. As another example, the first wiring structure 120 may include vias and a copper layer. In one embodiment, the first circuit 110 and the first wiring structure 120 may be used as a chiplet. A chiplet, as used herein, may be a component device, an integrated circuit, or a component of a larger module, assembly, package, or integrated circuit. The chiplet may be cut from a larger device or wafer, such as the first semiconductor structure 100. The dotted lines shown in FIG. 23 may identify example chiplets.

[0077] In one embodiment, the first semiconductor structure 100 may further include a first dielectric layer 130 and a first substrate 140 formed on a second side (or backside or inactive side) 100B of the first semiconductor structure 100. For example, the first substrate 140 may be a silicon substrate. In fabricating the first semiconductor structure 100, a silicon-on-insulator (SOI) substrate composed of the first substrate 140, the first dielectric layer 130, and bulk silicon 105 may be provided, the first circuit 110 may be formed in the bulk silicon 105 via photolithography, and the first wiring structure 120 may be formed to connect to the first circuit 110.

[0078] 23 further shows a carrier substrate 150 for the first semiconductor structure 100, attached to the first semiconductor structure 100. For example, the carrier substrate 150 can be a silicon wafer.

[0079] 24, the first side 100A of the first semiconductor structure 100 may be attached to a carrier wafer 150 using an attachment material 210. For example, the attachment material 210 may be identified as an adhesive layer, a bonding layer, a method for joining wafers that can be subsequently removed, a semiconductor-to-semiconductor with a native oxide at a dielectric interface, a metal-metal, a metal with an oxide coating, a metal with a SiC coating, a metal with a SiCN coating, a metal with an attached film that includes a semiconductor with a coating of one or more elements, or a combination thereof.

[0080] 25, the first substrate 140 can be removed to expose the first dielectric layer 130. For example, the first semiconductor structure 100 can be planarized via chemical mechanical planarization (also called chemical mechanical polishing) (CMP), where the CMP stops at the first dielectric layer 130 and the first substrate 140 is removed to expose the first dielectric layer 130.

[0081] 26, a first stress film 410 may be formed on the first dielectric layer 130. By depositing or forming the first stress film 410 on the first dielectric layer 130, any type of stress (i.e., compressive or tensile) can be induced in the bulk silicon 105. For example, a photoresist layer may be applied to the first dielectric layer 130 via spin coating or deposited on the first dielectric layer 130 to serve as the first stress film 410. As another example, the first stress film 410 may be made of silicon nitride, silicon oxide, etc., such as Si3N4, SiO x N y , Si, and SiO2. The first stress film 410 can be an ultraviolet (UV) crosslinkable stress film including a spin-on material, such as benzocyclobutene (BCB) and other materials with crosslinking properties. For example, the spin-on material can be exposed by direct write exposure and then baked to complete the process and establish the desired stress pattern and can be used for any one of the exemplary methods.

[0082] 27, the first stress film 410 may optionally be patterned to form a first patterned stress film 510 having stress regions 510A. For example, the stress regions 510A may be openings in the first patterned stress film 510. In one embodiment, the first stress film 410 may be patterned, exposed, and developed to remove the reacted (e.g., positive) photoresist layer and form the first patterned stress film 510. For example, a photomask may be used to form the first patterned stress film 510. As another example, the first stress film 410, e.g., a photoresist layer, may be patterned using a direct-write (or maskless) lithography tool, which simultaneously projects or uses a scanning motion to project a stress-modifying pattern onto the photoresist layer or a layer having a photoreactive agent. The patterned photoresist layer may then be developed to create a relief pattern. This relief pattern can function as a stress film or can be transferred to an underlying layer to become the first patterned stress film 510. For example, a digital light processing chip (DLP) can be used. As another example, a grating light valve or a laser galvanometer can be used. The direct write system can use a processing engine to control the amount / intensity of light at any given point on the substrate or film being exposed. Depending on the photo-reactive agent of the corresponding film, any of a variety of conventional light wavelengths can be used (or the film composition can be selected based on the available light wavelength). For stress relaxation, exposure at a lower resolution is sufficient to create the desired stress modification (or first patterned stress film 510). The stress modification pattern (or first patterned stress film 510) herein can form regions with stress induced by the stress film (or patterned stress film) and regions with reduced or no stress where the first writing tool has removed at least a portion of the stress film, resulting in a flatter substrate and optimizing photolithography accuracy.Although the pattern is shown extending only partially through the first stress film 410 / first patterned stress film 510, it should be understood that the pattern may extend completely therethrough to further modify the stress characteristics.

[0083] FIG. 27 further illustrates that a second stress film 520 can be deposited within the stress region 510A of the first patterned stress film 510. For example, the stress region 510A can be an opening in the first patterned stress film 510, and the second stress film 520 can fill the opening and be adjacent to the first patterned stress film 510. Thus, a composite of the first patterned stress film 510 and the second stress film 520 can be formed on the first dielectric layer 130. After the second stress film 520 is deposited and formed within the stress region 510A of the first patterned stress film 510, CMP can be performed to planarize the second stress film 520. In one embodiment, as shown in FIG. 27, the second stress film 520 can be formed only within the stress region 510A of the first patterned stress film 510. In another embodiment, the second stress film 520 can be further formed on the first patterned stress film 510. In yet another embodiment, the first stress film 410 may be unpatterned, and the second stress film 520 may be deposited and formed on the first stress film 410 to form a composite of the first stress film 410 and the second stress film 520. The second stress film 520 may be used to apply or reduce stress in specific regions of the first semiconductor structure 100 and chiplets to be formed in subsequent process steps. For example, the second stress film 520 may be different or the same as the first stress film 410 (and the first patterned stress film 510) to maintain a balance of stress across the entire region of the first semiconductor structure 100 and chiplets.

[0084] 28, the deposition material 210 can be removed to separate the first semiconductor structure 100 from the carrier substrate 150. For example, the deposition material 210 can be heated and evaporated such that the first semiconductor structure 100 can be separated from the carrier substrate 150. FIG. 28 also shows a second semiconductor structure 600 that can be coupled to the first semiconductor structure 100. For example, the second semiconductor structure 600 can have a second circuit 610 and a second wiring structure 620 that corresponds to the first wiring structure 120 of the first semiconductor structure 100.

[0085] 29 , the first semiconductor structure 100, together with the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520), can be cut, for example, via etching, to define multiple chiplets 750. Because the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520) is formed on the first semiconductor structure 100, the first semiconductor 100 (and the chiplets 750) can receive the same or different stress films and the same or different stress compensation patterns for localized stress regions, allowing for less complex wafer stress, the first semiconductor structure 100 (and the chiplets 750) can have a reduced thickness, and higher density 3D chiplets can be stacked. One or more of the chiplets 750 can be bonded to another semiconductor structure. For example, chiplet 750 may be coupled to a second semiconductor structure 600 having a second circuit 610 and a second wiring structure 620 that corresponds to the first wiring structure 120 of the first semiconductor structure 100.

[0086] As shown in FIG. 30, a chiplet 750 may be coupled to a second semiconductor structure 600 with the first wiring structure 120 of the chiplet 750 connected to the second wiring structure 620 of the second semiconductor structure 600 .

[0087] 31 , the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520) can be removed to expose the first dielectric layer 130. For example, the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520) can be removed via CMP, where the CMP stops at the first dielectric layer 130, exposing the first dielectric layer 130. FIG. 31 further illustrates that the first dielectric layer 130 can be removed. For example, the first dielectric layer 130 can be removed via CMP. In one embodiment, the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520) and the first dielectric layer 130 can be removed in a single CMP process. Thus, the chiplet 750 bonded to the second semiconductor structure 600 can be very thin.

[0088] 32-36 are cross-sectional views illustrating a second exemplary method for forming chiplets on a semiconductor structure according to some embodiments of the present disclosure. The second exemplary method differs from the first exemplary method in that, prior to forming the first stress film 410, both the first substrate 140 and the first dielectric layer 130 are removed, which may enable optimal stress transfer. As shown in FIG. 32, which follows FIG. 24, the first substrate 140 and the first dielectric layer 130 are removed. For example, the first substrate 140 and the first dielectric layer 130 may be removed in a single CMP process or in two corresponding CMP processes to expose the second side (or backside or inactive side) 100B of the first semiconductor structure 100.

[0089] 33, a first stress film 410 can be formed on the second side 100B of the first semiconductor structure 100 and can directly contact the bulk silicon 105. For example, a photoresist layer can be deposited on the second side 100B to serve as the first stress film 410.

[0090] As shown in FIG. 34 , the first stress film 410 can be patterned to form a first patterned stress film 510 having stress regions 510A. For example, a photomask can be used to form the first patterned stress film 510. As another example, the first stress film 410, e.g., a photoresist layer, can be patterned using a direct-write lithography tool. The patterned photoresist layer can then be developed to create a relief pattern. This relief pattern can function as the stress film or can be transferred to an underlying layer to become the first patterned stress film 510. For example, a DLP chip can be used. As another example, a grating light valve or a laser galvanometer can be used. FIG. 35 further illustrates that a second stress film 520 can be deposited within the stress regions 510A of the first patterned stress film 510 and on the first patterned stress film 510. Thus, a composite of the first patterned stress film 510 and the second stress film 520 may be formed on the first dielectric layer 130. After the second stress film 520 is deposited and formed in the stress region 510A of the first patterned stress film 510 and on the first patterned stress film 510, CMP may be performed to planarize the second stress film 520. In one embodiment, as shown in FIG. 35 , the second stress film 520 may be formed in the stress region 510A on the first patterned stress film 510 and on the first patterned stress film 510. In another embodiment, the second stress film 520 may be formed only in the stress region 510A of the first patterned stress film 510. In yet another embodiment, the first stress film 410 may not be patterned, and the second stress film 520 may be deposited and formed on the first stress film 410 to form a composite of the first stress film 410 and the second stress film 520.

[0091] As shown in FIG. 35 , the deposition material 210 can be removed to separate the first semiconductor structure 100 from the carrier substrate 150. For example, the deposition material 210 can be heated and evaporated so that the first semiconductor structure 100 can be separated from the carrier substrate 150. FIG. 35 further illustrates that the first semiconductor structure 100, along with the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520), can be cut, for example, via etching, to define a plurality of chiplets 1350. One or more of the chiplets 1350 can be bonded to another semiconductor structure. For example, the chiplet 1350 can be bonded to a second semiconductor structure 600 having a second circuit 610 and a second wiring structure 620 corresponding to the first wiring structure 120 of the first semiconductor structure 100. FIG. 35 further illustrates that the chiplet 1350 can be coupled to the second semiconductor structure 600 with the first wiring structure 120 of the chiplet 1350 connected to the second wiring structure 620 of the second semiconductor structure 600.

[0092] 36 , the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520) can be removed. For example, the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520) can be removed via CMP, which stops on the bulk silicon 105 of the first semiconductor structure 100, where the first circuit 110 is formed. Therefore, the chiplet 1350 bonded to the second semiconductor structure 600 can be very thin.

[0093] 37-39 are cross-sectional views illustrating a third exemplary method for forming chiplets on a semiconductor structure according to some embodiments of the present disclosure. In the third exemplary method, the first semiconductor structure 100 is cut together with the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520) to define the chiplets 750 / 1350, while the carrier substrate 150 and the deposition material 210 remain in place, and the chiplets 750 / 1550 are separated from the carrier substrate 150 at the chiplet level in a subsequent step. The third exemplary method may allow for control over cutting chiplets with a thicker underlying substrate. 37, which follows FIG. 34, the first semiconductor structure 100, including the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520), the first dielectric layer 130, and the first circuitry 110 (and the deposition material 210), may be sequentially cut, for example via etching, to define chiplets 1350. In one embodiment, the cutting process may stop at the carrier substrate 150, as shown in FIG. 37. In another embodiment, the carrier substrate 150 may be partially etched in the cutting process. Figure 37 can also follow Figure 27, and the first semiconductor structure 100 including the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520), as well as the first circuit 110, the first wiring structure 120, and the first dielectric layer 130 (and the deposition material 210) (and optionally the top of the carrier substrate 150), can be sequentially etched to define the chiplets 750.

[0094] 38 , optionally, a chiplet support 1610 can be formed on the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520) for each of the chiplets 1350 (or chiplets 750), and the attachment material 210 can be removed, for example, via heating, to separate the carrier substrate 150 from the chiplets 1350 (or chiplets 750). For example, the chiplet support 1610 can be formed on the first patterned stress film 510 (or the first stress film 410) and / or the second stress film 520 for each of the chiplets 1350 (or chiplets 750). FIG. 38 further illustrates that one or more of the chiplets 1350 (or chiplets 750) can be bonded to another semiconductor structure. For example, the chiplet 1350 (or chiplet 750) can be coupled to a second semiconductor structure 600 having a second circuit 610 and a second wiring structure 620, where the second wiring structure 620 corresponds to the first wiring structure 120 of the first semiconductor structure 100. In one embodiment, the chiplet supports 1610 can be used to hold the chiplet 750 (or chiplet 1350) in place during subsequent process steps, such as a sawing process step. For example, the chiplet supports 1610 can be adhesive. As another example, the chiplet supports 1610 can be formed on a surface of the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520) for each chiplet 750 (or chiplet 1350). The chiplet supports 1610 can be formed in any shape, for example, in a block as shown in FIG.

[0095] 39 , the chiplet 1350 (or chiplet 750) may be coupled to the second semiconductor structure 600, with the first wiring structure 120 of the chiplet 1350 (or chiplet 750) connected to the second wiring structure 620 of the second semiconductor structure 600. The chiplet support 1810 and the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520), (and the first dielectric layer 130 for the chiplet 750) may then be removed. For example, the chiplet support 1810, the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520), and the first dielectric layer 130 may be removed via CMP in a single process or multiple processes.

[0096] 40-44 are cross-sectional views illustrating a fourth exemplary method for forming chiplets on a semiconductor structure according to some embodiments of the present disclosure. The fourth exemplary method differs from the first and second exemplary methods in that, in the fourth exemplary method, a dual stress film stack of two or more layers may be deposited on the second side 100B of the first semiconductor structure 100, thereby eliminating the CMP process performed on the second stress film 520. In one embodiment, as shown in FIG. 40 following FIG. 32, a dual stress film stack of two or more layers, e.g., a composite of a first stress film 1810 and a second stress film 1820, may be deposited and formed on the second side 100B of the first semiconductor structure 100. In another embodiment following FIG. 25, a composite of a first stress film 1810 and a second stress film 1820 may be formed on a first dielectric layer 130. For example, a photoresist layer may be applied to or deposited on the first dielectric layer 130 via spin coating to serve as the first stress film 1810 (or the second stress film 1820). As another example, the first stress film 1810 (or the second stress film 1820) may include silicon nitride, silicon oxide, etc. The first stress film 1810 (or the second stress film 1820) may also be a UV cross-linked stress film including a spin-on material.

[0097] Optionally, the dual stress film stack may be patterned, as shown in FIG. 41 . For example, the first stress film 1810 may be patterned to form a first patterned stress film 1910 having stress regions 1910A. For example, a photomask may be used to form the first patterned stress film 1910. As another example, the first stress film 1810, e.g., a photoresist layer, may be patterned using a direct-write lithography tool. The patterned photoresist layer may then be developed to create a relief pattern. This relief pattern may function as the stress film or may be transferred to an underlying layer to become the first patterned stress film 1910. For example, a DLP chip may be used. As another example, a grating light valve or a laser galvanometer may be used. Thus, a composite of the first patterned stress film 1910 and the second stress film 1820 may be formed on the second surface 100B of the first semiconductor structure 100.

[0098] As shown in FIG. 42 , the deposition material 210 can be removed to separate the first semiconductor structure 100 from the carrier substrate 150. For example, the deposition material 210 can be heated and evaporated so that the first semiconductor structure 100 can be separated from the carrier substrate 150. FIG. 42 further illustrates that the first semiconductor structure 100, along with the composite of the first patterned stress film 1910 and the second stress film 1820 (or the composite of the first stress film 1810 and the second stress film 1820), can be cut, for example, via etching, to define a plurality of chiplets 2050. One or more of the chiplets 2050 can be bonded to another semiconductor structure. For example, the chiplet 2050 can be bonded to a second semiconductor structure 600 having a second circuit 610 and a second wiring structure 620 corresponding to the first wiring structure 120 of the first semiconductor structure 100.

[0099] Alternatively, the first semiconductor structure 100 can be cut together with the composite of the first patterned stress film 1910 and the second stress film 1820 (or the composite of the first stress film 1810 and the second stress film 1820) to define the chiplets 2050, and then the adhesion material 210 can be removed to separate the carrier substrate 150 from the chiplets 2050.

[0100] As shown in FIG. 43, the chiplet 2050 may be coupled to the second semiconductor structure 600 with the first wiring structure 120 of the chiplet 2050 connected to the second wiring structure 620 of the second semiconductor structure 600.

[0101] 44, the composite of the first patterned stress film 1910 and the second stress film 1820 (or the composite of the first stress film 1810 and the second stress film 1820) can be removed. For example, the composite of the first patterned stress film 1910 and the second stress film 1820 (or the composite of the first stress film 1810 and the second stress film 1820) can be removed via CMP, which stops on the bulk silicon 105 of the first semiconductor structure 100, where the first circuit 110 is formed.

[0102] 45 is a flowchart illustrating a fifth exemplary method 2300 of forming chiplets on a semiconductor structure according to some embodiments of the present disclosure. In one embodiment, some steps of the illustrated fifth exemplary method 2300 may be performed simultaneously or in a different order than those illustrated, may be replaced by other method steps, or may be omitted. Additional method steps may also be performed as desired. In another embodiment, the fifth exemplary method 2300 may correspond to the first, second, and fourth exemplary methods shown in FIGS. 23-36 and 40-44.

[0103] In step S2310, a first semiconductor structure may be provided. In one embodiment, the first semiconductor structure (e.g., first semiconductor structure 100) may include a first circuit (e.g., first circuit 110) and a first wiring structure (e.g., first wiring structure 120) formed on a first side (e.g., first side 100A) of the first semiconductor structure, and a first dielectric layer (e.g., first dielectric layer 130) and a first substrate (e.g., first substrate 140) formed on a second side (e.g., second side 100B) of the first semiconductor structure.

[0104] In step S2320, the first side of the first semiconductor structure may be attached to a carrier substrate. For example, the first side 100A of the first semiconductor structure 100 may be attached to the carrier substrate 150 using the attachment material 210.

[0105] In step S2330, the first substrate (and the first dielectric layer) may be removed. For example, the first substrate 140 (and the first dielectric layer 130) may be removed via CMP.

[0106] In step S2340, a composite of the first stress film and the second stress film may be formed on the second surface (or the first dielectric layer) of the first semiconductor structure. For example, as shown in FIG. 40 , a composite of the first stress film 1810 and the second stress film 1820 may be formed on the second surface 100B of the first semiconductor structure 100. As another example, a composite of the first stress film 1810 and the second stress film 1820 may be formed on the first dielectric layer 130 of the first semiconductor structure 100.

[0107] In step S2350, the first stress film may be patterned to form a first patterned stress film. For example, as shown in FIG. 27, the first stress film may be patterned using direct writing to form a composite of a first patterned stress film 510 and a second stress film 520. As another example, as shown in FIG. 41, the first stress film may be patterned to form a composite of a first patterned stress film 1910 and a second stress film 1820.

[0108] In step S2360, the first semiconductor structure may be separated from the carrier substrate. For example, the adhesion layer 210 may be heated and evaporated so that the first semiconductor structure 100 may be separated from the carrier substrate 150.

[0109] In step S2370, the first semiconductor structure may be cut together with the composite of the first patterned stress film and the second stress film (or the composite of the first stress film and the second stress film) to define a plurality of chiplets. For example, the first semiconductor structure 100 may be cut together with the composite of the first patterned stress film 1910 / 510 and the second stress film 1820 / 520 (or the composite of the first stress film 1810 / 410 and the second stress film 1820 / 520), e.g., via etching, to define a plurality of chiplets 750 / 1350 / 2050.

[0110] In step S2380, one or more of the chiplets may be coupled to another semiconductor structure. For example, chiplet 750 / 1350 / 2050 may be coupled to a second semiconductor structure 600 having a second circuit 610 and a second wiring structure 620, with the first wiring structure 120 of chiplet 750 / 1350 / 2050 connected to the second wiring structure 620 of the second semiconductor structure 600.

[0111] In step S2390, the composite of the first patterned stress film and the second stress film (or the composite of the first stress film and the second stress film), (and the first dielectric layer) may be removed. For example, the composite of the first patterned stress film 1910 / 510 and the second stress film 1820 / 520 (or the composite of the first stress film 1810 / 410 and the second stress film 1820 / 520) (and the first dielectric layer 130) may be removed via CMP.

[0112] 46 is a flowchart illustrating a sixth exemplary method 2400 of forming chiplets on a semiconductor structure according to some embodiments of the present disclosure. In one embodiment, some steps of the illustrated sixth exemplary method 2400 may be performed simultaneously or in a different order than those illustrated, may be replaced with other method steps, or may be omitted. Additional method steps may also be performed as desired. In another embodiment, the sixth exemplary method 2400 may correspond to the third exemplary method shown in FIGS. 37-39. The sixth exemplary method 2400 may also include steps S2310-S2350.

[0113] In step S2460, the first semiconductor structure, together with the composite of the first patterned stress film and the second stress film (or the composite of the first stress film and the second stress film), may be cut to define a plurality of chiplets. For example, the first semiconductor structure 100, together with the composite of the first patterned stress film 510 and the second stress film 520, may be cut, e.g., via etching, to form chiplets 750, with the carrier substrate 150 and the deposition material 210 held in place, and the chiplets 750 separated from the carrier substrate 150 at the chiplet level in a subsequent step.

[0114] In step S2465, optionally, for each chiplet, a chiplet support is formed on the composite of the first patterned stress film and the second stress film (or the composite of the first stress film and the second stress film). For example, for each chiplet 750, a chiplet support 1610 may be formed on the composite of the first patterned stress film 510 and the second stress film 520.

[0115] In step S2470, the chiplets may be separated from the carrier substrate. For example, adhesion layer 210 may be heated and evaporated so that chiplets 750 may be separated from carrier substrate 150.

[0116] In step S2480, one or more of the chiplets may be coupled to another semiconductor structure. For example, chiplet 750 may be coupled to a second semiconductor structure 600 having a second circuit 610 and a second wiring structure 620, with the first wiring structure 120 of chiplet 750 connected to the second wiring structure 620 of the second semiconductor structure 600.

[0117] In step S2490, the chiplet support and the composite of the first patterned stress film and the second stress film (or the composite of the first stress film and the second stress film), (and the first dielectric layer) may be removed. For example, the chiplet support 1610 and the composite of the first patterned stress film 510 and the second stress film 520, (and the first dielectric layer 130) may be removed via CMP.

[0118] According to some embodiments of the present disclosure, any combination of stresses is possible. Stress films can be compressive, tensile, or neutral in various regions on a semiconductor device, die, or wafer. Embodiments herein include two or more stresses of the same type, compressive or tensile, but different stress values ​​(or, alternatively, they may be different stress regions, i.e., compressive or tensile, on the same wafer). While examples herein show a two-layer stress film, more than two layers of stress films can also be used. Multiple types of stress films on the backside of a chiplet can provide another degree of freedom in enhancing photolithography.

[0119] In the foregoing description, specific details have been set forth, such as the particular configuration of the processing system and descriptions of the various components and processes used therein. However, it should be understood that the technology of the present invention may be practiced in other embodiments that deviate from these specific details, and that such details are for illustrative purposes only and are not intended to limit the present invention. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for explanatory purposes, specific numbers, materials, and configurations have been set forth to provide a thorough understanding. Nevertheless, multiple embodiments can be practiced without such specific details. Components having substantially the same functional structure are designated by similar reference numerals, and therefore, any redundant description may be omitted.

[0120] To facilitate understanding of various embodiments, various techniques have been described as multiple discrete operations. The order of description should not be construed as to imply that these operations are necessarily order dependent. In fact, these operations need not be performed in the order presented. The described operations may also be performed in a different order than in the described embodiments. In additional embodiments, various additional operations may be performed and / or described operations may be omitted.

[0121] As used herein, "substrate" or "target substrate" refers generally to an object to be processed in accordance with the present invention. The substrate may include any material portion or structure of a device, particularly a semiconductor device or other electronic device, and may be, for example, a base substrate structure such as a semiconductor wafer, a reticle, or a layer on or overlying the base substrate structure, e.g., a thin film. Thus, substrate is not limited to any particular base structure, underlying layer, or overlying layer, whether patterned or not, but rather is intended to include any such layer or base structure, and any combination of layers and / or base structures. While the description may refer to a particular type of substrate, this is for illustrative purposes only.

[0122] Those skilled in the art will also appreciate that many variations can be made to the operation of the techniques described above and still achieve the same objectives of the present invention. Such variations are intended to be encompassed within the scope of the present disclosure. Accordingly, the above description of embodiments of the present invention is not intended to be limiting. Rather, any limitations to embodiments of the present invention are presented in the following claims.

Claims

1. providing a first semiconductor structure, the first semiconductor structure having a first circuit and a first wiring structure formed on a first side of the first semiconductor structure; attaching the first side of the first semiconductor structure to a carrier substrate; forming a first stress film on a second side of the first semiconductor structure; patterning the first stress film to form a first patterned stress film having at least one recessed region; forming a second stress film in the recessed region and on the first patterned stress film; polishing the second stress film to planarize the second stress film; Separating the carrier substrate from the first semiconductor structure; cutting the first patterned stress film, the second stress film, and the first semiconductor structure to define at least one chiplet; coupling the at least one chiplet to a second semiconductor structure, the second semiconductor structure having a second circuit and a second wiring structure, the second wiring structure connected to the first wiring structure; A method comprising:

2. 10. The method of claim 1, further comprising removing the first patterned stress film and the second stress film after the at least one chiplet is bonded to the second semiconductor structure.

3. the first semiconductor structure further comprising a first dielectric layer formed on the second side of the first semiconductor structure; 2. The method of claim 1, wherein forming a first stress film on the second side of the first semiconductor structure comprises forming a first stress film on the first dielectric layer of the first semiconductor structure.

4. the first semiconductor structure further comprises a first substrate formed on the first dielectric layer; 4. The method of claim 3, further comprising removing the first substrate and leaving the first dielectric layer uncovered prior to forming a first stress film on the first dielectric layer of the first semiconductor structure.

5. the first side of the first semiconductor structure is attached to the carrier substrate using an attachment material; The method of claim 1 , wherein separating the carrier substrate from the first semiconductor structure comprises heating the deposition material such that the carrier substrate is separated from the first semiconductor structure.

6. The method of claim 1 , wherein the second stress film is further formed on the first patterned stress film.

7. 10. The method of claim 1, wherein the first patterned stress film is formed through a mask-based lithography tool, ultraviolet (UV) crosslinking, or a direct-write lithography tool.

8. 8. The method of claim 7, wherein the first patterned stress film is formed through a direct write lithography tool using a digital light processing (DLP) chip, a grating light valve, or a laser galvanometer.

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