Nonvolatile memory device and method of operating the same

Abstract

To provide a non-volatile memory device which prevents overshooting upon word line recovery and a method for operating the same.SOLUTION: An operation method includes: setting up a plurality of word lines coupled to a plurality of memory cells at respective target levels in a word line setup zone; applying a readout voltage to the selected word line which is included in the word lines and coupled to the target memory cell of the plurality of memory cells in a sensing zone and applying a readout path voltage to a non-selected word line included in the plurality of word lines to preform sensing operation; performing word line recovery operation of recovering a voltage level of the readout path voltage applied to the non-selected word line to the level of an inner voltage in a word line recovery zone; and activating a specific circuit of the non-volatile memory device to consume the inner voltage coupled to the non-selected word line in a discharge zone of the word line recovery zone. The specific circuit is coupled to the inner voltage and is not related to the word line recovery operation.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor memory device, and more particularly to a non-volatile memory device and an operating method thereof. [Background technology]

[0002] Semiconductor memory devices for storing data can be broadly divided into volatile memory devices and nonvolatile memory devices. Volatile memory devices, such as dynamic random access memory (DRAM), store data by charging or discharging a cell capacitor. Data is retained as long as power is applied, but the data is lost when the power is turned off. Nonvolatile memory devices, on the other hand, retain data even when the power is turned off. Volatile memory devices are primarily used as main memory in computers, while nonvolatile memory devices are used as large-capacity memory for storing programs and data in a wide range of applications, such as computers and portable communication devices.

[0003] In recent years, in order to improve the integration density of semiconductor memory devices, non-volatile memory devices in which memory cells are stacked in three dimensions, such as vertical NAND flash memory devices, have been actively researched. During a read operation in a non-volatile memory device, overshoot can occur during word line recovery. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-057097 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in view of the above-mentioned problems of the conventional technology, and an object of the present invention is to provide a nonvolatile memory device and an operating method thereof that prevent overshoot during word line recovery. [Means for solving the problem]

[0006] In order to achieve the above object, according to one aspect of the present invention, a method for operating a nonvolatile memory device having at least one memory block including a plurality of cell strings, each of which has a string selection transistor, a plurality of memory cells, and a ground selection transistor arranged in series in a vertical direction between a bit line and a common source line, includes the steps of: setting up a plurality of word lines connected to the plurality of memory cells to respective target levels in a word line setup period; applying a read voltage to a selected word line connected to a target memory cell of the plurality of memory cells among the word lines and applying a read pass voltage to unselected word lines among the plurality of word lines to perform a sensing operation in a word line recovery period; performing a word line recovery operation to restore a voltage level of the read pass voltage applied to the unselected word lines to a level of an internal voltage in a word line recovery period; and activating a specific circuit of the nonvolatile memory device to consume the internal voltage connected to the unselected word lines in a discharge period of the word line recovery period, wherein the specific circuit is connected to the internal voltage and is not involved in the word line recovery operation.

[0007] In order to achieve the above object, according to one aspect of the present invention, a nonvolatile memory device includes: a memory cell array having at least one memory block including a plurality of cell strings, each of which has a string select transistor, a plurality of memory cells, and a ground select transistor arranged in series in a vertical direction between a bit line and a common source line; and a control circuit that sets up a plurality of word lines connected to the plurality of memory cells to respective target levels in a word line setup period, applies a read voltage to a selected word line connected to a target memory cell of the plurality of memory cells among the plurality of word lines and applies a read pass voltage to unselected word lines among the word lines to perform a sensing operation in a word line recovery period, performs a word line recovery operation to restore a voltage level of the read pass voltage applied to the unselected word lines to a level of an internal voltage, and activates a specific circuit of the nonvolatile memory device in a discharge period of the word line recovery period to consume the internal voltage connected to the unselected word lines, wherein the specific circuit is connected to the internal voltage and is not involved in the word line recovery operation.

[0008] In order to achieve the above object, according to another aspect of the present invention, a nonvolatile memory device includes a memory cell array having at least one memory block including a plurality of cell strings, each of which has a string selection transistor, a plurality of memory cells, and a ground selection transistor arranged in series in a vertical direction between a bit line and a common source line; and a control circuit that performs a word line recovery operation in a word line setup period to set up a plurality of word lines connected to the plurality of memory cells to their respective target levels, in a sense period to apply a read voltage to a selected word line connected to a target memory cell of the plurality of memory cells among the plurality of word lines and to apply a read pass voltage to unselected word lines among the word lines to perform a sense operation, and in a word line recovery period to restore the voltage levels of the unselected word lines to the level of an external voltage provided from an external device. [Effects of the Invention]

[0009] According to the nonvolatile memory device and its operating method of the present invention, during a word line recovery operation, unselected word lines are recovered at an internal voltage level, and the internal voltage connected to the unselected word lines is consumed by a specific circuit within the nonvolatile memory device that is not related to the recovery operation, thereby reducing or preventing internal voltage overshoot that occurs during the word line recovery operation. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a flowchart illustrating a method of operating a nonvolatile memory device according to an embodiment of the present invention. [Figure 2] 2 is a diagram illustrating a step of dissipating an internal voltage in the nonvolatile memory device in the operating method of FIG. 1. [Figure 3] 2 is a diagram illustrating a step of dissipating an internal voltage in the nonvolatile memory device in the operating method of FIG. 1. [Figure 4] 2 is a diagram illustrating a step of dissipating an internal voltage in the nonvolatile memory device in the operating method of FIG. 1. [Figure 5] 1 is a block diagram showing the configuration of a memory system according to an embodiment of the present invention; [Figure 6] 6 is a block diagram showing a nonvolatile memory device in the memory system of FIG. 5. [Figure 7] 7 is a diagram illustrating a schematic structure of the nonvolatile memory device of FIG. 6. [Figure 8] 7 is a block diagram showing a memory cell array in the nonvolatile memory device of FIG. 6. FIG. [Figure 9] FIG. 9 is a circuit diagram showing one of the memory blocks in FIG. 8. [Figure 10] FIG. 10 is a diagram showing the structure of one cell string in the memory block of FIG. 9. [Figure 11] 7 is a diagram showing a connection between the memory cell array and the page buffer circuit in FIG. 6; [Figure 12] FIG. 2 is a detailed diagram of a page buffer circuit according to one embodiment of the present invention. [Figure 13]FIG. 13 is a diagram showing two inverters connected in series in FIG. 12. [Figure 14] FIG. 2 is a circuit diagram illustrating a cache unit according to an embodiment of the present invention. [Figure 15] 7 is a graph showing distribution of threshold voltages of memory cells when the memory cells included in the memory cell array of FIG. 6 are 4-bit QLC (Quadruple Level Cell). [Figure 16] 7 is a block diagram showing a configuration of an overshoot detector in the nonvolatile memory device of FIG. 6. FIG. [Figure 17] FIG. 7 is a block diagram showing the configuration of a control circuit in the nonvolatile memory device of FIG. 6. [Figure 18] FIG. 7 is a diagram showing the configuration of an address decoder in the nonvolatile memory device of FIG. 6. [Figure 19] 7 is a block diagram showing a configuration of a voltage generating circuit in the nonvolatile memory device of FIG. 6. FIG. [Figure 20] FIG. 20 is a diagram illustrating a configuration of a high voltage generator in the voltage generating circuit of FIG. [Figure 21] FIG. 20 is a diagram illustrating a configuration of a dummy voltage generator in the voltage generating circuit of FIG. [Figure 22] FIG. 21 is a diagram illustrating a configuration of an oscillator in the high voltage generator of FIG. 20. [Figure 23] FIG. 6 is a timing diagram illustrating the operation of the memory system of FIG. 5. [Figure 24] 7 is a timing diagram illustrating a read operation of the nonvolatile memory device of FIG. 6. [Figure 25] 10A and 10B are diagrams illustrating voltage levels of unselected word lines during a read operation of a nonvolatile memory device according to an embodiment of the present invention. [Figure 26] 26 is a diagram showing an example of the dump operation and word line recovery operation of FIG. 25. FIG. [Figure 27] 26 is a diagram showing an example of the dump operation and word line recovery operation of FIG. 25. FIG. [Figure 28] 26 is a diagram showing an example of the dump operation and word line recovery operation of FIG. 25. FIG. [Figure 29] 10A and 10B are diagrams illustrating voltage levels of unselected word lines during a read operation of a nonvolatile memory device according to an embodiment of the present invention. [Figure 30] 1 illustrates a nonvolatile memory device according to an embodiment of the present invention; [Figure 31] 31 is a diagram showing a first plane and a second plane in the nonvolatile memory device of FIG. 30. FIG. [Figure 32] 1 is a cross-sectional view illustrating a nonvolatile memory device according to an embodiment of the present invention; [Figure 33] 1 is a block diagram illustrating an electronic system including a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, specific examples of embodiments of the present invention will be described in detail with reference to the drawings. The same components in the drawings are designated by the same reference numerals, and duplicated descriptions of the same components will be omitted.

[0012] 1 is a flowchart illustrating a method of operating a nonvolatile memory device according to an embodiment of the present invention. Hereinafter, for convenience of explanation, the terms cell string, memory cell string, and NAND cell string are used interchangeably.

[0013] 1, as will be described later with reference to Figures 6, 11 to 23, a method of operating a nonvolatile memory device 100 having at least one memory block including a plurality of cell strings, each of which includes a string select transistor, a plurality of memory cells, and a ground select transistor arranged in series in a vertical direction between a bit line and a common source line, includes setting up word lines connected to the plurality of memory cells to their respective target levels in a word line setup period (step S110). That is, in the word line setup period, a voltage generation circuit of the nonvolatile memory device sets up a read voltage applied to a selected word line and a read pass voltage applied to unselected word lines to their respective target levels.

[0014] During the sensing period, a read voltage is applied to a selected word line connected to a target memory cell among the word lines, and a read pass voltage is applied to unselected word lines among the word lines to perform a sensing operation (step S130).

[0015] During the data dump period, the sensed data latched in the page buffer circuit is dumped to the input / output data circuit connected to the page buffer circuit (step S150).

[0016] In the discharge period of the word line recovery period, the internal voltage connected to the unselected word lines to which the read pass voltage is applied is consumed within the nonvolatile memory device, and the unselected word lines are restored to the level of the internal voltage (step S200). The discharge period will be described later with reference to FIG.

[0017] That is, when an internal voltage is connected to unselected word lines to restore the unselected word lines to the internal voltage level during a word line recovery period, the voltage level of the unselected word lines has a read pass voltage level higher than the internal voltage level, which can cause an overshoot in the internal voltage. In a nonvolatile memory device having multiple MATs, to increase design flexibility, internal voltages for two MATs are supplied to transistors included in peripheral circuits regardless of the operation of the MATs. Therefore, in the case of a plane independent read, logic may exist that includes transistors that use internal voltages belonging to different MATs. In such logic, a timing error may occur in the logic during a read operation of the first MAT.

[0018] However, in the method of operating a nonvolatile memory device according to an embodiment of the present invention, during the discharge period of the word line recovery period, the internal voltage connected to the unselected word lines to which the read pass voltage is applied is consumed within the nonvolatile memory device, and the unselected word lines are recovered to the level of the internal voltage, thereby preventing and / or reducing overshoot. For example, a specific circuit of the nonvolatile memory device that uses the internal voltage operates or is activated during the discharge period, thereby preventing or reducing overshoot of the internal voltage. The specific circuit does not substantially operate during the word line recovery period. That is, the specific circuit is not involved in (is not related to) the word line recovery operation.

[0019] FIG. 2 is a diagram illustrating steps in the operating method of FIG. 1 in which an internal voltage is consumed within the nonvolatile memory device.

[0020] As shown in FIG. 2, in order to consume the internal voltage within the nonvolatile memory device (step S200a), during the discharge period, as will be described later with reference to FIGS. 6, 11 to 14, 25, and 26, transistors using the internal voltage are repeatedly turned on and off in at least some of the page buffers of a page buffer circuit connected to at least one memory block via a plurality of bit lines and latching data sensed in a sensing operation (step S210).

[0021] FIG. 3 is a diagram illustrating steps in the operating method of FIG. 1 in which an internal voltage is consumed within the non-volatile memory device.

[0022] As shown in FIG. 3, in order to consume the internal voltage within the nonvolatile memory device (step S200b), during the discharge period, as will be described later with reference to FIGS. 20, 22, 25, and 27, an oscillator of a voltage generating circuit that generates word line voltages including a read voltage and a read pass voltage generates a corresponding clock signal based on the internal voltage (step S230).

[0023] FIG. 4 is a diagram illustrating steps in the operating method of FIG. 1 in which an internal voltage is consumed within the nonvolatile memory device.

[0024] As shown in FIG. 4, in order to consume the internal voltage within the nonvolatile memory device (step S200c), during the discharge period, as will be described later with reference to FIGS. 6, 19 to 21, 25, and 28, at least one voltage generator of a voltage generation circuit that generates word line voltages including a read voltage and a read pass voltage generates a corresponding voltage based on the internal voltage (step S250).

[0025] FIG. 5 is a block diagram showing the configuration of a memory system according to an embodiment of the present invention.

[0026] 5, the memory system 10 includes a memory controller 50 and at least one nonvolatile memory device 100. The memory system 10 is also called a storage device.

[0027] In one embodiment, the memory controller 50 and the non-volatile memory device 100 are each provided in a single chip, a single package, a single module, etc. Alternatively, the memory controller 50 and the non-volatile memory device 100 may be packaged in various packages and provided in a storage device such as a memory card.

[0028] The nonvolatile memory device 100 performs erase, write, or read operations under the control of the memory controller 50. Accordingly, a command signal CMD, an address signal ADDR, and data DATA are input to the nonvolatile memory device 100 via input / output lines. A control signal CTRL is also provided to the nonvolatile memory device 100 via a control line. An external voltage EVC is also provided to the nonvolatile memory device 100 from the memory controller 50.

[0029] FIG. 6 is a block diagram illustrating a nonvolatile memory device in the memory system of FIG.

[0030] 6, the nonvolatile memory device 100 includes a memory cell array 200 and a peripheral circuit 210. The peripheral circuit 210 includes a page buffer circuit 410, a data input / output circuit 420, a control circuit 450, a voltage generation circuit 500, and an address decoder 300. Although not shown in FIG. 6, the peripheral circuit 210 further includes an input / output interface, a column logic, a temperature sensor, and a column decoder.

[0031] The memory cell array 200 is connected to the address decoder 300 via a string select line SSL, a plurality of word lines WLs, and a ground select line GSL. The memory cell array 200 is also connected to a page buffer circuit 410 via a plurality of bit lines BLs. The memory cell array 200 includes a plurality of nonvolatile memory cells connected to the plurality of word lines WLs and the plurality of bit lines BLs.

[0032] In one embodiment, memory cell array 200 is a three-dimensional (or vertical) memory cell array formed on a substrate, where memory cell array 200 includes vertical memory cell strings including multiple memory cells stacked on top of each other.

[0033] The control circuit 450 receives a control signal CTRL, a command signal CMD, and an address signal ADDR from the memory controller 50, and controls the erase loop, program loop, and read operations of the nonvolatile memory device 100 based on the control signal CTRL, the command signal CMD, and the address signal ADDR, where the program loop includes a program operation and a program verify operation, and the erase loop includes an erase operation and an erase verify operation.

[0034] For example, the control circuit 450 generates a control signal CTLs for controlling the voltage generating circuit 500 and a page buffer control signal PCTL for controlling the page buffer circuit 410 based on the command signal CMD, generates a switching control signal SCS for controlling the address decoder 300, and generates a row address R_ADDR and a column address C_ADDR based on the address signal ADDR.

[0035] The control circuit 450 provides a row address R_ADDR to the address decoder 300 and a column address C_ADDR to the data input / output circuit 420. The control circuit 220 includes a status signal generator 485 that generates a status signal (or ready / busy signal) RnB that indicates the operating status of the nonvolatile memory device 100.

[0036] The address decoder 300 is connected to the memory cell array 200 via a string selection line SSL, a plurality of word lines WLs, and a ground selection line GSL. During a program operation or a read operation, the address decoder 300 determines one of the plurality of word lines WLs as a selected word line based on a row address R_ADDR provided from the control circuit 450, and determines the remaining word lines WLs other than the selected word line as unselected word lines.

[0037] The voltage generating circuit 500 generates the word line voltage VWLs required for the operation of the nonvolatile memory device 100 using the external voltage EVC based on the control signal CTLs provided by the control circuit 450. The voltage generating circuit 500 also generates the word line voltage VWLs using an internally generated internal voltage. The word line voltage VWLs generated by the voltage generating circuit 500 is applied to a plurality of word lines WLs by the address decoder 300.

[0038] For example, during an erase operation, the voltage generation circuit 500 applies an erase voltage to the well of a memory block and a ground voltage to all word lines of the memory block. During an erase verify operation, the voltage generation circuit 500 applies an erase verify voltage to all word lines of a memory block or applies an erase verify voltage on a word line basis.

[0039] For example, during a program operation, the voltage generation circuit 500 applies a program voltage to a selected word line and a program pass voltage to unselected word lines. During a program verify operation, the voltage generation circuit 500 applies a program verify voltage to a selected word line and a verify pass voltage to unselected word lines. During a read operation, the voltage generation circuit 500 applies a read voltage to a selected word line and a read pass voltage to unselected word lines.

[0040] The page buffer circuit 410 is connected to the memory cell array 200 via a plurality of bit lines BLs. The page buffer circuit 410 includes a plurality of page buffers PB. The page buffer circuit 410 temporarily stores data to be programmed into a selected page during a program operation, and temporarily stores data sensed from a selected page during a read operation.

[0041] In one embodiment, the page buffer units (e.g., PBU0 to PBUn in FIG. 11) included in each of the plurality of page buffers PB and the cache latches (e.g., CL0 to CLn in FIG. 11) included in each of the plurality of page buffers PB have a structure in which they are spaced apart from each other. This improves the degree of freedom for wiring arranged on the page buffer units and reduces the complexity of the layout. In addition, the cache latches are arranged adjacent to the data input / output lines, thereby reducing the distance between the carry latches and the data input / output lines and improving the data input / output speed.

[0042] The peripheral circuit 210 further includes an overshoot detector 430 .

[0043] The overshoot detector 430 compares the internal voltage IVC connected to the unselected word lines with a reference voltage when recovering the word lines during a read operation of the nonvolatile memory device 100, and provides an overshoot detection flag ODFC to the control circuit 450 if an overshoot occurs.

[0044] The data input / output circuit 420 is connected to the page buffer circuit 410 via a plurality of data lines DLs. During a program operation, the data input / output circuit 420 receives program data (DATA) from the memory controller 50 and provides the program data (DATA) to the page buffer circuit 410 based on a column address C_ADDR provided by the control circuit 450. During a read operation, the data input / output circuit 420 provides read data (DATA) stored in the page buffer circuit 410 to the memory controller 50 based on the column address C_ADDR provided by the control circuit 450.

[0045] FIG. 7 is a diagram illustrating a schematic structure of the nonvolatile memory device of FIG.

[0046] 7, the nonvolatile memory device 100 includes a first semiconductor layer L1 and a second semiconductor layer L2, where the first semiconductor layer L1 is stacked in a vertical direction VD relative to the second semiconductor layer L2. Specifically, the second semiconductor layer L2 is disposed below the first semiconductor layer L1 in the vertical direction VD, so that the second semiconductor layer L2 is disposed close to the substrate.

[0047] 6 is formed on a first semiconductor layer L1, and the peripheral circuit 210 of FIG. 6 is formed on a second semiconductor layer L2. As a result, the nonvolatile memory device 100 has a structure in which the memory cell array 200 is disposed above the peripheral circuit 210, i.e., a cell over periphery (COP) structure. The COP structure can effectively reduce the horizontal area and improve the integration density of the nonvolatile memory device 100.

[0048] In one embodiment, the second semiconductor layer L2 includes a substrate, and transistors and a metal pattern for wiring the transistors are formed on the substrate to form the peripheral circuit 210 in the second semiconductor layer L2. After the peripheral circuit 210 is formed in the second semiconductor layer L2, a first semiconductor layer L1 including the memory cell array 200 is formed, and a metal pattern for electrically connecting the word lines WL and bit lines BL of the memory cell array 200 to the peripheral circuit 210 formed in the second semiconductor layer L2 is formed. For example, the bit lines BL extend in a first horizontal direction HD1, and the word lines WL extend in a second horizontal direction HD2.

[0049] With the development of semiconductor processes, the greater the number of memory cell stages arranged in the memory cell array 200, i.e., the greater the number of stacked word lines WL, the smaller the area of ​​the memory cell array 200, and therefore the smaller the area of ​​the peripheral circuit 210. According to this embodiment, in order to reduce the area occupied by the page buffer circuit 410, the page buffer circuit 410 has a structure in which the page buffer unit and the cache latch are separated, and the sense nodes included in each page buffer unit are commonly connected to a combined sense node. This will be described in detail with reference to FIG. 9.

[0050] FIG. 8 is a block diagram showing a memory cell array in the nonvolatile memory device of FIG.

[0051] 8, the memory cell array 200 includes a plurality of memory blocks (BLK1 to BLKz, where z is a natural number equal to or greater than 3) arranged along a plurality of directions (HD1, HD2, VD). In one embodiment, the memory blocks are selected by the address decoder 300 in FIG. 6. For example, the address decoder 300 selects the memory block BLK corresponding to the block address of the memory blocks (BLK1 to BLKz).

[0052] FIG. 9 is a circuit diagram showing one memory block BLKi of the memory blocks (BLK1 to BLKz) in FIG.

[0053] 9 represents a three-dimensional memory block formed in a three-dimensional structure on a substrate SUB. For example, a plurality of memory cell strings included in the memory block BLKi are stacked in a direction VD perpendicular to the substrate SUB.

[0054] 9, the memory block BLKi includes a plurality of memory cell strings (or NAND strings NS11 to NS33) connected between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the memory cell strings NS11 to NS33 includes a string select transistor SST, a plurality of memory cells MC1, MC2, ..., MC8, and a ground select transistor GST.

[0055] The string select transistors SST are connected to corresponding string select lines (SSL1, SSL2, SSL3). The memory cells MC1, MC2, ..., MC8 are connected to corresponding word lines (WL1, WL2, ..., WL8), respectively. The ground select transistors GST are connected to corresponding ground select lines (GSL1, GSL2, GSL3). The string select transistors SST are connected to corresponding bit lines (BL1, BL2, BL3), and the ground select transistors GST are connected to a common source line CSL.

[0056] Word lines at the same height (for example, WL1) are commonly connected, and ground selection lines (GSL1, GSL2, GSL3) and string selection lines (SSL1, SSL2, SSL3) are separable from each other.

[0057] FIG. 10 is a diagram showing the structure of one cell string in the memory block of FIG.

[0058] 9 and 10, the cell string NS11 is provided with pillars PL on a substrate SUB, extending in a direction perpendicular to the substrate and in contact with the substrate SUB. The ground selection line GSL1, word lines (WL1 to WL8), and string selection line SSL1 shown in Fig. 10 are each formed of a conductive material, for example, a metal material, parallel to the substrate SUB. The pillars PL penetrate the conductive material forming the ground selection line GSL1, word lines (WL1 to WL8), and string selection line SSL1 to contact the substrate SUB.

[0059] 10 also shows a cross-sectional view along the line A-A'. For example, the cross-sectional view shows a first memory cell MC1 corresponding to a first word line WL1. The pillar PL includes a cylindrical body BD. An air gap AG is provided within the body BD.

[0060] The body BD includes P-type silicon and is a region where a channel is formed. The pillar PL further includes a cylindrical tunnel insulating film TI surrounding the body BD and a cylindrical charge trapping film CT surrounding the tunnel insulating film TI. A blocking insulating film BI is provided between the first word line WL1 and the pillar PL. The body BD, the tunnel insulating film TI, the charge trapping film CT, the blocking insulating film BI, and the first word line WL1 are charge trapping transistors formed in a direction perpendicular to the substrate SUB or the upper surface of the substrate SUB. The string select transistor SST, the ground select transistor GST, and other memory cells have the same structure as the first memory cell MC1.

[0061] FIG. 11 is a diagram showing the connection between the memory cell array and the page buffer circuit of FIG.

[0062] 11, the memory cell array 200 includes first through (n+1)th cell (NAND) strings (NS0 through NSn), each of which includes a ground selection transistor GST connected to a ground selection line GSL, a plurality of memory cells MC respectively connected to a plurality of word lines (WL0 through WLm), and a string selection transistor SST connected to a string selection line SSL, where the ground selection transistor GST, the plurality of memory cells MC, and the string selection transistor SST are connected in series with each other, where m is a positive integer.

[0063] The page buffer circuit 410 includes first through (n+1)th page buffer units (PBU0 through PBUn). The first page buffer unit PB0 is connected to the first cell (NAND) string NS0 via the first bit line BL0, and the (n+1)th page buffer unit PBUn is connected to the (n+1)th NAND string NSn via the (n+1)th bit line BLn. Here, n is a positive integer. For example, n is 7, and the page buffer circuit 410 has a structure in which eight stages of page buffer units (PBU0 through PBUn) are arranged in a row. For example, the first through (n+1)th page buffer units (PBU0 through PBUn) are arranged in a row along the extension direction of the first through (n+1)th bit lines (BL0 through BLn).

[0064] The page buffer circuit 410 further includes first to (n+1)th cache latches (CL0 to CLn) corresponding to the first to (n+1)th page buffer units (PBU0 to PBUn), respectively. The page buffer circuit 410 has a structure in which eight stages of cache latches (CL0 to CLn) are arranged in a row. For example, the first to (n+1)th cache latches (CL0 to CLn) are arranged in a row along the extension direction of the first to (n+1)th bit lines (BL0 to BLn).

[0065] The sense nodes of the first to (n+1)th page buffer units (PBU0 to PBUn) are commonly connected to a combined sense node SOC. The first to (n+1)th cache latches (CL0 to CLn) are also commonly connected to the combined sense node SOC. Thus, the first to (n+1)th page buffer units (PBU0 to PBUn) are connected to the first to (n+1)th cache latches (CL0 to CLn) via the combined sense node SOC.

[0066] FIG. 12 is a detailed diagram of a page buffer PB circuit according to one embodiment of the present invention.

[0067] 12, the page buffer PB corresponds to the page buffer PB in FIG. 6. The page buffer PB includes a page buffer unit PBU and a cache unit CU. The cache unit CU includes a cache latch (C-LATCH, CL), and the cache latch CL is connected to a data input / output line, so the cache unit CU is arranged adjacent to the data input / output line. As a result, the page buffer unit PBU and the cache unit CU are arranged separately from each other, and the page buffer PB has a separated structure of the page buffer unit PBU and the cache unit CU.

[0068] The page buffer unit PBU includes a main unit MU. The main unit MU includes main transistors in the page buffer PB. The page buffer unit PBU further includes a bit line selection transistor TR_hv connected to the bit line BL and driven by a bit line selection signal BLSLT. The bit line selection transistor TR_hv is implemented as a high voltage transistor, and therefore, the bit line selection transistor TR_hv is disposed in a well region, i.e., a high voltage unit HVU, different from the main unit MU.

[0069] The main unit MU includes a sense latch (S-LATCH) SL, a force latch (F-LATCH) FL, a most significant bit latch (M-LATCH) ML, and a least significant bit latch (L-LATCH) LL. In one embodiment, the sense latch SL, the force latch FL, the most significant bit latch ML, or the least significant bit latch LL are referred to as a "main latch." The main unit MU further includes a precharge circuit PC that controls a precharge operation for the bit line BL or the sense node SO based on a bit line clamp control signal BLCLAMP, and further includes a transistor PM' that is driven by a bit line setup signal BLSETUP.

[0070] The sense latch SL stores data stored in a memory cell or a sensed result of the threshold voltage of the memory cell during a read or program verify operation. The sense latch SL is also used to apply a program bit line voltage or a program inhibit voltage to the bit line BL during a program operation. The force latch FL is used to improve the threshold voltage distribution during a program operation. Specifically, the force latch FL stores force data. The force data is initially set to "1" and then inverted to "0" when the threshold voltage of the memory cell enters a forcing region that does not reach the target region. By using the force data, the bit line voltage can be controlled during a program operation to narrow the program threshold voltage distribution.

[0071] The upper bit latch ML, lower bit latch LL, and cache latch CL are used to store data input from the outside during a program operation and are referred to as "data latches." When programming 3 bits of data into one memory cell, the 3 bits of data are stored in the upper bit latch ML, lower bit latch LL, and cache latch CL, respectively. The upper bit latch ML, lower bit latch LL, and cache latch CL retain the stored data until the programming of the memory cell is completed. In addition, during a read operation, the cache latch CL outputs data read from the memory cell and transmitted from the sense latch SL to the outside via a data input / output line.

[0072] Moreover, the main unit MU further includes first to fourth transistors (NM1 to NM4) and a plurality of inverters (INV11, INV12, INV21, INV22, INV31, INV32, INV41, INV42).

[0073] The first transistor NM1 is connected between the sense node SO and the sense latch SL and is driven by a ground control signal SOGND passing through inverters INV11 and INV12. The second transistor NM2 is connected between the sense node SO and the force latch FL and is driven by a force monitor signal MON_F passing through inverters INV21 and INV22. The third transistor NM3 is connected between the sense node SO and the most significant bit latch ML and is driven by a most significant bit monitor signal MON_M passing through inverters INV31 and INV32. The fourth transistor NM4 is connected between the sense node SO and the least significant bit latch LL and is driven by a least significant bit monitor signal MON_L passing through inverters INV41 and INV42.

[0074] The main unit MU further includes fifth and sixth transistors NM5 and NM6 connected in series between the bit line select transistor TR_hv and the sense node SO. The fifth transistor NM5 is driven by a bit line shut-off signal BLSHF, and the sixth transistor NM6 is driven by a bit line connection control signal CLBLK. The main unit MU also includes a precharge transistor PM. The precharge transistor PM is connected to the sense node SO and driven by a load signal LOAD to precharge the sense node SO to a precharge level during a precharge period.

[0075] In this embodiment, the main unit MU further includes a pair of pass transistors, i.e., first and second pass transistors (TR, TR'), coupled to the sense node SO. In one embodiment, the first and second pass transistors (TR, TR') are referred to as "first and second sense node-coupled transistors." The first and second pass transistors (TR, TR') are driven by a pass control signal SO_PASS. In one embodiment, the pass control signal SO_PAS is referred to as "sense node-coupled control signal." Specifically, the first pass transistor TR is coupled between the first terminal SOC_U and the sense node SO, and the second pass transistor TR' is coupled between the sense node SO and the second terminal SOC_D.

[0076] For example, if the page buffer unit PBU is the second page buffer unit PBU1 in Fig. 11, the first terminal SOC_U is connected to one end of a pass transistor included in the first page buffer unit BU0, and the second terminal SOC_D is connected to one end of a pass transistor included in the third page buffer unit PBU2, so that the sense node SO is electrically connected to the coupled sense node SOC by the pass transistors included in each of the third to (n+1)th page buffer units (PBU2 to PBUn).

[0077] The page buffer PB verifies whether a selected memory cell among memory cells included in a NAND string connected to a bit line BL has been programmed during a program operation. Specifically, the page buffer PB stores data sensed through the bit line BL in a sense latch SL during a program verify operation. The upper bit latch ML and the lower bit latch LL, in which target data is stored, are set according to the sensed data stored in the sense latch SL.

[0078] For example, if the sensed data indicates that programming is complete, the upper bit latch ML and the lower bit latch LL are changed to a program inhibit setting for the selected memory cell in the subsequent program loop. The cache latch CL temporarily stores input data provided from the outside. During a program operation, target data to be stored in the cache latch CL is stored in the upper bit latch ML and the lower bit latch LL.

[0079] Hereinafter, it is assumed that signals for controlling the components of the page buffer circuit 410 are included in the page buffer control signal PCTL in FIG.

[0080] FIG. 13 is a diagram showing two inverters connected in series in FIG.

[0081] FIG. 13 shows inverters (INV11, INV12) that provide a ground control signal SOGND to the first transistor NM1.

[0082] As shown in FIG. 13, the inverter INV11 includes a PMOS transistor 411 and an NMOS transistor 412 connected in series between the internal voltage IVC and the ground voltage VSS, and the inverter INV12 includes a PMOS transistor 413 and an NMOS transistor 414 connected in series between the internal voltage IVC and the ground voltage VSS.

[0083] The PMOS transistor 411 is connected between the internal voltage IVC and a node N11, and the NMOS transistor 412 is connected between the node N11 and the ground voltage VSS. A ground control signal SOGND is provided to the gates of the PMOS transistor 411 and the NMOS transistor 412. Therefore, the inverter INV11 inverts the ground control signal SOGND.

[0084] The PMOS transistor 413 is connected between the internal voltage IVC and the node N12, and the NMOS transistor 414 is connected between the node N12 and the ground voltage VSS. The output of the inverter INV11 is provided to the gates of the PMOS transistor 413 and the NMOS transistor 414. Therefore, the inverter INV12 inverts the output of the inverter INV11 and applies it to the gate of the first transistor NM1.

[0085] FIG. 14 is a circuit diagram showing a cache unit CU according to one embodiment of the present invention.

[0086] 12 and 14, the cache unit CU includes a monitor transistor NM7 and a cache latch CL, which includes first and second inverters INV1 and INV2, a dump transistor 132, and transistors 131, 133, 134, 135, etc. The monitor transistor NM7 is driven by a cache monitor signal MON_C to control the connection between the coupled sense node SOC and the cache latch CL.

[0087] The first inverter INV1 is connected between the first node ND1 and the second node ND2, and the second inverter INV2 is connected between the second node ND2 and the first node ND1, and the first and second inverters INV1 and INV2 form a latch. The transistor 131 has a gate connected to the coupled sense node SOC.

[0088] The dump transistor 132 is driven by a dump signal DMP to transfer data stored in the cache latch CL to a main latch, such as a sense latch SL, in the page buffer unit PBU. The transistor 133 is driven by a data signal DI, the transistor 134 is driven by a data inverted signal nDI, and the transistor 135 is driven by a write control signal DIO_W. When the write control signal DIO_W is activated, the voltage levels of the first and second nodes ND1 and ND2 are determined by the data signal DI and the data inverted signal nDI.

[0089] The cache unit CU is connected to the data input / output line RDi through transistors 136 and 137. The transistor 136 has a gate connected to a second node ND2 and is turned on or off depending on the voltage level of the second node ND2. The transistor 137 is driven by a read control signal DIO_R. When the read control signal DIO_R is activated and the transistor 137 is turned on, the voltage level of the data input / output line RDi is determined to be "1" or "0" depending on the state of the cache latch CL.

[0090] FIG. 15 is a graph showing the distribution of threshold voltages of memory cells when the memory cells included in the memory cell array of FIG. 6 are 4-bit QLC (Quadruple Level Cell).

[0091] If the memory cell is a 4-bit multi-level cell programmed with 4 bits, the memory cell has an erased state E or one of the first to fifteenth programmed states (P1 to P15). Compared to single-level cells, multi-level cells have narrower spacing between threshold voltage Vth distributions, so small changes in threshold voltage Vth can cause significant problems in multi-level cells.

[0092] The first read voltage Vr1 has a voltage level between the distribution of memory cells having the erased state E and the distribution of memory cells having the first programmed state P1. The second to fifteenth read voltages (Vr2 to Vr15) have voltage levels between the distributions of memory cells having the corresponding adjacent programmed states (P1 to P15).

[0093] In one embodiment, when the first read voltage Vr1 is applied and the memory cell is turned on, it is determined that data "1" is stored, and when the memory cell is turned off, it is determined that data "0" is stored. However, the present invention is not limited to this. In other embodiments, when the first read voltage Vr1 is applied and the memory cell is turned on, it is determined that data "0" is stored, and when the memory cell is turned off, it is determined that data "1" is stored. In this way, the assignment of logical levels of data may vary depending on the embodiment.

[0094] FIG. 16 is a block diagram showing the configuration of the overshoot detector in the nonvolatile memory device of FIG.

[0095] As shown in FIG. 16, the overshoot detector 430 includes a voltage comparator 431 .

[0096] The voltage comparator 431 compares the internal voltage IVC with a reference voltage VREF_OVS, which is the basis for overshoot detection, and generates an overshoot detection flag ODFG that is activated in response to the level of the internal voltage IVC being equal to or higher than the reference voltage VREF_OVS based on the comparison, and provides the overshoot detection flag ODFG to the control circuit 450.

[0097] In this embodiment, the control circuit 450 sets the discharge interval based on the overshoot detection flag ODFG, i.e., the control circuit 450 sets the start and end points of the discharge interval based on the overshoot detection flag ODFG.

[0098] FIG. 17 is a block diagram showing the configuration of a control circuit in the nonvolatile memory device of FIG.

[0099] As shown in FIG. 17, the control circuit 450 includes a command decoder 460, an address buffer 470, a control signal generator 480, and a status signal generator 485.

[0100] The command decoder 460 decodes the command signal CMD and provides the decoded command D_CMD to the control signal generator 480 and the status signal generator 485 .

[0101] The address buffer 470 receives the address signal ADDR, and provides the row address R_ADDR of the address signal ADDR to the address decoder 300 and the column address C_ADDR to the data input / output circuit 420 .

[0102] The control signal generator 480 receives the decoded command D_CMD, generates a control signal CTLs based on an operation instructed by the decoded command D_CMD, and provides the control signal CTLs to the voltage generating circuit 500. The control signal generator 480 generates a page buffer control signal PCTL based on an operation instructed by the decoded command D_CMD, and provides the page buffer control signal PCTL to the page buffer circuit 410, and generates a switching control signal SCS and provides the switching control signal SCS to the address decoder 300.

[0103] The status signal generator 485 receives the decoded command D_CMD, monitors the operation indicated by the decoded command D_CMD, and transitions the status signal RnB, which indicates a ready state or a busy state, based on whether the operation indicated by the decoded command D_CMD is completed.

[0104] FIG. 18 is a diagram showing the configuration of the address decoder in the nonvolatile memory device of FIG.

[0105] As shown in FIG. 18, the address decoder 300 includes a driver circuit 310 and a path switch circuit 360.

[0106] The driver circuit 310 provides the voltage provided from the voltage generating circuit 500 to the memory cell array 200 in response to a block address. The driver circuit 310 includes a block select driver 320, a string select driver 330, a word line driver 340, and a ground select driver 350.

[0107] In response to a block address, the block select driver 320 provides a high voltage VPPH, provided from the voltage generation circuit 500, to the pass switch circuit 360. The block select driver 320 provides a high voltage to a block word line BLKWL connected to the gates of a plurality of pass transistors (GPT, PT1 to PTn, SSPT) included in the pass switch circuit 360. The block select driver 320 controls the time points at which the pass voltage, the program voltage, and the read voltage are applied.

[0108] The string selection driver 330 provides a voltage provided from the voltage generating circuit 500 as a string selection signal SS. During a program operation, the string selection driver 330 applies the string selection signal SS to turn on all string selection transistors selected in one memory block.

[0109] The word line driver 340 provides the program voltage VPGM, pass voltage VPASS, verify voltage VPV, read voltage VRD, internal voltage IVC, and negative voltage VNEG provided from the voltage generating circuit 500 to the word lines (WL1 to WLn) through the drive lines (S1 to Sn) and pass transistors (PT1 to PTn) in response to the operation of the nonvolatile memory device 100.

[0110] In this embodiment, the word lines (WL1 to WLn) include at least one dummy word line and a normal word line. The dummy memory cells are activated by the dummy word lines and do not store valid data read from an external device. Data stored in the dummy memory cells connected to the dummy word lines is not transferred to the outside of the memory cell array by a select signal. The dummy word lines are not connected to bit lines that provide connections to normal memory cells. A dummy voltage VDUM is applied to the dummy word lines.

[0111] The ground select driver 350 provides a ground select signal GS to the ground select line GSL through a pass transistor GPT.

[0112] The pass transistors (GPT, PT1 to PTn, SSPT) are configured to electrically connect the ground selection line GSL, the word lines (WL1 to WLn), and the string selection line SSL to corresponding drive lines in response to activation of a high voltage signal provided via the block word line BLKWL. The pass transistors (GPT, PT1 to PTn, SSPT) are high-voltage transistors that can withstand high voltages.

[0113] FIG. 19 is a block diagram showing the configuration of a voltage generating circuit in the nonvolatile memory device of FIG.

[0114] 19, the voltage generating circuit 500 includes a high voltage generator 510 and a low voltage generator 530. In this embodiment, the voltage generating circuit 500 further includes a negative voltage generator 550 and a dummy voltage generator 570.

[0115] The high voltage generator 510 generates a program voltage VPGM, a pass voltage VPASS, a high voltage VPPH, and an erase voltage VRES in response to the first control signal CTL1 according to the operation instructed by the decoded command D_CMD.

[0116] A program voltage VPGM is applied to a selected word line, a pass voltage VPASS is applied to unselected word lines, and an erase voltage VRES is provided to the well of the memory block or to the drains of each of the pass transistors coupled to the bit lines and the common source line. A high voltage VPPH is applied to the gates of each of the pass transistors coupled to the word lines, string select lines, and ground select lines. The first control signal CTL1 includes multiple bits and indicates the operation indicated by the decoded command D_CMD.

[0117] The low voltage generator 530 generates a program verify voltage VPV, a read voltage VRD, a drive voltage VDRV, and an internal voltage IVC in response to the second control signal CTL2 according to an operation instructed by the decoded command D_CMD. The program verify voltage VPV and the read voltage VRD are applied to a selected word line according to the operation. The internal voltage IVC is applied to unselected word lines during recovery of unselected word lines according to a read operation. The drive voltage VDRV is applied to a selected string select line SSL and a selected ground select line GSL according to an operation of the nonvolatile memory device 100. The second control signal CTL2 includes multiple bits and indicates an operation instructed by the decoded command D_CMD.

[0118] The negative voltage generator 550 generates a negative voltage VNEG having a negative level according to an operation indicated by the decoded command D_CMD in response to a third control signal CTL3. The third control signal CTL3 includes multiple bits and indicates an operation indicated by the decoded command D_CMD. The negative voltage VNEG is applied to a selected word line and unselected word lines during a program recovery period, and to unselected word lines during a bit line setup period.

[0119] The dummy voltage generator 570 is activated in response to the first activation signal EN1 and generates a dummy voltage VDUM based on the internal voltage IVC. The control circuit 450 activates the first activation signal EN1 to operate the dummy voltage generator 570 during testing of the nonvolatile memory device 100 or during the discharge period of the recovery period of the read operation described above.

[0120] When the dummy voltage generator 570 is activated in the discharge period of the recovery period, the dummy voltage generator 570 consumes the internal voltage IVC.

[0121] FIG. 20 is a diagram showing the configuration of a high voltage generator in the voltage generating circuit of FIG.

[0122] As shown in FIG. 20, the high voltage generator 510 includes a reference voltage generator 511, an oscillator 610, a program voltage detector (VD_VPGM) 513, a program voltage pump (PUMP_VPGM) 514, a pass voltage detector (VD_VPASS) 515, a pass voltage pump (PUMP_VPASS) 516, a high voltage detector (VD_VPPH) 517, a high voltage pump (PUMP_VPPH) 518, an erase voltage detector (VD_VERS) 519, and an erase voltage pump (PUMP_VERS) 521.

[0123] The reference voltage generator 511 generates one or more reference voltages VREFH based on the external voltage EVC. The oscillator 610 generates a clock signal CLKH based on the internal voltage IVC.

[0124] A program voltage detector (VD_VPGM) 513 receives a reference voltage VREFH and a clock signal CLKH, detects a program voltage VPGM, and generates a clock CLK_VPGM for the program voltage. A program voltage pump (PUMP_VPGM) 514 operates a boost circuit based on the program voltage clock CLK_VPGM to generate the program voltage VPGM.

[0125] A pass voltage detector (VD_VPASS) 515 receives a reference voltage VREFH and a clock signal CLKH, detects a pass voltage VPASS, and generates a pass voltage clock CLK_VPASS. A pass voltage pump (PUMP_VPASS) 516 operates a boost circuit based on the pass voltage clock CLK_VPASS to generate the pass voltage VPASS.

[0126] The high voltage detector (VD_VPPH) 517 receives the reference voltage VREFH and the clock signal CLKH, detects the high voltage VPPH, and generates the high voltage clock CLK_VPP. The high voltage pump (PUMP_VPPH) 518 operates a boost circuit based on the high voltage clock CLK_VPP to generate the high voltage VPPH. Although not shown, the high voltage detector 517 further includes a voltage divider 525, which divides the high voltage VPPH and outputs a high voltage VPPH_L having a lower level than the high voltage VPPH.

[0127] The erase voltage detector (VD_VERS) 519 receives the reference voltage VREFH and the clock signal CLKH, detects the erase voltage VERS, and generates a clock signal CLK_VERS for the erase voltage. The erase voltage pump (PUMP_VERS) 520 operates a boost circuit based on the erase voltage clock signal CLK_VERS to generate the erase voltage VERS.

[0128] Although not shown, an internal voltage IVC is applied to at least one of the program voltage detector 513, the program voltage pump 514, the pass voltage detector 515, the pass voltage pump 516, the high voltage detector 517, the high voltage pump 518, the erase voltage detector 519, and the erase voltage pump 520.

[0129] The control circuit 450 in FIG. 6 provides the second activation signal EN2 to the oscillator 610 in the discharge period of the word line recovery period, and operates the oscillator 610 to consume the internal voltage IVC during the word line recovery operation of the unselected word lines.

[0130] FIG. 21 is a diagram showing a configuration of a dummy voltage generator in the voltage generating circuit of FIG.

[0131] As shown in FIG. 21, the dummy voltage generator 570 includes an operational amplifier 571, a PMOS transistor 572, and a feedback circuit 573.

[0132] The operational amplifier 571 receives the feedback voltage VFB and the reference voltage VREF1, amplifies the difference between the feedback voltage VFB and the reference voltage VREF1, and outputs the amplified difference.

[0133] The PMOS transistor 572 has a source connected to the internal voltage IVC, a drain connected to the output node NO, and a gate receiving the output of the operational amplifier 571. The PMOS transistor 572 regulates the internal voltage IVC based on the output of the operational amplifier 571 and outputs a dummy voltage VDUM from the output node NO.

[0134] The feedback circuit 573 includes a first feedback resistor Rf1 and a second feedback resistor Rf2 connected in series between the output node NO and the ground voltage VSS, and provides a feedback voltage VFB to the operational amplifier 571 from a feedback node FN to which the first feedback resistor Rf1 and the second feedback resistor Rf2 are connected.

[0135] In this embodiment, during the sensing period of a read operation, a dummy voltage VDUM is applied to the dummy word lines of the memory cell array 200 through the word line driver 340 of FIG.

[0136] FIG. 22 is a diagram showing a configuration of an oscillator in the high voltage generator of FIG.

[0137] As shown in FIG. 22, the oscillator 610 includes a reference voltage generator 620, a first comparison circuit 630, a second comparison circuit 640, and a latch circuit 650.

[0138] The reference voltage generator 620 generates a reference voltage VREF2 based on the internal voltage IVC and provides the reference voltage VREF2 to the first comparison circuit 630 and the second comparison circuit 640.

[0139] The reference voltage generator 620 includes a PMOS transistor 621, a resistor R1, and NMOS transistors (623, 624, 625).

[0140] The PMOS transistor 621 has a source coupled to the internal voltage IVC, a gate receiving a second enable signal EN2, and a drain coupled to a resistor R1.

[0141] The NMOS transistor 623 has a drain connected to the resistor R1 at node N21, a gate connected to node N21, and a source connected to ground voltage VSS. The NMOS transistor 624 has a drain connected to the first comparison circuit 630 at node N22, a gate connected to node N21, and a source connected to ground voltage VSS. The NMOS transistor 625 has a drain connected to the second comparison circuit 640 at node N24, a gate connected to node N21, and a source connected to ground voltage VSS.

[0142] Each of the NMOS transistors (624, 625) forms a current mirror with the NMOS transistor 623.

[0143] In response to the second activation signal EN2, the PMOS transistor 621 provides the reference current IREF to the node N21 via the resistor R1. A reference voltage VREF2 based on the reference current IREF is induced at the node N21. Therefore, the level of the reference voltage VREF2 is induced according to the activation interval of the second activation signal EN2.

[0144] The latch circuit 650 includes a first NAND gate 651 and a second NAND gate 653. The first NAND gate 651 performs a NAND operation on the first comparison signal CS1 provided from the first comparison circuit 630 and the second latch signal LS2 output from the second NAND gate 653, and outputs a first latch signal LS1. The second NAND gate 653 performs a NAND operation on the second comparison signal CS2 provided from the second comparison circuit 640 and the first latch signal LS1 output from the first NAND gate 651, and outputs a second latch signal LS2, and provides the second latch signal LS2 as a clock signal CLKH.

[0145] The first comparison circuit 630 includes a PMOS transistor 631, an NMOS transistor 633, an operational amplifier 635, and a capacitor C1.

[0146] The PMOS transistor 631 is connected between the internal voltage IVC and the node N23 and has a gate receiving the second latch signal LS2. The NMOS transistor 633 is connected between the node N23 and the node N22 and has a gate receiving the second latch signal LS2. That is, the PMOS transistor 631 and the NMOS transistor 633 invert the second latch signal LS2.

[0147] Capacitor C1 is connected between node N23 and ground voltage VSS to store the voltage of node N23. Operational amplifier 635 compares the voltage level of node N23 with reference voltage VREF2 and provides a first comparison signal CS1 to latch circuit 650 based on the comparison result.

[0148] The second comparison circuit 640 includes a PMOS transistor 641, an NMOS transistor 643, an operational amplifier 645, and a capacitor C2.

[0149] The PMOS transistor 641 is connected between the internal voltage IVC and the node N25 and has a gate receiving the first latch signal LS1. The NMOS transistor 643 is connected between the node N25 and the node N24 and has a gate receiving the first latch signal LS1. That is, the PMOS transistor 641 and the NMOS transistor 643 invert the first latch signal LS1.

[0150] Capacitor C2 is connected between node N25 and ground voltage VSS to store the voltage of node N25. Operational amplifier 645 compares the voltage level of node N25 with reference voltage VREF2 and provides a second comparison signal CS2 to latch circuit 650 based on the comparison result.

[0151] During an interval in which the second activation signal EN2 is activated to a low level, the NMOS transistors 624 and 625 are turned on in response to the reference voltage VREF2, and the sources of the NMOS transistors 624 and 625 are connected to the ground voltage VSS. Therefore, during an interval in which the second activation signal EN2 is activated to a low level, the oscillator 610 outputs the second latch signal LS2 as the clock signal CLKH based on a result of comparing the second latch signal LS2 with the reference voltage VREF2 and a result of comparing the first latch signal LS1 with the reference voltage VREF2. Thus, the oscillator 610 outputs the clock signal CLKH that toggles during an interval in which the second activation signal EN2 is activated to a low level.

[0152] FIG. 23 is a timing diagram showing the operation of the memory system of FIG.

[0153] As shown in FIGS. 5 and 23, the memory controller 50 reads the sensed data before the word line recovery of the non-volatile memory device 100 is completed.

[0154] The memory controller 50 provides a read command to the nonvolatile memory device 100 during a high interval of the status signal RnB. The read command is provided, for example, in a command sequence (00h-ADDR-30h). When the input of the read command is completed, the nonvolatile memory device 100 transitions the status signal RnB to a low level "L." At this time, when a status read command (e.g., 70h) is provided through the data input / output terminal I / O, the nonvolatile memory device 100 outputs a busy state (Busy).

[0155] In response to a read command, the nonvolatile memory device 100 generates a word line voltage to be applied to a selected memory region and applies the generated word line voltage to the selected memory region. This operation is performed during a word line setup period WLS corresponding to a period T0-T1. Next, the nonvolatile memory device 100 senses and latches cells in the selected memory region. This operation is performed during a sensing period SEBSING corresponding to a period T1-T2. The sensed data is then dumped to the data input / output circuit 420. This operation is performed during a dump period DUMP shown in a period T2-T3.

[0156] At time T3 when the dumping of the sensed data to the data input / output circuit 420 is completed, the nonvolatile memory device 100 performs a word line recovery operation in a word line recovery period RCY, which discharges the bulk, word line, bit line, select line, common source line, etc. of the selected memory cell. The word line recovery operation is performed during the word line recovery period RCY, which corresponds to the period (T3-T4) of FIG. 23. Also, at time T3 when the dumping of the sensed data is completed, the nonvolatile memory device 100 transitions the state signal RnB to a high level "H." After the state signal RnB transitions to a high level "H," data can be output from the nonvolatile memory device 100 to the outside. When the memory controller 50 activates the read enable signal ( / RE) based on the state signal RnB, the dumped data is output from the nonvolatile memory device 100.

[0157] Here, a definition of the time during which sensed data can be output is required since the word line recovery operation of the nonvolatile memory device 100 is being performed. Although the status signal RnB is substantially at a high level (H), no external command should be provided during the time period (T3 to T4) during which the word line recovery operation of the nonvolatile memory device 100 is being performed. This is because even if a command is input from the memory controller 50 to the nonvolatile memory device 100, a malfunction may occur due to the incomplete word line recovery operation.

[0158] Therefore, during the time (tRC) from when the status signal RnB transitions from low level (L) to high level (H) in response to a read command until the recovery operation is completed, command input is prohibited even if data output is completed. This time (tRC) is referred to as the command wait time tRC. During an access operation of the nonvolatile memory device 100, after the command wait time tRC has elapsed, the memory controller 50 provides a subsequent command such as read / program / erase.

[0159] FIG. 24 is a timing diagram illustrating a read operation of the nonvolatile memory device of FIG.

[0160] As shown in FIGS. 6 and 24, the nonvolatile memory device 100 performs a read operation by sequentially executing a word line setup (WLS), sensing (SENSING), dump (DUMP), and word line recovery (RCY) operation in response to a read command signal (CMD).

[0161] When a read command is received while the status signal (or ready / busy signal) RnB is at a high level (H), the nonvolatile memory device 100 transitions the status signal RnB to a low level (L) and begins all procedures for sensing the selected memory cell.

[0162] First, at time t0, the nonvolatile memory device 100 performs a word line setup (WLS) operation. A high-level (H) power supply voltage VCC is applied to the string select line SSL of a selected memory block of the nonvolatile memory device 100. A read voltage VRD is applied to the selected word line WL_SEL, and a read pass voltage VPASS is applied to the unselected word lines WL_UNSEL.

[0163] At time t1, the nonvolatile memory device 100 senses a selected memory cell. To sense the memory cell, a read voltage VRD is applied to the selected word line WL_SEL. Although not shown, the bit line of the memory cell is precharged to a specific level for the sensing operation. In this state, when a sense enable signal S_EN is applied from the control circuit 450, the page buffer circuit 410 senses the bit line or the sense node to which the bit line precharge voltage is applied. That is, the page buffer circuit 410 stores the sensed data in a latch according to the level of the sense node.

[0164] At time t2, the control circuit 450 provides a dump signal DMP to the page buffer circuit 410. In response to the dump signal DMP, the page buffer circuit 410 outputs sensed data from an internal latch to the data input / output circuit 420. The sensed data output from the page buffer circuit 410 is stored in a latch terminal provided in the data input / output circuit 420. This dump operation continues until time t3.

[0165] At time t3, the control circuit 450 controls the memory cell array 200, address decoder 300, page buffer circuit 410, voltage generator circuit 500, etc. to discharge any voltages (or currents) provided for the read operation. That is, a recovery operation is performed at time t3 to restore the bias state of the memory cell array 200 to the state before the read operation. The control circuit 450 transitions the status signal RnB to a high level (H) at time t3 when the data dump operation is completed. Then, if a status read command is provided during this period, the control circuit 450 outputs a ready state (Ready). When the status signal RnB transitions to a high level (H), the read enable signal ( / RE) of the read data stored in the data input / output circuit 420 is activated. For example, the nonvolatile memory device 100 does not output the dumped data through the input / output terminal I / O while the read enable signal ( / RE) is activated.

[0166] During the command wait time tRC when the state signal RnB is at a high level, a word line recovery operation of the nonvolatile memory device 100 occurs. For example, the word line recovery operation discharges the string selection line SSL from the power supply voltage VCC to the ground voltage VSS level. Furthermore, the read voltage applied to the selected word line WL_SEL is discharged to the ground voltage VSS level. During the word line recovery operation, the read pass voltage applied to the unselected word lines WL_UNSEL is discharged to the internal voltage IVC level. The control circuit 450 activates specific circuits of the nonvolatile memory device 110 during a discharge period (t4 to t5) when the discharge signal DSCHG is activated, thereby consuming the internal voltage IVC connected to the unselected word lines WL_UNSEL within the nonvolatile memory device 100. That is, during the discharge period (t4 to t5) when the discharge signal DSCHG is activated, the specific circuits are supplied with the internal voltage IVC connected to the unselected word lines WL_UNSEL and are activated. At time t4, the control circuit provides an activated discharge signal DSCHG to the page buffer circuit 410. Therefore, by operating a specific circuit during the discharge period, overshoot of the internal voltage IVC can be prevented / reduced. Although the discharge signal DSCHG is shown as being deactivated at time t5, the discharge signal DSCHG may be deactivated earlier than time t5.

[0167] The command waiting time tRC during which command input is prohibited after the state signal RnB transitions to high level (H) is determined in consideration of the start and completion times of the word line recovery operation.

[0168] The discharge of the selected word line WL_SEL and the unselected word line WL_UNSEL is maintained until time t6.

[0169] Here, the voltages of the word line WLs, the string selection line SSL, and the bit line in the period (t3 to t5) in which the word line recovery operation occurs are not limited to the waveforms shown in the figure.

[0170] FIG. 25 is a diagram illustrating voltage levels of unselected word lines in a read operation of a nonvolatile memory device according to an embodiment of the present invention.

[0171] As shown in FIGS. 6, 24, and 25, the nonvolatile memory device 100 sequentially performs word line setup (WLS), sensing, dump, and word line recovery (RCY) operations in response to a read command signal (CMD).

[0172] In the word line setup section WLS (T21 to T22), the control circuit 450 controls the voltage generation circuit 500 to set up the selected word line and unselected word lines to their respective target levels. During the word line setup section WLS (T21 to T22), the voltage level of the unselected word lines rises from the level of the internal voltage IVC to the read pass voltage (VPASS) level.

[0173] In the sensing period SENSING (T22 to T23), the control circuit 450 performs a sensing operation on the target memory cell connected to the selected word line and holds the unselected word lines at the read pass voltage (VPASS) level.

[0174] In the dump period DUMP (T23 to T24), the control circuit 450 provides the sensed data latched in the page buffer circuit 410 to the data input / output circuit 420.

[0175] During a word line recovery period RCY (T24 to T27), the control circuit 450 restores the voltage level of the unselected word lines to the internal voltage IVC level for subsequent operations. During a discharge period (T25 to T26) within the word line recovery period RCY, the control circuit 450 activates specific circuits of the nonvolatile memory device 100 to consume the internal voltage IVC connected to the unselected word lines WL_UNSEL within the nonvolatile memory device 100 in order to prevent overshoot of the internal voltage IVC. Here, the discharge period is predetermined. That is, during the discharge period, specific circuits are activated by receiving the internal voltage IVC connected to the unselected word lines WL_UNSEL.

[0176] FIG. 26 is a diagram showing the dump section and the recovery section of FIG.

[0177] 6, 12, 13, 25, and 26, during a dump interval DUMP (T23-T24), the control circuit 450 provides a dump signal DMP to the page buffer circuit 410, and the page buffer circuit 410 outputs sensed data from its internal latch to the data I / O circuit 420. During a discharge interval INT11 from time T25 to time T26 after time T24, the control circuit 450 activates a discharge signal DSCHG. The control circuit 450 generates a toggling ground control signal SOGND and toggling monitor signals (MON_F, MON_M, MON_L) based on the activated discharge signal DSCHG, and provides the toggling ground control signal SOGND and toggling monitor signals (MON_F, MON_M, MON_L) to the page buffer circuit 410.

[0178] During the discharge period INT11 in which the discharge signal DSCHG is activated, the control circuit 450 repeatedly turns on and off the transistors (e.g., inverters (INV11, INV12, INV21, INV22, INV31, INV32, INV41, INV42) in FIG. 12) that use the internal voltage IVC in each of the page buffers included in the page buffer circuit 410, thereby consuming the internal voltage IVC connected to the unselected word lines. The transistors of the inverters (INV11, INV12, INV21, INV22, INV31, INV32, INV41, INV42) are connected to the internal voltage IVC and are turned on and off by the toggling ground control signal SOGND and the toggling monitor signals MON_F, MON_M, MON_L. Thus, the internal voltage IVC is consumed by activating the transistors of the inverters (INV11, INV12, INV21, INV22, INV31, INV32, INV41, INV42) during the discharge period (INT11).

[0179] 12 and 13, the PMOS transistors of the inverters INV11, INV12, INV21, INV22, INV31, INV32, INV41, and INV42 are connected to the internal voltage IVC. Therefore, when the transistors of the page buffer connected to one page are repeatedly turned on and off during the discharge interval INT11, the internal voltage IVC connected to the unselected word lines is consumed, thereby preventing or reducing overshoot of the internal voltage IVC.

[0180] The read pass voltage (VPASS) is applied to the unselected word lines WL_UNSEL until time T24, after which the unselected word lines WL_UNSEL are recovered to the internal voltage IVC level.

[0181] The control circuit 450 determines the number of transistors involved in the discharge operation among the transistors of the page buffer connected to one page. The control circuit 450 can also change the timing and end point of the discharge interval INT11. In one embodiment, the discharge interval INT11 is predetermined by the control circuit 450. In another embodiment, the discharge interval INT11 is determined based on the internal voltage IVC and a reference voltage.

[0182] Since the page buffer circuit 410 operates during the word line setup interval WLS and the sensing interval SENSING to sense and latch data from a selected page of the memory cell array 200, the page buffer circuit 410 not operating during the discharge interval INT11 does not affect the operation of the nonvolatile memory device 100. That is, the page buffer circuit 410 is not involved in the word line recovery operation (RCY) during a read operation.

[0183] FIG. 27 is a diagram showing the dump operation and word line recovery operation of FIG.

[0184] 6, 20, 22, and 27, during a dump period (T23 to T24), the control circuit 450 provides a dump signal DMP to the page buffer circuit 410, and the page buffer circuit 410 outputs sensed data from an internal latch to the data input / output circuit 420. During a discharge period INT11 from time T25 to time T26 after time T24, the control circuit 450 activates the discharge signal DSCHG.

[0185] During the discharge interval INT11 in which the discharge signal DSCHG is activated, the control circuit 450 activates the second activation signal EN2 to a low level and operates the oscillator (OSC) 610 to consume the internal voltage IVC connected to the unselected word lines. For example, the oscillator 610 generates a toggling clock signal CLKH based on the activated discharge signal DSCHG and the second activation signal EN2.

[0186] As described in FIG. 22, the PMOS transistor 621 and the PMOS transistors 631 and 641 of the reference voltage generator 620 of the oscillator 610 are connected to the internal voltage IVC. During the discharge interval INT11, the clock signal CLKH from the oscillator 610 toggles between a high level and a low level repeatedly. In FIG. 20, the high voltage generator 510 consumes the internal voltage IVC by toggling the clock signal CLKH. By consuming the internal voltage IVC connected to the unselected word lines during the interval in which the second activation signal EN2 is activated to a low level, overshoot of the internal voltage IVC can be prevented or reduced.

[0187] The read pass voltage (VPASS) is applied to the unselected word lines WL_UNSEL until time T24, after which the unselected word lines WL_UNSEL are recovered to the internal voltage IVC level.

[0188] Since the oscillator 610 is included in the high voltage generator 510, which operates during the bit line setup period WLS and the sensing period SENSING to generate the program voltage VPGM, the pass voltage VPASS, the high voltage VPPH, and the erase voltage VRES, its operation during the discharge period INT11 does not affect the operation of the nonvolatile memory device 100. That is, the oscillator 610 is not involved in the word line recovery operation (RCY) of the read operation.

[0189] The control circuit 450 can change the activation period of the second activation signal EN2.

[0190] FIG. 28 is a diagram showing the dump operation and word line recovery operation of FIG.

[0191] 6, 19, 21, 25, and 28, during a dump interval DUMP (T23 to T24), the control circuit 450 provides a dump signal DMP to the page buffer circuit 410, and the page buffer circuit 410 outputs sensed data from its internal latch to the data input / output circuit 420. During a discharge interval INT11 from time T25 to time T26 after time T24, the control circuit 450 activates the discharge signal DSCHG.

[0192] During the discharge interval INT11 in which the discharge signal DSCHG is activated, the control circuit 450 activates the first activation signal EN1 to operate the dummy voltage generator 570 and consume the internal voltage IVC connected to the unselected word lines.

[0193] As described in FIG. 21, the PMOS transistor 572 of the dummy voltage generator 570 is connected to the internal voltage IVC, and therefore consumes the internal voltage IVC connected to the unselected word lines during the period in which the first activation signal EN1 is activated, thereby preventing or reducing overshoot of the internal voltage IVC.

[0194] The read pass voltage (VPASS) is applied to the unselected word lines WL_UNSEL until time T24, after which the unselected word lines WL_UNSEL are recovered to the internal voltage IVC level.

[0195] Since the dummy voltage generator 570 generates the dummy voltage VDUM during the word line setup period WLS and the sensing period SENSING, the dummy voltage generator 570 operating during the discharge period INT11 does not affect the operation of the nonvolatile memory device 100. That is, the dummy voltage generator 570 is not involved in the word line recovery operation (RCY) of the read operation.

[0196] The control circuit 450 can change the activation period of the first activation signal EN1.

[0197] FIG. 29 is a diagram illustrating voltage levels of unselected word lines in a read operation of a nonvolatile memory device according to an embodiment of the present invention.

[0198] As shown in FIGS. 6 and 29, the nonvolatile memory device 100 sequentially performs word line setup (WLS), sensing (SENSING), dump (DUMP), and word line recovery (RCY) operations in response to a read command signal (CMD).

[0199] In the word line setup section WLS (T31 to T32), the control circuit 450 controls the voltage generation circuit 500 to set up the selected word line and unselected word lines to their respective target levels. The unselected word lines rise from the level of the internal voltage IVC to the read pass voltage (VPASS) level.

[0200] During the sensing period (T32 to T33), the control circuit 450 performs a sensing operation on the target memory cell connected to the selected word line, and holds the unselected word lines at the read pass voltage (VPASS) level.

[0201] During the dump period (T33 to T34), the control circuit 450 provides the sensed data latched in the page buffer circuit 410 to the data input / output circuit 420.

[0202] During the word line recovery period (T34 to T36), the control circuit 450 recovers the voltage levels of the unselected word lines to the external voltage EVC level for subsequent operations, and then recovers the voltage levels from the external voltage EVC level to the internal voltage IVC level, which is higher than the internal voltage IVC level.

[0203] In the first sub-period (T34 to T35) of the word line recovery period (T34 to T36), the control circuit 450 recovers the voltage level of the unselected word lines from the read pass voltage (VPASS) to the external voltage EVC level, and in the second sub-period (T35 to T36), the control circuit 450 recovers the voltage level of the unselected word lines from the external voltage EVC level to the internal voltage IVC level.

[0204] Since the unselected word lines are recovered to the internal voltage IVC level after being recovered to the external voltage EVC level, overshoot can be reduced or prevented even if the unselected word lines are connected to the internal voltage IVC.

[0205] In a nonvolatile memory device and an operating method thereof according to an embodiment of the present invention, during a read recovery operation, unselected word lines are recovered to an internal voltage level, and the voltage of the unselected word lines connected to the internal voltage is consumed by circuit elements within the nonvolatile memory device that are not related to the recovery operation, thereby reducing or preventing overshoot of the internal voltage that occurs during the recovery operation.

[0206] FIG. 30 is a diagram illustrating a nonvolatile memory device according to an embodiment of the present invention.

[0207] The nonvolatile memory device 100a in Figure 30 has a multi-plane structure. In Figure 30, the nonvolatile memory device 100a is shown as having a two-plane structure including two planes, i.e., a first plane 230 and a second plane 240, but this is for convenience of explanation, and the nonvolatile memory device 100a may have various multi-plane structures, such as a four-plane structure or a six-plane structure, having four or more planes.

[0208] The nonvolatile memory device 100a includes a memory cell array 200a, a first address decoder 300a, a second address decoder 300b, a first page buffer circuit 410a (PBC1), a second page buffer circuit 410b (PBC2), a data input / output circuit 420a, a control circuit 450a, and a voltage generating circuit 500a. The nonvolatile memory device 100a further includes an overshoot detector 430a.

[0209] The memory cell array 200a includes a first plane 230 and a second plane 240, and each of the first plane 230 and the second plane 240 includes a plurality of memory blocks as shown in FIG.

[0210] Each of the memory blocks in the first plane 230 and the second plane 240 is connected to the address decoders 300a and 300b via word lines WLs, at least one string select line SSL, and at least one ground select line GSL. The memory blocks in the first plane 230 are connected to a first page buffer circuit 410a via bit lines BLs, and the memory blocks in the second plane 240 are connected to a second page buffer circuit 410b via bit lines BLs.

[0211] The first page buffer circuit 410a and the second page buffer circuit 410b are connected to the data input / output circuit 420a. The control circuit 450a controls the first address decoder 300a, the second address decoder 300b, the first page buffer circuit 410a, the second page buffer circuit 410b, the data input / output circuit 420a, and the voltage generating circuit 500a based on a control signal CTRL, a command signal CMD, and an address signal ADDR from the memory controller 50.

[0212] The voltage generating circuit 500a generates a word line voltage VWLs based on the external voltage EVC, and provides the word line voltage VWLs to the memory cell array 200a through the first address decoder 300a and the second address decoder 300b.

[0213] The overshoot detector 430a compares the internal voltage IVC connected to the unselected word lines with a reference voltage when recovering the word lines during a read operation of the nonvolatile memory device 100a, and provides an overshoot detection flag ODFC to the control circuit 450a if an overshoot occurs.

[0214] The control circuit 450a controls the recovery operation to recover the unselected word lines to the internal voltage level during a read operation on the target memory cell and to consume the voltage of the unselected word lines connected to the internal voltage within the nonvolatile memory device 100a.

[0215] Each of the first address decoder 300a and the second address decoder 300b employs the address decoder 300 in FIG.

[0216] Therefore, each of the first address decoder 300a and the second address decoder 300b included in the nonvolatile memory device 100a can accommodate various changes in word line load values ​​in the plane independent read (PIR) and plane independent core (PIC) schemes.

[0217] FIG. 31 is a diagram showing the first plane and the second plane in the nonvolatile memory device of FIG.

[0218] As shown in FIG. 31 , one of the memory blocks included in the first plane 230 includes a plurality of cell strings (CS11, CS12, CS21, CS22). Each plane (230, 240) includes a plurality of memory blocks, and one of the memory blocks includes a plurality of string selection lines (SSL1a, SSL1b) for selecting at least one of the plurality of cell strings (CS11, CS12, CS21, CS22). For example, when a selection voltage is applied to the first string selection line SSL1a of the first plane 230, the first and second cell strings (CS11, CS12) are selected. Similarly, when a selection voltage is applied to the second string selection line SSL1b of the first plane 230, the third and fourth cell strings (CS21, CS22) are selected.

[0219] The first and second planes (230, 240) have substantially the same physical structure. For example, like the first plane 230, the second plane 240 includes a plurality of memory blocks and a plurality of cell strings formed on one plane. Similarly, the second plane 240 includes a plurality of string selection lines (SSL2a, SSL2b) for selecting at least one cell string from the plurality of cell strings.

[0220] The planes (230, 240) do not share word lines, bit lines, string select lines, ground select lines, or common source lines, and each plane is assumed to be connected to two bit lines and seven word lines, but this is merely an example and each plane can be connected to more than two bit lines or more than seven or fewer word lines.

[0221] Each cell string (CS11, CS12, CS21, CS22) includes at least one string select transistor, a memory cell, and at least one ground select transistor. For example, in one cell string CS22, one ground select transistor GST, multiple memory cells (MC1 to MC7), and one string select transistor SST are sequentially formed vertically on the substrate. The remaining cell strings have the same configuration as cell string CS22.

[0222] The string selection lines connected to each of the planes (230, 240) are exclusively connected to the corresponding one of the planes. For example, each of the string selection lines (SSL1a, SSL1b) is connected only to the first plane 230. Similarly, each of the string selection lines (SSL2a, SSL2b) is connected only to the second plane 240. Therefore, one string selection line selects only cell strings included in one plane. Furthermore, by independently controlling each string selection line, cell strings are independently selected for each plane.

[0223] For example, the cell strings CS11 and CS12 are independently selected by independently applying a select voltage to the first string selection line SSL1a. When the select voltage is applied to the first string selection line SSL1a, the select voltage turns on the string selection transistors of the corresponding cell strings CS11 and CS12. When the string selection transistors are turned on, the memory cells of the cell strings CS11 and CS12 are electrically connected to the bit lines.

[0224] On the other hand, when a non-select voltage is applied to the first string select line SSL1a, the string select transistors of the cell strings CS11 and CS12 are turned off, and the cell strings CS11 and CS12 are not selected. Therefore, the memory cells of the cell strings CS11 and CS12 are electrically isolated from the bit lines.

[0225] According to the above configuration, separate string selection lines are provided for each plane. Such a separate string selection line structure can minimize the impact of a defect in a portion of the string selection line. Furthermore, the separate string selection lines for each plane can independently select cell strings for each plane. That is, the cell strings included in the first plane 230 are selected completely independently of the cell strings included in the second plane 240. This independent selection structure facilitates control of the nonvolatile memory device 100a.

[0226] FIG. 32 is a cross-sectional view illustrating a nonvolatile memory device according to an embodiment of the present invention.

[0227] 32, the nonvolatile memory device 2000 has a C2C (chip to chip) structure. The C2C structure refers to fabricating an upper chip including a cell region CELL on a first wafer, fabricating a lower chip including a peripheral circuit region PERI on a second wafer different from the first wafer, and then connecting the upper and lower chips to each other using a bonding method. For example, the bonding method refers to a method of electrically connecting a bonding metal formed on the top metal layer of the upper chip to a bonding metal formed on the top metal layer of the lower chip to each other. For example, if the bonding metal is made of copper (Cu), the bonding method is Cu-to-Cu bonding, and the bonding metal is made of aluminum (Al) or tungsten (W).

[0228] Each of the peripheral circuit area PERI and the cell area CELL of the nonvolatile memory device 2000 includes an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

[0229] The peripheral circuit region PERI includes a first substrate 2210, an interlayer insulating layer 2215, a plurality of circuit elements (2220a, 2220b, 2220c) formed on the first substrate 2210, first metal layers (2230a, 2230b, 2230c) connected to each of the plurality of circuit elements (2220a, 2220b, 2220c), and second metal layers (2240a, 2240b, 2240c) formed on the first metal layers (2230a, 2230b, 2230c). In one embodiment, the first metal layers (2230a, 2230b, 2230c) are made of tungsten, which has a relatively high electrical resistivity, and the second metal layers (2240a, 2240b, 2240c) are made of copper, which has a relatively low electrical resistivity.

[0230] Although only the first metal layers (2230a, 2230b, 2230c) and the second metal layers (2240a, 2240b, 2240c) are shown and described in this specification, the present invention is not limited thereto, and at least one or more metal layers may be further formed on the second metal layers (2240a, 2240b, 2240c). At least a portion of the one or more metal layers formed on the second metal layers (2240a, 2240b, 2240c) is formed to have a lower electrical resistivity than copper forming the second metal layers (2240a, 2240b, 2240c), and is formed of, for example, aluminum.

[0231] The interlayer insulating layer 2215 is disposed on the first substrate 2210 to cover the plurality of circuit elements (2220a, 2220b, 2220c), the first metal layer (2230a, 2230b, 2230c), and the second metal layer (2240a, 2240b, 2240c), and includes an insulating material such as silicon oxide, silicon nitride, etc.

[0232] Lower bonding metals (2271b, 2272b) are formed on the second metal layer 2240b of the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals (2271b, 2272b) of the peripheral circuit region PERI are electrically connected to the upper bonding metals (2371b, 2372b) of the cell region CELL by bonding, and the lower bonding metals (2271b, 2272b) and the upper bonding metals (2371b, 2372b) are formed of aluminum, copper, tungsten, or the like.

[0233] The cell region CELL provides at least one memory block. The cell region CELL includes a second substrate 2310 and a common source line 2320. A plurality of word lines (2331, 2332, 2333, 2334, 2335, 2336, 2337, 2338, 2330) are stacked on the second substrate 2310 along a direction VD perpendicular to the upper surface of the second substrate 2310. A string select line and a ground select line are arranged above and below the word lines 2330, respectively, and a plurality of word lines 2330 are arranged between the string select line and the ground select line.

[0234] In the bit line bonding region BLBA, the channel structure CH extends in a vertical direction VD relative to the top surface of the second substrate 2310, penetrating the word line 2330, the string select line, and the ground select line. The channel structure CH includes a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer is electrically connected to the first metal layer 2350c and the second metal layer 2360c. For example, the first metal layer 2350c is a bit line contact, and the second metal layer 2360c is a bit line. In this embodiment, the bit line 2360c extends along a second horizontal direction HD2 parallel to the top surface of the second substrate 2310.

[0235] 32, the region where the channel structure CH and the bit line 2360c are disposed is defined as a bit line bonding region BLBA. The bit line 2360c is electrically connected in the bit line bonding region BLBA to a circuit element 2220c that provides a page buffer 2393 in the peripheral circuit region PERI. For example, the bit line 2360c is connected to upper bonding metals 2371c and 2372c in the peripheral circuit region PERI, and the upper bonding metals 2371c and 2372c are connected to lower bonding metals 2271c and 2272c that are connected to the circuit element 2220c of the page buffer 2393.

[0236] In the word line bonding region WLBA, the word lines 2330 extend along a second horizontal direction HD2 that is perpendicular to the first horizontal direction HD1 and parallel to the top surface of the second substrate 310, and are connected to a plurality of cell contact plugs (2341, 2342, 2343, 2344, 2345, 2346, 3347, 3340). The word lines 2330 and the cell contact plugs 2340 are connected to each other through pads that are provided by extending at least portions of the word lines 2330 to different lengths along the first horizontal direction HD1. A first metal layer 2350b and a second metal layer 2360b are sequentially connected to the top of the cell contact plugs 2340 connected to the word lines 2330. The cell contact plug 2340 is connected to the peripheral circuit region PERI through upper bonding metals 2371b and 2372b of the cell region CELL and lower bonding metals 2271b and 2272b of the peripheral circuit region PERI in the word line bonding region WLBA.

[0237] The cell contact plug 2340 is electrically coupled in the peripheral circuit region PERI to a circuit element 2220b that forms an address decoder or row decoder 2394. In one embodiment, the operating voltage of the circuit element 2220b that forms the row decoder 2394 is different from the operating voltage of the circuit element 2220c that forms the page buffer 2393. As an example, the operating voltage of the circuit element 2220c that forms the page buffer 2393 is higher than the operating voltage of the circuit element 2220b that forms the row decoder 2394. The circuit element 2220b that forms the row decoder 2394 includes the pass transistor described above.

[0238] A common source line contact plug 2380 is disposed in the external pad bonding area PA. The common source line contact plug 2380 is made of a conductive material such as metal, metal compound, or polysilicon, and is electrically connected to the common source line 2320. A first metal layer 2350a and a second metal layer 2360a are sequentially stacked on the common source line contact plug 2380. For example, the area where the common source line contact plug 2380, the first metal layer 2350a, and the second metal layer 2360a are disposed is defined as the external pad bonding area PA.

[0239] Meanwhile, input / output pads (2205, 2305) are arranged in the external pad bonding area PA. A lower insulating film 2201 covering the lower surface of the first substrate 2210 is formed under the first substrate 2210, and a first input / output pad 2205 is formed on the lower insulating film 2201. The first input / output pad 2205 is connected to at least one of a plurality of circuit elements (2220a, 2220b, 2220c) arranged in the peripheral circuit area PERI through a first input / output contact plug 2203 and is separated from the first substrate 2210 by the lower insulating film 2201. In addition, a side insulating film is arranged between the first input / output contact plug 2203 and the first substrate 2210, and the side insulating film electrically separates the first input / output contact plug 2203 from the first substrate 2210.

[0240] An upper insulating film 2301 covering the upper surface of the second substrate 2310 is formed on the second substrate 2310, and a second I / O pad 2305 is disposed on the upper insulating film 2301. The second I / O pad 2305 is connected to at least one of a plurality of circuit elements (2220a, 2220b, 2220c) disposed in the peripheral circuit region (PERI) through a second I / O contact plug 2303. In this embodiment, the second I / O pad 2305 is electrically connected to the circuit element 2220a.

[0241] In this embodiment, the second substrate 2310 and the common source line 2320 are not arranged in the region where the second I / O contact plug 2303 is arranged. In addition, the second I / O pad 2305 does not overlap the word line 2380 in the vertical direction VD. The second I / O contact plug 2303 is separated from the second substrate 2310 in a direction parallel to the top surface of the second substrate 2310 and is connected to the second I / O pad 2305 through the interlayer insulating layer 2315 of the cell region CELL.

[0242] In one embodiment, the first I / O pads 2205 and the second I / O pads 2305 are selectively formed. For example, the memory device 2000 may include only the first I / O pads 2205 disposed on the top of the first substrate 2201, or only the second I / O pads 2305 disposed on the top of the second substrate 2301. Alternatively, the memory device 2000 may include both the first I / O pads 2205 and the second I / O pads 2305.

[0243] In each of the external pad bonding area PA and bit line bonding area BLBA included in the cell area CELL and the peripheral circuit area PERI, the metal pattern of the uppermost metal layer exists as a dummy pattern, or the uppermost metal layer is empty.

[0244] In the nonvolatile memory device 2000, a lower metal pattern 2273a having the same shape as the upper metal pattern 2372a in the cell region CELL is formed in the uppermost metal layer of the peripheral circuit region PERI in the external pad bonding region PA, corresponding to the upper metal pattern 2372a formed in the uppermost metal layer of the cell region CELL. The lower metal pattern 2273a formed in the uppermost metal layer of the peripheral circuit region PERI is not connected to another contact in the peripheral circuit region PERI. Similarly, in the external pad bonding region PA, an upper metal pattern 2372a having the same shape as the lower metal pattern 2273a in the peripheral circuit region PERI may be formed in the upper metal layer of the cell region CELL in the external pad bonding region PA, corresponding to the lower metal pattern 2273a formed in the uppermost metal layer of the peripheral circuit region PERI.

[0245] Lower bonding metals 2271b and 2272b are formed on the second metal layer 2240b of the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 2271b and 2272b of the peripheral circuit region PERI are electrically connected to the upper bonding metals 2371b and 2372b of the cell region CELL by bonding.

[0246] In the bit line bonding region BLBA, an upper metal pattern 2392 having the same shape as the lower metal pattern 2252 in the peripheral circuit region PERI is formed in the uppermost metal layer of the cell region CELL in correspondence with the lower metal pattern 2252 formed in the uppermost metal layer of the peripheral circuit region PERI. No contact is formed on the upper metal pattern 2392 formed in the uppermost metal layer of the cell region CELL.

[0247] The above-mentioned word line voltage is provided to at least one memory block in the cell area CELL through lower bonding metals (2271b, 2272b) in the peripheral circuit area PER1 and upper bonding metals (2371b, 2372b) in the cell area CELL. The control circuit internally consumes the internal voltage coupled to the unselected word lines and restores the voltage levels of the unselected word lines to the internal voltage level.

[0248] FIG. 33 is a block diagram showing an electronic system including a semiconductor device according to one embodiment of the present invention.

[0249] 33, an electronic system 3000 includes a semiconductor device 3100 and a controller 3200 electrically coupled to the semiconductor device 3100. The electronic system 3000 is a storage device including one or more semiconductor devices 3100, or an electronic device including a storage device. For example, the electronic system 3000 is a solid state drive (SSD) device, a universal serial bus (USB), a computer system, a medical device, or a communication device including one or more semiconductor devices 3100.

[0250] The semiconductor device 3100 is a nonvolatile memory device, such as the nonvolatile memory device described with reference to FIGS. 6 to 22. The semiconductor device 3100 includes a first structure 3100F and a second structure 3100S on the first structure 3100F. The first structure 3100F is a peripheral circuit structure including a decoder circuit 3110, a page buffer circuit (PBC) 3120, and a logic circuit 3130. The second structure 3100S is a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0251] In the second structure 3100S, each memory cell string CSTR includes lower transistors (LT1, LT2) adjacent to a common source line CSL, upper transistors (UT1, UT2) adjacent to a bit line BL, and multiple memory cell transistors MCT arranged between the lower transistors (LT1, LT2) and the upper transistors (UT1, UT2). The number of lower transistors (LT1, LT2) and the number of upper transistors (UT1, UT2) vary depending on the embodiment.

[0252] In this embodiment, the upper transistors (UT1, UT2) include string selection transistors, and the lower transistors (LT1, LT2) include ground selection transistors. The lower gate lines (LL1, LL2) are the gate electrodes of the lower transistors (LT1, LT2), respectively. The word line WL is the gate electrode of the memory cell transistor MCT, and the upper gate lines (UL1, UL2) are the gate electrodes of the upper transistors (UT1, UT2), respectively.

[0253] In this embodiment, the lower transistors (LT1, LT2) include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors (UT1, UT2) include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT1 is used in an erase operation that erases data stored in the memory cell transistor MCT using a gate-induced drain leakage (GIDL) phenomenon.

[0254] The common source line CSL, the first and second lower gate lines (LL1, LL2), the word lines WL, and the first and second upper gate lines (UL1, UL2) are electrically connected to the decoder circuit 3110 through first connecting lines 3115 extending from within the first structure 3100F to the second structure 3100S. The bit lines BL are electrically connected to the page buffer circuit 3120 through second connecting lines 3125 extending from within the first structure 3100F to the second structure 3100S.

[0255] In the first structure 3100F, the decoder circuit 1110 and the page buffer circuit 3120 perform control operations on at least one selected memory cell transistor of the plurality of memory cell transistors MCT. The decoder circuit 3110 and the page buffer circuit 3120 are controlled by a logic circuit 3130. The semiconductor device 3000 communicates with the controller 3200 through an input / output pad 3101 electrically connected to the logic circuit 3130. The input / output pad 3101 is electrically connected to the logic circuit 3130 through an input / output connecting wiring 3135 extending from within the first structure 3100F to the second structure 3100S.

[0256] The controller 3200 includes a processor 3210, a NAND controller 3220, and a host interface 3230. In one embodiment, the electronic system 3000 includes multiple semiconductor devices 3100, where the controller 3200 controls the multiple semiconductor devices 3000.

[0257] The processor 3210 controls the overall operation of the electronic system 3000, including the controller 3200. The processor 3210 operates according to predetermined firmware and controls the NAND controller 3220 to access the semiconductor device 3100. The NAND controller 3220 includes a NAND interface 3221 that processes communication with the semiconductor device 3100. Control commands for controlling the semiconductor device 3100, data to be written to the memory cell transistors MCT of the semiconductor device 3100, data to be read from the memory cell transistors MCT of the semiconductor device 3100, etc. are transmitted through the NAND interface 3221. The host interface 3230 provides a communication function between the electronic system 3000 and an external host. When a control command is received from the external host through the host interface 3230, the processor 3210 controls the semiconductor device 3100 in response to the control command.

[0258] Non-volatile memory or storage devices according to embodiments of the present invention may be implemented using various types of packages.

[0259] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical concept of the present invention. [Explanation of symbols]

[0260] 10 Memory System 50 Memory Controller 100, 100a, 2000 Non-volatile memory device 131, 133-137 Transistors 132 Dump Transistor 200, 200a Memory Cell Array (MCA) 210 Peripheral Circuit 230, 240 1st and 2nd planes 300 Address Decoder 300a, 300b First and second address decoders 310 Driver Circuit 320 Block Selection Driver 330 String Select Driver 340 Word Line Driver 350 Ground Select Driver 360 Path Switch Circuit 410 Page buffer circuit 410a, 410b First and second page buffer circuits (PBC1, PBC2) 411, 413, 572, 621, 631, 641 PMOS transistors 412, 414, 623-625, 633, 643 NMOS transistors 420, 420a Data input / output circuit 430, 430a Overshoot detector 431 Voltage Comparator 450, 450a control circuit 460 Command Decoder 470 Address Buffer 480 Control Signal Generator 485 State Signal Generator 500, 500a voltage generation circuit 510 High Voltage Generator 511, 620 Reference Voltage Generator 513 Program voltage detector (VD_VPGM) 514 Program Voltage Pump (PUMP_VPGM) 515 Pass Voltage Detector (VD_VPASS) 516 Pass Voltage Pump (PUMP_VPASS) 517 High voltage detector (VD_VPPH) 518 High Voltage Pump (PUMP_VPPH) 519 Erase Voltage Detector (VD_VERS) 520 Erase Voltage Pump (PUMP_VERS) 525 Voltage Divider 530 Low Voltage Generator 550 Negative Voltage Generator 570 Dummy Voltage Generator 571, 635, 645 operational amplifiers 573 Feedback Circuit 610 Oscillator (OSC) 630, 640 1st and 2nd comparison circuit 650 Latch Circuit 651, 653 1st and 2nd NAND gates 2201, 2301 Lower and upper insulating films 2203 First input / output contact plug 2205, 2305 I / O pads 2210, 2310 First and second boards 2215, 2315 Interlayer insulation layer 2220a, 2220b, 2220c circuit elements 2230a, 2230b, 2230c, 2350a, 2350b, 2350c First metal layer 2240a, 2240b, 2240c, 2360a, 2360b Second metal layer 2252, 2273a Lower metal pattern 2360c bit line (second metal layer) 2271b, 2272b Lower bonding metal 2271c, 2272c, 2371b, 2371c, 2372b, 2372c Upper bonding metal 2303 Second input / output contact plug 2305 2nd I / O pad 2320 common source line 2330, 2331~2338 Word lines 2340~2346, 3340, 3347 Cell Contact Plug 2372a, 2392 upper metal pattern 2380 Common Source Line Contact Plug 2393 page buffers 2394 Line Decoder 3000 Electronic Systems 3100 Semiconductor equipment 3100F, 3100S 1st and 2nd structures 3101 Input / Output Pad 3110 Decoder Circuit 3115, 3125 1st and 2nd connection wiring 3120 Page Buffer Circuit (PBC) 3130 Logic Circuit 3135 Input / output connection wiring 3200 Controller 3210 processor 3220 NAND controller 3221 NAND interface (I / F) 3230 Host Interface (I / F) / RE Read enable signal ADDR Address signal AG Air Gap BD Body BI blocking insulating film BL, BLs, BL1 to BL3 bit lines BL0~BLn 1st to (n+1)th bit lines BLBA Bit Line Bonding Area BLCLAMP Bit line clamp control signal BLK, BLKi, BLK1 to BLKz memory blocks BLKWL Block Word Line BLSETUP Bit line setup signal BLSHF Bit line shutoff signal BLSLT Bit line select signal C_ADDR Column address C1, C2 capacitors CELL Cell area CH Channel structure CL, C-LATCH cache latch CL0~CLn 1st to (n+1st) cache latches CLBLK Bit line connection control signal CLK_VERS Clock for erase voltage CLK_VPASS Clock for pass voltage CLK_VPGM Program voltage clock CLK_VPP High voltage clock CLKH Clock signal CMD Command signal CS1, CS2 1st, 2nd comparison signal CS11, CS12, CS21, CS22 1st to 4th cell strings CSL Common Source Line CSTR Memory Cell String CT charge trapping film CTL1~CTL3 1st~3rd control signals CTLs, CTRL control signals CU Cache Unit D_CMD Decoded command DATA data, program data, read data DI Data Signal DIO_R Read control signal DIO_W Write control signal DLs data lines DMP Dump Signal DSCHG Discharge signal DUMP Dump section E erased state EN1, EN2 1st and 2nd activation signals EVC external voltage FL, F-LATCH Force Latch FN Feedback Node GPT Pass Transistor GS Ground selection signal GSL Ground Select Line GSL1~GSL3 Ground selection lines GST Ground Select Transistor HD1, HD2 1st, 2nd horizontal direction HVU High Voltage Unit I / O Data input / output terminal INT11 Discharge section INV1, INV2 1st and 2nd inverters INV11, INV12, INV21, INV22, INV31, INV32, INV41, INV42 inverters IREF Reference Current IVC Internal Voltage L1, L2 First and second semiconductor layers LL, L-LATCH Lower bit latch LL1, LL2 1st and 2nd gate lower lines LOAD Load signal LS1, LS2 First and second latch signals LT1 Lower transistor (lower erase control transistor) LT2 Lower transistor (ground selection transistor) MC memory cell MC1 to MC8 1st to 8th memory cells ML, M-LATCH High-order bit latch MON_C Cache monitor signal MON_F Force monitor signal MON_L Lower bit monitor signal MON_M Upper bit monitor signal MU Main Unit N11, N12, N21 to N25 nodes ND1, ND2 1st and 2nd nodes nDI Data inversion signal NM1~NM6 1st to 6th transistors NM7 monitor transistor NO output node NS0~NSn 1st to (n+1)th cell (NAND) string NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32, NS33 (Memory) Cell Strings (NAND Strings) ODFG Overshoot detection flag P1~P15 1st to 15th program states PA External Pad Bonding Area PB Page Buffer PBU Page Buffer Unit PBU0 to PBUn 1st to (n+1)th page buffer units PC Precharge circuit PCTL Page buffer control signal PERI Peripheral circuit area PL pillar PM precharge transistor PM' Transistor driven by BLSETUP PT1~PTn pass transistors R_ADDR Row Address R1 Resistor RCY Word line recovery section RDi data input / output line RnB status signal (ready / busy signal) Rf1, Rf2 First and second feedback resistors S_EN Sense enable signal S1~Sn drive wires SCS Switching control signal SEBSING detection section SL, S-LATCH Sense latch SO Sense Node SO_PASS Pass control signal (sense node connection control signal) SOC Combined Sense Node SOC_D, SOC_U 2nd, 1st terminal SOGND Ground control signal SS String Select Signal SSL String Selection Line SSL1~SSL3 string selection line SSL1a, SSL1b 1st and 2nd string selection lines SSL2a, SSL2b string selection lines SSPT Pass Transistor SST String Select Transistor SUB board TI tunnel insulating film TR, TR': First and second pass transistors (sense node connected transistors) TR_hv Bit line select transistor tRC Command wait time UL1, UL2 1st and 2nd gate upper lines UT1 Upper transistor (string select transistor) UT2 upper transistor (upper erase control transistor) VCC power supply voltage VD vertical direction VDRV drive voltage VDUM dummy voltage VERS Erase voltage VFB Feedback voltage VNEG Negative voltage VPASS Pass voltage VPGM Program voltage VPPH High Voltage VPPH_L High voltage with a level lower than VPPH VPV verification voltage Vr1 to Vr15 1st to 15th read voltages VRD read voltage VREF_OVS Reference voltage for overshoot detection VREF1, VREF2, VREFH reference voltage VSS Ground voltage Vth threshold voltage VWLs Word Line Voltage WL, WLs, WL0 to WLm word lines WL_UNSEL Unselected word line WL-SEL Selected word line WL1~WL8 1st to 8th word lines WLBA Word Line Bonding Area WLS Word line setup section

Claims

1. 1. A method for operating a nonvolatile memory device including at least one memory block including a plurality of cell strings, each of which includes a string selection transistor, a plurality of memory cells, and a ground selection transistor arranged in series in a vertical direction between a bit line and a common source line, comprising: setting up a plurality of word lines connected to the plurality of memory cells to their respective target levels during a word line setup period; performing a sensing operation by applying a read voltage to a selected word line connected to a target memory cell of the plurality of memory cells among the word lines and applying a read pass voltage to unselected word lines among the plurality of word lines during a sensing period; performing a word line recovery operation in a word line recovery period to recover the voltage level of the read pass voltage applied to the unselected word lines to the level of an internal voltage; and activating a specific circuit of the nonvolatile memory device during a discharge period of the word line recovery period to consume the internal voltage connected to the unselected word lines, The method for operating a nonvolatile memory device, wherein the specific circuit is connected to the internal voltage and is not involved in the word line recovery operation.

2. the step of consuming the internal voltage includes the step of repeatedly turning on and off a transistor of the specific circuit during the discharge period; performing the sensing operation includes sensing data of the target memory cell by a page buffer selected from a plurality of page buffers of a page buffer circuit of the nonvolatile memory device; 2. The method of claim 1, wherein the specific circuit comprises a plurality of page buffers connected to the at least one memory block via a plurality of bit lines.

3. the step of consuming the internal voltage includes the step of generating a clock signal that toggles based on the internal voltage from the specific circuit during the discharge period; performing the sensing operation includes generating a word line voltage including the read voltage and the read pass voltage from a voltage generating circuit of the nonvolatile memory device; 2. The method of claim 1, wherein the specific circuit comprises an oscillator included in the voltage generating circuit to generate the toggling clock signal.

4. the step of consuming the internal voltage includes generating a dummy voltage based on the internal voltage from the specific circuit during the discharge period; performing the sensing operation includes generating word line voltages including the read voltage, the read pass voltage, and the dummy voltage from a voltage generating circuit of the nonvolatile memory device; 2. The method of claim 1, wherein the specific circuit comprises a dummy voltage generator included in the voltage generating circuit to generate the dummy voltage.

5. 2. The method of claim 1, wherein the discharge interval is determined based on a comparison between the internal voltage and a reference voltage.

6. 2. The method of claim 1, wherein the discharge interval is predetermined by a control circuit that controls the operation of the nonvolatile memory device.

7. 2. The method of claim 1, wherein the start and end points of the discharge interval are variable.

8. 1. A non-volatile memory device, comprising: a memory cell array including at least one memory block including a plurality of cell strings, each of which includes a string selection transistor, a plurality of memory cells, and a ground selection transistor arranged in series in a vertical direction between a bit line and a common source line; a control circuit for setting up a plurality of word lines connected to the plurality of memory cells to respective target levels in a word line setup period, applying a read voltage to a selected word line connected to a target memory cell of the plurality of memory cells among the plurality of word lines and applying a read pass voltage to unselected word lines among the word lines to perform a sensing operation in a sense period, performing a word line recovery operation in a word line recovery period to restore a voltage level of the read pass voltage applied to the unselected word lines to a level of an internal voltage, and activating a specific circuit of the nonvolatile memory device in a discharge period of the word line recovery period to consume the internal voltage connected to the unselected word lines, The nonvolatile memory device, wherein the specific circuit is connected to the internal voltage and is not involved in the word line recovery operation.

9. a voltage generating circuit that generates word line voltages including the read voltage and the read pass voltage based on a control signal; an address decoder that provides the word line voltage to the at least one memory block based on a row address; 10. The nonvolatile memory device of claim 8, further comprising: a page buffer circuit connected to the memory cell array via a plurality of bit lines, and latching data sensed in the sensing operation.

10. the specific circuit includes a plurality of page buffers included in the page buffer circuit; 10. The nonvolatile memory device of claim 9, wherein the control circuit consumes the internal voltage by repeatedly turning on and off transistors that use the internal voltage in each of the plurality of page buffers during the discharge period.

11. 11. The nonvolatile memory device of claim 10, wherein a transistor using the internal voltage in each of the plurality of page buffers activates a transistor connected to a sense node and a latch of each of the plurality of page buffers.

12. the specific circuit includes an oscillator included in the voltage generating circuit, 10. The nonvolatile memory device of claim 9, wherein the control circuit controls the voltage generating circuit to generate a clock signal that toggles based on the internal voltage from the oscillator during the discharge period.

13. 13. The nonvolatile memory device of claim 12, wherein the control circuit activates the oscillator during the discharge period to consume the internal voltage.

14. the specific circuit includes a dummy voltage generator included in the voltage generating circuit, the control circuit controls the dummy voltage generator to generate a dummy voltage based on the internal voltage during the discharge period; 10. The nonvolatile memory device of claim 9, wherein the control circuit consumes the internal voltage by activating the dummy voltage generator during the discharge period.

15. an overshoot detector that compares the internal voltage with a reference voltage and generates an overshoot detection flag based on a result of the comparison; 10. The nonvolatile memory device of claim 9, wherein the control circuit sets the discharge interval based on the overshoot detection flag.

16. further comprising a data input / output circuit connected to the page buffer circuit; The control circuit dumps the sensed data latched in the page buffer circuit to the data input / output circuit during a dump period; 10. The nonvolatile memory device of claim 9, wherein the control circuit sets a state signal from a busy state to a ready state before the end of the word line recovery period and after the data input / output circuit stores the sensed data.

17. 17. The nonvolatile memory device of claim 16, wherein the control circuit receives a command from an external device after a reference time has elapsed since the state signal transitioned to the ready state.

18. the memory cell array is disposed on a first semiconductor layer; the control circuit, the voltage generating circuit, the address decoder, and the page buffer circuit are disposed on a second semiconductor layer; The nonvolatile memory device of claim 9 , wherein the first semiconductor layer and the second semiconductor layer are arranged in a vertical direction.

19. a memory cell array including at least one memory block including a plurality of cell strings, each of which includes a string selection transistor, a plurality of memory cells, and a ground selection transistor arranged in series in a vertical direction between a bit line and a common source line; a control circuit that sets up a plurality of word lines connected to the plurality of memory cells to respective target levels during a word line setup period, applies a read voltage to a selected word line connected to a target memory cell of the plurality of memory cells among the plurality of word lines and applies a read pass voltage to unselected word lines among the word lines to perform a sensing operation during a word line recovery period, and performs a word line recovery operation that restores the voltage levels of the unselected word lines to the level of an external voltage provided from an external device.

20. a voltage generating circuit that generates a word line voltage including the read voltage and the read pass voltage, and an internal voltage using the external voltage based on a control signal; an address decoder that provides the word line voltage to the at least one memory block based on a row address; a page buffer circuit connected to the memory cell array via a plurality of bit lines and configured to latch data sensed during the sensing operation; a data input / output circuit coupled to the page buffer circuit, The control circuit dumps the sensed data latched in the page buffer circuit to the data input / output circuit during a dump period; 20. The nonvolatile memory device of claim 19, wherein the control circuit sets a status signal from a busy state to a ready state before the word line recovery period ends and after the data input / output circuit stores the sensed data.

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