Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device capable of suppressing a decrease in a threshold voltage, and the manufacturing method thereof.SOLUTION: A semiconductor device comprises: a first electrode; a first semiconductor layer of a first conductivity type connected to the first electrode and containing silicon and carbon; a second semiconductor layer of a second conductivity type arranged on a part of the first semiconductor layer and containing silicon and carbon; a third semiconductor layer of the first conductivity type arranged on a part of the second semiconductor layer, facing the first semiconductor layer via the second semiconductor layer, and containing silicon and carbon, a side surface facing the first semiconductor layer being dislocated so as to approach the first semiconductor layer as it courses upward; a second electrode layer connected to the third semiconductor layer; and a third electrode arranged in a region right above a portion between the first semiconductor layer and the third semiconductor layer at least in the second semiconductor layer facing the portion via a first insulation film.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] In order to improve the balance between the on-resistance and breakdown voltage of semiconductor devices, semiconductor devices using silicon carbide as the semiconductor material have been developed. In such semiconductor devices, it is preferable to shorten the channel length in order to further reduce the on-resistance, but shortening the channel length reduces the threshold voltage, making operation unstable. fixed This may occur. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-036210 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiments is to provide a semiconductor device capable of suppressing a decrease in threshold voltage and a method for manufacturing the same. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor layer of a first conductivity type connected to the first electrode, containing silicon and carbon, a second semiconductor layer of a second conductivity type arranged on a portion of the first semiconductor layer, containing silicon and carbon, a third semiconductor layer of the first conductivity type arranged on a portion of the second semiconductor layer, facing the first semiconductor layer via the second semiconductor layer, the side surface facing the first semiconductor layer being displaced upward so as to approach the first semiconductor layer, and containing silicon and carbon, a second electrode connected to the third semiconductor layer, and a third electrode arranged in a region directly above at least a portion of the second semiconductor layer between the first semiconductor layer and the third semiconductor layer, facing the portion via a first insulating film.

[0006] a step of forming a spacer film covering the mask member on the first semiconductor layer and the second semiconductor layer; a step of forming a third semiconductor layer of the first conductivity type on a portion of an upper part of the second semiconductor layer by injecting a second impurity into the second semiconductor layer through the spacer film using the mask member as a mask; a step of removing the spacer film and the mask member; a step of forming a first insulating film on at least a portion of the second semiconductor layer between the first semiconductor layer and the third semiconductor layer; and a step of forming a first electrode connected to the first semiconductor layer, a second electrode connected to the third semiconductor layer, and a third electrode disposed on the first insulating film. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line AA' shown in FIG. [Figure 3] FIG. 3 is a partially enlarged cross-sectional view showing region B in FIG. [Figure 4] 4(a) to 4(c) are cross-sectional views illustrating the steps of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] 5(a) to 5(c) are cross-sectional views illustrating the steps of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 6(a) and 6(b) are cross-sectional views showing the steps of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 7] 7A and 7B are cross-sectional views showing steps in a method for manufacturing a semiconductor device according to a comparative example. [Figure 8] FIG. 8 is a partially enlarged cross-sectional view showing a semiconductor device according to a comparative example. [Figure 9] FIG. 9(a) is a diagram showing the test method of the first test example, and FIGS. 9(b) to 9(d) are diagrams showing the results of the first test example. [Figure 10] 10(a) and 10(b) are diagrams showing the results of the second test example. DETAILED DESCRIPTION OF THE INVENTION

[0008] First Embodiment FIG. 1 is a plan view showing a semiconductor device according to this embodiment. FIG. 2 is a cross-sectional view taken along line AA' shown in FIG. FIG. 3 is a partially enlarged cross-sectional view showing region B in FIG. Note that each figure is a schematic diagram, and has been simplified and emphasized as appropriate. Furthermore, the shapes and dimensional ratios of each component element may not be strictly consistent between figures. The same applies to other figures described below.

[0009] 1 and 2, the semiconductor device 1 according to this embodiment includes a drain electrode 11, a semiconductor portion 20, a source electrode 12, a gate electrode 13, a gate insulating film 31, and an inter-electrode insulating film 32. The semiconductor portion 20 is disposed between the drain electrode 11 and the source electrode 12. The drain electrode 11 is disposed over the entire or substantially the entire lower surface of the semiconductor portion 20. The source electrode 12 is disposed over substantially the entire upper surface of the semiconductor portion 20, excluding a gate pad (not shown). In FIG. 1, the source electrode 12, the gate insulating film 31, and the inter-electrode insulating film 32 are not shown, and the gate electrode 13 is indicated by a two-dot chain line. The semiconductor device 1 is a vertical MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).

[0010] For convenience of explanation, this specification employs an XYZ Cartesian coordinate system. The arrangement direction of the drain electrodes 11 and source electrodes 12 is defined as the "Z direction," the channel length direction of the MOSFET configured in the semiconductor device 1 is defined as the "X direction," and the channel width direction is defined as the "Y direction." In addition, within the Z direction, the direction from the drain electrodes 11 toward the source electrodes 12 is also referred to as "up," and the opposite direction is also referred to as "down," but these expressions are also for convenience and are unrelated to the direction of gravity.

[0011] The semiconductor portion 20 is made of single-crystal silicon carbide (SiC), and the conductivity type of each portion is set by locally containing impurities. + n-type drain layer 21 - a p-type drift layer 22, a p-type base layer 23, and a p-type + contact layer 24 and n + A source layer 25 of the type is provided. + Type" is "n - "p-type" means that the carrier concentration is higher than "p-type" - The "carrier concentration" refers to the effective concentration of impurities that function as donors or acceptors.

[0012] The drain layer 21 is in contact with and connected to the drain electrode 11. In this specification, "connection" means electrical connection. The drift layer 22 is disposed on the drain layer 21 and in contact with the drain layer 21. The base layer 23 is disposed on a portion of the drift layer 22 and in contact with the drift layer 22. The remaining portion 22a of the drift layer 22, i.e., the top surface of the portion 22a on which the base layer 23 is not disposed, forms part of the top surface 20a of the semiconductor portion 20.

[0013] The contact layer 24 is disposed on a portion of the base layer 23 and is in contact with the base layer 23. The source layer 25 is disposed on another portion of the base layer 23 and is in contact with the base layer 23. The contact layer 24 and the source layer 25 may be in contact with each other. The contact layer 24 and the source layer 25 are separated from the drift layer 22 via the base layer 23. At the top surface 20a of the semiconductor portion 20, the source layer 25 faces the drift layer 22 via the base layer 23. The remaining portion 23a of the base layer 23, i.e., the top surface of the portion on which the contact layer 24 or the source layer 25 is not disposed, constitutes part of the top surface 20a of the semiconductor portion 20.

[0014] In the semiconductor device 1, for example, a plurality of base layers 23 are provided on the drift layer 22 and are arranged at a distance from each other along the X direction. Each base layer 23 extends in the Y direction. Furthermore, a contact layer 24 and a source layer 25 are provided on each base layer 23. For example, each base layer 23 includes one contact layer 24 and two source layers 25 sandwiching the contact layer 24. The contact layer 24 and the source layer 25 extend in the Y direction. However, the positional relationship between the contact layer 24 and the source layer 25 in the XY plane is not limited to this example.

[0015] The gate insulating film 31 is disposed on the upper surface 20a of the semiconductor portion 20. The gate insulating film 31 is made of, for example, silicon oxide (SiO). The gate insulating film 31 is in contact with the upper surface of the portion 22a of the drift layer 22, the upper surface of the portion 23a of the base layer 23, and the upper surface of the portion 25a of the source layer 25 that is on the portion 23a side of the base layer 23.

[0016] The gate electrode 13 is disposed on the gate insulating film 31 and is in contact with the gate insulating film 31. The gate electrode 13 is disposed at least in a region directly above a portion 23a of the base layer 23 between the drift layer 22 and the source layer 25, and faces the portion 23a via the gate insulating film 31. For example, the gate electrode 13 is disposed across a region directly above the portion 22a of the drift layer 22 located between two adjacent base layers 23, a region directly above the portion 23a between the portion 22a of these two base layers 23 and the source layer 25, and a region directly above the portion 25a of the source layer 25 on the portion 23a side of the base layer 23, and faces these portions via the gate insulating film 31. The gate electrode 13 extends in the Y direction and is connected to a gate pad (not shown).

[0017] The inter-electrode insulating film 32 is disposed on a portion of the semiconductor portion 20 and on the entire gate insulating film 31, and covers the gate electrode 13. The inter-electrode insulating film 32 is made of, for example, silicon oxide. The source electrode 12 is disposed on the semiconductor portion 20 and covers the inter-electrode insulating film 32. Therefore, the source electrode 12 covers the gate electrode 13 via the inter-electrode insulating film 32. As a result, the source electrode 12 is insulated from the gate electrode 13 by the inter-electrode insulating film 32. The source electrode 12 is connected to the contact layer 24 and the source layer 25 on the upper surface 20a of the semiconductor portion 20.

[0018] 3, a side surface 25b of the source layer 25 on the X-direction side faces a portion 22a of the drift layer 22 via a portion 23a of the base layer 23. The shape of the side surface 25b in the XZ cross section is a shape that follows an imaginary arc 99. A center 99c of the arc 99 is located above the source layer 25, for example, within the gate electrode 13. Therefore, the side surface 25b is displaced upward so as to approach the portion 22a of the drift layer 22. That is, in a certain XZ cross section, an upper edge 25c of the side surface 25b is closest to the portion 22a on the side surface 25b, and a lower edge 25d of the side surface 25b is farthest from the portion 22a on the side surface 25b.

[0019] Furthermore, the distance D1 in the X direction between the upper edge 25c and the lower edge 25d when viewed from above, i.e., in the Z direction, is preferably greater than the distance D2 in the Z direction between the upper edge 25c and the lower edge 25d when viewed from the side, i.e., in the Y direction. That is, it is preferable that D1 > D2. The distance D2 is the thickness of the source layer 25. The distance D3 shown in FIG. 3 is the channel length of the MOSFET.

[0020] Next, a method for manufacturing the semiconductor device according to this embodiment will be described. 4(a) to 5(c) are cross-sectional views showing the steps of the method for manufacturing a semiconductor device according to this embodiment.

[0021] First, as shown in Fig. 4(a), a semiconductor substrate 50 is prepared. The semiconductor substrate 50 is, for example, + n on silicon carbide wafers - 4(a), the base layer 23, the contact layer 24, and the source layer 25 are not yet formed.

[0022] 4(b), a mask member 51 is formed on the semiconductor substrate 50. The mask member 51 is formed of, for example, silicon oxide. Next, using the mask member 51 as a mask, impurities 52 that will become acceptors are ion-implanted into the upper layer portion of the semiconductor substrate 50, i.e., the portion corresponding to the drift layer 22. As a result, a p-type base layer 23 is formed in part of the upper portion of the drift layer 22.

[0023] 4(c), a spacer film 53 is formed on the semiconductor substrate 50 to cover the mask member 51. The spacer film 53 is made of, for example, silicon oxide, silicon nitride (SiN), or silicon (Si).

[0024] 5(a), using the mask member 51 as a mask, impurities 54 that will serve as donors are ion-implanted into the base layer 23 through the spacer film 53. At this time, the acceleration voltage for the ion implantation of the impurities 54 is set to a voltage that causes the impurities 54 ion-implanted from above to scatter within the spacer film 53 and reach the upper part of the base layer 23.

[0025] As a result, as shown in FIG. 5(b), n + A source layer 25 of the type is formed. The distribution of the ion-implanted impurities 54 spreads spherically around a center 99c located within the spacer film 53. Therefore, the shape of the portion of the semiconductor substrate 50 where the impurities 54 are distributed, i.e., the shape of the source layer 25, is a shape of numerous spheres continuously distributed along the XY plane. Therefore, the shape of the source layer 25 spreads along the XY plane and becomes a substantially flat plate with a constant thickness in the Z direction. The top surface of the source layer 25 contacts the spacer film 53, and the side surface 25b of the source layer 25 has a shape that conforms to a part of a cylinder, and the shape of the side surface 25b in a cross section parallel to the Z direction is a shape that conforms to an imaginary arc 99 centered at the center 99c.

[0026] 5(c), the spacer film 53 and the mask member 51 are removed, thereby exposing the upper surface of the semiconductor substrate 50.

[0027] 2, a mask member (not shown) is formed, and impurities to be acceptors are ion-implanted using the mask member as a mask. As a result, p + A mold contact layer 24 is formed. Next, the mask member is removed. Next, an activation heat treatment is performed to activate the impurities implanted into the semiconductor substrate 50. Next, the semiconductor substrate 50 is subjected to a thermal oxidation treatment. As a result, a gate insulating film 31 is formed over the entire upper surface of the semiconductor substrate 50. The gate insulating film 31 is formed at least on a portion 23a of the base layer 23 between the drift layer 22 and the source layer 25.

[0028] Next, the gate electrode 13 is formed on the gate insulating film 31. Next, the gate insulating film 31 is etched using the gate electrode 13 as a mask, so that the gate insulating film 31 remains in the region directly below the gate electrode 13 and is removed from other regions. Next, an inter-electrode insulating film 32 is formed on the semiconductor substrate 50 and the gate electrode 13. Next, the inter-electrode insulating film 32 is selectively removed. As a result, a part of the source layer 25 and the contact layer 24 are exposed from the inter-electrode insulating film 32, while the gate electrode 13 remains covered with the inter-electrode insulating film 32.

[0029] Next, a source electrode 12 is formed on the semiconductor substrate 50 and the inter-electrode insulating film 32. The source electrode 12 is insulated from the gate electrode 13 by the inter-electrode insulating film 32, and is in contact with the source layer 25 and the contact layer 24. Furthermore, a drain electrode 11 is formed on the lower surface of the semiconductor substrate 50. The drain electrode 11 is in contact with the lower surface of the semiconductor substrate 50. Next, the structure including the drain electrode 11, semiconductor substrate 50, gate insulating film 31, gate electrode 13, inter-electrode insulating film 32, and source electrode 12 is diced into individual pieces. In this way, a plurality of semiconductor devices 1 are manufactured.

[0030] Next, the effects of this embodiment will be described. As shown in FIG. 3, in the semiconductor device 1 according to this embodiment, the side surface 25b of the source layer 25 is displaced upward so as to approach the portion 22a of the drift layer 22. Therefore, the source layer 25 is not interposed between the portion 23a of the base layer 23 where an inversion layer is formed and the portion 22b (see FIG. 2) of the drift layer 22 located directly below the portion 23a. Therefore, the potential of the drain electrode 11 is easily transmitted to the portion 23a, making it difficult for an inversion layer to form. As a result, the threshold voltage of the MOSFET increases. This shortens the distance D3, which is the channel length, and reduces the on-resistance, while ensuring a predetermined threshold voltage and stabilizing the operation of the semiconductor device 1. For example, when the MOSFET is in the off state, it is possible to prevent the unintended formation of an inversion layer due to noise or the like, which would otherwise cause conduction.

[0031] Furthermore, the above-mentioned effect can be more reliably obtained by making the distance D1 in the X direction between the upper edge 25c and the lower edge 25d of the side surface 25b of the source layer 25 larger than the distance D2 in the Z direction, which is the thickness of the source layer 25. This also ensures the threshold voltage of the semiconductor device 1 and makes the operation more stable.

[0032] <Second embodiment> This embodiment is another method for manufacturing the semiconductor device according to the first embodiment. 6(a) and 6(b) are cross-sectional views showing the steps of the method for manufacturing a semiconductor device according to this embodiment.

[0033] First, the steps shown in FIG. 4(a) to FIG. 4(c) are carried out. 6(a), the spacer film 53 is subjected to anisotropic etching such as RIE (Reactive Ion Etching). At this time, care is taken not to completely remove the spacer film 53 on the upper surface of the semiconductor substrate 50. As a result, the spacer film 53 becomes thin on the upper surface of the semiconductor substrate 50 and the upper surface of the mask member 51. On the other hand, the spacer film 53 does not become very thin on the side surfaces of the mask member 51.

[0034] This allows the thickness t1 of the spacer film 53 in the Z direction on the upper surface of the semiconductor substrate 50 and the thickness t2 of the spacer film 53 in the X direction on the side surface of the mask member 51 to be controlled independently of each other. In this embodiment, the thickness t1 is thinner than the thickness t2. <t2である。

[0035] 6(b), using the mask member 51 as a mask, impurities 54 that serve as donors are ion-implanted into the base layer 23 through the spacer film 53. As a result, n ions are implanted into a portion of the upper part of the base layer 23. + A type source layer 25 is formed. The acceleration voltage for ion implantation of the impurity 54 is set to a voltage such that the impurity 54 ions implanted from above are scattered within the spacer film 53 and reach the top of the base layer 23. Next, the step shown in FIG. 5(c) is carried out. The subsequent steps are the same as those in the first embodiment.

[0036] Next, the effects of this embodiment will be described. 6(a) and 6(b), in this embodiment, the thickness t1 of the spacer film 53 in the Z direction is thinner than in the first embodiment, so the acceleration voltage of the impurities 54 can be lowered to form a source layer 25 with a predetermined thickness. This makes it possible to suppress the spread of the impurities 54 along the XY plane. As a result, the shape of the source layer 25 can be controlled with high precision.

[0037] As described above, according to this embodiment, the shape and the like of the source layer 25 can be controlled by adjusting the thickness t1 of the spacer film 53 in the Z direction. Meanwhile, the channel length (distance D3) can be controlled by adjusting the thickness t2 of the spacer film 53 in the X direction. The thickness t2 of the spacer film 53 can be adjusted by controlling the deposition amount of the spacer film 53 in the step shown in FIG. 4(c). As described above, according to this embodiment, the shape and the like of the source layer 25 and the channel length (distance D3) can be controlled independently of each other. Other configurations, manufacturing methods, and effects of this embodiment are the same as those of the first embodiment.

[0038] <Comparative Example> 7A and 7B are cross-sectional views showing the steps of a method for manufacturing a semiconductor device according to this comparative example. FIG. 8 is a partially enlarged cross-sectional view showing the semiconductor device according to this comparative example. FIG. 8 shows the area corresponding to FIG.

[0039] First, the steps shown in FIG. 4(a) to FIG. 4(c) are carried out. 7(a), the spacer film 53 is anisotropically etched to remove it from the upper surface of the semiconductor substrate 50. At this time, the spacer film 53 is left on the side surfaces of the mask member 51. That is, the thickness t1 shown in FIG. 6(a) is set to 0, and the thickness t2 is set to a value greater than 0.

[0040] 7(b), using the mask member 51 and the spacer film 53 as a mask, impurities 54 that will serve as donors are ion-implanted into the base layer 23. At this time, the impurities 54 are implanted directly into the semiconductor substrate 50 without going through the spacer film 53. As a result, the impurities 54 spread in a spherical shape centered on a center 99c located within the semiconductor substrate 50. As a result, the source layer 25 is formed.

[0041] As shown in FIG. 8, in the semiconductor device 101 according to this comparative example, the center 99c of the imaginary arc 99 is located within the source layer 25, and therefore a portion 25e of the source layer 25 is interposed between a portion 23b of the upper layer of the base layer 23, which is on the source layer 25 side, and a portion 22b of the drift layer 22 (see FIG. 2) located directly below the portion 23b. This makes it difficult for the potential of the drain electrode to be transmitted to the portion 23b, facilitating the formation of an inversion layer. As a result, the threshold voltage of the MOSFET decreases. Therefore, the semiconductor device 101 has a lower threshold voltage than the semiconductor device 1 according to the first embodiment, given the same channel length (distance D3). A lower threshold voltage may result in unstable operation.

[0042] In order to ensure a sufficient threshold voltage in semiconductor device 101, the channel length (distance D3) can be increased, but this increases the on-resistance. Alternatively, the semiconductor substrate may be made of silicon (Si) instead of silicon carbide (SiC), and impurities shallowly implanted near the top surface of the semiconductor substrate may be thermally diffused to form a source layer having a shape similar to source layer 25 shown in FIG. 3. However, in this case, the band gap of silicon is narrower than that of silicon carbide, and the balance between the on-resistance and the breakdown voltage deteriorates.

[0043] <First test example> FIG. 9(a) is a diagram showing the test method of this test example, and FIGS. 9(b) to 9(d) are diagrams showing the results of this test example. 9(b) to 9(d) are diagrams tracing the simulation results.

[0044] 9(a), in this test example, three types of samples were assumed, each having a spacer film 53 made of polysilicon formed on a semiconductor substrate 50 made of silicon carbide. The thickness of the spacer film 53 was varied between the samples. Then, for these samples, a simulation was performed in which nitrogen as an impurity was ion-implanted into the semiconductor substrate 50 to simulate the behavior of the nitrogen. The acceleration voltage for the ion implantation was adjusted for each sample so that the depth and concentration of nitrogen in the semiconductor substrate 50 were approximately the same between the samples.

[0045] 9(b), the thickness of the spacer film 53 was set to 200 nm in the sample 201. As a result, nitrogen was mainly scattered within the spacer film 53, and the portion in the semiconductor substrate 50 in which nitrogen was distributed had a shape similar to the bottom of a sphere whose center was located within the spacer film 53, with a spreading width of approximately 300 nm.

[0046] 9(c), the thickness of the spacer film 53 was set to 50 nm in the sample 202. As a result, nitrogen was scattered in the spacer film 53 and the semiconductor substrate 50, and the portion in the semiconductor substrate 50 in which nitrogen was distributed became spherical with its center located within the semiconductor substrate 50, and the spreading width was approximately 160 nm.

[0047] 9(d), in sample 203, the thickness of the spacer film 53 was set to 0 nm. In other words, the spacer film 53 was not provided. As a result, nitrogen was scattered within the semiconductor substrate 50, and the portion in which nitrogen was distributed within the semiconductor substrate 50 had a shape close to a sphere with its center located within the semiconductor substrate 50, and the spreading width was approximately 100 nm.

[0048] <Second test example> 10(a) and 10(b) are diagrams showing the results of this test example. In this test example, the manufacturing methods of the semiconductor devices according to the first embodiment and the comparative example were simulated, and the threshold voltages of the respective devices were calculated. In FIGS. 10(a) and 10(b), the darker the color, the higher the donor concentration. FIGS. 10(a) and 10(b) are traces of the simulation results of the impurity concentration distribution. Due to tracing limitations, not all of the simulation results can be shown. However, based on the original simulation results, the interface between the base layer 23 and the source layer 25 is distinguishable, and therefore, the interface is shown in FIGS. 10(a) and 10(b).

[0049] Sample 301 shown in FIG. 10(a) is a test example of the first embodiment. In sample 301, a spacer film 53 was deposited to a thickness of 200 nm, and no etch-back was performed on the spacer film 53. Therefore, the thickness t1 of the spacer film 53 was 200 nm. Then, impurities 54 were ion-implanted by selecting an acceleration voltage so as to form a source layer 25 with a predetermined thickness and impurity concentration. As a result, as shown in FIG. 10(a), the shape of the side surface 25b of the source layer 25 in sample 301 was a shape that followed a circular arc 99 with a center 99c located above the semiconductor portion 20. The threshold voltage Th of sample 301 was 4.6 V.

[0050] Sample 302 shown in FIG. 10(b) is a comparative test example. In sample 302, a spacer film 53 was deposited to a thickness of 80 nm and etched back by 80 nm. That is, the spacer film 53 was not left, and the thickness t1 was set to 0 nm. Then, impurities 54 were ion-implanted by selecting an acceleration voltage so as to form a source layer 25 with a predetermined thickness and impurity concentration. As a result, as shown in FIG. 10(b), the shape of the side surface 25b of the source layer 25 in sample 302 was a shape that followed an arc 99 whose center 99c was located within the semiconductor portion 20. The threshold voltage Th of sample 302 was 4.0 V.

[0051] As described above, the threshold voltage Th (4.6 V) of the sample 301 according to the first embodiment was higher than the threshold voltage Th (4.0 V) of the sample 302 according to the comparative example.

[0052] According to the embodiment described above, it is possible to realize a semiconductor device and a manufacturing method thereof that can suppress a decrease in threshold voltage even when the channel length is shortened.

[0053] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

[0054] The present invention includes the following aspects.

[0055] (Appendix 1) A first electrode; a first semiconductor layer of a first conductivity type, the first semiconductor layer including silicon and carbon, and the first electrode; a second semiconductor layer of a second conductivity type, the second semiconductor layer including silicon and carbon and disposed on a portion of the first semiconductor layer; a third semiconductor layer of the first conductivity type, which is disposed on a portion of the second semiconductor layer, faces the first semiconductor layer via the second semiconductor layer, and whose side surface facing the first semiconductor layer is displaced upward so as to approach the first semiconductor layer, and which contains silicon and carbon; a second electrode connected to the third semiconductor layer; a third electrode disposed directly above at least a portion of the second semiconductor layer between the first semiconductor layer and the third semiconductor layer, and facing the portion via a first insulating film; A semiconductor device comprising:

[0056] (Appendix 2) 2. The semiconductor device according to claim 1, wherein the cross-sectional shape of the side surface of the third semiconductor layer is a shape that follows an imaginary arc having a center located above the third semiconductor layer.

[0057] (Appendix 3) 3. The semiconductor device according to claim 1, wherein the distance between the upper edge and the lower edge of the side surface when viewed from above is greater than the thickness of the third semiconductor layer when viewed from the side.

[0058] (Appendix 4) The semiconductor device according to any one of appendices 1 to 3, wherein the third electrode is arranged on a portion of the first semiconductor layer above which the second semiconductor layer is not arranged, and on a portion of the third semiconductor layer on the second semiconductor layer side, via the first insulating film.

[0059] (Appendix 5) the second electrode is in contact with the third semiconductor layer, 5. The semiconductor device according to claim 1, wherein the second electrode covers the third electrode via a second insulating film.

[0060] (Appendix 6) 6. The semiconductor device according to claim 1, wherein the first semiconductor layer is disposed on the first electrode and is in contact with the first electrode.

[0061] (Appendix 7) forming a mask member on a first semiconductor layer of a first conductivity type containing silicon and carbon; forming a second semiconductor layer of a second conductivity type on a portion of an upper part of the first semiconductor layer by implanting a first impurity into the first semiconductor layer using the mask member as a mask; forming a spacer film on the first semiconductor layer and the second semiconductor layer to cover the mask member; forming a third semiconductor layer of the first conductivity type on a part of an upper portion of the second semiconductor layer by injecting a second impurity into the second semiconductor layer through the spacer film using the mask member as a mask; removing the spacer film and the mask member; forming a first insulating film on at least a portion of the second semiconductor layer between the first semiconductor layer and the third semiconductor layer; forming a first electrode connected to the first semiconductor layer, a second electrode connected to the third semiconductor layer, and a third electrode disposed on the first insulating film; A method for manufacturing a semiconductor device comprising:

[0062] (Appendix 8) After the step of forming the spacer film and before the step of forming the third semiconductor layer, further comprising the step of thinning the spacer film; 8. The method for manufacturing a semiconductor device according to claim 7, wherein in the step of forming the third semiconductor layer, the spacer film remains on the second semiconductor layer.

[0063] (Appendix 9) 9. The method for manufacturing a semiconductor device according to claim 7, wherein in the step of forming the third semiconductor layer, the second impurity is scattered within the spacer film and reaches an upper portion of the second semiconductor layer. [Explanation of symbols]

[0064] 1: Semiconductor device 11: Drain electrode 12: Source electrode 13: Gate electrode 20: Semiconductor part 20a:Top surface 21: Drain layer 22: Drift layer 22a, 22b: Part 23: Base layer 23a, 23b: Part 24: Contact layer 25: Source layer 25a: part 25b: Side 25c: Upper edge 25d: lower edge 25e:part 31: Gate insulating film 32: Interelectrode insulating film 50: Semiconductor substrate 51: Mask material 52: Impurities 53: Spacer film 54: Impurities 99: Arc 99c:center 101: Semiconductor device 201, 202, 203, 301, 302: Sample D1, D2, D3: distance t1, t2: thickness Th: threshold voltage

Claims

1. A first electrode; a first semiconductor layer of a first conductivity type, the first semiconductor layer including silicon and carbon, connected to the first electrode; a second semiconductor layer of a second conductivity type, the second semiconductor layer including silicon and carbon and disposed on a portion of the first semiconductor layer; a third semiconductor layer of the first conductivity type, which is disposed on a portion of the second semiconductor layer, faces the first semiconductor layer via the second semiconductor layer, and whose side surface facing the first semiconductor layer is displaced upward so as to approach the first semiconductor layer, and which contains silicon and carbon; a second electrode connected to the third semiconductor layer; a third electrode disposed directly above at least a portion of the second semiconductor layer between the first semiconductor layer and the third semiconductor layer, and facing the portion via a first insulating film; Equipped with A semiconductor device in which the distance between the upper edge and the lower edge of the side surface as viewed from above is greater than the thickness of the third semiconductor layer as viewed from the side.

2. A first electrode; a first semiconductor layer of a first conductivity type, the first semiconductor layer including silicon and carbon, connected to the first electrode; a second semiconductor layer of a second conductivity type, the second semiconductor layer including silicon and carbon and disposed on a portion of the first semiconductor layer; a third semiconductor layer of the first conductivity type, which is disposed on a portion of the second semiconductor layer, faces the first semiconductor layer via the second semiconductor layer, and whose side surface facing the first semiconductor layer is displaced upward so as to approach the first semiconductor layer, and which contains silicon and carbon; a second electrode connected to the third semiconductor layer; a third electrode disposed directly above at least a portion of the second semiconductor layer between the first semiconductor layer and the third semiconductor layer, and facing the portion via a first insulating film; Equipped with A semiconductor device in which the cross-sectional shape of the side surface of the third semiconductor layer is a shape that follows an imaginary arc whose center is located above the third semiconductor layer.

3. 2. The semiconductor device according to claim 1, wherein the third electrode is arranged on a portion of the first semiconductor layer above which the second semiconductor layer is not arranged, and on a portion of the third semiconductor layer on the second semiconductor layer side, via the first insulating film.

4. the second electrode is in contact with the third semiconductor layer, 2. The semiconductor device according to claim 1, wherein the second electrode covers the third electrode via a second insulating film.

5. The semiconductor device according to claim 1 , wherein the first semiconductor layer is disposed on the first electrode and is in contact with the first electrode.

6. forming a mask member on a first semiconductor layer of a first conductivity type containing silicon and carbon; forming a second semiconductor layer of a second conductivity type on a portion of an upper part of the first semiconductor layer by implanting a first impurity into the first semiconductor layer using the mask member as a mask; forming a spacer film on the first semiconductor layer and the second semiconductor layer to cover the mask member; forming a third semiconductor layer of the first conductivity type on a part of an upper portion of the second semiconductor layer by injecting a second impurity into the second semiconductor layer through the spacer film using the mask member as a mask; removing the spacer film and the mask member; forming a first insulating film on at least a portion of the second semiconductor layer between the first semiconductor layer and the third semiconductor layer; forming a first electrode connected to the first semiconductor layer, a second electrode connected to the third semiconductor layer, and a third electrode disposed on the first insulating film; A method for manufacturing a semiconductor device comprising:

7. forming a mask member on a first semiconductor layer of a first conductivity type containing silicon and carbon; forming a second semiconductor layer of a second conductivity type on a portion of an upper part of the first semiconductor layer by implanting a first impurity into the first semiconductor layer using the mask member as a mask; forming a spacer film on the first semiconductor layer and the second semiconductor layer to cover the mask member; thinning the spacer film; forming a third semiconductor layer of the first conductivity type on a part of an upper portion of the second semiconductor layer by injecting a second impurity into the second semiconductor layer through the spacer film using the mask member as a mask; removing the spacer film and the mask member; forming a first insulating film on at least a portion of the second semiconductor layer between the first semiconductor layer and the third semiconductor layer; forming a first electrode connected to the first semiconductor layer, a second electrode connected to the third semiconductor layer, and a third electrode disposed on the first insulating film; Equipped with A method for manufacturing a semiconductor device, wherein the spacer film remains on the second semiconductor layer in the step of forming the third semiconductor layer.

8. 7. The method for manufacturing a semiconductor device according to claim 6, wherein in the step of forming the third semiconductor layer, the second impurity is scattered within the spacer film and reaches an upper portion of the second semiconductor layer.

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