Trench gate type switching element and manufacturing method thereof

Abstract

To suppress the deterioration in insulating performance of an interlayer insulating film.SOLUTION: A trench gate type switching element includes a semiconductor substrate having a trench formed on an upper surface thereof, a gate electrode, an interlayer insulating film, and an upper electrode. The gate electrode is disposed in the trench. An upper surface of the gate electrode exists lower than the upper surface of the semiconductor substrate. The interlayer insulating film covers the upper surface of the gate electrode while being not in contact with the upper surface of the semiconductor substrate. The upper electrode covers the upper surface of the semiconductor substrate and the upper surface of the interlayer insulating film. The upper surface of the interlayer insulating film includes a convex part and a particular surface provided between the convex part and each side surface of the trench. Each particular surface is inclined to the upper surface of the semiconductor substrate so as to displace downward as getting closer to the convex part, or is parallel to the upper surface of the semiconductor substrate.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a trench gate type switching element.

[0002] A trench-gate switching element includes a gate electrode disposed in a trench, an interlayer insulating film covering the upper surface of the gate electrode, and an upper electrode covering the upper surface of the interlayer insulating film and the upper surface of the semiconductor substrate. The upper electrode is insulated from the gate electrode by the interlayer insulating film. To miniaturize switching elements, a technique is known in which an interlayer insulating film is formed on the upper surface of the gate electrode without covering the upper surface of the semiconductor substrate. In this technique, an interlayer insulating film is first formed on the upper surface of the semiconductor substrate and the upper surface of the gate electrode in the trench. Next, the interlayer insulating film is etched to remove the interlayer insulating film outside the trench, leaving the interlayer insulating film on the upper surface of the gate electrode. This allows the interlayer insulating film to be formed on the upper surface of the gate electrode without covering the upper surface of the semiconductor substrate. However, this technique has the problem that the interlayer insulating film on the upper surface of the gate electrode may be removed during etching, making it difficult to control the etching. In response to this problem, Patent Document 1 discloses an interlayer insulating film with a convex portion on its upper surface. This structure allows the interlayer insulating film to easily remain on the upper surface of the gate electrode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-102450 Summary of the Invention [Problem to be solved by the invention]

[0004] As shown in FIG. 11 , in Patent Document 1, the thickness of the interlayer insulating film 120 decreases from the center of the trench toward both side walls of the trench. That is, the side surfaces of the interlayer insulating film 120 form inclined surfaces 120a that slope downward toward both side walls of the trench. Therefore, a V-shaped groove is formed by the side walls of the trench and the inclined surfaces 120a of the interlayer insulating film 120. An upper electrode 122 is filled in the V-shaped groove. Therefore, the upper electrode 122 has a protrusion 122a that protrudes sharply downward near the side wall of the trench. When a potential difference occurs between the gate electrode 118 and the upper electrode 122 during operation of the switching element, an electric field is applied to the interlayer insulating film 120. At this time, electric field concentration occurs near the protrusion 122a that protrudes sharply toward the interlayer insulating film 120. That is, a high electric field is applied to the interlayer insulating film 120 near the protrusion 122a. This may result in degradation of the insulating performance of the interlayer insulating film 120. This specification proposes a technique for suppressing the deterioration of the insulating performance of an interlayer insulating film. [Means for solving the problem]

[0005] The trench-gate switching element disclosed in this specification includes a semiconductor substrate, a gate insulating film, a gate electrode, an interlayer insulating film, and an upper electrode. A trench is formed in the upper surface of the semiconductor substrate. The gate insulating film covers the inner surface of the trench. The gate electrode is disposed within the trench. The gate electrode is insulated from the semiconductor substrate by the gate insulating film. The upper surface of the gate electrode is located lower than the upper surface of the semiconductor substrate. The interlayer insulating film covers the upper surface of the gate electrode without contacting the upper surface of the semiconductor substrate. The upper electrode covers the upper surface of the semiconductor substrate and the upper surface of the interlayer insulating film, and is insulated from the gate electrode by the interlayer insulating film. The upper surface of the interlayer insulating film has a convex portion and specific surfaces provided between the convex portion and each side surface of the trench. Each of the specific surfaces is inclined with respect to the upper surface of the semiconductor substrate so as to be displaced downward as it approaches the convex portion, or is parallel to the upper surface of the semiconductor substrate.

[0006] In this switching element, the upper surface of the interlayer insulating film has a special surface provided between the protrusion and each side surface of the trench. Each special surface is inclined with respect to the upper surface of the semiconductor substrate so as to be displaced downward as it approaches the protrusion, or is parallel to the upper surface of the semiconductor substrate. Therefore, the upper electrode does not have a protrusion that protrudes sharply downward near the side surface of the trench. This makes it possible to suppress electric field concentration in the interlayer insulating film and to suppress deterioration of the insulating performance of the interlayer insulating film.

[0007] This specification also proposes a method for manufacturing a trench-gate switching element. The manufacturing method includes the steps of: preparing a wafer; the wafer having a semiconductor substrate, a gate insulating film, and a gate electrode; a trench formed in an upper surface of the semiconductor substrate; the gate insulating film covering the inner surface of the trench; the gate electrode disposed within the trench; the gate electrode being insulated from the semiconductor substrate by the gate insulating film; and an upper surface of the gate electrode located below the upper surface of the semiconductor substrate. The manufacturing method includes the steps of forming an interlayer insulating film covering the upper surface of the semiconductor substrate and the upper surface of the gate electrode and having a recess in an upper center portion of the trench; forming a polysilicon layer covering the upper surface of the interlayer insulating film; etching the polysilicon layer to remove the polysilicon layer outside the recess, leaving the polysilicon layer within the recess; and etching the polysilicon layer and the interlayer insulating film using an etching method whose etching rate for the polysilicon layer is lower than that for the interlayer insulating film. The step of etching the interlayer insulating film includes etching the polysilicon layer and the interlayer insulating film to satisfy the following conditions: (1) removing the polysilicon layer; (2) removing the interlayer insulating film covering the upper surface of the semiconductor substrate; (3) leaving the interlayer insulating film covering the upper surface of the gate electrode in the trench; (4) forming a convex portion on the upper surface of the remaining interlayer insulating film at a position directly below the polysilicon layer; (5) forming specific surfaces between the convex portion on the upper surface of the remaining interlayer insulating film and each side surface of the trench; and (6) each of the specific surfaces is inclined with respect to the upper surface of the semiconductor substrate so as to be displaced downward as it approaches the convex portion, or is parallel to the upper surface of the semiconductor substrate. The manufacturing method includes a step of forming an upper electrode covering the upper surface of the semiconductor substrate and the upper surface of the interlayer insulating film, and being insulated from the gate electrode by the interlayer insulating film.

[0008] According to this manufacturing method, it is possible to manufacture a switching element in which electric field concentration is unlikely to occur in the interlayer insulating film. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. [Figure 2] Enlarged cross section of trench (if certain surfaces are inclined). [Figure 3] Enlarged cross section of trench (when the specified surface is not tilted). [Figure 4] 5A to 5C are explanatory diagrams of a method for manufacturing a switching element. [Figure 5] 5A to 5C are explanatory diagrams of a method for manufacturing a switching element. [Figure 6] 5A to 5C are explanatory diagrams of a method for manufacturing a switching element. [Figure 7] 5A to 5C are explanatory diagrams of a method for manufacturing a switching element. [Figure 8] 5A to 5C are explanatory diagrams of a method for manufacturing a switching element. [Figure 9] 5A to 5C are explanatory diagrams of a method for manufacturing a switching element. [Figure 10] FIG. 10 is an enlarged cross-sectional view of a switching element according to a modified example. [Figure 11] FIG. 1 is a cross-sectional view of a switching element disclosed in Patent Document 1. DETAILED DESCRIPTION OF THE INVENTION

[0010] In the switching element disclosed in the present specification, the specific surface may be inclined at an angle of 30 degrees or less with respect to the upper surface of the semiconductor substrate.

[0011] This configuration can suppress the concentration of the electric field near the protruding portion of the interlayer insulating film.

[0012] In the switching element disclosed in the present specification, the upper end of the convex portion may be located below the upper surface of the semiconductor substrate.

[0013] According to this configuration, the top surface of the upper electrode can be flattened.

[0014] In the switching element disclosed in the present specification, the upper surface of the interlayer insulating film may have a plurality of the protrusions.

[0015] In the switching element disclosed in this specification, the semiconductor substrate may have: a first n-type region in contact with the upper electrode and in contact with the gate insulating film on a side surface of the trench; a p-type body region in contact with the gate insulating film on the side surface of the trench below the first n-type region; and a second n-type region in contact with the gate insulating film on the side surface of the trench below the body region. For example, the first n-type region may be a source region, and the second n-type region may be a drift region.

[0016] The switching element 10 of the embodiment shown in FIG. 1 has a semiconductor substrate 12. The semiconductor substrate 12 is made of SiC. However, the semiconductor substrate 12 may be made of other semiconductor materials (e.g., Si, GaN, etc.). Hereinafter, a direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x-direction, and a direction parallel to the upper surface 12a and perpendicular to the x-direction is referred to as the y-direction. A plurality of trenches 14 are provided in the upper surface 12a of the semiconductor substrate 12. Each trench 14 extends elongatedly in the y-direction and is spaced apart in the x-direction. The inner surface of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is disposed in each trench 14. The gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. The upper surface of the gate electrode 18 is disposed below the upper surface 12a of the semiconductor substrate 12. An interlayer insulating film 20 is disposed in each trench 14. The interlayer insulating film 20 covers the upper surface of the gate electrode 18. An upper electrode 22 is disposed on the upper part of the semiconductor substrate 12. The upper electrode 22 covers the upper surface 12a of the semiconductor substrate 12 and the upper surface of the interlayer insulating film 20. The upper electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20. A lower electrode 24 is disposed on the lower part of the semiconductor substrate 12. The lower electrode 24 covers the lower surface 12b of the semiconductor substrate 12.

[0017] The semiconductor substrate 12 has a plurality of source regions 30, a plurality of contact regions 32, a body region , a drift region , and a drain region .

[0018] Each source region 30 is an n-type region having a high n-type impurity concentration. Each source region 30 contacts the gate insulating film 16 on the side surface of the corresponding trench 14. Each source region 30 also makes ohmic contact with the upper electrode 22.

[0019] Each contact region 32 is a p-type region having a high p-type impurity concentration and is in ohmic contact with the upper electrode 22.

[0020] The body region 34 is a p-type region having a lower p-type impurity concentration than the contact region 32. The body region 34 contacts each source region 30 and each contact region 32 from below. The body region 34 contacts the gate insulating film 16 on the underside of each source region 30.

[0021] The drift region 36 is an n-type region having a lower n-type impurity concentration than the source region 30. The drift region 36 contacts the body region 34 from below. The drift region 36 contacts the gate insulating film 16 on the underside of the body region 34.

[0022] The drain region 38 is an n-type region having a higher n-type impurity concentration than the drift region 36. The drain region 38 contacts the drift region 36 from below. The drain region 38 is in ohmic contact with the lower electrode 24.

[0023] The source region 30, the contact region 32, the body region 34, the drift region 36, the drain region 38, the gate electrode 18, and the gate insulating film 16 form a metal-oxide-semiconductor field effect transistor (MOSFET).

[0024] FIG. 2 is an enlarged cross-sectional view of the trench 14. As shown in FIG. 2, the interlayer insulating film 20 covers the upper surface of the gate electrode 18 without contacting the upper surface 12a of the semiconductor substrate 12. A protrusion 40 is provided on the upper surface of the interlayer insulating film 20. The protrusion 40 is provided in the center of the trench 14 in the x-direction. The upper surface of the interlayer insulating film 20 also has special surfaces 42 disposed on both sides of the protrusion 40. Each special surface 42 is disposed between the protrusion 40 and the side surface of the trench 14. The special surfaces 42 are inclined downward from the side surface of the trench 14 toward the protrusion 40. The inclination angle θ of the special surfaces 42 with respect to the upper surface 12a of the semiconductor substrate 12 is 30 degrees or less. Note that, as shown in FIG. 3, the special surfaces 42 may be parallel to the upper surface 12a (i.e., the inclination angle θ may be 0 degrees). The upper ends of the protrusions 40 are located below the upper surface 12a of the semiconductor substrate 12. That is, the protrusion 40 does not protrude above the upper surface 12a.

[0025] When the switching element 10 is in use, a higher potential is applied to the lower electrode 24 than to the upper electrode 22. Furthermore, when the switching element 10 is in use, the potential of the gate electrode 18 is controlled between a gate-off potential, which is the same as or lower than the upper electrode 22, and a gate-on potential, which is higher than the upper electrode 22. When the gate-on potential is applied to the gate electrode 18, the switching element 10 turns on, and when the gate-off potential is applied to the gate electrode 18, the switching element 10 turns off. When a potential difference occurs between the gate electrode 18 and the upper electrode 22 due to gate voltage control, an electric field is applied to the interlayer insulating film 20. If the upper electrode 122 has a protrusion 122a that protrudes downward adjacent to the side of the trench, as shown in FIG. 11 , the electric field concentrates in the interlayer insulating film 120 near the protrusion 122a. This can easily degrade the insulating performance of the interlayer insulating film 120. In contrast, in the switching element 10 of the embodiment, as shown in FIG. 2 or 3, a special surface 42 is provided between the protrusion 40 and the side surface of the trench 14. The special surface 42 is inclined so as to be displaced downward toward the protrusion 40, or the special surface 42 is parallel to the upper surface 12a of the semiconductor substrate 12. Therefore, the upper electrode 22 does not have a protrusion that protrudes sharply downward (i.e., a protrusion such as the protrusion 122a in FIG. 11). This prevents a high electric field from being applied to the interlayer insulating film 20. Therefore, in the switching element 10 of the embodiment, the insulating performance of the interlayer insulating film 20 is less likely to deteriorate.

[0026] Furthermore, when the specific surface 42 is inclined so as to be displaced downward toward the convex portion 40 as shown in FIG. 2 , an acute corner 44 is formed at a position adjacent to the convex portion 40. If the corner 44 is sharp, a high electric field is likely to be generated near the corner 44. However, in this embodiment, the inclination angle θ of the specific surface 42 with respect to the upper surface 12a is 30 degrees or less, so the corner 44 is not so sharp. This prevents a high electric field from being applied to the interlayer insulating film 20 near the corner 44. This also prevents deterioration of the insulating performance of the interlayer insulating film 20.

[0027] Next, a method for manufacturing the switching element 10 will be described. First, a source region 30, a contact region 32, a body region 34, a drift region 36, and a drain region 38 are formed in the semiconductor substrate 12 by epitaxial growth, ion implantation, or the like. Next, a trench 14 is formed as shown in FIG. 4 by selectively etching the upper surface 12a of the semiconductor substrate 12. Next, as shown in FIG. 5, a gate insulating film 16 made of silicon oxide is formed on the inner surface of the trench 14 and on the upper surface 12a of the semiconductor substrate 12. Next, a gate electrode 18 made of polysilicon is grown in the trench 14 and on the upper surface 12a of the semiconductor substrate 12 (i.e., on the surface of the gate insulating film 16). Next, as shown in FIG. 6, the gate electrode 18 is etched to remove the gate electrode 18 on the upper surface 12a, leaving the gate electrode 18 in the trench 14. Here, etching is performed so that the upper surface of the remaining gate electrode 18 is located within the trench 14 (i.e., the upper surface of the remaining gate electrode 18 is located below the upper surface 12a). Next, as shown in FIG. 7, an interlayer insulating film 20 made of silicon oxide is grown on the wafer. That is, the interlayer insulating film 20 is grown in the trench 14 and on the upper surface 12a (i.e., the surface of the gate insulating film 16). Above the gate electrode 18, the interlayer insulating film 20 grows from the upper surface of the gate electrode 18 and the side surfaces of the trench 14. Therefore, the interlayer insulating film 20 is formed thicker above the gate electrode 18 than on the upper surface 12a. Furthermore, since the interlayer insulating film 20 grows along the shape of the trench 14, a recess 20a is formed on the upper surface of the interlayer insulating film 20 above the central portion of the trench 14. Next, as shown in FIG. 7, a polysilicon layer 50 is grown on the interlayer insulating film 20. Here, the recess 20a is filled with the polysilicon layer 50. Next, as shown in FIG. 8, the polysilicon layer 50 is etched. Here, the polysilicon layer 50 is left in the recess 20a, and the polysilicon layer 50 outside the recess 20a is removed. The width of the remaining polysilicon layer 50 is narrower than the width of the trench 14 .

[0028] Next, the polysilicon layer 50 and the interlayer insulating film 20 are dry-etched using an etching gas having a higher etching rate for the interlayer insulating film 20 than for the polysilicon layer 50. Here, as shown in FIG. 9 , the etching is performed so that the interlayer insulating film 20 outside the trench 14 (i.e., on the upper surface 12a of the semiconductor substrate 12) is removed, the polysilicon layer 50 is removed, and the interlayer insulating film 20 remains in the trench 14. Note that the gate insulating film 16 is also removed in the area where the interlayer insulating film 20 has been removed. Because the polysilicon layer 50 exists above the gate electrode 18 before etching, etching proceeds slowly above the gate electrode 18. This makes it easy to leave the interlayer insulating film 20 above the gate electrode 18 (i.e., within the trench 14). By leaving the interlayer insulating film 20 in the trench 14 in this way, the interlayer insulating film 20 can be formed in a self-aligned manner above the gate electrode 18. Therefore, even if the distance between adjacent trenches 14 is narrow, the interlayer insulating film 20 can be accurately formed above the gate electrode 18. Since the distance between adjacent trenches 14 can be narrowed, the switching element 10 can be made smaller.

[0029] Furthermore, before etching, the central portion of the interlayer insulating film 20 above the gate electrode 18 is covered with the polysilicon layer 50. Therefore, etching progresses more slowly in the central portion of the trench 14 than in the vicinity of the side surface of the trench 14. Therefore, after etching, a protrusion 40 is formed in the central portion of the upper surface of the interlayer insulating film 20 in the trench 14 (i.e., the central portion of the trench 14 in the x-direction). Since a large difference in etching rate can be achieved between the polysilicon layer 50 and the interlayer insulating film 20 (i.e., silicon oxide), the side surface of the protrusion 40 is less likely to have a tapered shape and can be made approximately parallel to the thickness direction of the semiconductor substrate 12. Therefore, a special surface 42 having a small inclination angle with respect to the upper surface 12a is formed between the protrusion 40 and the side surface of the trench 14. That is, the special surface 42 can be made to be inclined with respect to the upper surface 12a of the semiconductor substrate 12 so as to be displaced downward as it approaches the protrusion 40, or can be made to be parallel to the upper surface 12a of the semiconductor substrate 12. Here, the specific surface 42 is formed so that the inclination angle θ of the specific surface 42 with respect to the upper surface 12a is 0 to 30 degrees. Also, here, the protrusions 40 are formed so that the upper ends of the protrusions 40 do not protrude above the upper surface 12a of the semiconductor substrate 12.

[0030] Next, as shown in FIG. 2, an upper electrode 22 is formed to cover the upper surface of the interlayer insulating film 20 and the upper surface 12a of the semiconductor substrate 12. The upper electrode 22 contacts the interlayer insulating film 20 at the upper surfaces of the protrusions 40, the side surfaces of the protrusions 40, and the special surface 42. In this structure, the upper electrode 22 can contact the interlayer insulating film 20 over a wider area than when the side surfaces of the protrusions 40 are tapered. Therefore, the upper electrode 22 can be adhered to the interlayer insulating film 20 with high strength. Furthermore, because the special surface 42 is formed, the upper electrode 22 does not have a protrusion that protrudes downward, such as the protrusion 122a in FIG. 11. Furthermore, because the inclination angle θ of the special surface 42 is 0 to 30 degrees, the corners 44 are not very sharp. This makes it possible to manufacture a switching element 10 in which electric field concentration is less likely to occur in the interlayer insulating film 20.

[0031] Furthermore, because the upper end of the protrusion 40 does not protrude above the upper surface 12a of the semiconductor substrate 12, it is possible to prevent a protrusion from being formed on the upper surface of the upper electrode 22. Therefore, there is no need to perform a process to flatten the upper surface of the upper electrode 22 after forming the upper electrode 22. Although not shown, after forming the upper electrode 22, a step of forming a polyimide resin layer that covers the outer periphery of the upper surface 12a of the semiconductor substrate 12 is performed. At this time, the outer periphery of the upper electrode 22 is covered with the polyimide resin layer. Because the upper surface of the upper electrode 22 is flat, a polyimide resin layer can be formed on the upper electrode 22 with a uniform thickness. After forming the upper electrode 22, the lower electrode 24 is formed. This completes the switching element of FIG. 1.

[0032] In the above embodiment, the protrusions 40 do not protrude above the upper surface 12a. However, the protrusions 40 may protrude above the upper surface 12a. Even in this case, if the specific surface 42 is appropriately provided, it is possible to prevent a high electric field from being applied to the interlayer insulating film 20.

[0033] In the above embodiment, the interlayer insulating film 20 has one protrusion 40. However, as shown in Fig. 10, the interlayer insulating film 20 may have multiple protrusions 40. Even in this case, by providing a specific surface 42 between the protrusion 40 and the side surface of the trench 14, it is possible to prevent a high electric field from being applied to the interlayer insulating film 20.

[0034] In the above embodiment, the switching elements are MOSFETs, but the technology disclosed in this specification may be applied to other switching elements such as IGBTs (insulated gate bipolar transistors).

[0035] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0036] 10: switching element, 12: semiconductor substrate, 14: trench, 18: gate electrode, 20: interlayer insulating film, 40: protrusion, 42: specific surface

Claims

1. A trench gate type switching element, a semiconductor substrate (12) having a trench (14) formed in an upper surface thereof; a gate insulating film (16) covering the inner surface of the trench; a gate electrode (18) disposed in the trench, the gate electrode being insulated from the semiconductor substrate by the gate insulating film, the upper surface of the gate electrode being located below the upper surface of the semiconductor substrate; an interlayer insulating film (20) covering the upper surface of the gate electrode without contacting the upper surface of the semiconductor substrate; an upper electrode (22) covering the upper surface of the semiconductor substrate and the upper surface of the interlayer insulating film and insulated from the gate electrode by the interlayer insulating film; and the upper surface of the interlayer insulating film has a convex portion (40) and a specific surface (42) provided between the convex portion and each side surface of the trench; Each of the specific surfaces is inclined with respect to the upper surface of the semiconductor substrate so as to be displaced downward as it approaches the convex portion, or is parallel to the upper surface of the semiconductor substrate. Switching element.

2. 2. The switching element according to claim 1, wherein the inclination angle of the specific surface relative to the upper surface of the semiconductor substrate is 30 degrees or less.

3. The switching element according to claim 1 , wherein an upper end of the convex portion is located below the upper surface of the semiconductor substrate.

4. The switching element according to claim 1 , wherein the upper surface of the interlayer insulating film has a plurality of the protrusions.

5. A method for manufacturing a switching element, comprising: A wafer, a semiconductor substrate having a trench formed on an upper surface thereof; a gate insulating film covering the inner surface of the trench; a gate electrode disposed in the trench, the gate electrode being insulated from the semiconductor substrate by the gate insulating film, and the upper surface of the gate electrode being located lower than the upper surface of the semiconductor substrate; providing the wafer having: forming an interlayer insulating film covering the upper surface of the semiconductor substrate and the upper surface of the gate electrode, the interlayer insulating film having a recess in an upper portion at the center of the trench; forming a polysilicon layer covering the upper surface of the interlayer insulating film; etching the polysilicon layer to remove the polysilicon layer outside the recess, leaving the polysilicon layer within the recess; a step of etching the polysilicon layer and the interlayer insulating film by an etching method having an etching rate for the polysilicon layer lower than an etching rate for the interlayer insulating film, removing the polysilicon layer; removing the interlayer insulating film covering the top surface of the semiconductor substrate; leaving the interlayer insulating film covering the upper surface of the gate electrode in the trench; a protrusion is formed on the upper surface of the remaining interlayer insulating film at a position directly below the polysilicon layer; a specific surface is formed between the protrusion of the upper surface of the remaining interlayer insulating film and each side surface of the trench; Each of the specific surfaces is inclined with respect to the upper surface of the semiconductor substrate so as to be displaced downward as it approaches the convex portion, or is parallel to the upper surface of the semiconductor substrate. etching the polysilicon layer and the interlayer insulating film so as to satisfy the condition: forming an upper electrode covering the upper surface of the semiconductor substrate and the upper surface of the interlayer insulating film and insulated from the gate electrode by the interlayer insulating film; A manufacturing method comprising the steps of:

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