Indication device

Abstract

To provide a structure that alleviates electric field concentration that may occur between a source electrode and a drain electrode and suppresses deterioration in switching characteristics in a bottom gate type thin film transistor and a method for manufacturing the same.SOLUTION: A bottom gate type thin film transistor has an oxide semiconductor layer on a source electrode and a drain electrode. By making an angle θ1 of a side surface of the source electrode in contact with the oxide semiconductor layer and an angle θ2 of a side surface of the drain electrode 20° or more and less than 90°, a distance from an electrode upper end to an electrode lower end at a side surface of the source electrode and the drain electrode is increased.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a display device using an oxide semiconductor and a manufacturing method thereof. [Background technology]

[0002] As typified by liquid crystal display devices, thin film transistors formed on flat plates such as glass substrates are , amorphous silicon, and polycrystalline silicon. Thin film transistors using silicon have low field effect mobility, but are suitable for enlarging the area of ​​glass substrates. On the other hand, thin film transistors using crystalline silicon have high field effect mobility. However, a crystallization process such as laser annealing is required, and enlarging the glass substrate is essential. However, it has the characteristic of not being adaptable.

[0003] In response to this, thin film transistors are being fabricated using oxide semiconductors, and they are being used in electronic devices and optical devices. For example, zinc oxide and In-G Thin film transistors were fabricated using a-Zn-O oxide semiconductors and used as switches for image display devices. Patent Documents 1 and 2 disclose techniques used in chip elements and the like. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-096055 Summary of the Invention [Problem to be solved by the invention]

[0005] In bottom-gate thin-film transistors, there is a risk of this occurring between the source and drain electrodes. To provide a structure and a manufacturing method thereof that alleviates electric field concentration and suppresses deterioration of switching characteristics. One of the goals is to

[0006] Another object is to provide a structure that improves coverage of an oxide semiconductor layer and a manufacturing method thereof. This is one of the topics. [Means for solving the problem]

[0007] Bottom-gate thin-film transistor having an oxide semiconductor layer on a source electrode and a drain electrode The angle θ1 of the side surface of the source electrode in contact with the oxide semiconductor layer and the angle θ2 of the side surface of the drain electrode By setting the angle θ2 to 20° or more and less than 90°, the side surfaces of the source electrode and the drain electrode The distance from the upper end of the electrode to the lower end of the electrode is increased.

[0008] One of the configurations of the invention disclosed in this specification is a gate electrode on a substrate having an insulating surface. an insulating layer on the source electrode; a source electrode and a drain electrode on the insulating layer; and a side surface of the source electrode. An oxide layer overlapping the gate electrode and the side surface of the drain electrode facing the side surface with an insulating layer interposed therebetween. a semiconductor layer, and an angle formed by a substrate surface of the substrate and a side surface of the source electrode and a surface of the substrate and a drain electrode. a semiconductor device characterized in that the angle formed between the inner electrode and the side surface of the inner electrode is 20° or more and less than 90° is.

[0009] The above configuration solves at least one of the above problems.

[0010] Depending on the metal material used for the source and drain electrodes, A native oxide film is formed on at least the side surfaces of the silicon nitride film. This native oxide film is then removed by atmospheric etching. It is formed when the oxide semiconductor layer is exposed to an atmosphere containing oxygen such as Even if the film-forming atmosphere contains oxygen, a natural oxide film is formed on the side of the electrode. do.

[0011] In addition, in order to prevent the formation of a natural oxide film on the surface of the electrode, a metal obtained by sputtering is used. A buffer layer (n + It is possible to continuously deposit layers (also called "layers") without exposing them to the atmosphere. Preferably, the buffer layer is an oxide semiconductor layer having a lower resistance than the oxide semiconductor layer, It functions as a source region or a drain region.

[0012] In the above-mentioned structure, a buffer layer is provided on the upper surfaces of the source electrode and the drain electrode, The oxide semiconductor layer is disposed on the buffer layer (n + layer) without contact with the atmosphere By successively depositing the films, a native oxide film is formed on the top surfaces of the source and drain electrodes. Prevent this.

[0013] In addition, in a bottom gate thin film transistor, the gate electrode is provided with a voltage sufficiently higher than the threshold voltage. When a large voltage is applied to the transistor to turn it on, the drain current path (in the channel length direction) The current path is first from the drain electrode through the oxide semiconductor layer near the interface with the gate insulating film. This provides a path to the source electrode.

[0014] In addition, a bottom-gate thin film transistor having an oxide semiconductor layer on the source electrode and the drain electrode is used. The channel length of a transistor corresponds to the shortest distance between the source and drain electrodes. The distance between the gate insulating film and the drain electrode is the oxide semiconductor layer near the interface with the gate insulating film. .

[0015] n + When the layer is formed in contact with the top surfaces of the drain electrode and the source electrode, the layer formed on the side surfaces of the electrodes If the conductivity of the native oxide film is low, the main path of the drain current is from the drain electrode to the n + Layer The oxide semiconductor layer is located near the interface of the drain electrode side, and the gate insulating film is located near the interface. through the oxide semiconductor layer near the interface on the side of the source electrode, + layer The oxide semiconductor layer obtained by sputtering has a path that leads to the source electrode. The quality of the film near the interface with the film-forming surface tends to be affected by the material of the surface on which the film is being formed. The layer is n + Interface with the layer, interface with the side of the source electrode (and the side of the drain electrode), gate insulation The oxide semiconductor has an interface with a film and at least three interfaces with different materials. In the body layer, the interface state with the native oxide film on the side of the drain electrode and the interface state with the gate insulating film Since the states are different, the oxide semiconductor layer near the interface on the side of the drain electrode is the first electric field concentration relaxation region. In addition, the interface state with the native oxide film on the side of the source electrode and the gate insulating film Since the interface state is different, the oxide semiconductor layer near the interface on the side of the source electrode is the second electric field concentration. It acts as a relaxation zone.

[0016] In this way, the side surfaces of the source electrode and the drain electrode in the oxide semiconductor layer are overlapped. The region functions as an electric field concentration relaxation region.

[0017] The oxide semiconductor used in this specification is InMO3(ZnO) m Thin (m>0) A thin film is formed, and a thin film transistor is fabricated using the thin film as the semiconductor layer. , Ga, Fe, Ni, Mn, and Co. For example, M can be Ga, or it can be Ga and Ni or Ga and Fe, etc. In addition, in the oxide semiconductor, the metal element M may be contained. In addition to the metal elements contained in the alloy, Fe, Ni and other transition metal elements, or the transition metal elements, may be contained as impurity elements. In this specification, this thin film is called In-Ga- It is also called a Zn-O-based non-single crystal film.

[0018] The crystalline structure of the In-Ga-Zn-O non-single crystal film is amorphous according to XRD analysis. The In-Ga-Zn-O non-single crystal film analyzed was formed by sputtering, Heat treatment is carried out at 200 to 500°C, typically 300 to 400°C, for 10 to 100 minutes. There are.

[0019] Angle θ1 of the side surface of the source electrode and angle θ2 of the side surface of the drain electrode that are in contact with the oxide semiconductor layer is set to 20° or more and less than 90°, and the angle from the top end of the electrode on the side surface of the source electrode and the drain electrode By increasing the distance to the lower end of the electrode, the length of the first electric field concentration relaxation region and the second electric field concentration relaxation region can be reduced. The length of the field concentration relaxation region is increased to relax the electric field concentration. By increasing the thickness of the electrode, the distance from the top to the bottom of the electrode on the side surface can be reduced. The distance can be increased.

[0020] In addition, when the oxide semiconductor layer is formed by sputtering, the film is formed on the side of the electrode perpendicular to the substrate surface. The thickness of the film formed on the oxide semiconductor layer may be thinner than the thickness of the film formed on the top surface of the electrode. The angle θ1 of the side surface of the source electrode and the angle θ2 of the side surface of the drain electrode are set to 20° or more and less than 90°. By satisfying the condition, the uniformity of the film thickness can be improved even on the side surfaces, and the electric field concentration can be alleviated. It can also be done as follows.

[0021] As shown in Figure 1, the line connecting the bottom edge of the source electrode side surface and the top edge of the source electrode side surface is If the straight line is approximately the same as the slope of the side surface of the source electrode, the source electrode has a tapered shape. However, the angle θ1 between the substrate surface and the side surface of the source electrode can also be called the first taper angle. In addition, a line that starts from the lower end of the side of the drain electrode and connects the upper end of the side of the drain electrode is If the slope of the drain electrode side surface is approximately equal to the slope of the drain electrode side surface, the drain electrode is said to have a tapered shape. The angle θ2 formed between the substrate surface and the side surface of the drain electrode can also be called a second taper angle.

[0022] The electrode side is not limited to a shape having one angle, and may be formed at least under the source electrode. The angle θ1 of the side surface of the end portion and the angle θ2 of the side surface of the lower end portion of the drain electrode are 20° to 90° If the difference is less than 1 / 2 mm, the electrode side surface may have a step.

[0023] Another aspect of the present invention is a structure of a gate electrode on a substrate having an insulating surface, and an insulating film on the gate electrode. a source electrode and a drain electrode on the insulating layer; a side surface of the source electrode; The gate electrode and the oxide semiconductor layer are overlapped between the side surfaces of the drain electrode and the insulating layer. The angle between the substrate surface and the side of the lower end of the source electrode and the angle between the substrate surface and the drain electrode A semiconductor device characterized in that the angle between the bottom end and the side surface is 20° or more and less than 90°. be.

[0024] In the above-described configuration, the angle formed between the substrate surface of the substrate and the side surface of the lower end of the source electrode is and the side surface of the upper end of the source electrode. The angle between the plate surface and the side of the lower end of the drain electrode is The angle between the side surface of the source electrode and the side surface of the drain electrode facing each other with the oxide semiconductor layer sandwiched therebetween is different. The cross-sectional shapes of the rain electrode side surfaces are almost identical because they are subjected to the same etching process.

[0025] For example, the angle of the side surface of the bottom end of the source electrode (and drain electrode) and the The angle of the side surface of the upper end of the source electrode (and drain electrode) is changed, and the side of the upper end of the source electrode (and drain electrode) The angle of the side surface of the upper end of the source electrode (and drain electrode) may be set to 90°. By making the angle of the side surface of the bottom end of the source electrode (and drain electrode) larger, the source The mask spacing for forming the electrode and drain electrode can be designed to be narrow, resulting in For example, the channel length can be designed to be 1 μm to 10 μm. Cut.

[0026] The side surfaces of the source electrode and the drain electrode have at least a partial curved surface. For example, in the cross-sectional shape of the source electrode and the drain electrode, the lower end of the electrode may be There may also be one curved surface defined by the center of curvature radius located outside the pole. The side shapes of the source and drain electrodes are flared from the top surface of the electrodes toward the substrate. The cross-sectional shape may be:

[0027] The electrodes having the various cross-sectional shapes described above can be formed by dry etching or wet etching. The etching equipment used for dry etching is a reactive ion etching equipment. Etching equipment using the RIE method and ECR (Electron C yclotron Resonance) and ICP(Inductively Coup) A dry etching device using a high-density plasma source such as LED Plasma is used. In addition, compared to ICP etching equipment, a uniform discharge can be obtained over a wide area. For dry etching equipment that is prone to damage, the upper electrode is grounded and the lower electrode is connected to a 13.56M Hz high frequency power supply is connected to the bottom electrode, and a 3.2 MHz low frequency power supply is connected to the bottom electrode. CP(Enhanced Capacitively Coupled Plasma) There is an etching system in this ECCP mode. For example, It can also be used for 10th generation substrates that are over 3m in size. Cut.

[0028] The source electrode and the drain electrode may be a single layer or may be made of at least two different materials. It may be a multi-layer structure of two or more layers made of materials.

[0029] One of the configurations of the present invention relating to the manufacturing method for realizing the above structure is a method for manufacturing a semiconductor device having an insulating surface. a gate electrode is formed on the substrate, a gate insulating layer is formed to cover the gate electrode, and a gate insulating layer is formed on the substrate; A conductive layer and a buffer layer are laminated on the layer without being exposed to the atmosphere, and the buffer layer and the conductive layer are The side surface is selectively etched to form an angle of 20° or more and less than 90° with the substrate surface. A source electrode and a drain electrode are formed on the insulating layer. The present invention relates to a method for manufacturing a semiconductor device in which an oxide semiconductor layer is formed on a pole.

[0030] In the structure according to the above manufacturing method, the buffer layer contains indium, gallium, and zinc. The same target as that for forming the oxide semiconductor layer over the buffer layer can be used. By changing the deposition atmosphere, the buffer layer and the oxide semiconductor layer can be formed separately. By using a common target, the manufacturing cost can be reduced.

[0031] In the structure according to the above manufacturing method, the conductive layer and the buffer layer are exposed to the atmosphere on the gate insulating layer. One of the features of this method is that it allows for continuous film formation without any gaps.

[0032] In the structure according to the above manufacturing method, the conductive layer forming the source electrode and the drain electrode is , aluminum, tungsten, chromium, tantalum, titanium, molybdenum and other metal materials The conductive layer may be formed using a material selected from the group consisting of a metal, a silicon dioxide, a silicon nitride, a silicon nitride, a silicon dioxide alloy, a silicon dioxide film ... For example, a laminated structure having an aluminum film as the lower layer and a titanium film as the upper layer, a tungsten film as the lower layer, The upper layer is a molybdenum film, and the lower layer is an aluminum film and the upper layer is a molybdenum film. A laminate in which

[0033] In this specification, continuous film formation refers to a process from a first film formation process performed by sputtering to a second film formation process performed by sputtering. During the series of processes up to the film formation process, the atmosphere in which the substrate is placed is contaminated, such as air. Always keep the device in a vacuum or inert gas atmosphere (nitrogen or rare gas atmosphere) without contact with the atmosphere. By performing continuous film formation, the quality of the processed substrate is improved. Film formation can be performed while avoiding re-adhesion of moisture and the like to the plate.

[0034] A series of processes from the first film formation process to the second film formation process are carried out in the same chamber. is considered to be within the scope of continuous film formation in this specification.

[0035] In addition, a series of processes from the first film formation process to the second film formation process are carried out in different chambers. In this case, after the first film formation step is completed, the substrate is transported between chambers without being exposed to the atmosphere. The application of a second film is also considered to be within the scope of successive film formation in this specification.

[0036] Between the first and second film-forming steps, a substrate transfer step, an alignment step, and a slow cooling step are performed. a step of heating or cooling the substrate to a temperature required for the first step or the second step, Even if the film thickness is small, it is considered to be within the scope of continuous film formation in this specification.

[0037] However, processes that use liquids, such as cleaning, wet etching, and resist formation, are the first If the film formation is performed between the first film formation process and the second film formation process, it does not fall within the scope of continuous film formation as defined in this specification. Let's say that doesn't happen.

[0038] In this specification, terms indicating directions such as top, bottom, side, horizontal, vertical, etc. refer to the direction of a device on a substrate surface. This refers to the direction based on the board surface when the chair is placed.

[0039] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of processes or stacking. Furthermore, the specific names used in this specification are not intended to identify the invention. This does not indicate [Effects of the Invention]

[0040] The angle between the substrate surface and the side surface of the source electrode and the angle between the substrate surface and the side surface of the drain electrode are By adjusting the angle, the oxide semiconductor layer provided on the source electrode and the drain electrode can be Improves coverage.

[0041] By providing an electric field concentration relaxation region, the electric field concentration that may occur between the source electrode and the drain electrode can be reduced. It reduces electric field concentration and suppresses deterioration of the switching characteristics of thin film transistors. [Brief explanation of the drawings]

[0042] [Figure 1] 1 is a cross-sectional view illustrating an example of a semiconductor device. [Figure 2] 1 is a cross-sectional view illustrating an example of a semiconductor device. [Figure 3] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 4] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 5] 1A to 1C are top views illustrating an example of a method for manufacturing a semiconductor device. [Figure 6] 1A to 1C are top views illustrating an example of a method for manufacturing a semiconductor device. [Figure 7] 1A to 1C are top views illustrating an example of a method for manufacturing a semiconductor device. [Figure 8] 1A to 1C are top views illustrating an example of a method for manufacturing a semiconductor device. [Figure 9] 1A and 1B are diagrams showing an example of a cross-sectional view and an example of a top view of a terminal portion; [Figure 10] 1A to 1C are top views illustrating an example of a method for manufacturing a semiconductor device. [Figure 11] 1 is a cross-sectional view illustrating an example of a semiconductor device. [Figure 12] FIG. 1 illustrates an example of a block diagram of a semiconductor device. [Figure 13] FIG. 2 is a diagram illustrating an example of the configuration of a signal line driver circuit. [Figure 14] 10 is a timing chart illustrating an example of the operation of the signal line driver circuit. [Figure 15] 10 is a timing chart illustrating an example of the operation of the signal line driver circuit. [Figure 16] FIG. 2 is a diagram illustrating an example of the configuration of a shift register. [Figure 17] 17 is a diagram for explaining the connection configuration of the flip-flop shown in FIG. 16. FIG. [Figure 18] FIG. 2 is a diagram illustrating an example of a pixel equivalent circuit of a semiconductor device. [Figure 19] 1 is a cross-sectional view illustrating an example of a semiconductor device. [Figure 20] 1A and 1B are a cross-sectional view and a top view illustrating an example of a semiconductor device. [Figure 21] 1 is a cross-sectional view illustrating an example of a semiconductor device. [Figure 22] 1A and 1B are a cross-sectional view and a top view illustrating an example of a semiconductor device. [Figure 23] 1A and 1B are diagrams illustrating examples of usage of electronic paper. [Figure 24] FIG. 1 is an external view showing an example of an electronic book. [Figure 25] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 26] 1 is an external view showing an example of a gaming machine. [Figure 27] FIG. 1 is an external view showing an example of a mobile phone. [Figure 28] FIG. 10 is a diagram illustrating an example of electrical characteristics of a thin film transistor. [Figure 29] FIG. 1 is a top view of a thin film transistor fabricated for measuring electrical characteristics. [Figure 30] 1A to 1C are cross-sectional views showing steps for producing a sample. [Figure 31] 1A and 1B are a photograph and a cross-sectional view showing a part of a cross section of a sample. [Figure 32] 1A is a diagram showing an example of a cross-sectional structure of a semiconductor device, FIG. 1B is an equivalent circuit diagram, and FIG. 1C is a top view. [Figure 33] FIG. 2 is a cross-sectional view showing the structure of a calculation model. [Figure 34] 10 is a graph showing calculation results. [Figure 35] 10 is a graph showing calculation results. [Figure 36] 10 is a graph showing calculation results. [Figure 37]10 is a graph showing the calculation results (Comparative Example). DETAILED DESCRIPTION OF THE INVENTION

[0043] This embodiment will be described below.

[0044] (Embodiment 1) FIG. 1 shows an example in which a thin film transistor 170 is provided on a substrate. 1 is an example of a cross-sectional view of a rotor.

[0045] A gate electrode 101 provided on a substrate 100 having an insulating surface is connected to a gate insulating layer 102. The gate insulating layer 102 is covered with the gate electrode 101, and the first wiring or the second wiring is disposed on the gate insulating layer 102 which overlaps the gate electrode 101. The first wiring layer functions as the source electrode layer 105a or the drain electrode layer 105b. A buffer layer is provided on each of the source electrode layers 105a and the second wiring. A first buffer layer 104a is provided on the drain electrode layer 105b, and a second buffer layer 104b is provided on the drain electrode layer 105b. A first buffer layer 104a and a second buffer layer 104b are provided. The oxide semiconductor layer 103 is provided on the photoresist layer 104b.

[0046] In FIG. 1, a substrate 100 having light transmissivity is made of Corning 7059 glass or 173 Barium borosilicate glass and aluminoborosilicate glass, such as 7-glass, A glass substrate can be used.

[0047] The gate electrode 101 is a single layer or a laminated layer made of different metal materials. The material of the pole 101 is metal material (aluminum (Al), copper (Cu), titanium (Ti), Ta (Ta), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Nd (Neo Elements selected from Zr (Zr), Sc (Scandium), or alloys containing the above elements ) is used, and the angle of the side surface of the gate electrode 101 is set to 20° or more and less than 90°. The gate electrode 101 is formed by etching so that a tapered shape is formed in the portion.

[0048] The gate insulating layer 102 is made of silicon oxide obtained by sputtering or plasma CVD. film, silicon oxynitride film, silicon nitride film, aluminum oxide film, tantalum oxide film, etc. An insulating film may be used and formed as a single layer or a laminated structure made of these materials. The source electrode layer 105a and the drain electrode layer 105b are formed on the gate insulating layer 102. When etching, it is preferable to select a material that has a sufficient selectivity. When the electrode layer 105a and the drain electrode layer 105b are etched, the gate insulating layer 102 The surface may be etched to about 20 nm, and in order to eliminate etching residues of metal materials, For this purpose, it is preferable to remove a small amount of the surface layer.

[0049] The source electrode layer 105a and the drain electrode layer 105b may be formed of a single layer or different metal materials. The source electrode layer 105a and the drain electrode layer 105b are made of a metal material ( Aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), Nd (neodymium), Sc (scandium ) or an alloy containing the above elements) is used.

[0050] As shown in FIG. 1, the cross-sectional shape of the source electrode layer 105a is determined by the surface of the substrate and the surface of the source electrode layer 105b. The angle θ1 between the drain electrode layer 1 and the side surface of the drain electrode layer 1 is 20° or more and less than 90°. As shown in FIG. 1, the cross-sectional shape of the drain electrode layer 105b is a cross section of the substrate surface and the side surface of the drain electrode layer 105b. The angle θ2 between the two points is 20° or more and less than 90°. Since the angle θ1 and the angle θ2 are almost the same, The angle θ1 of the side surface of the source electrode layer 105a in contact with the oxide semiconductor layer and the angle θ2 of the drain electrode The angle θ2 of the side surface of the source electrode layer 105b is set to 20° or more and less than 90°. a and the distance from the upper end to the lower end of the electrode on the side surface of the drain electrode layer 105b is increased. do.

[0051] In FIG. 1, the angles θ1 and θ2 are shown with the rear surface of the substrate as the substrate surface. The surface plane of the substrate is not limited to the above, and the rear surface plane and the surface plane of the substrate are parallel to each other even if the surface plane of the substrate is the substrate surface. Therefore, it goes without saying that the angles will be the same.

[0052] The oxide semiconductor layer 105 is formed on the source electrode layer 105a and the drain electrode layer 105b having such shapes. The oxide semiconductor layer 103 is an oxide semiconductor containing In, Ga, and Zn. Using a target (In2O3:Ga2O3:ZnO=1:1:1), the substrate and target were The distance between the nozzles was 170 mm, the pressure was 0.4 Pa, the DC power was 0.5 kW, and the oxygen content was After forming the film under an argon atmosphere, a resist mask is formed and selectively etched to remove the unwanted The necessary parts are removed to form the desired shape. If a pulsed direct current (DC) power supply is used, the amount of waste can be reduced. This is preferable because the film thickness distribution is uniform. In this embodiment, the oxide semiconductor film has a thickness of 100 nm.

[0053] Note that the first buffer layer 104 is provided between the source electrode layer 105a and the oxide semiconductor layer 103. In addition, a is preferably provided between the drain electrode layer 105b and the oxide semiconductor layer 103. It is preferable to provide a second buffer layer 104b.

[0054] The first buffer layer 104a and the second buffer layer 104b are formed on the oxide semiconductor layer 103. The oxide semiconductor layer (n + layer) as the source or drain region. It works.

[0055] n + The layer was formed using a target of In2O3:Ga2O3:ZnO=1:1:1. The conditions were a pressure of 0.4 Pa, a power of 500 W, a film formation temperature of room temperature, and argon gas. Sputtering was performed with a gas flow rate of 40 sccm. Although a 1:1:1 target was intentionally used, the size of 1n was In-Ga-Zn-O based non-single crystal films containing crystal grains of 10 nm to 100 nm may be formed. The target component ratio, deposition pressure (0.1 Pa to 2.0 Pa), and power (250 W to 3000W: 8 inch φ), temperature (room temperature to 100℃), reactive sputtering film formation conditions, etc. By adjusting appropriately, the presence or absence of crystal grains, the density of crystal grains, and the diameter size can be adjusted to 1nm to 10nm. The thickness of the second In-Ga-Zn-O based non-single crystal film can be adjusted within the range of 5 Of course, if crystal grains are contained in the film, the size of the crystal grains contained therein is In this embodiment, the second In—Ga—Zn—O system non-single crystal The thickness of the crystal film is 5 nm.

[0056] In addition, a conductive film to be the source electrode layer 105a or the drain electrode layer 105b and an n + Layered Acid The semiconductor film is deposited by sputtering without being exposed to the atmosphere, and the source is removed during the manufacturing process. This can prevent the electrode layer or the drain electrode layer from being exposed and causing dust to adhere thereto.

[0057] The oxide semiconductor layer 103 obtained by a sputtering method has a film quality near the interface with the surface on which the film is to be formed. The oxide semiconductor layer tends to be affected by the material of the n + the interface with the source electrode layer It has an interface with the side surface (and the drain electrode layer side surface) and an interface with the gate insulating film, and is made of different materials Therefore, the oxide semiconductor layer 103 has at least three interfaces with the drain electrode. The interface state with the native oxide film on the side of the electrode is different from the interface state with the gate insulating film. The oxide semiconductor layer near the interface on the side surface of the electrode layer functions as a first electric field concentration relaxation region 106a. In addition, the interface state between the source electrode and the native oxide film on the side surface is different from the interface state between the source electrode and the gate insulating film. Therefore, the oxide semiconductor layer near the interface on the side of the source electrode becomes the second electric field concentration relaxation region 106. It functions as b. Angle θ1 of the side surface of the source electrode and angle θ2 of the side surface of the drain electrode that are in contact with the oxide semiconductor layer is set to 20° or more and less than 90°, and the angle from the top end of the electrode on the side surface of the source electrode and the drain electrode By increasing the distance to the lower end of the electrode, the length L of the first electric field concentration relaxation region 106a The length L2 of the first and second electric field concentration relief regions 106b is increased to relieve the electric field concentration. In addition, by increasing the film thickness of the source electrode and the drain electrode, the electrode The distance from the top end to the bottom end of the electrode can be increased.

[0058] In addition, when the oxide semiconductor layer 103 is formed by sputtering, the oxide semiconductor layer 103 is formed on the side surface of the electrode perpendicular to the substrate surface. The thickness of the oxide semiconductor layer may be thinner than the thickness of the oxide semiconductor layer formed on the electrode. The angle θ1 of the side of the source electrode and the angle θ2 of the side of the drain electrode that contact each other are set to 20° or more. By setting the angle to less than 0°, the uniformity of the film thickness can be improved even on the side surfaces, and the oxide semiconductor layer It is also possible to reduce the area where the layer 103 is locally thin, thereby mitigating the electric field concentration.

[0059] (Embodiment 2) In FIG. 1, the source electrode layer (drain electrode layer) is The line connecting the top ends of the side of the source electrode layer (drain electrode layer) is approximately the same as the slope of the side of the source electrode layer (drain electrode layer). However, in this embodiment, a step is formed on the side surface of the source electrode layer (drain electrode layer). An example in which the angle θ1 of the side surface of the lower end of the source electrode layer is , and the angle θ2 of the side surface of the lower end of the drain electrode layer is 20° or more and less than 90°, The side surface may have a step. In FIG. 2, the same reference numerals are used for the parts common to FIG. 1. .

[0060] A gate electrode 101 provided on a substrate 100 having an insulating surface is connected to a gate insulating layer 102. The gate insulating layer 102 is covered with the gate electrode 101, and the first wiring or the second wiring is disposed on the gate insulating layer 102 which overlaps the gate electrode 101. The first electrode layer 405 functions as the source electrode layer 405a or the drain electrode layer 405b. A buffer layer is provided on each of the source electrode layers 405a and the second wiring. A first buffer layer 404a is provided on the drain electrode layer 405b, and a second buffer layer 404b is provided on the drain electrode layer 405b. A first buffer layer 404a and a second buffer layer 404b are provided. The oxide semiconductor layer 403 is provided over the photoresist layer 404b.

[0061] The substrate 100 having an insulating surface, the gate electrode 101, and the gate insulating layer 102 are Since this is the same as the first embodiment, a detailed description will be omitted here.

[0062] The source electrode layer 405a and the drain electrode layer 405b may be formed of a single layer or different metal materials. The source electrode layer 405a and the drain electrode layer 405b are made of a metal. Materials (aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tang Stainless steel (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc) The element selected from the group consisting of aluminum, zinc, and an alloy containing the above elements is used.

[0063] Here, the source electrode layer 405a and the drain electrode layer 405b are made of 100 nm thick tantalum. A single layer of stainless steel was used, and an ICP etching system with a coil antenna was used. The side surfaces of the source electrode layer 405a and the drain electrode layer 405b are formed as shown in FIG. An example of this will be explained.

[0064] In this embodiment, the gas flow rate of CF4 is 25 (sccm), and the gas flow rate of Cl3 is 25 (sccm). ccm), and the O2 gas flow rate was 10 (sccm). 500W RF (13.56MHz) power is applied to generate plasma and perform etching. 10 W of RF (13.56 MHz) power was also applied to the substrate side (sample stage). A qualitatively negative self-bias voltage is applied. At least the gate insulating film 102 is exposed to some extent. By stopping this etching at this stage, the electrode side surface having a step is formed. will be done.

[0065] Under the above etching conditions, the cross-sectional shape of the source electrode layer 405a is such that the substrate surface of the substrate and the source The angle θ1 formed between the electrode layer 405a and the side surface of the lower end portion can be set to 20° or more and less than 90°. 2, θ1 is about 40°. The angle formed between the top end side surface of the oxide semiconductor layer 403 and the top end side surface of the oxide semiconductor layer 403 is approximately 90°. The cross-sectional shapes of the side surface of the source electrode layer 405a and the side surface of the drain electrode layer 405b facing each other are the same etched shape. They are almost identical because they go through a coating process.

[0066] In this way, the angle of the side surface of the upper end of the source electrode layer 405a (and the drain electrode layer 405b) The angle of the side surface of the lower end of the source electrode layer 405a (and the drain electrode layer 405b) is set to be larger than the angle of the side surface of the lower end of the source electrode layer 405a (and the drain electrode layer 405b). By reducing the thickness, the film thickness for forming the source electrode layer 405a and the drain electrode layer 405b can be reduced. The spacing between the mask (or resist mask) can be narrowed, resulting in a channel The channel length can be designed to be short, for example, 1 μm to 10 μm.

[0067] The method is not limited to the above. The etching rate of the etching gas used is different from that of the lower layer. When etching is performed using a material layer with a low grit and a material layer with a high etching rate on top, A step can be formed on the side surface of the electrode.

[0068] By providing a step on the side surfaces of two electrodes facing each other with the oxide semiconductor layer 403 interposed therebetween, The distance from the upper end to the lower end of the electrode on the side of the source electrode layer and the drain electrode layer is increased. By doing so, the length L3 of the first electric field concentration relaxation region 406a and the length L4 of the second electric field concentration relaxation region The length L4 of 406b is increased to alleviate the electric field concentration.

[0069] Furthermore, the distance from the upper end to the lower end of the electrode on the side surface of the source electrode layer and the drain electrode layer In order to increase the thickness, wet etching is further performed after the dry etching described above. The side surfaces of two electrodes facing each other with the oxide semiconductor layer 403 interposed therebetween may be partially curved.

[0070] Furthermore, the source electrode layer and the drain electrode layer are formed by etching, instead of the dry etching described above. By performing wet etching, at least the angle θ1 of the side surface of the lower end of the source electrode layer and the The angle θ2 of the side surface of the lower end of the rain electrode layer may be 20° or more and less than 90°, and the upper surface of the electrode Alternatively, the cross section may have a shape that widens from the top to the bottom of the substrate.

[0071] This embodiment mode can be freely combined with Embodiment Mode 1.

[0072] (Embodiment 3) In this embodiment mode, a thin film transistor and a manufacturing process thereof will be described with reference to FIGS. explain.

[0073] In FIG. 3(A), a light-transmitting substrate 100 is made of barium borosilicate glass or aluminum. A glass substrate such as borosilicate glass can be used.

[0074] Next, a conductive layer is formed on the entire surface of the substrate 100, and then a first photolithography process is performed. A resist mask is formed, and unnecessary parts are removed by etching to form wiring and electrodes (gate A gate wiring including an electrode 101, a capacitance wiring 108, and a first terminal 121 are formed. At this time, etching is performed so that at least the end of the gate electrode 101 is tapered. The top view at this stage is shown in Figure 3(A). The top view at this stage corresponds to Figure 5. do.

[0075] The gate wiring including the gate electrode 101, the capacitance wiring 108, and the first terminal 121 of the terminal portion are Tantalum (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium ( Elements selected from the group consisting of Cr, Nd, aluminum (Al), and copper (Cu), is an alloy containing the above elements as components, an alloy film containing a combination of the above elements, or It is formed from nitrides containing elements such as aluminum (Al) and copper (Cu). It is desirable to form it with a low-resistance conductive material, but aluminum alone has poor heat resistance and is prone to corrosion. Titanium (Ti), tantalum (Ta), tungsten (W), An element selected from molybdenum (Mo), chromium (Cr), and Nd (neodymium), or The film is formed of an alloy film combining the above elements, or a nitride film containing the above elements as components.

[0076] Next, a gate insulating layer 102 is formed on the entire surface of the gate electrode 101. The film 2 is formed to a thickness of 50 to 250 nm by using a sputtering method or the like.

[0077] For example, a silicon oxide film is used as the gate insulating layer 102 by sputtering, and the thickness is 100 nm. Of course, the gate insulating layer 102 is not limited to such a silicon oxide film. Silicon oxide nitride film, silicon nitride film, aluminum oxide, tantalum oxide film It may be formed as a single layer or a laminated structure made of these materials using other insulating films such as those mentioned above. stomach.

[0078] Next, a conductive film made of a metal material is formed on the gate insulating layer 102 by sputtering or vacuum deposition. The conductive film material is an element selected from Al, Cr, Ta, Ti, Mo, and W, or or an alloy containing the above elements as a component, or an alloy film of a combination of the above elements. Here, an aluminum (Al) film is used as the conductive film, and a thin film on the aluminum (Al) film is used. The conductive film may have a three-layer structure, and a Ti film is laminated on the tungsten film. The conductive film may have a single layer structure of an aluminum film containing silicon. Alternatively, a single layer structure of a tungsten film may be used.

[0079] Next, a first oxide semiconductor film (a first In-Ga-Zn-O In this example, a non-single crystal film (In2O3:Ga2O3:ZnO= The film formation conditions were a pressure of 0.4 Pa and a power of 500. The film formation temperature was set to room temperature, and argon gas flow rate was 40 sccm. A target of In2O3:Ga2O3:ZnO=1:1:1 was intentionally used. Despite this, the In-Ga-Zn film contains crystal grains of 1 nm to 10 nm in size immediately after deposition. -O-based non-single crystal film may be formed. Note that the target component ratio, film formation pressure (0. 1Pa~2.0Pa), power (250W~3000W: 8 inch diameter), temperature (room temperature~10 0℃), and by appropriately adjusting the film formation conditions of reactive sputtering, the presence or absence of crystal grains and the size of the crystal grains can be determined. It can be said that the density and diameter size can be adjusted in the range of 1 nm to 10 nm. The thickness of the Ga-Zn-O based non-single crystal film is set to 5 nm to 20 nm. When included, the size of the included crystal grains does not exceed the film thickness. In this example, the thickness of the first In—Ga—Zn—O based non-single-crystal film is set to 5 nm.

[0080] Next, a second photolithography step is performed to form a resist mask, and the first In- Etching of Ga-Zn-O based non-single crystal film. Here, ITO07N (Kanto Chemical Co., Ltd.) In the pixel area, unnecessary parts are removed by wet etching using -Ga-Zn-O based non-single crystal films 111a and 111b are formed. The etching is not limited to wet etching, but dry etching may also be used.

[0081] Next, using the same resist mask as that used in etching the first In-Ga-Zn-O based non-single crystal film, Then, unnecessary portions are removed by etching to form the source electrode layer 105a and the drain electrode layer 105b. The etching method used here may be wet etching or dry etching. Here, a mixture of SiCl4, Cl2 and BCl3 is used as the reaction gas. The conductive film, which is a laminate of an Al film and a Ti film, is etched by dry etching. The electrode layer 105a and the drain electrode layer 105b are formed. A cross-sectional view at this stage is shown in FIG. The top view at this stage is shown in Figure 6.

[0082] This etching reduces the amount of the source electrode layer 105a that will be in contact with the oxide semiconductor layer to be formed later. and the angle θ2 of the side surface of the drain electrode layer 105b is set to 20° or more and less than 90°. By tapering the side surfaces of the two electrodes that face each other with the oxide semiconductor layer sandwiched between them, The regions of the oxide semiconductor layer that overlap with the side surfaces of the source electrode layer and the drain electrode layer are It can function as a field concentration relaxation region.

[0083] In this second photolithography step, the source electrode layer 105a and the drain electrode layer 105b are The second terminal 122 made of the same material as the electrode layer 105b is left in the terminal portion. 122 is electrically connected to the source wiring (source wiring including the source electrode layer 105a). In addition, in the terminal portion, the second terminal 122 is located above the second terminal 122. The first In—Ga—Zn—O based non-single-crystal film 123 overlapping the first In—Ga—Zn—O based non-single-crystal film 123 remains.

[0084] In the capacitor portion, the same material as the source electrode layer 105a and the drain electrode layer 105b is used. The capacitor electrode layer 124 is left as it is. The first In—Ga—Zn—O-based non-single-crystal film 111c overlapping the capacitor electrode layer 124 remains.

[0085] Next, after removing the resist mask, the second oxide semiconductor film (in this embodiment) was formed without being exposed to the air. In this case, a second In-Ga-Zn-O-based non-single crystal film is formed. Depositing the second In-Ga-Zn-O based non-single crystal film without exposing it to air is effective in improving the gate insulation. This is useful in that it prevents dust and other foreign matter from adhering to the interface between the insulating layer and the semiconductor film. The oxide semiconductor target containing In, Ga, and Zn (In2O3:Ga2O3:Z nO=1:1:1), the distance between the substrate and the target was 170 mm, and the pressure was 0.4 The film was formed at 100 Pa, with a direct current (DC) power supply of 0.5 kW, under an argon or oxygen atmosphere. Using a direct current (DC) power supply is preferable because it reduces dust and makes the film thickness distribution uniform. The thickness of the second In—Ga—Zn—O based non-single crystal film is set to 5 nm to 200 nm. In this embodiment, the thickness of the second In—Ga—Zn—O based non-single-crystal film is 100 nm.

[0086] The second In-Ga-Zn-O based non-single crystal film is By changing the film formation conditions from the first In-Ga-Zn-O based non-single crystal film, the electrical resistance of the second In-Ga-Zn-O based non-single crystal film is reduced. For example, under the film formation conditions of the first In-Ga-Zn-O based non-single crystal film, The ratio of the oxygen gas flow rate to the argon gas flow rate is used to determine the thickness of the second In-Ga-Zn-O system non-single crystal film. The film formation conditions are set so that the ratio of the oxygen gas flow rate is high. Specifically, the first I The conditions for forming n-Ga-Zn-O non-single crystal films are rare gas (argon, helium, etc.) In the atmosphere (or oxygen gas 10% or less, argon gas 90% or more), the second In-G The conditions for forming the a-Zn-O non-single crystal film were an oxygen atmosphere (or oxygen gas flow rate and argon gas flow rate). The ratio of the flow rate to the gas flow rate shall be 1:1 or more.

[0087] Next, it is preferable to carry out a heat treatment at 200°C to 600°C, typically 300°C to 500°C. Here, the sample is placed in a furnace and heat-treated at 350°C for 1 hour in a nitrogen or air atmosphere. This heat treatment causes rearrangement at the atomic level in the In-Ga-Zn-O non-single crystal film. This heat treatment releases the distortion that inhibits carrier movement. The timing of the heat treatment (including photo-annealing) is important. There are no particular limitations as long as it is performed after the formation of an a-Zn-O based non-single crystal film, for example, after the formation of a pixel electrode. It is also possible.

[0088] Next, a third photolithography process is performed to form a resist mask and then etching is performed. The unnecessary portions are removed to form the semiconductor layer 103. The second In-Ga-Zn-O non-single crystal film was then formed by wet etching using a SiO2 film (manufactured by SiO2). The semiconductor layer 103 is formed by removing the film by wet etching. The oxide semiconductor can be regenerated from the waste liquid and reused for manufacturing targets.

[0089] Indium and gallium contained in oxide semiconductors are known to be rare metals. It is known that recycling can save resources and also The cost of the manufactured product can be reduced.

[0090] The first In-Ga-Zn-O based non-single-crystal film and the second In-Ga-Zn-O based non-single-crystal film Since the crystal film uses the same etchant, the etching here produces the first In-Ga-Z Therefore, the second In-Ga-Zn-O based non-single crystal film is removed. The side of the covered first In-Ga-Zn-O based non-single crystal film is protected, but as shown in FIG. As shown, the exposed first In-Ga-Zn-O based non-single-crystal films 111a and 111b is etched to form a first buffer layer 104a and a second buffer layer 104b. The etching of the semiconductor layer 103 is not limited to wet etching, but may be dry etching. By the above steps, a thin film transistor having the semiconductor layer 103 as a channel forming region is formed. The cross section at this stage is shown in FIG. The top view in Fig. 7 corresponds to Fig. 7.

[0091] Next, the resist mask is removed, and a protective insulating film 107 is formed to cover the semiconductor layer. The insulating film 107 is a silicon nitride film, a silicon oxide film, a nitriding film, etc. obtained by sputtering. silicon oxide film, aluminum oxide film, aluminum oxynitride film, tantalum oxide film, etc. You can be there.

[0092] Next, a fourth photolithography step is performed to form a resist mask, and a protective insulating film 1 A contact hole 125 reaching the drain electrode layer 105b is formed by etching in step 07. In addition, the etching here forms a contact hole 122 that reaches the second terminal 122. Also, a contact hole reaching the capacitor electrode layer 124 is formed by etching here. In order to reduce the number of masks, the same resist mask is used to form the hole 109. Furthermore, the gate insulating layer is etched to form a contact hole 126 that reaches the gate electrode, at the same level. It is preferable to form the mask using a resist mask. The cross section at this stage is shown in Figure 4(B).

[0093] Next, the resist mask is removed, and then a transparent conductive film is formed. are indium oxide (In2O3) and indium oxide tin oxide alloy (In2O3-SnO 2, abbreviated as ITO) is formed using a sputtering method or a vacuum deposition method. Etching of such materials is done with a hydrochloric acid solution. However, etching of ITO in particular Residues tend to be generated, so indium oxide zinc oxide alloy is used to improve etching processability. Gold (In2O3-ZnO) may also be used.

[0094] Next, a fifth photolithography step is performed to form a resist mask and then to perform etching. The pixel electrode 110 is formed by removing unnecessary portions.

[0095] In this fifth photolithography step, the gate insulating layer 10 in the capacitance section 2 serves as a dielectric, and the capacitor electrode layer 124 and pixel electrode 110 form a storage capacitor. The wiring 108 is electrically connected to the capacitor electrode layer 124 through a contact hole 109 .

[0096] In the fifth photolithography step, the first terminal and the second terminal are formed by resist. The transparent conductive films 128 and 129 formed on the terminal portions are left covered with a mask. 8, 129 are electrodes or wiring used for connection with the FPC. The formed transparent conductive film 129 is a connection terminal electrode that functions as an input terminal of the source wiring. is.

[0097] Next, the resist mask is removed, and the cross-sectional view at this stage is shown in FIG. The top view at this stage corresponds to Figure 8.

[0098] 9(A1) and 9(A2) are a top view and a cross section of the gate wiring terminal portion at this stage. 9(A1) is a cross section taken along line C1-C2 in FIG. 9(A2). 9A. In FIG. 9A, a transparent conductive film 15 is formed on a protective insulating film 154. 5 is a terminal electrode for connection that functions as an input terminal. In the terminal section, a first terminal 151 made of the same material as the gate wiring and a second terminal 152 made of the same material as the source wiring are provided. The transparent conductive film 1 is formed by a gate insulating layer 152 and a connection electrode 153 made of a material. 55. The transparent conductive film 128 and the first terminal 12 shown in FIG. 9A1 and the first terminal 151 are in contact with each other. This corresponds to the part that is being

[0099] 9(B1) and 9(B2) show a source line terminal portion different from that shown in FIG. 4(C). 9(B1) shows a top view and a cross-sectional view of the source wiring terminal portion. This corresponds to a cross-sectional view taken along the line D1-D2 in FIG. 9(B2). The transparent conductive film 155 formed on the insulating film 154 is a connection terminal that functions as an input terminal. In FIG. 9(B1), the terminal portion is made of the same material as the gate wiring. The electrode 156 is electrically connected to the source line and is disposed below the second terminal 150. The electrode 156 is not electrically connected to the second terminal 150. The electrode 156 is set to a potential different from that of the second terminal 150, for example, floating, GND, 0V, etc. By setting the capacitance as a countermeasure against noise or static electricity, The second terminal 150 is electrically connected to the transparent conductive film 155 via the protective insulating film 154. are emotionally connected.

[0100] A plurality of gate wirings, source wirings, and capacitance wirings are provided depending on the pixel density. In addition, in the terminal section, a first terminal has the same potential as the gate wiring, a second terminal has the same potential as the source wiring, and The second terminal, the third terminal with the same potential as the capacitance wiring, and so on are arranged in a row. The number of terminals may be any number and may be determined appropriately by the implementer.

[0101] In this way, five photolithography processes were carried out using five photomasks to create the bottom A pixel having a thin film transistor 170 which is a gate-type n-channel thin film transistor. The thin film transistor and storage capacitor can be completed. By arranging the pixels in a matrix corresponding to the active matrix type, For the sake of convenience, the present specification will discuss such a substrate. Such a substrate is called an active matrix substrate.

[0102] When manufacturing an active matrix liquid crystal display device, an active matrix substrate a liquid crystal layer is provided between the active matrix substrate and an opposing substrate on which an opposing electrode is provided; The common electrode is electrically connected to the counter electrode provided on the counter substrate. A fourth terminal electrically connected to the common electrode is provided on the active matrix substrate. This fourth terminal is used to set the common electrode to a fixed potential, such as GND or 0V. This is a terminal for connecting the

[0103] In addition, this embodiment is not limited to the pixel configuration of FIG. 8, and an example of a top view different from that of FIG. 8 is shown in FIG. In FIG. 10, no capacitance wiring is provided, and the pixel electrodes are arranged adjacent to each other using the gate insulating layer as a dielectric. In this example, a storage capacitor is formed by a gate wiring of a pixel and a capacitor electrode layer that overlaps with the gate insulating layer. In this case, the capacitance wiring and the third terminal connected to the capacitance wiring can be omitted. In addition, in Fig. 10, the same parts as in Fig. 8 are described using the same reference numerals.

[0104] In an active matrix liquid crystal display device, pixel electrodes arranged in a matrix form By driving the selected pixels, a display pattern is formed on the screen. A voltage is applied between the electrode and the counter electrode corresponding to the pixel electrode. The liquid crystal layer disposed between the electrode and the counter electrode is optically modulated, and this optical modulation produces a display pattern. is perceived by the observer as

[0105] When displaying moving images on a liquid crystal display device, the response of the liquid crystal molecules themselves is slow, which can cause afterimages. In order to improve the moving image characteristics of the LCD device, There is a driving technique called black insertion, which displays black every other frame.

[0106] In addition, the response speed can be improved by increasing the normal vertical cycle by 1.5 or 2 times or more. Also, the gradation to be written for each divided field in each frame is selected, so-called double speed. There is also a drive technology called drive.

[0107] In addition, in order to improve the video characteristics of the LCD display, multiple LEDs (light emitting diodes) are used as backlights. A surface light source is formed by using a diode) light source or multiple EL light sources, etc., and a surface light source is formed. There is also a driving technology that drives each light source to light intermittently within one frame period. Therefore, three or more types of LEDs may be used, or white-emitting LEDs may be used. Since multiple LEDs can be controlled, the LE can be switched in accordance with the timing of the optical modulation of the liquid crystal layer. This driving technology can also synchronize the timing of the LEDs to be turned off. This is especially useful when displaying images with a large proportion of black areas occupying the entire screen. This can reduce power consumption.

[0108] By combining these driving technologies, the display characteristics such as the video characteristics of the LCD device can be improved. can be improved compared to the past.

[0109] The n-channel transistor obtained in this embodiment is an In-Ga-Zn-O based non-single crystal The semiconductor layer of the crystal film is used in the channel formation region, and has good dynamic characteristics. Drive technologies can be combined.

[0110] In addition, when a light-emitting display device is manufactured, one electrode (also called a cathode) of the organic light-emitting element is In order to set the low power supply potential, for example, GND or 0V, the cathode is connected to the terminal. A fourth terminal is provided for setting the voltage level, for example, GND, 0V, etc. When manufacturing a device, a power supply line is provided in addition to a source line and a gate line. Therefore, the terminal section is provided with a fifth terminal that is electrically connected to the power supply line.

[0111] In this embodiment mode, a gate electrode layer, a gate insulating layer, a source electrode layer, a drain electrode layer, a silicon nitride film, and a silicon nitride film are formed. a source region or a drain region (an oxide semiconductor layer containing In, Ga, and Zn), a semiconductor layer ( a thin-film transistor having a stacked structure of a semiconductor layer (oxide semiconductor layer containing In, Ga, and Zn) The surface of the gate insulating layer is modified by plasma treatment, and the thickness of the semiconductor layer is reduced to a thin film. Even if the thin film is thin, the parasitic capacitance can be suppressed. Since the proportion of the capacitance is sufficient, the parasitic capacitance is sufficiently suppressed.

[0112] According to this embodiment, a thin film transistor with a high on-off ratio can be obtained, and good operation can be achieved. Therefore, it is possible to manufacture thin film transistors with high electrical properties and high reliability. A semiconductor device having a transistor can be provided.

[0113] (Fourth embodiment) In this embodiment, an example of electronic paper will be shown as a semiconductor device.

[0114] FIG. 11 shows an active matrix type electronic device as an example of a semiconductor device different from a liquid crystal display device. The thin film transistor 581 used in the pixel portion of the semiconductor device is It can be fabricated in the same manner as the thin film transistor of the pixel portion shown in the third embodiment, and is an In-Ga-Zn-O system The thin film transistor includes a non-single crystal film as a semiconductor layer. As shown in the figure, the side surfaces of the two electrodes facing each other with the oxide semiconductor layer sandwiched between them are tapered, so that the To realize electronic paper equipped with highly reliable thin film transistors with field relaxation regions. This can be done.

[0115] The electronic paper in Figure 11 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. and a potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying by generating a magnetic field and controlling the orientation of spherical particles.

[0116] The thin film transistor 581 is a thin film transistor with a bottom gate structure, and the source electrode layer The drain electrode layer is in contact with the first electrode layer 587 through an opening formed in the insulating layer 585. The first electrode layer 587 and the second electrode layer 588 are electrically connected to each other. 90a and white area 590b, and includes a cavity 594 filled with liquid therearound. The spherical particles 589 are provided with a filler 595 such as a resin. It is filled (see Figure 11).

[0117] Also, instead of the twist ball, an electrophoretic element can be used. and a diameter of 10 μm to 20 μm that contains positively charged white particles and negatively charged black particles. Microcapsules of about 0 μm in size are used. When an electric field is applied by the first and second electrode layers, the microcapsules turn white. White particles and black particles move in opposite directions, allowing the display to be white or black. A display element that applies this principle is an electrophoretic display element, also known as electronic paper. Since electrophoretic display elements have a higher reflectivity than liquid crystal display elements, auxiliary lights are not required. It consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the , a semiconductor device with a display function (simply a display device, or a semiconductor device equipped with a display device) from a radio wave source Even if the device (also called the body device) is moved away, the displayed image can be saved. become.

[0118] By the above process, electronic paper can be manufactured as a semiconductor device with reduced manufacturing costs. This can be done.

[0119] This embodiment is applicable to the configuration described in the first, second, or third embodiment. It is possible to carry out any combination of these.

[0120] (Embodiment 5) In this embodiment, in a display device which is an example of a semiconductor device, at least An example of manufacturing a part of a driver circuit and a thin film transistor disposed in a pixel portion will be described below. do.

[0121] The thin film transistor disposed in the pixel portion is formed according to the first or second embodiment. The thin film transistor described in Embodiment 1 or 2 is an n-channel TFT. Therefore, some of the driver circuits can be configured with n-channel TFTs. The thin film transistors in the pixel portion are formed on the same substrate.

[0122] FIG. 1 shows an example of a block diagram of an active matrix liquid crystal display device, which is an example of a semiconductor device. 12(A). The display device shown in FIG. 12(A) is a display device having a display element on a substrate 5300. A pixel portion 5301 having a plurality of pixels, a scanning line driver circuit 5302 for selecting each pixel, and a scanning line driver circuit 5303 for selecting each pixel. and a signal line driver circuit 5303 for controlling input of a video signal to the pixel.

[0123] The pixel portion 5301 is a signal line driver circuit 5303. The signal line driver circuit 5303 is arranged to extend in the column direction. The signal line driver circuit 5303 is connected to the signal line driver circuit 5303 by lines S1 to Sm (not shown). A plurality of scanning lines G1 to Gn (not shown) are arranged extending from 5302 in the row direction. The scanning line driver circuit 5302 is connected to the signal lines S1 to Sm and the scanning lines G1 to Gn. The image sensor has a plurality of pixels (not shown) arranged in a matrix. signal line Sj (one of the signal lines S1 to Sm), scanning line Gi (one of the scanning lines G1 to Gn), (either one) is connected.

[0124] The thin film transistor described in Embodiment 1 or 2 is an n-channel TFT. A signal line driver circuit configured with n-channel TFTs will be described with reference to FIG.

[0125] The signal line driver circuit shown in FIG. 13 includes a driver IC 5601 and a group of switches 5602_1 to 5602_56. 02_M, a first wiring 5611, a second wiring 5612, a third wiring 5613 and a wiring 56 Each of the switch groups 5602_1 to 5602_M includes: A first thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor It has a transistor 5603c.

[0126] The driver IC 5601 is connected to a first wiring 5611, a second wiring 5612, and a third wiring 5613. and are connected to the wirings 5621_1 to 5621_M. 5602_M are connected to the first wiring 5611, the second wiring 5612, and the third wiring 561 3 and wiring 5621_1 to 5621_5 corresponding to the switch groups 5602_1 to 5602_M, respectively. Each of the wirings 5621_1 to 5621_M is connected to the first A thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor For example, the wiring 5621 in the Jth column is connected to three signal lines via a resistor 5603c. _J (one of the wirings 5621_1 to 5621_M) is connected to the switch group 5602 The first thin film transistor 5603a, the second thin film transistor 5603b, and and the third thin film transistor 5603c, the signal line Sj-1, the signal line Sj, the signal line S j+1 is connected to the

[0127] The first wiring 5611, the second wiring 5612, and the third wiring 5613 are each connected to a signal line. The number is entered.

[0128] It is desirable that the driver IC 5601 be formed on a single crystal semiconductor substrate. Furthermore, the switch group 5602_1 to 5602_M is formed on the same substrate as the pixel section. Therefore, the driver IC 5601 and the switch group 5602_1 to 5602_56 It is recommended to connect to 02_M via an FPC or similar.

[0129] Next, the operation of the signal line driver circuit shown in FIG. 13 will be described with reference to the timing chart of FIG. The timing chart in FIG. 14 will be explained with reference to the timing chart when the i-th scanning line Gi is selected. Furthermore, the timing chart shows the selection period of the i-th scanning line Gi. is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, when a scanning line of another row is selected, the signal line driving circuit of FIG. In this case, the same operation as in FIG. 14 is performed.

[0130] In the timing chart of FIG. 14, the wiring 5621_J in the Jth column is connected to the first thin-film transistor. a second thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor 560 When connected to signal line Sj-1, signal line Sj, and signal line Sj+1 via 3c It shows.

[0131] In the timing chart of FIG. 14, the timing at which the i-th scanning line Gi is selected, The on / off timing 5703a of the first thin film transistor 5603a, The on / off timing 5703b of the third thin film transistor 56 The on / off timing of 03c is input to 5703c and the J-th row wiring 5621_J. Signal 5721_J is shown.

[0132] The wirings 5621_1 to 5621_M are connected to the first sub-selection period T1 and the second sub-selection period T2. In the first sub-selection period T2 and the third sub-selection period T3, different video signals are input. For example, the video signal input to the wiring 5621_J in the first sub-selection period T1 is The signal is input to the signal line Sj-1 and input to the wiring 5621_J in the second sub-selection period T2. The video signal to be output is input to the signal line Sj, and the signal is output to the wiring 5621 during the third sub-selection period T3. The video signal input to the first sub-selection period is input to the signal line Sj+1. During the period T1, the second sub-selection period T2, and the third sub-selection period T3, the wiring 5621_ The video signals input to J are Data_j-1, Data_j, and Data_j+ Let's say it's 1.

[0133] As shown in FIG. 14, in the first sub-selection period T1, the first thin film transistor 5603 a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c At this time, Data_j-1 input to the wiring 5621_J is turned off. The signal is input to the signal line Sj-1 via the transistor 5603a. Second sub-selection period T2 In this case, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a The third thin film transistor 5603c is turned off. The output Data_j is input to the signal line Sj via the second thin film transistor 5603b. In the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first The first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the third thin film transistor 56 It is input to the signal line Sj+1 via 03c.

[0134] From the above, the signal line driver circuit in FIG. 13 can achieve the following by dividing one gate selection period into three. During one gate selection period, a video signal is input from one wiring 5621 to three signal lines. Therefore, the signal line driver circuit of FIG. The number of connections between the substrate on which the display is mounted and the substrate on which the pixel section is formed is reduced to about one-third of the number of signal lines. By reducing the number of connections to about one-third, the signal line driver circuit of FIG. This can improve productivity and yield.

[0135] As shown in Figure 13, one gate selection period is divided into multiple sub-selection periods, and multiple sub-selection periods are During each selection period, a video signal is input from one line to each of multiple signal lines. As long as this can be achieved, there are no limitations on the arrangement, number, driving method, etc. of the thin film transistors.

[0136] For example, three or more signal lines are connected to one wiring in each of three or more sub-selection periods. When a video signal is input to each, a thin film transistor and a thin film transistor are controlled. However, it is necessary to divide one gate selection period into four or more sub-selection periods. Therefore, one gate selection period is divided into two or Preferably, it is divided into three sub-selection periods.

[0137] As another example, as shown in the timing chart of FIG. 15, one selection period is precharged. The first sub-selection period Tp, the first sub-selection period T1, the second sub-selection period T2, and the third selection period T3 are Furthermore, in the timing chart of FIG. 15, the i-th scanning line Gi is selected. the timing at which the first thin film transistor 5603a is turned on and off; a, the on / off timing 5803b of the second thin film transistor 5603b, The on / off timing 5803c of the membrane transistor 5603c and the J-th column wiring 562 15, the signal 5821_J input to the precharge During the period Tp, the first thin film transistor 5603a and the second thin film transistor 5603 At this time, the input to the wiring 5621_J is turned on. The input precharge voltage Vp is applied to the first thin film transistor 5603a, the second thin film transistor 5603b, and the and the signal line Sj- 1, signal line Sj, and signal line Sj+1. The thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor At this time, the membrane transistor 5603c is turned off. a_j-1 is input to the signal line Sj-1 via the first thin film transistor 5603a. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor The third thin film transistor 5603a and the third thin film transistor 5603c are turned off. Data_j input to the wiring 5621_J is input to the second thin film transistor 5603b. During the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5 At this time, Data_j+1 input to the wiring 5621_J is The signal is input to the signal line Sj+1 via the third thin film transistor 5603c.

[0138] From the above, the signal line driver circuit of FIG. 13 to which the timing chart of FIG. 15 is applied By providing a precharge selection period before the block selection period, the signal lines can be precharged. This allows for high-speed writing of video signals to the pixels. 14 are denoted by the same reference numerals, and the same parts or similar functions are shown. A detailed description of the portion having the symbol will be omitted.

[0139] The configuration of the scanning line driving circuit will be described. The scanning line driving circuit includes a shift register, a buffer, and a In some cases, a level shifter may be included. In the circuit, a clock signal (CLK) and a start pulse signal (SP) are input to the shift register. ) is input, the selection signal is generated. The generated selection signal is The signal is buffered and amplified in the scanning line and then supplied to the corresponding scanning line. The gate electrodes of the transistors are connected. Since they must all be turned on at the same time, the buffer must be able to pass a large current. It is used.

[0140] One form of a shift register used as part of a scanning line driving circuit is shown in FIGS. 16 and 17. I will explain.

[0141] The circuit configuration of the shift register is shown in Figure 16. The shift register shown in Figure 16 has multiple free Flip-flop 5701_i (any of flip-flops 5701_1 to 5701_n) It also consists of a first clock signal, a second clock signal, a start pulse It operates when a signal and a reset signal are input.

[0142] The connection relationship of the shift register in Fig. 16 will be explained. The shift register in Fig. 16 has i-stage Flip-flop 5701_i (flip-flop 5701_1~5701_n) In either case, the first wiring 5501 shown in FIG. 17 is connected to the seventh wiring 5717_i-1. 17 is connected to the seventh wiring 5717_i+1. 17 is connected to the seventh wiring 5717_i, and The sixth wiring 5506 is connected to the fifth wiring 5715 .

[0143] In addition, the fourth wiring 5504 shown in FIG. 17 is the second wiring in the odd-numbered flip-flops. 5712, and in the even-numbered flip-flops, it is connected to the third wiring 5713. The fifth wiring 5505 shown in FIG.

[0144] However, the first wiring 5501 shown in FIG. 17 of the first-stage flip-flop 5701_1 is 17 of the n-th stage flip-flop 5701_n. The second wiring 5502 is connected to the sixth wiring 5716 .

[0145] The first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 57 16 can be called the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fourth wiring 5714 and the fifth wiring 5715 are respectively connected to the first power supply line and the This may also be called the power line 2.

[0146] Next, the details of the flip-flop shown in FIG. 16 are shown in FIG. 17. The flip-flop includes a first thin film transistor 5571, a second thin film transistor 5572, A third thin film transistor 5573, a fourth thin film transistor 5574, a fifth thin film transistor a sixth thin film transistor 5575, a sixth thin film transistor 5576, a seventh thin film transistor 5577, and and an eighth thin film transistor 5578. A second thin film transistor 5572, a third thin film transistor 5573, a fourth thin film transistor a fifth thin film transistor 5574, a fifth thin film transistor 5575, a sixth thin film transistor 5576, The seventh thin film transistor 5577 and the eighth thin film transistor 5578 are n-channel A transistor in which the gate-source voltage (Vgs) exceeds the threshold voltage (Vth) When this occurs, the device is in a conductive state.

[0147] Next, the connection configuration of the flip-flop shown in FIG. 16 will be described below.

[0148] A first electrode (either a source electrode or a drain electrode) of the first thin film transistor 5571 is connected to a fourth wiring 5504, and a second electrode (source) of the first thin film transistor 5571 is connected to a The other of the source electrode and the drain electrode is connected to a third wiring 5503 .

[0149] A first electrode of the second thin film transistor 5572 is connected to the sixth wiring 5506, and A second electrode of the thin film transistor 5572 is connected to a third wiring 5503 .

[0150] A first electrode of the third thin film transistor 5573 is connected to a fifth wiring 5505. The second electrode of the thin film transistor 5573 is the gate electrode of the second thin film transistor 5572. , and the gate electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505. will be done.

[0151] A first electrode of the fourth thin film transistor 5574 is connected to a sixth wiring 5506, and The second electrode of the thin film transistor 5574 is the gate electrode of the second thin film transistor 5572. , and the gate electrode of the fourth thin film transistor 5574 is connected to the first thin film transistor 5 It is connected to the gate electrode of 571.

[0152] A first electrode of the fifth thin film transistor 5575 is connected to a fifth wiring 5505. The second electrode of the thin film transistor 5575 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501. will be done.

[0153] A first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506. The second electrode of the thin film transistor 5576 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the sixth thin film transistor 5576 is connected to the second thin film transistor 5 It is connected to the gate electrode of 572.

[0154] A first electrode of the seventh thin film transistor 5577 is connected to the sixth wiring 5506. The second electrode of the thin film transistor 5577 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the seventh thin film transistor 5577 is connected to the second wiring 5502. A first electrode of the eighth thin film transistor 5578 is connected to the sixth wiring 5506. The second electrode of the eighth thin film transistor 5578 is connected to the gate of the second thin film transistor 5572. The gate electrode of the eighth thin film transistor 5578 is connected to the first wiring 550. Connected to 1.

[0155] The gate electrode of the first thin film transistor 5571 and the gate electrode of the fourth thin film transistor 5574 the gate electrode of the fifth thin film transistor 5575, the second electrode of the sixth thin film transistor The connection point of the second electrode of the seventh thin film transistor 5576 and the second electrode of the seventh thin film transistor 5577 is Further, the gate electrode of the second thin film transistor 5572, the gate electrode of the third thin film transistor 5573, and the gate electrode of the third thin film transistor 5574 are connected to the gate electrode of the second thin film transistor 5575. a second electrode of the fourth thin film transistor 5573; a second electrode of the fourth thin film transistor 5574; The gate electrode of the sixth thin film transistor 5576 and the gate electrode of the eighth thin film transistor 5578 The connection point of the two electrodes is designated as node 5544.

[0156] The first wiring 5501, the second wiring 5502, the third wiring 5503 and the fourth wiring 5504 are 504 can be called the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fifth wiring 5505 is a first power supply line, and the sixth wiring 5506 is a second power supply line. It can also be called.

[0157] In addition, the signal line driver circuit and the scanning line driver circuit may be the same as those shown in the first or second embodiment. It is also possible to fabricate a transistor using only a panel-type TFT. Since the mobility is large, it is possible to increase the driving frequency of the driving circuit. The n-channel TFT shown in Embodiment 1 or 2 has a source region or a drain region. Since the parasitic capacitance is reduced, the frequency characteristics (called f characteristics) are high. The scanning line driver circuit using the n-channel TFT shown in Embodiment 1 or 2 operates at high speed. This allows for a higher frame rate or the insertion of a black screen. It is also possible to achieve things like this.

[0158] Furthermore, the channel width of the transistor of the scanning line driving circuit can be increased, and multiple scanning lines can be formed. By arranging the drive circuit, it is possible to achieve an even higher frame frequency. When multiple scanning line driving circuits are arranged, the scanning line driving circuits for driving the even-numbered scanning lines are The circuit for driving the odd-numbered scanning lines is placed on one side, and the scanning line driving circuit for driving the odd-numbered scanning lines is placed on the other side. By placing the frame frequency at a higher level, it is possible to increase the frame frequency.

[0159] In addition, when an active matrix light-emitting display device, which is an example of a semiconductor device, is manufactured, At least one pixel is provided with a plurality of thin film transistors, so that multiple scanning line driving circuits are required. An example of a block diagram of an active matrix light emitting display device is shown in FIG. 2(B).

[0160] The light-emitting display device shown in FIG. 12B has a plurality of pixels each having a display element over a substrate 5400. A pixel portion 5401 for selecting each pixel, a first scanning line driver circuit 5402 for selecting each pixel, and a second scanning line driver circuit 5403 for selecting each pixel. A driver circuit 5404 and a signal line driver circuit 5405 for controlling the input of a video signal to a selected pixel 403 and

[0161] When a video signal input to a pixel of the light-emitting display device shown in FIG. 12(B) is in a digital format, When a pixel is turned on, it emits light or does not emit light by switching the transistor on or off. Therefore, gray scale display can be performed using area gray scale or time gray scale. The stacked gray scale method divides one pixel into multiple sub-pixels, and each sub-pixel is independently driven based on a video signal. The time gray scale method is a driving method that displays gray scales by moving the pixel. This is a driving method that displays gradation by controlling the period during which the light is turned on.

[0162] Light-emitting elements have a higher response speed than liquid crystal elements, making them more suitable for time gray scale modulation than liquid crystal elements. Specifically, when displaying using the time gray scale method, one frame period is divided into multiple subframes. Then, in accordance with the video signal, the light emitting element of the pixel is By dividing the period into multiple subframes, The total length of the period during which pixels actually emit light during one frame is controlled by the video signal. It is possible to control the brightness and display gradation.

[0163] In the light-emitting display device shown in FIG. 12B, one pixel has a switching TFT and a When two TFTs are arranged, the first TFT is the gate wiring of the switching TFT. The signal input to the scanning line is generated by the first scanning line driver circuit 5402, and the current control TFT A signal input to the second scanning line, which is the gate wiring of the second scanning line, is generated by a second scanning line driver circuit 5404. The example shows a signal input to the first scanning line and a signal input to the second scanning line. The signals to be output may be generated by a single scanning line driving circuit. The operation of the switching element is controlled by the number of transistors that the switching element has. In this case, a plurality of first scanning lines may be provided for each pixel. Alternatively, all of the signals input to the plurality of first scanning lines may be generated by one scanning line driver circuit. Alternatively, the signals may be generated by a plurality of scanning line driving circuits.

[0164] In addition, in the light-emitting display device, the driver circuit may be configured with an n-channel TFT. A part of the driver circuit can be formed on the same substrate as the thin film transistor of the pixel portion. In addition, the signal line driver circuit and the scanning line driver circuit may be the same as those shown in Embodiment 1 or 2. It is also possible to fabricate the device using only channel TFTs.

[0165] Through the above steps, a highly reliable display device can be manufactured as a semiconductor device.

[0166] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0167] (Embodiment 6) In this embodiment mode, a light-emitting display device is shown as an example of a semiconductor device. Here, a light-emitting element that uses electroluminescence is used as the element. Light-emitting devices that utilize electroluminescence are either organic or inorganic compounds that emit light. Generally, the former is called an organic EL element and the latter is called an inorganic EL element. It's been discovered.

[0168] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0169] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0170] FIG. 18 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0171] The configuration and operation of a pixel to which digital time gray scale driving can be applied will be described. The n-type semiconductor uses an oxide semiconductor layer (In-Ga-Zn-O based non-single crystal film) in the channel formation region. 1 shows an example in which two channel-type transistors are used in one pixel.

[0172] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, It has a light emitting element 6404 and a capacitor element 6403. 01 has a gate connected to a scanning line 6406 and a first electrode (one of the source and drain electrodes) The first electrode (the other of the source electrode and the drain electrode) is connected to a signal line 6405, and the second electrode (the other of the source electrode and the drain electrode) is connected to a drive The driving transistor 6402 is connected to the gate of the driving transistor 6402. The gate is connected to a power supply line 6407 via a capacitor element 6403, and the first electrode is connected to a power supply line 640 7, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to the common electrode 6408 .

[0173] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. The low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. Then, in order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or greater than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0174] The capacitor element 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. The gate capacitance of the driving transistor 6402 is determined by the channel region A capacitance may be formed between the gate electrode and the transistor.

[0175] In the case of a voltage input voltage driving method, the gate of the driving transistor 6402 is connected to The driving transistor 6402 is either fully on or off. A video signal is input, that is, the driving transistor 6402 is operated in a linear region. The driving transistor 6402 is operated in a linear region, so that the voltage of the driving transistor 6402 is higher than the voltage of the power supply line 6407. A high voltage is applied to the gate of the driving transistor 6402. The signal line 6405 is connected to A voltage equal to or greater than (power supply line voltage+Vth of the driving transistor 6402) is applied.

[0176] Furthermore, when analog grayscale driving is performed instead of digital time grayscale driving, the input of the signal is different. By using the same pixel configuration as in FIG. 18, it is possible to use the same pixel configuration as in FIG.

[0177] When analog gradation driving is performed, a light emitting element 6404 is connected to the gate of a driving transistor 6402. A voltage equal to or greater than the forward voltage of the light emitting element 64 and the Vth of the driving transistor 6402 is applied. The forward voltage in 04 refers to the voltage required to achieve the desired brightness, and It should be noted that the driving transistor 6402 is designed to operate in the saturation region. By inputting an optical signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is The potential of the light emitting element is made higher than the gate potential of the capacitor 6402. A current corresponding to a video signal is passed through 6404, enabling analog gradation driving.

[0178] Note that the pixel configuration shown in Fig. 18 is not limited to this. For example, A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added.

[0179] Next, the structure of the light emitting element will be explained with reference to FIGS. 19(A), 19(B), and 19(C). Here, the case where the driving TFT is the thin film transistor 170 shown in FIG. 1(B) is taken as an example. The cross-sectional structure of the pixel will be described with reference to FIGS. 19(A), 19(B), and 19(C). The TFTs 7001, 7011, and 7021 are driver TFTs used in the semiconductor device , which can be manufactured in the same manner as the thin film transistor 170 shown in Embodiment 1. The thin film transistor has excellent electrical characteristics and includes a non-single-crystal film as a semiconductor layer.

[0180] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and top emission. There are light-emitting elements with a double-sided emission structure in which light is emitted from the side surface. The present invention can also be applied to a light emitting element with an injection structure.

[0181] A light emitting element with a top emission structure will be described with reference to FIG.

[0182] In FIG. 19(A), the driving TFT TFT7001 is a thin film transistor shown in FIG. 1(B). When the light emitted from the light emitting element 7002 exits to the anode 7005 side, 19A shows a cross-sectional view of a pixel. In FIG. 19A, a cathode 7003 of a light-emitting element 7002 and a driving TF The TFT 7001 is electrically connected to a cathode 7003, and a light-emitting layer 7004 is formed on the cathode 7003. The cathode 7003 has a small work function and reflects light. Various materials can be used as long as they are conductive films that reflect light. For example, Ca, Al, CaF, The light-emitting layer 7004 is preferably made of MgAg, AlLi, or the like. It may be configured as a single layer or as a laminate of multiple layers. In this case, an electron injection layer, an electron transport layer, an emitting layer, a hole transport layer, and a hole The anode 7005 is a light-transmitting layer. The insulating film is formed using a light-transmitting conductive material, for example, an indium-ion conductive material containing tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium tin oxide, titanium oxide, indium tin oxide (hereinafter referred to as ITO) ), indium zinc oxide, indium tin oxide doped with silicon oxide, etc. Alternatively, a conductive film having a conductive property may be used.

[0183] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 is the light-emitting element 7002. In the case of the pixel shown in FIG. 19(A), the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as shown by the mark.

[0184] Next, a light emitting element with a bottom emission structure will be described with reference to FIG. 011 is the thin film transistor 170 shown in FIG. 1A, and the light emitted from the light-emitting element 7012 19(B) shows a cross-sectional view of a pixel when light emitted from the driving A light-emitting element is formed on a light-transmitting conductive film 7017 electrically connected to the active TFT 7011. A cathode 7013 is formed on the cathode 7012, and a light-emitting layer 7014 and an anode 70 are formed on the cathode 7013. In addition, when the anode 7015 is transparent, a transparent insulating film 15 is formed on the anode 7015 so as to cover the anode. As shown in FIG. 7, a shielding film 7016 for reflecting or blocking light may be formed. 13, as in the case of FIG. 19(A), various conductive materials with small work functions can be used. However, the film thickness should be such that light can be transmitted (preferably 5 nm to 3 For example, an aluminum film having a thickness of 20 nm is used as the cathode 7013. The light-emitting layer 7014 can be formed as a single layer, as in FIG. The anode may be formed of a single layer or a plurality of layers stacked together. 7015 does not need to transmit light, but as in FIG. 19(A), it is a conductive material having light-transmitting properties. The shielding film 7016 can be formed using a material such as a metal that reflects light. For example, a resin containing a black pigment can be used. You can also be there.

[0185] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 19B, light emitted from the light-emitting element 7012 corresponds to The light is emitted toward the cathode 7013 as shown by the arrow.

[0186] Next, a light emitting element with a dual emission structure will be described with reference to FIG. Then, on the conductive film 7027 having light-transmitting properties and electrically connected to the driving TFT 7021, A cathode 7023 of the light-emitting element 7022 is formed as a film. A light-emitting layer 7024 is formed on the cathode 7023. The cathode 7023 is laminated in the same manner as in FIG. Various conductive materials with small electrical conductivity can be used. For example, Al having a thickness of 20 nm is used as the cathode 7023. The light-emitting layer 7024 can be formed of a single layer, as in FIG. The anode 70 may be formed by laminating a plurality of layers. 25 is formed using a light-transmitting conductive material, similar to FIG. 19(A). It is possible.

[0187] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 is the light-emitting element 70. In the case of the pixel shown in FIG. 19C, the light emitted from the light emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as shown by the arrows.

[0188] Although organic EL elements have been described as light-emitting elements here, inorganic EL elements can also be used as light-emitting elements. It is also possible to provide an L element.

[0189] In this embodiment, a thin film transistor (driving TFT) that controls driving of a light emitting element is Although an example in which the light emitting element is electrically connected has been shown, it is possible to prevent a current from flowing between the driving TFT and the light emitting element. A control TFT may be connected.

[0190] Note that the semiconductor device described in this embodiment mode has the same structure as that shown in FIGS. The present invention is not limited to the above-described configuration, and various modifications based on the disclosed technical idea are possible. do.

[0191] Next, the upper surface and the lower surface of a light-emitting display panel (also referred to as a light-emitting panel), which corresponds to one mode of a semiconductor device, The cross section will be explained using Figures 22(A) and 22(B). Figure 22(A) shows the first The thin film transistor and the light emitting element formed on the substrate are sandwiched between the second substrate and the substrate by a sealing material. 22(B) is a top view of the panel sealed by the HI in FIG. 22(A). This corresponds to a cross-sectional view.

[0192] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler 4507 by the sealant. Highly airtight protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the product in a protective film (such as a film) or a cover material.

[0193] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b have a plurality of thin film transistors. In FIG. 22B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45 shows an example of a thin film transistor 4509 included in a line driver circuit 4503a.

[0194] The thin film transistors 4509 and 4510 are made of In-Ga-Zn-O based non-single crystal films as semiconductor layers. The highly reliable thin film transistor described in Embodiment 1 can be applied.

[0195] Further, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured by a first electrode layer 4517, an electroluminescent layer The second electrode layer 4512 and the second electrode layer 4513 are stacked in a stacked structure. The direction of the light emitting element 4511 is adjusted according to the direction of the light extracted from the light emitting element 4511. The configuration can be changed as appropriate.

[0196] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable to form the inclined surface so that the inclined surface has a continuous curvature.

[0197] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0198] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511. A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be a silicon nitride film, A silicon nitride oxide film, a DLC film, or the like can be formed.

[0199] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are transmitted through the FPC 4518a, 4518b, and It is supplied by b.

[0200] In this embodiment, the connection terminal electrode 4515 is connected to the first electrode layer 4 The terminal electrode 4516 is formed from the same conductive film as the thin film transistors 4509 and 517. The source electrode layer and the drain electrode layer 510 are formed from the same conductive film.

[0201] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. are electrically connected to each other.

[0202] The second substrate is not transparent to light, and is positioned in the direction of light extraction from the light emitting element 4511. In this case, glass plates, plastic plates, polyester films or A light-transmitting material such as an acrylic film is used.

[0203] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It can be made of oil or thermosetting resin, and PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used.

[0204] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0205] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A single crystal semiconductor substrate or a polycrystalline semiconductor film is formed on an insulating substrate. Alternatively, the signal line driver circuit may be implemented as a drive circuit formed by a thin film. Alternatively, only a part of the scanning line driver circuit or only a part of the scanning line driver circuit may be separately formed and mounted. This embodiment is not limited to the configurations of FIGS. 22(A) and 22(B).

[0206] Through the above steps, a light-emitting display device (display panel) can be manufactured at reduced manufacturing costs. can.

[0207] This embodiment is applicable to the configuration described in the first, second, or third embodiment. It is possible to carry out any combination of these.

[0208] (Embodiment 7) In this embodiment mode, a top view and a cross section of a liquid crystal display panel, which corresponds to one mode of a semiconductor device, are shown. This will be explained using Figures 20(A1), 20(A2), and 20(B). 20A2 shows the In-G film shown in Embodiment 1 formed on the first substrate 4001. Thin film transistors 4010 and 4011 containing a-Zn-O based non-single crystal film as a semiconductor layer, The liquid crystal element 4013 is sealed between the second substrate 4006 and the liquid crystal element 4013 by a sealant 4005. 20(A1) and 20(A2). This corresponds to the cross-sectional view in

[0209] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this way, a sealing material 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealing material 4005, and a second substrate 4006. The first substrate 4001 is sealed together with the liquid crystal layer 4008. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0210] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, Wire bonding or TAB method can be used. is an example of mounting a signal line driver circuit 4003 by the COG method, and FIG. 20(A2) is This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0211] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 20B, the thin film transistor included in the pixel portion 4002 is A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 Insulating layers 4020 and 4022 are formed on the thin film transistors 4010 and 4011. 1 is provided.

[0212] The thin film transistors 4010 and 4011 are made of an In-Ga-Zn-O based non-single crystal film as a semiconductor layer. The thin film transistor described in Embodiment 1 can be applied. The thin film transistor 4011 corresponds to the thin film transistor 170 shown in FIG.

[0213] The pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are The overlapping portion corresponds to the liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033 .

[0214] The first substrate 4001 and the second substrate 4006 may be made of glass or metal (typically, stainless steel). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Aluminum foil can also be used with PVF film or polyester film. A sheet sandwiched between films can also be used.

[0215] 4035 is a columnar spacer obtained by selectively etching the insulating film. To control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 A spherical spacer may be used. is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the opposing electrode layer 40 via conductive particles disposed between the pair of substrates. The conductive particles can electrically connect the sealing material 40 to the common potential line. Included in 05.

[0216] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 10 μs to It is optically isotropic, requiring no alignment treatment, and has little viewing angle dependency. stomach.

[0217] Although this embodiment is an example of a transmissive liquid crystal display device, a transflective liquid crystal display device may also be used. It can also be applied to a liquid crystal display device.

[0218] In the liquid crystal display device of this embodiment, a polarizing plate is provided on the outer side (viewing side) of the substrate, and a polarizing plate is provided on the inner side. An example is shown in which a colored layer and an electrode layer used for a display element are provided in this order, but the polarizing plate is provided on the inner side of the substrate. The laminated structure of the polarizing plate and the colored layer is not limited to that of the present embodiment. The coloring layer may be appropriately selected depending on the material and manufacturing process conditions of the coloring layer. A light-shielding film that functions as a light-shielding film may be provided.

[0219] In this embodiment, in order to reduce the surface unevenness of the thin film transistor, In order to improve the reliability of the thin film transistor obtained in the first embodiment, a protective film or The insulating layer 4020 and the insulating layer 4021 are covered with insulating layers that function as planarizing insulating films. The protective film also prevents contamination by organic matter, metals, water vapor, and other polluting impurities floating in the air. The protective film is formed by sputtering. Silicon oxide film, silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film, nitride A single layer or multilayer of an aluminum film, an aluminum oxynitride film, or an aluminum nitride oxide film In this embodiment, an example in which the protective film is formed by sputtering is shown. There is no limitation to the method, and the method may be a PCVD method or other various methods.

[0220] Here, an insulating layer 4020 having a stacked structure is formed as a protective film. As the first layer of the silicon dioxide film, a silicon dioxide film is formed by sputtering. By using the above, it is possible to prevent hillocks in the aluminum film used as the source electrode layer and the drain electrode layer. It is effective in stopping

[0221] In addition, an insulating layer is formed as the second layer of the protective film. Then, a silicon nitride film is formed by sputtering. When a silicon nitride film is used as a protective film, Prevents ions such as thorium from penetrating into the semiconductor region and changing the electrical characteristics of the TFT. It can be controlled.

[0222] After forming the protective film, the semiconductor layer may be annealed (at 300°C to 400°C). stomach.

[0223] An insulating layer 4021 is formed as a planarization insulating film. Heat-resistant organic compounds such as amide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials can also be used. , siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. In addition, by stacking multiple insulating films made of these materials, it is possible to obtain an insulating layer. 4021 may be formed.

[0224] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0225] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife When the insulating layer 4021 is formed using a material liquid, The semiconductor layer may be annealed (at 300°C to 400°C) at the same time as the step of annealing. By combining the firing process of the edge layer 4021 with the annealing of the semiconductor layer, semiconductor devices can be efficiently manufactured. It becomes possible to do this.

[0226] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material can be used.

[0227] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer (conductive polymer The conductive composition can be used to form the conductive film. The pixel electrode has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity is 0.1 Ω·cm or less.

[0228] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0229] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials applied to 002 are supplied from FPC4018.

[0230] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode layer 40 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the same conductive film as the thin film transistors 4010 and 40 The source electrode layer and the drain electrode layer 11 are formed of the same conductive film.

[0231] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0232] In addition, in FIG. 20(A1) and FIG. 20(A2), a signal line driver circuit 4003 is separately formed. 10, an example in which the first substrate 4001 is mounted is shown, but this embodiment is not limited to this configuration. The scanning line driver circuit may be formed separately and mounted, or may be mounted as part of the signal line driver circuit or Alternatively, only a part of the scanning line driving circuit may be separately formed and mounted.

[0233] FIG. 21 shows a liquid crystal display module constructed as a semiconductor device using a TFT substrate 2600. An example is shown.

[0234] FIG. 21 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate is fixed by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate and the bonding material 2602. A display element 2604, a colored layer 2605, and a polarizing plate 2606 are provided to form a display area. The coloring layer 2605 is necessary for color display. In the case of the RGB system, it contains red, green, A colored layer corresponding to each color of blue is provided for each pixel. On the outer side of the substrate 2601, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. The light source is composed of a cold cathode fluorescent lamp 2610 and a reflector 2611, and the circuit board 2612 is , and connected to the wiring circuit section 2608 of the TFT substrate 2600 by a flexible wiring substrate 2609. It also incorporates external circuits such as a control circuit and a power supply circuit. The liquid crystal layer may be laminated with a retardation plate interposed therebetween.

[0235] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) Switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment), ASM(Axially Symmetric aligned Mic ro-cell) mode, OCB(Optical Compensated Bire) fringence mode, FLC (Ferroelectric Liquid Crystal Crystal mode, AFLC (AntiFerroelectric Liquid Crystal) can be used.

[0236] By the above steps, a liquid crystal display panel can be manufactured as a semiconductor device at reduced manufacturing costs. This can be done.

[0237] This embodiment is applicable to the configuration described in the first, second, or third embodiment. It is possible to carry out any combination of these.

[0238] (Embodiment 8) Electronic paper can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, trains, etc. This applies to in-vehicle advertisements, credit card and other card displays, etc. Examples of electronic devices are shown in Figures 23 and 24.

[0239] FIG. 23(A) shows a poster 2631 made of electronic paper. In the case of printed matter, the advertisements are exchanged manually. By using electronic paper, the display of advertisements can be changed in a short time. The poster is designed to be able to send and receive information wirelessly. It may also be possible to use the following.

[0240] FIG. 23(B) shows an advertisement 2632 inside a vehicle such as a train. In the case of paper printouts, the advertisements are exchanged manually. By using electronic paper, it is possible to change the display of advertisements in a short time without requiring much manpower. In addition, stable images can be displayed without any distortion. It may be configured to be able to send and receive information.

[0241] 24 shows an example of an electronic book 2700. For example, the electronic book 2700 includes: It consists of two housings, housing 2701 and housing 2703. The body 2703 is integrated with a shaft 2711, and the opening and closing movement is performed around the shaft 2711. This configuration allows the device to operate like a paper book. This becomes:

[0242] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 24) and An image can be displayed on the display unit 2707 in FIG.

[0243] 24 shows an example in which the housing 2701 is provided with an operation unit. 701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. It may also be configured to include a touch panel, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB A configuration including a terminal that can be connected to various cables, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. That's fine.

[0244] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0245] (Embodiment 9) The semiconductor device can be applied to various electronic devices (including gaming machines). Examples of such devices include television sets (also called televisions or television receivers), Computer monitors, digital cameras, digital video cameras, digital photos Frame, mobile phone (also called mobile phone or mobile phone device), portable game machine, portable information Examples include terminals, audio playback devices, and large game machines such as pachinko machines.

[0246] FIG. 25(A) shows an example of a television device 9600. The display unit 9603 is incorporated in the housing 9601. In this case, the housing 9601 is supported by a stand 9605. This shows a configuration in which the above is supported.

[0247] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the information displayed on the display 9603 is In addition, the remote control operation device 9610 can operate the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0248] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0249] FIG. 25(B) shows an example of a digital photo frame 9700. The photo frame 9700 has a display unit 9703 built into a housing 9701. The unit 9703 is capable of displaying various images, for example, images taken with a digital camera. By displaying the image data, it can function like a normal photo frame.

[0250] The Digital Photo Frame 9700 has an operation panel, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section. These components may be incorporated on the same surface as the display unit, but they may be incorporated on the side or back. It is preferable to have a recording medium for a digital photo frame as it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The image data can be captured and the captured image data can be displayed on the display portion 9703 .

[0251] The digital photo frame 9700 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure the device so that desired image data can be wirelessly acquired and displayed.

[0252] FIG. 26(A) shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in 26(A) also includes a speaker unit 9884, a recording medium insertion unit 988 6, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration (including functions for measuring movement, smell, or infrared rays), microphone 9889) Of course, the configuration of the portable gaming machine is not limited to the above, and at least in the embodiment In the case of a configuration including a semiconductor device having a thin film transistor according to the first or second embodiment, Other auxiliary equipment may be provided as appropriate. The portable gaming machine reads out the program or data recorded on the recording medium and displays it on the display unit. It has the function of displaying information and the function of sharing information with other portable gaming machines through wireless communication. The functions of the portable gaming machine shown in FIG. 26(A) are not limited to these, and various functions may be provided. It is possible.

[0253] FIG. 26(B) shows an example of a slot machine 9900, which is a large gaming machine. The machine 9900 has a display unit 9903 built into a housing 9901. Machine 9900 also has other operating means such as a start lever and stop switch, coin It is equipped with an insertion slot, a speaker, etc. Of course, the configuration of the slot machine 9900 is The thin film transistor is not limited to the one shown in the first embodiment or the second embodiment. It is sufficient that the semiconductor device has the above configuration, and other auxiliary equipment is appropriately provided. It is possible.

[0254] FIG. 27 shows an example of a mobile phone 1000. The mobile phone 1000 has a housing 100 1, in addition to the display unit 1002, operation buttons 1003, an external connection port 1004, It is equipped with a speaker 1005, a microphone 1006, etc.

[0255] The mobile phone 1000 shown in FIG. 27 allows users to input information by touching the display unit 1002 with a finger or the like. In addition, operations such as making a call or sending an email can be performed by the display unit 100. This can be done by touching 2 with a finger or something.

[0256] The screen of the display unit 1002 has three main modes. The first is a display mode that mainly displays images. The first mode is a display mode, and the second mode is an input mode that mainly inputs information such as characters. This is a display + input mode that combines two modes: display mode and input mode.

[0257] For example, when making a call or creating an email, the display unit 1002 is used to input characters. This is the main character input mode, and you can input characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002. I wish.

[0258] In addition, the mobile phone 1000 may include a sensor for detecting tilt, such as a gyro or an acceleration sensor. By providing a detection device having the above configuration, the orientation of the mobile phone 1000 (portrait or landscape) can be determined and the display The screen display of the display unit 1002 can be automatically switched.

[0259] The screen mode can be switched by touching the display unit 1002 or by operating the housing 1001. This is done by operating the button 1003. Also, depending on the type of image displayed on the display unit 1002, For example, if the image signal to be displayed on the display unit is a video signal, If it is data, the display mode is switched to, and if it is text data, the input mode is switched to.

[0260] In the input mode, the optical sensor of the display unit 1002 detects a signal and displays it. If there is no input by touch operation of the part 1002 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0261] The display unit 1002 can also function as an image sensor. By touching the palm or fingers to the sensor 02, the palm print, fingerprint, etc. can be captured and identity authentication can be performed. In addition, the display unit may be equipped with a backlight that emits near-infrared light or a sensor that emits near-infrared light. By using a scanning light source, it is also possible to capture images of finger veins, palm veins, etc.

[0262] (Embodiment 10) In the first and second embodiments, an example in which a buffer layer is provided is shown. In this example, no buffer layer is provided. An example of configuring an inverter circuit using a capacitor will be described below.

[0263] The driver circuit for driving the pixel section is composed of an inverter circuit, a capacitor, a resistor, etc. When two n-channel TFTs are combined to form an inverter circuit, When forming a combination of a ment type transistor and a depletion type transistor ( EDMOS circuit) and enhancement-type TFTs (hereinafter referred to as In addition, when the threshold voltage of the n-channel TFT is positive, is defined as an enhancement type transistor, and the threshold voltage of the n-channel TFT is negative. In this case, the transistor is defined as a depletion-type transistor, and this definition is followed throughout the specification. Let's say.

[0264] The pixel section and the driver circuit are formed on the same substrate, and the pixel section is arranged in a matrix. An enhancement-type transistor is used to switch the voltage applied to the pixel electrode on and off. The enhancement type transistor disposed in this pixel portion uses an oxide semiconductor. The electrical characteristics are as follows: the on-off ratio is 10 at a gate voltage of ±20V. 9 Because that's all, The leakage current is small, and low power consumption driving can be achieved.

[0265] The cross-sectional structure of the inverter circuit of the driver circuit is shown in FIG. A first gate electrode 1401 and a second gate electrode 1402 are provided on a plate 1400. The materials of the first gate electrode 1401 and the second gate electrode 1402 are molybdenum, titanium, chromium, and the like. Metallic materials such as chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium It can be formed in a single layer or a laminated layer using a material or an alloy material containing these as the main component. do.

[0266] For example, a two-layer structure of a first gate electrode 1401 and a second gate electrode 1402 is used. For example, a two-layer structure with a molybdenum layer on an aluminum layer or a molybdenum layer on a copper layer is used. Two-layer structure with laminated ribdenum layer, or titanium nitride layer or tantalum nitride layer on copper layer Preferably, the titanium nitride layer and the molybdenum layer are laminated together, or the titanium nitride layer and the molybdenum layer are laminated together. The three-layer structure is a tungsten layer or tungsten nitride layer and an aluminum layer. and silicon alloy or aluminum and titanium alloy with titanium nitride or titanium layer. A laminated layer is preferred.

[0267] In addition, the gate insulating layer 1401 covers the first gate electrode 1401 and the second gate electrode 1402. On the substrate 1403, a first wiring 1409, a second wiring 1410, and a third wiring 1411 are provided. The wiring 1410 is connected to the gate insulating layer 1403 via a contact hole 1404 formed in the gate insulating layer 1403. 1402. The second gate electrode 1402 is directly connected to the first gate electrode 1402.

[0268] In addition, a first wiring 1409 and a second wiring 1410 are provided at positions overlapping the first gate electrode 1401. The first oxide semiconductor layer 1405 and the second gate electrode 1402 are overlapped with each other. A second oxide semiconductor layer 1407 is provided on and in contact with a second wiring 1410 and a third wiring 1411. can.

[0269] The first thin film transistor 1430 includes a first gate electrode 1401 and a gate insulating layer 140 a first oxide semiconductor layer 1405 overlapping with the first gate electrode 1401 via a gate electrode 3; The first wiring 1409 is a power supply line (ground power supply line) of the ground potential. Alternatively, it may be a power supply line to which a negative voltage VDL is applied (negative power supply line).

[0270] The second thin film transistor 1431 has a second gate electrode 1402 and a gate insulating layer a second oxide semiconductor layer 1407 overlapping the second gate electrode 1402 with a gate electrode 1403 interposed therebetween; The third wiring 1411 is a power supply line (positive power supply line) to which a positive voltage VDD is applied.

[0271] The side surfaces of the first wiring 1409 and the second wiring 1409 facing each other with the first oxide semiconductor layer 1405 interposed therebetween. By making the side surface of the source electrode layer 10 tapered, the side surface of the oxide semiconductor layer 10 and the side surface of the source electrode layer 10 The region overlapping the side surface of the drain electrode layer functions as an electric field concentration relaxation region.

[0272] The side surfaces of the second wiring 1410 and the third wiring 1411 facing each other with the second oxide semiconductor layer 1407 interposed therebetween are The side surface of the line 1411 is tapered, so that the source electrode layer in the oxide semiconductor layer The side surface and the region overlapping with the side surface of the drain electrode layer function as an electric field concentration relaxation region.

[0273] As shown in FIG. 32A, the first oxide semiconductor layer 1405 and the second oxide semiconductor layer 14 The second wiring 1410 electrically connecting both of the gate insulating layer 1403 and the gate insulating layer 1407 is formed in the gate insulating layer 1403. A second gate electrode of the second thin film transistor 1431 is connected to the second gate electrode of the second thin film transistor 1431 through the contact hole 1404. The second wiring 1410 and the second gate electrode 1402 are directly connected. By connecting the two, good contact can be achieved and contact resistance can be reduced. The second gate electrode 1402 and the second wiring 1410 can be formed by another conductive film, for example, a transparent conductive film. Compared to connecting via a contact hole, the number of contact holes can be reduced. This reduces the amount of space required.

[0274] A top view of the inverter circuit of the driver circuit is shown in FIG. The cross section taken along the chain line Z1-Z2 corresponds to FIG.

[0275] The equivalent circuit of the EDMOS circuit is shown in Figure 32(B). The circuit connection shown corresponds to FIG. 32(B), and the first thin film transistor 1430 is enhanced. The second thin film transistor 1431 is a depletion type n-channel transistor. This is an example of a junction-type n-channel transistor.

[0276] In addition, although an example of an EDMOS circuit is shown in this embodiment, both are enhancement type A driver circuit may be configured using an EEMOS circuit that uses n-channel transistors.

[0277] In addition, in this embodiment, an example in which a buffer layer is not provided is shown, but this is not particularly limited. As in the first embodiment, the upper surface of the first wiring 1409, the upper surface of the second wiring 1410, and the upper surface of the third wiring A buffer layer may be provided on the upper surface of 1411.

[0278] This embodiment can be combined with any one of the first to ninth embodiments.

[0279] (Embodiment 11) In this embodiment, stress is applied to a thin film transistor having a model structure shown in FIG. The degree of deterioration of electrical characteristics is calculated.

[0280] The structure shown in FIG. 33(A) includes a gate electrode layer 302 and a gate insulating layer 303 on a glass substrate 301. 3 are stacked in this order, and a source electrode layer 304 and a drain electrode layer 305 are formed thereon. An oxide layer 307 is formed on the side of the source electrode layer 304, and an oxide layer 308 is formed on the side of the drain electrode layer 305. An oxide layer 308 is provided on the surface. In this case, the oxide layers 307 and 308 are the source electrode. The source electrode layer 304 and the drain electrode layer 305 are natural oxide films. An oxide semiconductor layer 306 is formed covering the drain electrode layer 305 and the oxide layers 307 and 308. Complete.

[0281] The gate electrode layer 302 is made of molybdenum, and the source electrode layer 304 and the drain electrode layer 305 are made of molybdenum. The gate insulating layer 303 is a silicon oxide film. The oxide semiconductor layer 306 has a thickness of 50 nm and a relative dielectric constant εr of 4.1. The material is an In-Ga-Zn-O based non-single crystal film. The transistor channel length L is 10 μm and the channel width W is 10 μm.

[0282] The stress applied to the thin film transistor is the gate voltage Vgs=2V, the source electrode and the drain The voltage between the electrodes is Vds = 20V, and the time for applying this stress is 1000 seconds. The electrical characteristics are compared before and after the application of stress.

[0283] In this calculation, we used the simulation software "Atlas" made by Silvaco. This was calculated.

[0284] The taper angle θ1 of the source electrode layer 304 is set to 27 degrees, 45 degrees, or 63 degrees. The taper angle θ1 of the source electrode layer 304 was calculated by Set it to the same angle as the angle θ.

[0285] FIG. 34 shows the calculation results when the taper angle θ1 of the source electrode layer 304 is 27 degrees.

[0286] FIG. 35 shows the calculation results when the taper angle θ1 of the source electrode layer 304 is 45 degrees. show.

[0287] FIG. 36 shows the calculation results when the taper angle θ1 of the source electrode layer 304 is 63 degrees. show.

[0288] From the results of FIGS. 34, 35, and 36, it can be seen that the taper angle θ1 of the source electrode layer 304 is small. The lower the temperature, the less likely it is to deteriorate.

[0289] For comparison, the results of a similar calculation performed on the structure shown in Figure 33(B) with the angle set to 90 degrees are also shown. The structure shown in Figure 33(B) is the same as Figure 33(A) except for the angle. are identical.

[0290] For comparison, the oxide layer on the side of the source electrode layer 304 and the drain electrode The results of a similar calculation performed on the structure shown in FIG. 33(C) where there is no oxide layer on the side of the layer 305 are shown in FIG. If there is no oxide layer on the side, the same result will be obtained regardless of the taper angle θ1. When there is no oxide layer on the side, the gate insulating layer 303 and the oxide semiconductor layer 306 Since the interface with the source electrode layer 304 becomes a current path, the taper angle of the side surface of the source electrode layer 304 is does not affect the current path.

[0291] From these results, it is found that the oxide layer 307 is formed on the side of the source electrode layer 304 and the drain electrode layer 30 The oxide layer 308 is provided on the side surface of the 5, and the taper angle θ1 is set to be smaller than 90 degrees. It can be said that this can suppress the deterioration of the electrical characteristics of the thin film transistor.

[0292] The embodiment having the above configuration will be described in more detail with reference to the following examples. This will be done. [Example]

[0293] Example 1 In this example, characteristics of a thin film transistor manufactured using an oxide semiconductor layer will be described. .

[0294] A method for manufacturing the transistor used in this example will be described below.

[0295] First, a first conductive film is formed on a substrate, and then the first conductive film is photolithographically The gate electrode 502 was formed by patterning using the A gate insulating layer 503 was formed on the electrode 502. Then, a second conductive layer was formed on the gate insulating layer 503. The second conductive film and the buffer layer were formed successively without exposing the substrate to the atmosphere. A buffer layer was formed. Subsequently, the second conductive film and the buffer layer were photolithographically The source electrode layer 506 is patterned by the method so that a part of the source electrode layer 506 overlaps with the gate electrode. Then, a gate insulating layer, a source electrode layer, and a drain electrode layer 506b were formed. After forming an oxide semiconductor layer on the rain electrode layer, the oxide semiconductor layer is photolithographically By patterning using the silicon dioxide method, an island-shaped oxide film that functions as a channel formation region is formed. Then, a heat treatment was carried out in a nitrogen atmosphere at 350° C. for 1 hour. Ta.

[0296] A glass substrate (product name AN100) manufactured by Asahi Glass Co., Ltd. was used as the substrate.

[0297] As the first conductive film that will become the gate electrode 502, a 100 nm thick tantalum film is deposited by sputtering. A titanium film was formed.

[0298] As the gate insulating layer 503, a silicon oxynitride film having a thickness of 100 nm was deposited by plasma CVD. A film was formed.

[0299] A second conductive film to be the source electrode layer 506a and the drain electrode layer 506b was formed by sputtering. A tungsten film with a thickness of 100 nm was formed using this method.

[0300] The buffer layer is a 5 to 10 nm thick In-Ga-Zn-O non-single crystal film formed by sputtering. The film was formed using argon gas only, and the target was In2O3:Ga2O 3: A target with ZnO=1:1:1 was used.

[0301] The oxide semiconductor layer is a 150 nm In-Ga-Zn-O non-single crystal film formed by sputtering. The film was formed under the conditions of a pressure of 0.4 Pa, a power of 500 W, and a film-forming temperature of 25°C. ° C., the argon gas flow rate was 10 sccm, the oxygen flow rate was 5 sccm, and the glass substrate The distance between the target and the source was 170 mm, and DC (Direct Current) The target was In2O3:Ga2O3:ZnO=1:1:1. The substrate was a SiO2 (In:Ga:Zn=1:1:0.5). After plasma treatment, The oxide semiconductor layer was formed continuously without exposing the substrate 500 to the air. The composition of the oxide semiconductor layer obtained under these conditions was analyzed by inductively coupled plasma mass spectrometry. ly Coupled Plasma Mass Spectrometry:ICP- The results of measurements using the MS analysis method were 0.94 Zn 0.40 O 3.31 was .

[0302] FIG. 28 shows the Vg-Id curve of the thin film transistor. The measurement was performed with the drain voltage (drain voltage relative to the source voltage) set to 1V. Ta.

[0303] In this example, the transistor structure was formed as shown in FIG. The channel length L of the transistor is 100 μm, the channel width W is 100 μm, and the source electrode layer 5 The overlap length Ls of the drain electrode layer 506a and the gate electrode 502 is 5 μm. The overlapping length Ld of the electrode 502 is 5 μm, and the oxide semiconductor The length of the region where the body layer 510 does not overlap with the source electrode layer 506a and the drain electrode layer 506b A was set to 5 μm.

[0304] As a result, the second conductive film and the buffer layer were formed in succession without exposing the substrate to the atmosphere. This increases the on / off ratio of the transistor and increases the field-effect mobility. It was found that... [Example]

[0305] In this example, an example of the electrode shape after etching is shown. First, a sample is prepared. The process will be described with reference to FIG. 30. Example 1 refers to a process in which the source electrode layer and the drain electrode layer are The only differences are the cross-sectional shape of the doped electrode layer and the absence of a buffer layer. Therefore, the same parts will be described using the same reference numerals.

[0306] First, a first conductive film is formed on a substrate, and then the first conductive film is photolithographically The gate electrode 502 was formed by patterning using the A gate insulating layer 503 was formed on the electrode 502 (see FIG. 30(A)). A second conductive film was formed on the layer 503. Subsequently, the second conductive film was formed by photolithography. The source electrode layer 606 is patterned by a method to form a layer that partially overlaps the gate electrode. A gate insulating layer 606a and a drain electrode layer 606b were formed (see FIG. 30B). After forming an oxide semiconductor layer over the source electrode layer and the drain electrode layer, The layer is patterned by photolithography to form a channel forming region. An island-shaped oxide semiconductor layer 610 functioning as a gate insulating film was formed (see FIG. 30C).

[0307] A glass substrate (product name AN100) manufactured by Asahi Glass Co., Ltd. was used as the substrate.

[0308] As the first conductive film that will become the gate electrode 502, a 100 nm thick tantalum film is deposited by sputtering. A titanium film was formed.

[0309] As the gate insulating layer 503, a silicon oxynitride film having a thickness of 100 nm was deposited by plasma CVD. A film was formed.

[0310] A second conductive film to be the source electrode layer 606a and the drain electrode layer 606b was formed by sputtering. A tungsten film with a thickness of 100 nm was formed using this method.

[0311] The oxide semiconductor layer is a 150 nm In-Ga-Zn-O non-single crystal film formed by sputtering. The film formation conditions were the same as in Example 1.

[0312] The source electrode layer 606a and the drain electrode layer 606b are etched to form a coil antenna. The etching was carried out using an ICP etching system. The gas flow rate of CF4 was 25 (sccm), The gas flow rate of I2 is 25 (sccm), the gas flow rate of O2 is 10 (sccm), and the At a pressure of a, 500 W of RF (13.56 MHz) power was applied to the coil-shaped electrode to generate plasma. The substrate side (sample stage) is also equipped with a 10W RF (13.56 MHz) power is applied and a substantially negative self-bias voltage is applied. By stopping this etching midway when the insulating film 503 is exposed to a certain extent, A differential electrode side surface is formed.

[0313] Under the above etching conditions, the cross-sectional shape of the source electrode layer 606a is such that the substrate surface of the substrate and the source The angle θ1 formed between the electrode layer 606a and the side surface of the lower end portion can be set to 20° or more and less than 90°. A cross-sectional photograph of the area surrounded by the dotted line in Figure 30(C) is shown in Figure 31(A). Fig. 31(B) is a schematic diagram of Fig. 31(A). As shown in Fig. 31(A), θ1 is about 40 31(A), the substrate surface of the substrate and the top of the source electrode layer 606a The angle formed between the end side surface and the oxide semiconductor layer 610 is approximately 90°. The cross-sectional shapes of the side surface of the source electrode layer 606a and the side surface of the drain electrode layer 606b are the same etching process. They are almost identical because they go through the same process.

[0314] According to this example, the cross-sectional shapes of the source electrode layer and the drain electrode layer shown in Embodiment 2 are formed. It can be said that this suggests that [Explanation of symbols]

[0315] 100: Substrate 101: Gate electrode 102: Gate insulating layer 103: Oxide semiconductor layer 104a: First buffer layer 104b: second buffer layer 105a: Source electrode layer 105b: Drain electrode layer

Claims

1. a pixel portion including a first pixel having a first transistor and a second pixel having a second transistor; the first pixel and the second pixel are arranged adjacent to each other in a first direction, a first conductive layer that functions as a gate electrode of the first transistor; a first insulating layer having a region in contact with an upper surface of the first conductive layer; a second conductive layer having a region in contact with a top surface of the first insulating layer and functioning as one of a source electrode and a drain electrode of the first transistor; a third conductive layer having a region in contact with an upper surface of the first insulating layer and functioning as the other of the source electrode and the drain electrode of the first transistor; a first oxide semiconductor layer including a region in contact with the second conductive layer and a region in contact with the third conductive layer and including a channel formation region of the first transistor; a fourth conductive layer having a region in contact with the third conductive layer and functioning as a pixel electrode of the first pixel; a fifth conductive layer made of the same material as the first conductive layer and having a function as a gate electrode of the second transistor and a function as one electrode of a capacitor element; a sixth conductive layer having a region in contact with an upper surface of the first insulating layer and a region overlapping with the fifth conductive layer, and having a function as the other electrode of the capacitor element; the second conductive layer is electrically connected to a second oxide semiconductor layer having a channel formation region of the second transistor; the first insulating layer has a region in contact with an upper surface of the fifth conductive layer; the fourth conductive layer has a region overlapping with the fifth conductive layer via the sixth conductive layer, the sixth conductive layer has the same material as the second conductive layer and the third conductive layer; A display device, wherein, when viewed cross-sectionally in the first direction, the fifth conductive layer has a region that extends beyond an end of the sixth conductive layer.

2. a pixel portion including a first pixel having a first transistor and a second pixel having a second transistor; the first pixel and the second pixel are arranged adjacent to each other in a first direction, a first conductive layer that functions as a gate electrode of the first transistor; a first insulating layer having a region in contact with an upper surface of the first conductive layer; a second conductive layer having a region in contact with a top surface of the first insulating layer and functioning as one of a source electrode and a drain electrode of the first transistor; a third conductive layer having a region in contact with an upper surface of the first insulating layer and functioning as the other of the source electrode and the drain electrode of the first transistor; a first oxide semiconductor layer including a region in contact with the second conductive layer and a region in contact with the third conductive layer and including a channel formation region of the first transistor; a fourth conductive layer having a region in contact with the third conductive layer and functioning as a pixel electrode of the first pixel; a fifth conductive layer made of the same material as the first conductive layer and having a function as a gate electrode of the second transistor and a function as one electrode of a capacitor element; a sixth conductive layer having a region in contact with an upper surface of the first insulating layer and a region overlapping with the fifth conductive layer, and having a function as the other electrode of the capacitor element; the second conductive layer is electrically connected to a second oxide semiconductor layer having a channel formation region of the second transistor; the first insulating layer has a region in contact with an upper surface of the fifth conductive layer; the fourth conductive layer has a region overlapping with the fifth conductive layer via the sixth conductive layer, the sixth conductive layer has the same material as the second conductive layer and the third conductive layer; When viewed in a cross section in the first direction, the fifth conductive layer has a region that extends beyond an end of the sixth conductive layer, A display device, wherein, in a plan view, the fourth conductive layer has a region that extends beyond an end of the fifth conductive layer toward the second pixel.

3. In claim 1 or 2, The display device, wherein the first insulating layer has a laminated structure.

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