Semiconductor Devices

Abstract

To provide a semiconductor device having a novel structure.SOLUTION: A semiconductor device includes a first wiring, a second wiring, a third wiring, a fourth wiring, a first transistor 160 including a first gate electrode, a first source electrode, and a first drain electrode, and a second transistor 162 including a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided over a substrate including a semiconductor material and the second transistor includes an oxide semiconductor layer. The first gate electrode is electrically connected to one of the second source electrode and the second drain electrode. The first wiring is electrically connected to the first source electrode. The second wiring is electrically connected to the first drain electrode. The third wiring is electrically connected to the other of the second source electrode and the second drain electrode. The fourth wiring is electrically connected to the second gate electrode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The disclosed invention relates to a semiconductor device using a semiconductor element and a manufacturing method thereof. do. [Background technology]

[0002] Memory devices that use semiconductor elements are volatile memory devices that lose their contents when the power supply is cut off. and non-volatile memory devices, which retain their contents even when the power supply is cut off. can be.

[0003] A typical example of a volatile memory device is a DRAM (Dynamic Random Access Memory). DRAM is a memory element that can be selected from transistors. By storing charge in the capacitor, information is stored.

[0004] Based on the above principle, in DRAM, when information is read, the charge in the capacitor is lost. Therefore, every time data is read, a write operation is required again. The transistors that make up the transistors have leakage current, and when the transistors are not selected, Therefore, the data retention period is short. A write operation (refresh operation) is required, and power consumption must be reduced sufficiently. Furthermore, if the power supply is cut off, the memory contents are lost, making it difficult to store long-term memories. To store the data, a separate storage device using magnetic or optical materials is required.

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM uses circuits such as flip-flops to store the memory contents. In order to retain data, no refresh operation is required, which is an advantage over DRAM. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. In addition, there is a problem that the memory contents are lost when the power supply is cut off. In this regard, it is no different from DRAM.

[0006] A typical example of a nonvolatile memory device is flash memory. A floating gate is provided between the gate electrode of the transistor and the channel forming region, Since memory is stored by holding an electric charge in the floating gate, the data retention period is extremely long. The advantage is that it lasts for a very long time (semi-permanent) and does not require the refresh operations required for volatile storage devices. The point is as follows (see, for example, Patent Document 1).

[0007] However, the gate insulating layer that constitutes the memory element is damaged by the tunnel current that occurs during writing. The memory element deteriorates, and repeated writing causes it to stop functioning. To avoid this problem, for example, the number of write operations to each memory element may be made uniform. However, to achieve this, complex peripheral circuits are required. However, even if such a method is adopted, the fundamental problem of lifespan will not be resolved. Therefore, flash memory is not suitable for applications where information needs to be rewritten frequently.

[0008] In addition, to inject or remove charges into or from the floating gate, high Furthermore, it takes a relatively long time to inject or remove the charge. However, there is also the problem that it is not easy to speed up writing and erasing. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 57-105889 Summary of the Invention [Problem to be solved by the invention]

[0010] In view of the above-mentioned problems, one embodiment of the disclosed invention provides a method for storing stored contents even when power is not supplied. To provide a semiconductor device having a new structure that can retain data and has no limit on the number of times it can be written. This is one of the purposes of the organization. [Means for solving the problem]

[0011] One embodiment of the present invention is a transistor formed using an oxide semiconductor and a transistor formed using other materials. The semiconductor device has a stacked structure with a transistor formed using the above-mentioned method. Such a configuration can be adopted.

[0012] One embodiment of the present invention is a semiconductor device including a first wiring (source line), a second wiring (bit line), and a third wiring. (first signal line), a fourth wiring (second signal line), a first gate electrode, and a first source electrode a first transistor having a first drain electrode, a second gate electrode, a second a second transistor having a source electrode and a second drain electrode; The first transistor is provided on a substrate including a semiconductor material, and the second transistor is provided on an oxide semiconductor substrate. a first gate electrode and a second source electrode or a second drain electrode; The first wiring (source line) and the first source electrode are electrically connected to each other. The second wiring (bit line) and the first drain electrode are electrically connected. The third wiring (first signal line) and the other of the second source electrode and the second drain electrode are connected to each other. are electrically connected, and the fourth wiring (second signal line) and the second gate electrode are electrically It is a semiconductor device connected to the

[0013] In the above, the first transistor is a channel-forming transistor provided in a substrate including a semiconductor material. a region, impurity regions provided so as to sandwich the channel forming region, and a region on the channel forming region a first gate insulating layer; a first gate electrode on the first gate insulating layer; and an impurity region and an electric and a first source electrode and a first drain electrode electrically connected to the first source electrode.

[0014] In the above, the second transistor has a second gate electrode on a substrate including a semiconductor material. a second gate insulating layer on the second gate electrode; and an oxide semiconductor layer on the second gate insulating layer. a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer; and,

[0015] In the above, the substrate containing a semiconductor material may be a single crystal semiconductor substrate or an SOI substrate. It is preferable to use a plate, and it is particularly preferable that the semiconductor material is silicon.

[0016] In the above, the oxide semiconductor layer is made of an In-Ga-Zn-O based oxide semiconductor material. In particular, the oxide semiconductor layer preferably contains In2Ga2ZnO7 crystals. Furthermore, the hydrogen concentration in the oxide semiconductor layer is preferably 5×10 19 atoms / cm 3 The off-state current of the second transistor is preferably 1×10 or less. -13 A The off-state current of the second transistor is preferably 1×10 or less. -20 A The following is more preferable.

[0017] In the above, the second transistor is provided in a region overlapping with the first transistor. The configuration can be as follows.

[0018] In this specification, the terms "above" and "below" refer to the positional relationship of a component, such as "directly above" or "below." For example, the term "gate electrode on a gate insulating layer" is not limited to "directly under" the gate insulating layer. If the expression "electrode" is used, it excludes those that include other components between the gate insulating layer and the gate electrode. In addition, the terms "upper" and "lower" are merely expressions used for the convenience of explanation, and Unless otherwise specified, this also includes the reversed top and bottom.

[0019] In addition, the terms "electrode" and "wiring" used in this specification refer to these components functionally. This is not a limitation. For example, an "electrode" may be used as part of a "wiring." , and vice versa. Furthermore, the terms "electrode" and "wiring" are used interchangeably to refer to the plural "electrodes." This also includes cases where the "wiring" is formed integrally.

[0020] Also, the functions of "source" and "drain" may differ depending on whether transistors with different polarities are used or not. However, they may be swapped when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" are used interchangeably. It is assumed that this is possible.

[0021] In this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a wire. is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between the connection objects.

[0022] For example, "something that has some kind of electrical effect" includes not only electrodes and wiring, but also transistors. Switching elements such as transistors, resistive elements, inductors, capacitors, and other various devices This includes elements that have functions such as:

[0023] Generally, an "SOI substrate" is a substrate with a silicon semiconductor layer on an insulating surface. However, in this specification, a semiconductor layer made of a material other than silicon is provided on an insulating surface. In other words, the semiconductor layer of an "SOI substrate" The substrate in the "SOI substrate" is not limited to a silicon semiconductor layer. Not only semiconductor substrates such as wafers, but also glass substrates, quartz substrates, sapphire substrates, metal substrates, etc. This includes any non-semiconductor substrate, i.e., a conductive substrate with an insulating surface or a semiconductor on an insulating substrate. The term "SOI substrate" broadly includes those having a layer of material. In this context, the term "semiconductor substrate" does not only refer to a substrate made of semiconductor material alone, but also to a substrate made of semiconductor material. In other words, in this specification, "SOI substrate" is also broadly used to refer to "semiconductor substrates." This is included in the "conductor substrate." [Effects of the Invention]

[0024] In one embodiment of the present invention, a transistor including a material other than an oxide semiconductor is provided in a lower portion, and A semiconductor device including a transistor including an oxide semiconductor is provided.

[0025] Since a transistor using an oxide semiconductor has an extremely small off-state current, It is possible to retain the memory contents for a much longer period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations to an extremely low level. Therefore, power consumption can be reduced sufficiently. , it is possible to retain the stored contents for a long period of time.

[0026] Furthermore, no high voltage is required to write information, and there is no problem of element degradation. Information is written by switching the transistor between on and off, so Also, by controlling the potential input to the transistor, Since it is rewritable, there is also the advantage that there is no need to erase the information. do.

[0027] In addition, a transistor using a material other than an oxide semiconductor is Compared to the conventional memory, it can operate at a higher speed, so by using it, the contents of the memory can be It is possible to perform reading at high speed.

[0028] In this way, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating a transistor, a semiconductor device with unprecedented features can be realized. It is possible. [Brief explanation of the drawings]

[0029] [Figure 1] Circuit diagram for explaining a semiconductor device [Figure 2] 1A and 1B are cross-sectional and plan views illustrating a semiconductor device; [Figure 3]1A and 1B are cross-sectional views illustrating a manufacturing process of a semiconductor device; [Figure 4] 1A and 1B are cross-sectional views illustrating a manufacturing process of a semiconductor device; [Figure 5] 1A and 1B are cross-sectional views illustrating a manufacturing process of a semiconductor device; [Figure 6] 1 is a cross-sectional view illustrating a semiconductor device; [Figure 7] 1 is a cross-sectional view illustrating a semiconductor device; [Figure 8] 1 is a cross-sectional view illustrating a semiconductor device; [Figure 9] 1 is a cross-sectional view illustrating a semiconductor device; [Figure 10] FIG. 1 is a diagram illustrating an electronic device using a semiconductor device. [Figure 11] Vertical cross-sectional view of an inverted staggered transistor using an oxide semiconductor [Figure 12] Energy band diagram (schematic diagram) at the A-A' cross section of Figure 11 [Figure 13] (A) A diagram showing the state when a positive potential (+VG) is applied to the gate (GE1), and (B) a diagram showing the state when a negative potential (-VG) is applied to the gate (GE1). [Figure 14] Diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ) [Figure 15] Circuit diagram for explaining a semiconductor device [Figure 16] Circuit diagram for explaining a semiconductor device [Figure 17] Circuit diagram for explaining a semiconductor device [Figure 18] Circuit diagram for explaining a semiconductor device [Figure 19] Circuit diagram for explaining a semiconductor device [Figure 20] Timing chart showing the relationship between potentials [Figure 21] Circuit diagram for explaining a semiconductor device [Figure 22] 1A and 1B are cross-sectional and plan views illustrating a semiconductor device; [Figure 23] 1 is a cross-sectional view illustrating a semiconductor device; [Figure 24] 1 is a cross-sectional view illustrating a semiconductor device; [Figure 25] Characteristics of a transistor including an oxide semiconductor [Figure 26] Circuit diagram for evaluating the characteristics of a transistor using an oxide semiconductor [Figure 27] Timing chart for evaluating the characteristics of a transistor using an oxide semiconductor [Figure 28] Characteristics of a transistor including an oxide semiconductor [Figure 29] Characteristics of a transistor including an oxide semiconductor [Figure 30] Characteristics of a transistor including an oxide semiconductor [Figure 31] Figure showing the results of the memory window width survey DETAILED DESCRIPTION OF THE INVENTION

[0030] An example of an embodiment of the present invention will be described below with reference to the drawings. and the present invention is not limited to the above description, and may be modified in various forms and forms without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention is not to be construed as being limited to the description of the embodiment shown in the accompanying drawings.

[0031] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily accurate to facilitate understanding. The actual position, size, range, etc. may not be shown. It is not limited to the position, size, range, etc. shown.

[0032] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. It should be noted that the numbers are added to avoid any unnecessary errors and are not intended to limit the number of errors.

[0033] (Embodiment 1) In this embodiment, a structure and a manufacturing method of a semiconductor device according to one embodiment of the disclosed invention will be described. This will be described with reference to FIGS.

[0034] <Circuit configuration of semiconductor device> FIG. 1 shows an example of a circuit configuration of a semiconductor device. A transistor 160 using a material (for example, silicon) and a transistor using an oxide semiconductor In the following description, the semiconductor device shown in FIG. It is sometimes called.

[0035] Here, the gate electrode of transistor 160 and the source electrode or drain of transistor 162 are The first line (1st Line) is electrically connected to one of the drain electrodes. The source line SL is electrically connected to the source electrode of the transistor 160. The second wiring (also called the bit line BL) and the drain of the transistor 160 The first signal line is electrically connected to the second signal line. The line S1 and the other of the source electrode and the drain electrode of the transistor 162 are connected to each other. The fourth line (also called the second signal line S2) is electrically connected to the The gate electrode of the transistor 162 is electrically connected.

[0036] The transistor 160 using a material other than an oxide semiconductor is a transistor using an oxide semiconductor. Compared to the conventional memory, it can operate at a higher speed, so by using it, the contents of the memory can be In addition, a transistor using an oxide semiconductor can be used. The transistor 162 has a feature of having an extremely small off-state current. By turning off the transistor 62, the potential of the gate electrode of the transistor 160 is maintained for a very long time. In addition, the transistor 162 using an oxide semiconductor can Another advantage is that the short channel effect is less likely to occur.

[0037] By utilizing the feature that the potential of the gate electrode can be maintained, It is possible to write, hold, and read data.

[0038] First, writing and holding of information will be explained. First, the potential of the fourth wiring is set to The potential is set to turn on the transistor 162, thereby turning on the transistor 162. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 160 (write After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off. By turning off the transistor 162, the gate electrode of the transistor 160 The potential is maintained (retention).

[0039] Since the off-state current of the transistor 162 is extremely small, the gate electrode of the transistor 160 For example, if the potential of the gate electrode of transistor 160 is If the potential is such that the transistor 160 is turned on, the transistor 160 will remain on for a long time. The potential of the gate electrode of the transistor 160 is maintained for a certain period of time. If the potential is such that the transistor 160 is turned off, the transistor 160 will remain in the off state for a long time. is maintained over time.

[0040] Next, the reading of information will be described. As described above, when the transistor 160 is in the ON state, Alternatively, when the off state is maintained, a predetermined potential (low potential) is applied to the first wiring. When the transistor 160 is turned on, the potential of the second wiring changes depending on whether the transistor 160 is turned on or off. For example, when the transistor 160 is on, the potential of the first wiring As a result, the potential of the second wiring is lowered. In the OFF state, the potential of the second wiring does not change.

[0041] In this way, in the state where the information is held, the potential of the second wiring is compared with a predetermined potential. This allows the information to be read out.

[0042] Next, the rewriting of information will be described. That is, the potential of the fourth wiring is held when the transistor 162 is turned on. This turns on the transistor 162. (the potential related to the new information) is applied to the gate electrode of the transistor 160. The potential of the fourth wiring is set to a potential at which the transistor 162 is turned off. By turning off 62, the new information is held.

[0043] In this way, the semiconductor device according to the disclosed invention can directly write information again. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need for an erase operation, and can suppress a decrease in operation speed due to the erase operation. That is, high-speed operation of the semiconductor device is realized.

[0044] The off-state current of the writing transistor 162 using an oxide semiconductor is extremely small. The potential of the gate electrode of the transistor 160 is maintained for a long time. The refresh operation required in conventional DRAM is no longer necessary, or the refresh operation is It is possible to reduce the frequency of this operation to an extremely low level (for example, once a month to once a year). As described above, the semiconductor device of the disclosed invention has the characteristics of a substantially nonvolatile memory device. There are.

[0045] Furthermore, unlike conventional DRAM, the semiconductor device of the disclosed invention does not read information. Since the information is not lost, there is no need to rewrite it every time it is read. Compared to DRAM, the frequency of writing information can be significantly reduced, resulting in lower power consumption. It is possible to sufficiently suppress the above.

[0046] In addition, the semiconductor device of the disclosed invention can directly write information to the semiconductor device again. This allows the information to be rewritten automatically. Therefore, the erase operation that is required is not necessary, and the decrease in operation speed caused by the erase operation can be suppressed. In other words, high-speed operation of the semiconductor device is realized. Since it does not require the high voltage required for writing and erasing with transistors, it is a semiconductor The power consumption of the device can be further reduced.

[0047] The semiconductor device according to the disclosed invention further includes a write transistor and a read transistor. Each memory cell needs to contain at least six transistors. It is possible to significantly reduce the area per memory cell compared to SRAM, which requires Therefore, semiconductor devices can be arranged at high density.

[0048] In addition, in conventional floating gate transistors, the gate insulating film (transistor) The charge transfer in the gate insulating film (tunnel insulating film) causes deterioration of the gate insulating film (tunnel insulating film). However, in the memory cell according to one embodiment of the present invention, The information is written by the switching operation of the read transistor, which is a problem that has not been solved in the past. This can eliminate the deterioration of the gate insulating film that was previously caused by the This means that there is no limit to the number of writes, and the rewrite endurance is extremely high. 10 9 No degradation in current-voltage characteristics is observed even after more than 1 billion writes .

[0049] Note that the field-effect mobility of the writing transistor 162 using an oxide semiconductor is In this state, 3 cm 2 / Vs or more 250cm 2 / Vs or less, preferably 5cm 2 / Vs or later Upper 200cm 2 / Vs or less, preferably 10cm 2 / Vs or more 150cm 2 / Vs or later In addition, a transistor using an oxide semiconductor has a subthreshold swing value (S value) should be 0.1V / dec. or less. Such a transistor should be used. This makes it possible to sufficiently shorten the time required to write information.

[0050] The channel length L of the writing transistor 162 using an oxide semiconductor is 10 nm or more. It is preferable that the channel size is 400 nm or less. This provides various benefits, such as faster operation of the register, lower power consumption, and higher integration.

[0051] The read transistor 160 is a transistor using crystalline silicon. In particular, from the viewpoint of increasing the speed of the read operation, it is preferable to use single crystal silicon. It is preferable to use an n-channel transistor. The capacitor can be formed, for example, using bulk silicon (so-called silicon wafer). do.

[0052] The above explanation applies to the case where an n-type transistor (n-channel transistor) is used. However, p-type transistors can be used instead of n-type transistors. It goes without saying.

[0053] <Plane and cross-sectional configurations of semiconductor device> 2A and 2B show an example of the configuration of the semiconductor device. 2(B) shows a plan view of the semiconductor device. These correspond to the cross sections taken along lines A1-A2 and B1-B2 in FIG. 2(A) and FIG. 2(B). The semiconductor device shown in FIG. 1 has a transistor 160 using a material other than an oxide semiconductor in the lower part. The transistor 162 includes an oxide semiconductor in the upper portion. Transistor 160 and transistor 162 are both described as n-type transistors. However, a p-type transistor may also be used. In particular, the transistor 160 is preferably a p-type transistor. It is easy to do this.

[0054] The transistor 160 includes a channel forming region 11 provided in a substrate 100 including a semiconductor material. 6, and the impurity region 114 and the high concentration impurity region 115 provided so as to sandwich the channel forming region 116. The pure region 120 (collectively referred to as the impurity region) and the channel forming region 11 6, and a gate electrode provided on the gate insulating layer 108. 110 and a source or drain electrode 130a electrically connected to the impurity region 114. , and a source electrode or a drain electrode 130b.

[0055] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110. In addition, as shown in the cross-sectional view, the region of the substrate 100 that does not overlap with the sidewall insulating layer 118 The semiconductor substrate 1 has a high-concentration impurity region 120, and a metal compound region 1 24 is present on the substrate 100. Also, an element isolation insulating film is present on the substrate 100 so as to surround the transistor 160. The layer 106 is provided over the transistor 160 and includes an interlayer insulating layer 126 and a An interlayer insulating layer 128 is provided. The source or drain electrode 130b is formed on the interlayer insulating layer 126 and the interlayer insulating layer 128. The source electrode is electrically connected to the metal compound region 124 through the opening. Alternatively, the drain electrode 130a and the source or drain electrode 130b may be formed in a metal compound region. The high concentration impurity region 120 and the impurity region 114 are electrically connected through the region 124. The gate electrode 110 is connected to a source electrode or a drain electrode 130a and a source electrode 130b. The electrode 130c provided similarly to the electrode or drain electrode 130b is electrically connected to the do.

[0056] The transistor 162 includes a gate electrode 136d provided on the interlayer insulating layer 128 and a gate A gate insulating layer 138 is provided on the electrode 136d, and a gate insulating layer 138 is provided on the gate insulating layer 138. an oxide semiconductor layer 140; and a metal oxide film provided on the oxide semiconductor layer 140. The source or drain electrode 142a is electrically connected to the source or drain electrode 142b. and an inner electrode 142b.

[0057] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. Similarly to the gate electrode 136d, the source electrode or The electrode 136a is in contact with the drain electrode 130a, and the source or drain electrode 130b Electrode 136b is formed in contact with electrode 130c, and electrode 136c is formed in contact with electrode 130c. do.

[0058] In addition, a protective film is formed on the transistor 162 so as to be in contact with part of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with a source electrode or a drain electrode. An opening is provided that reaches the source electrode 142a and the source or drain electrode 142b. Through the openings, the electrodes 150d and 150e are connected to the source and drain electrodes. The electrode 142a is formed in contact with the source electrode or the drain electrode 142b. As well as electrodes 150d and 150e, gate insulating layer 138, protective insulating layer 144, interlayer insulating layer The electrodes 136a, 136b, and 136c are in contact with each other through openings provided in the layer 146. Electrodes 150a, 150b, and 150c are formed.

[0059] Here, the oxide semiconductor layer 140 is highly purified by sufficiently removing impurities such as hydrogen. Specifically, the hydrogen concentration of the oxide semiconductor layer 140 is preferably 5×10 19 atoms / cm 3 Below 5×10 18 atoms / cm 3 Below, more hope Preferably 5 x 10 17 atoms / cm 3 This will reduce the general silicon wafer The carrier in the wafer (silicon wafer to which trace amounts of impurity elements such as phosphorus and boron are added) Rear density (1 x 10 14 / cm 3 A sufficiently small value of the carrier concentration (e.g. For example, 1 x 10 12 / cm 3 Less than or equal to 1.45 x 10 10 / cm 3 (less than) In this way, the hydrogen concentration is sufficiently reduced and the material is highly purified, becoming intrinsic (i-type) or substantially By using an oxide semiconductor that has been made intrinsic (i-type), it is possible to obtain extremely excellent off-current characteristics. For example, the transistor 162 can be obtained at room temperature (25° C.). The off-state current (here, the value per unit channel width (1 μm)) is 10 zA / μm ( 1zA (zeptoampere) is 1 x 10 -21 A) or less, preferably 1zA / μm or less At 85°C, the current is 100zA / μm (1×10 -19 A / μm) or less, preferably is 10zA / μm (1×10 -20 A / μm) or less. The oxide semiconductor layer 140 is reduced to an intrinsic state or substantially intrinsic state, and the transistor By reducing the off-current of the transistor 162, a semiconductor device with a new configuration can be realized. The hydrogen concentration in the oxide semiconductor layer 140 can be measured by secondary ion mass spectrometry ( Measured by SIMS (Secondary Ion Mass Spectroscopy) This is what was done.

[0060] An insulating layer 152 is provided on the interlayer insulating layer 146, and a buried insulating layer 152 is provided on the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so that the electrodes are embedded in the Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150a. b, electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 54d is in contact with electrode 150e.

[0061] That is, in the semiconductor device shown in FIG. 2, the gate electrode 110 of the transistor 160 and the The source electrode or drain electrode 142a of the transistor 162 is connected to the electrode 130c, the electrode 1 36c, electrode 150c, electrode 154c and electrode 150d. do.

[0062] <Method for manufacturing semiconductor device> Next, an example of a method for manufacturing the semiconductor device will be described. The method for fabricating the transistor 160 will be explained with reference to FIG. A method for manufacturing the capacitor 162 will be described with reference to FIGS.

[0063] <Method for manufacturing the lower transistor> First, a substrate 100 containing a semiconductor material is prepared (see FIG. 3(A)). The plate 100 may be a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be used. Here, the substrate 100 containing a semiconductor material is a single crystal silicon substrate. An example will be given below.

[0064] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an element isolation insulating layer. (See FIG. 3(A)). The protective layer 102 may be made of, for example, silicon oxide or silicon nitride. An insulating layer made of silicon nitride oxide or the like can be used. In order to control the threshold voltage of the transistor, impurities that give n-type conductivity are used. The substrate 100 may be doped with an impurity element that imparts p-type conductivity or a metal element that imparts p-type conductivity. In the case of silicon, impurities that give n-type conductivity include phosphorus and arsenic. In addition, impurities that impart p-type conductivity include, for example, boron and aluminum. Sodium, gallium, etc. can be used.

[0065] Next, etching is performed using the protective layer 102 as a mask, and the The part of the substrate 100 in the area where the semiconductor substrate 100 is not exposed is removed. The conductive region 104 is formed (see FIG. 3(B)). It is preferable to use an etching gas or an etchant, but wet etching may also be used. The etching liquid can be appropriately selected depending on the material to be etched.

[0066] Next, an insulating layer is formed so as to cover the semiconductor region 104, and the region overlapping the semiconductor region 104 is The insulating layer is selectively removed to form an element isolation insulating layer 106 (see FIG. 3(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon nitride oxide, etc. The insulating layer can be removed by polishing such as CMP or etching. After the semiconductor region 104 is formed or after the element isolation insulating film is formed, After the layer 106 is formed, the protective layer 102 is removed.

[0067] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. do.

[0068] The insulating layer will later become the gate insulating layer and is obtained using a method such as CVD or sputtering. Silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide It is preferable to use a single layer or multilayer structure of a film containing aluminum, tantalum oxide, etc. The surface of the semiconductor region 104 is oxidized or nitrided by plasma treatment or thermal oxidation treatment. The insulating layer may be formed by the high density plasma treatment. Using a mixture of rare gases such as Xe and oxygen, nitrogen oxide, ammonia, nitrogen, and hydrogen The thickness of the insulating layer is not particularly limited, but may be, for example, 1 nm or more and 10 nm or less. It can be 0 nm or less.

[0069] The layer containing the conductive material is made of a metal material such as aluminum, copper, titanium, tantalum, or tungsten. Also, the insulating film can be formed using a semiconductor material such as polycrystalline silicon containing a conductive material. The method for forming the conductive material layer is not particularly limited, and examples thereof include vapor deposition, C Various film formation methods such as VD method, sputtering method, and spin coating method can be used. In this embodiment mode, the layer containing a conductive material is formed using a metal material. The following information will be provided.

[0070] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108. Then, the gate electrode 110 is formed (see FIG. 3(C)).

[0071] Next, an insulating layer 112 is formed to cover the gate electrode 110 (see FIG. 3(C)). Phosphorus (P) or arsenic (As) is added to the conductive region 104 to form a shallow junction with the substrate 100. In this case, an n-type transistor is formed. However, when forming a p-type transistor, Impurity elements such as boron (B) and aluminum (Al) can be added. By forming the region 114, a channel-forming region is formed below the gate insulating layer 108 in the semiconductor region 104. A region 116 is formed (see FIG. 3(C)). Here, the concentration of the added impurity is set appropriately. However, when semiconductor elements are highly miniaturized, the concentration can be increased. In this case, the impurity region 114 is formed after the insulating layer 112 is formed. However, the process of forming the insulating layer 112 after forming the impurity region 114 is adopted. It is also possible to do so.

[0072] Next, a sidewall insulating layer 118 is formed (see FIG. 3(D)). The layer 118 is formed by forming an insulating layer to cover the insulating layer 112 and then applying a highly anisotropic By applying a simple etching process, it can be formed in a self-aligned manner. Then, the insulating layer 112 is partially etched to expose the upper surface of the gate electrode 110 and the impurity region 1. It is advisable to expose the top surface of 14.

[0073] Next, a layer is formed so as to cover the gate electrode 110, the impurity region 114, the sidewall insulating layer 118, etc. An insulating layer is formed on the impurity region 114. Then, phosphorus ( By adding ions such as P and arsenic (As), a high concentration impurity region 120 is formed (see FIG. 3(E)). After that, the insulating layer is removed, and the gate electrode 110, the sidewall insulating layer 118, A metal layer 122 is formed so as to cover the high concentration impurity region 120 and the like (see FIG. 3(E)). The metal layer 122 can be formed by various film forming methods such as vacuum deposition, sputtering, and spin coating. The metal layer 122 can be formed using the semiconductor material that constitutes the semiconductor region 104. It is desirable to form the electrode using a metal material that reacts with the electrode to form a low-resistance metal compound. Such metal materials include, for example, titanium, tantalum, tungsten, nickel, and cobalt. Examples include platinum and platinum.

[0074] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. A metal compound region 124 is formed in contact with the high concentration impurity region 120 (see FIG. 3(F)). When polycrystalline silicon or the like is used as the gate electrode 110, the gate electrode 110 A metal compound region is also formed in the portion in contact with the metal layer 122.

[0075] The heat treatment may be, for example, a heat treatment by irradiation with a flash lamp. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds In order to improve the controllability of the heat treatment, it is desirable to use a method that can realize a very short time of heat treatment. The metal compound region is preferably formed by a reaction between a metal material and a semiconductor material. The metal compound region is formed in a region where the conductivity is sufficiently increased. This can sufficiently reduce the electrical resistance and improve the device characteristics. After forming region 124, metal layer 122 is removed.

[0076] Next, an interlayer insulating layer 126 and an interlayer insulating layer 127 are formed to cover the respective components formed by the above-described steps. The interlayer insulating layer 126 and the interlayer insulating layer 128 are formed by oxidation. Silicon, silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, titanium oxide The insulating layer can be formed using a material containing an inorganic insulating material such as palladium. It is also possible to form the layer using an organic insulating material such as acrylic resin. The structure is a two-layer structure of an interlayer insulating layer 126 and an interlayer insulating layer 128. After the interlayer insulating layer 128 is formed, the surface may be subjected to a process such as CMP or etching. It is desirable to flatten the surface by using a method such as

[0077] Thereafter, openings are formed in the interlayer insulating layers 126 and 128, reaching the metal compound region 124. The source or drain electrode 130a and the source or drain electrode 130b are formed in the opening. The source electrode or drain electrode 130a or the like is formed (see FIG. 3(H)). The source electrode or drain electrode 130b is formed by, for example, PVD or CVD in the region including the opening. After forming a conductive layer using a method such as a silicon nitride film, the upper layer is then removed using a method such as etching or CMP. It can be formed by removing a portion of the conductive layer.

[0078] In addition, a part of the conductive layer is removed to form the source electrode or drain electrode 130a and the source electrode Alternatively, when forming the drain electrode 130b, the surface thereof is processed to be flat. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When a tungsten film is formed to fill the opening, the inclusions are removed by the subsequent CMP. It removes the necessary tungsten film, titanium film, titanium nitride film, etc., and also maintains the flatness of the surface. In this way, the source electrode or drain electrode 130a, By planarizing the surface including the source or drain electrode 130b, it is possible to This makes it possible to form good electrodes, wiring, insulating layers, semiconductor layers, and the like.

[0079] Here, the source electrode or drain electrode 130 in contact with the metal compound region 124 Although only the gate electrode 130a and the source electrode or the drain electrode 130b are shown, The electrode in contact with the port electrode 110 (for example, the electrode 130c in FIG. 2) is also formed. The source or drain electrode 130a, the source or drain electrode There are no particular limitations on the material that can be used for the electrode 130b, and various conductive materials can be used. For example, molybdenum, titanium, chromium, tantalum, tungsten, Conductive materials such as aluminum, copper, neodymium, and scandium can be used.

[0080] In this manner, the transistor 160 is formed using the substrate 100 containing a semiconductor material. After the above steps, electrodes, wiring, insulating layers, etc. may be further formed. In addition, by adopting a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers, Therefore, it is possible to provide a highly integrated semiconductor device.

[0081] <How to make the upper transistor> Next, referring to FIGS. 4 and 5, a process for forming a transistor 162 on the interlayer insulating layer 128 will be described. 4 and 5 show various electrodes and transistors on the interlayer insulating layer 128. Since the figure shows the manufacturing process of the transistor 162, the The transistor 160 and other components that correspond to it are omitted.

[0082] First, an interlayer insulating layer 128, a source electrode or drain electrode 130a, and a source electrode or drain electrode 130b are formed. An insulating layer 132 is formed on the drain electrode 130b and the electrode 130c (see FIG. 4(A)). The edge layer 132 can be formed by using a PVD method, a CVD method, or the like. silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The insulating film 10 can be formed using a material containing an inorganic insulating material such as silica.

[0083] Next, the source or drain electrode 130a, the source or drain electrode 130b, and the insulating layer 132 are Openings are formed that reach the drain electrode 130b and the electrode 130c. An opening is also formed in the region where the gate electrode 136d is to be formed. A conductive layer 134 is formed to fill the opening (see FIG. 4B). The mask can be formed by a method such as etching using a photomask. It can be formed by a method such as exposure. As for etching, wet etching is used. Either etching or dry etching may be used, but from the viewpoint of fine processing, dry etching is preferred. The conductive layer 134 is preferably formed by etching. The conductive layer 134 can be formed by a film formation method. are molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium Examples include conductive materials such as aluminum and scandium, as well as their alloys and compounds (e.g., nitrides). It can be obtained.

[0084] More specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then CV After forming a thin titanium nitride film by the D method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method is The outer electrode (here, the source electrode or the drain electrode 130a, the source electrode or the drain electrode The oxide film on the surface of the electrode 130b, electrode 130c, etc. is reduced to reduce the contact resistance with the lower electrode. In addition, the titanium nitride film formed afterwards has the function of suppressing the diffusion of the conductive material. It also has a barrier function that prevents the formation of a barrier film made of titanium or titanium nitride. Afterwards, a copper film may be formed by plating.

[0085] After the conductive layer 134 is formed, the conductive layer 134 is removed by etching or CMP. 34 is removed to expose the insulating layer 132, and the electrodes 136a, 136b, and 136c are formed. 36c and a gate electrode 136d are formed (see FIG. 4(C)). Parts are removed to form electrodes 136a, 136b, 136c, and gate electrode 136d. When doing so, it is desirable to process the insulating layer 13 so that the surface is flat. 2. Planarizing the surfaces of the electrodes 136a, 136b, 136c, and gate electrode 136d This allows for the formation of good electrodes, wiring, insulating layers, semiconductor layers, etc. in subsequent processes. This becomes possible.

[0086] Next, the insulating layer 132, the electrode 136a, the electrode 136b, the electrode 136c, and the gate electrode 136d The gate insulating layer 138 is formed to cover the gate insulating layer 138 (see FIG. 4(D)). The gate insulating layer can be formed by using a CVD method, a sputtering method, or the like. 138 is silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, oxide It is preferable to form the gate insulating film so as to contain hafnium, tantalum oxide, etc. The layer 138 may have a single layer structure or a multilayer structure. Silicon oxynitride was produced by plasma CVD using silane (SiH4), oxygen, and nitrogen. The thickness of the gate insulating layer 138 is not particularly limited. However, it can be, for example, 10 nm or more and 500 nm or less. For example, a first gate insulating layer having a film thickness of 50 nm or more and 200 nm or less and a first gate insulating layer It is preferable to laminate a second gate insulating layer having a thickness of 5 nm to 300 nm on the layer.

[0087] Note that an oxide semiconductor (high-temperature oxide semiconductor) that has been made i-type or substantially i-type by removing impurities is Since the purified oxide semiconductor is extremely sensitive to the interface states and the interface charges, When such an oxide semiconductor is used for the oxide semiconductor layer, the interface with the gate insulating layer is important. That is, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer has a high-quality oxide semiconductor layer. Quality will be required.

[0088] For example, the high density plasma CVD method using microwaves (2.45GHz) produces dense and high dielectric strength materials. This is advantageous in that a high quality gate insulating layer 138 can be formed. The contact between the conductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. This is because it can be made into something that is

[0089] Of course, if it can form a good insulating layer as a gate insulating layer, highly purified Even when an oxide semiconductor layer is used, other methods such as sputtering and plasma CVD are used. In addition, the film quality and the oxide semiconductor layer can be improved by heat treatment after the formation. Alternatively, an insulating layer may be applied to modify the interface properties of the gate insulating layer 138. The film quality as a gate insulating film is good, and the interface state density with the oxide semiconductor layer is reduced, resulting in a good interface. All that is required is to form something that can form a surface.

[0090] When impurities are contained in an oxide semiconductor, stresses such as a strong electric field or high temperature can cause The bond between the impurity and the main component of the oxide semiconductor is broken, and the resulting dangling bond is This induces a shift in Vth.

[0091] Impurities in the oxide semiconductor, particularly impurities such as hydrogen and water, are removed as much as possible, and the above-mentioned By improving the interface characteristics with the insulation layer, it is possible to withstand stresses such as strong electric fields and high temperatures. Therefore, it is possible to obtain a highly stable transistor.

[0092] Next, an oxide semiconductor layer is formed over the gate insulating layer 138 and etched using a mask. The oxide semiconductor layer is processed by the above method to form an island-shaped oxide semiconductor layer 140. (See Figure 4(E)).

[0093] The oxide semiconductor layer includes In-Ga-Zn-O, In-Sn-Zn-O, and In-A l-Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn -O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn- It is preferable to use an O-based or Zn—O-based oxide semiconductor layer, especially an amorphous oxide semiconductor layer. In this embodiment, an In—Ga—Zn—O-based oxide semiconductor is formed as the oxide semiconductor layer. An amorphous oxide semiconductor layer is formed by a sputtering method using a target for sputtering. Note that adding silicon to an amorphous oxide semiconductor layer can suppress crystallization. Therefore, for example, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used. An oxide semiconductor layer may be formed using the above-mentioned method.

[0094] Examples of targets for forming an oxide semiconductor layer by sputtering include oxide A target for forming an oxide semiconductor film containing zinc as a main component can be used. A target for forming oxide semiconductor films containing Ga and Zn (composition ratio: In2O3:G It is also possible to use In, As a target for forming oxide semiconductor films containing Ga and Zn, In2O3:Ga2O3 :ZnO=1:1:2 [molar ratio], or In2O3:Ga2O3:ZnO=1:1: A target having a composition ratio of 4 [mol ratio] may also be used. The target filling rate is 90% or more and 100% or less, preferably 95% or more (for example, 99.9%). By using a target for oxide semiconductor film formation with a high filling rate, dense oxide A compound semiconductor layer is formed.

[0095] The oxide semiconductor layer is formed in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or Alternatively, it is preferable to use a mixed atmosphere of rare gas (typically argon) and oxygen. Specifically, the concentration of impurities such as hydrogen, water, compounds with hydroxyl groups, or hydrides. It is preferable to use a high-purity gas in which the amount of CO₂ has been reduced to about several ppm (preferably about several ppb). It is suitable.

[0096] When forming the oxide semiconductor layer, the substrate is held in a treatment chamber kept in a reduced pressure state. The temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating, the impurity concentration in the oxide semiconductor layer can be reduced. In addition, damage to the oxide semiconductor layer caused by sputtering can be reduced. Then, the sputtering gas from which hydrogen and water have been removed is introduced while removing the remaining moisture in the processing chamber. The oxide semiconductor layer is formed by using a metal oxide as a target. To remove the particles, it is preferable to use an adsorption type vacuum pump. For example, a cryopump Pumps, ion pumps, and titanium sublimation pumps can be used. The stage may be a turbopump plus a cold trap. The film-forming chamber evacuated using a pump contains, for example, hydrogen atoms, water ( Since compounds containing hydrogen atoms such as H2O are exhausted, the oxide semiconductor formed in the film formation chamber The concentration of impurities contained in the conductor layer can be reduced.

[0097] The formation conditions are, for example, a distance of 100 mm between the substrate and the target, a pressure of 0.6 Pa, DC power 0.5kW, oxygen atmosphere (oxygen flow rate 100%), The following conditions can be applied. When a pulsed direct current (DC) power supply is used, film formation can be performed. This reduces the amount of powdery material (also called particles or dust) that is generated at times, and reduces the film thickness distribution. The thickness of the oxide semiconductor layer is preferably 2 nm or more and 200 nm or less, more preferably 5 nm or less. The thickness is from 100 nm to 30 nm. The appropriate thickness varies depending on the oxide semiconductor material used. Therefore, the thickness may be appropriately selected depending on the material used.

[0098] Before forming the oxide semiconductor layer by sputtering, argon gas was introduced to Reverse sputtering is performed to generate a smear, and dust adhering to the surface of the gate insulating layer 138 is removed. Here, the reverse sputtering is a method of removing the sputtering Instead of bombarding the target with ions, the treatment surface is bombarded with ions. The method of bombarding the treated surface with ions is as follows: A high frequency voltage is applied to the surface to be treated in an argon atmosphere to generate plasma near the substrate. In addition, nitrogen atmosphere, helium atmosphere, oxygen atmosphere, etc. can be used instead of argon atmosphere. An atmosphere or the like may also be used.

[0099] The oxide semiconductor layer can be etched by either dry etching or wet etching. Of course, both can be used in combination. To enable etching, the etching conditions (etching gas, etching solution, etc.) are adjusted to suit the material. The etching time, temperature, etc. are set appropriately.

[0100] The etching gas used in dry etching is, for example, a gas containing chlorine (chlorine-based gas, For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride ( CCl4) and other gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride). Fluorine (CF4), sulfur fluoride (SF6), nitrogen fluoride (NF3), trifluoromethane (CHF 3), hydrogen bromide (HBr), oxygen (O2), and the addition of helium (He) or argon (Ar). A gas containing a rare gas such as argon (Ar) may also be used.

[0101] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A plasma-coupled plasma etching method can be used. As shown in the figure, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) The amount of power, the temperature of the electrode on the substrate, etc. are set appropriately.

[0102] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) or the like may be used.

[0103] Next, the oxide semiconductor layer is preferably subjected to first heat treatment. The oxide semiconductor layer can be dehydrated or dehydrogenated by the first heat treatment. The temperature is set to 300°C or higher and 750°C or lower, preferably 400°C or higher and lower than the strain point of the substrate. For example, The substrate is placed in an electric furnace using a resistance heating element or the like, and the oxide semiconductor layer 140 is heated in a nitrogen atmosphere. Heat treatment is performed at 450° C. in air for 1 hour. Avoid contact and ensure that water or hydrogen is not recontaminated.

[0104] The heat treatment device is not limited to an electric furnace, and may be any device that uses heat conduction from a medium such as heated gas, or It may also be a device that heats the object to be treated by thermal radiation. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure water A device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp such as a silver lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. A gas is used.

[0105] For example, in the first heat treatment, the substrate is immersed in an inert gas heated to a high temperature of 650°C to 700°C. After heating for several minutes, the substrate is taken out of the inert gas (GRTA) treatment. GRTA treatment allows high-temperature heat treatment in a short time. Because it is a heat treatment, it can be applied even at temperatures exceeding the distortion point of the substrate.

[0106] The first heat treatment is performed in a gas atmosphere containing nitrogen or a rare gas (helium, neon, argon, etc.) as the main component. It is desirable to carry out the process in an atmosphere that does not contain water, hydrogen, etc. The purity of nitrogen or rare gases such as helium, neon, and argon introduced into the heat treatment device is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e. The impurity concentration is 1 ppm or less, preferably 0.1 ppm or less.

[0107] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized. For example, the crystallinity may be 90% or more, or 80% or more. % or more of a microcrystalline oxide semiconductor layer. Depending on the material of the oxide semiconductor layer, it may become an amorphous oxide semiconductor layer that does not contain crystalline components. There are also cases where this is the case.

[0108] In addition, microcrystals (grain size of 1 nm or less) are formed on the amorphous oxide semiconductor (for example, on the surface of the oxide semiconductor layer). The oxide semiconductor layer is a mixture of the upper 20 nm or less (typically 2 nm to 4 nm). There are cases like this.

[0109] In addition, the electrical properties of the oxide semiconductor layer can be changed by arranging microcrystals in the amorphous region. For example, it is possible to use an In-Ga-Zn-O based oxide semiconductor film formation target. When forming an oxide semiconductor layer using a SiO2 substrate, the In2Ga2Z layer has electrical anisotropy. By forming a microcrystalline part where the crystal grains of nO7 are oriented, the electrical properties of the oxide semiconductor layer can be changed. It can be made into

[0110] More specifically, for example, the c-axis of In2Ga2ZnO7 is perpendicular to the surface of the oxide semiconductor layer. By orienting the oxide semiconductor layer in this direction, the conductivity in the direction parallel to the surface of the oxide semiconductor layer is improved. This can improve the insulating properties in the direction perpendicular to the surface of the oxide semiconductor layer. The microcrystalline portion has a function of suppressing the penetration of impurities such as water and hydrogen into the oxide semiconductor layer. It has.

[0111] The oxide semiconductor layer having the above-described microcrystalline portion is formed by GRTA treatment. It can be formed by heating. In addition, the Zn content is higher than the In or Ga content. By using a small sputtering target, it is possible to form the film more suitably.

[0112] The first heat treatment on the oxide semiconductor layer 140 is performed to process the oxide semiconductor layer 140 into an island-shaped oxide semiconductor layer 140. In this case, the first heat treatment is performed on the oxide semiconductor layer. The substrate is then removed and subjected to a photolithography process.

[0113] The first heat treatment has the effect of dehydrating and dehydrogenating the oxide semiconductor layer 140. Therefore, it can also be called dehydration treatment, dehydrogenation treatment, etc. The hydrogenation treatment is carried out after forming the oxide semiconductor layer, by forming a source electrode or a drain electrode on the oxide semiconductor layer 140. After laminating the source electrode and drain electrode, a protective insulating layer is formed on the source electrode or drain electrode. In addition, such dehydration treatment, dehydration The oxidation treatment may be carried out not only once but also multiple times.

[0114] Next, a source electrode or drain electrode 142a, The source or drain electrode 142b is formed (see FIG. 4(F)). The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 1 After forming a conductive layer to cover 40, the conductive layer is selectively etched. It can be formed.

[0115] The conductive layer is formed using PVD methods such as sputtering, or CVD methods such as plasma CVD. The conductive layer can be formed using a material such as aluminum, chromium, copper, Elements selected from tantalum, titanium, molybdenum, and tungsten, or the above elements Alloys containing manganese, magnesium, zirconium, beryllium, etc. can be used. Alternatively, one or more materials selected from the group consisting of aluminum and thorium may be used. Titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium Alternatively, a material containing a single element selected from the group consisting of aluminum and a combination of multiple elements may be used. It may have a single layer structure or a laminated structure of two or more layers. Single-layer aluminum film structure, two-layer aluminum film with titanium film laminated on top, titanium Examples of such a structure include a three-layer structure in which a film, an aluminum film, and a titanium film are laminated.

[0116] Here, ultraviolet light, KrF laser light, ArF Preferably, a laser beam is used.

[0117] The channel length (L) of the transistor is the distance from the bottom end of the source or drain electrode 142a to the , is determined by the distance between the lower end of the source electrode or drain electrode 142b. When exposure is performed with a channel length (L) of less than 25 nm, the channel length is extremely small, ranging from several nm to several tens of nm. Extreme ultraviolet light with extremely short wavelengths is used to create a mask-shaped Extreme ultraviolet light exposure provides high resolution and a large depth of focus. The channel length (L) of the formed transistor is set to 10 nm or more and 1000 nm or less. Furthermore, the off-state current is extremely small, This prevents the power consumption from becoming too large.

[0118] When etching the conductive layer, the oxide semiconductor layer 140 is not removed. The materials and etching conditions are adjusted appropriately. In this step, a part of the oxide semiconductor layer 140 is etched to form a groove (a recess ) may be formed as an oxide semiconductor layer.

[0119] In addition, between the oxide semiconductor layer 140 and the source electrode or the drain electrode 142a, An oxide conductive layer is formed between the conductive layer 140 and the source or drain electrode 142b. The oxide conductive layer and the source or drain electrode 142a or the source or drain electrode 142b may be The metal layer for forming the drain electrode 142b is formed continuously (continuous film formation). The oxide conductive layer can function as a source region or a drain region. By providing such an oxide conductive layer, it is possible to reduce the resistance of the source region or the drain region. This allows the transistor to operate at high speed.

[0120] In order to reduce the number of masks used and the number of processes, an exposure method is used in which the transmitted light has multiple intensities. A resist mask is formed using a multi-tone mask, which is a mask, and an etching process is performed using this. The resist mask formed using the multi-tone mask has a plurality of thicknesses. The shape becomes stepped, and the shape can be further deformed by ashing. It can be used for multiple etching processes to process different patterns. A multi-tone mask allows for resist masks that correspond to at least two different patterns. Therefore, the number of exposure masks can be reduced, and the corresponding photomasks can be formed. The lithography process can also be eliminated, simplifying the process.

[0121] After the above process, plasma treatment using gas such as N2O, N2, or Ar may be performed. It is preferable that the plasma treatment is performed on the exposed surface of the oxide semiconductor layer. Adhered water and other substances are removed. In addition, plasma treatment is performed using a mixture of oxygen and argon gas. You may go.

[0122] Next, the protective insulating layer 14 in contact with a part of the oxide semiconductor layer 140 is removed without being exposed to the air. 4 is formed (see Figure 4(G)).

[0123] The protective insulating layer 144 is formed by a method such as sputtering, which does not mix impurities such as water or hydrogen into the protective insulating layer 144. The thickness of the insulating film is 1 nm or more. Examples of materials that can be used for the protective insulating layer 144 include silicon oxide, silicon nitride, and silicon oxynitride. The structure may be a single layer structure or a multilayer structure. The substrate temperature when the protective insulating layer 144 is formed is set to be equal to or higher than room temperature and equal to or lower than 300° C. The atmosphere is preferably a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare A mixed atmosphere of gas (typically argon) and oxygen is preferred.

[0124] If hydrogen is contained in the protective insulating layer 144, the hydrogen may penetrate into the oxide semiconductor layer or the oxide semiconductor layer may be damaged by the hydrogen. Oxygen is extracted from the oxide semiconductor layer by the oxide semiconductor layer. Therefore, the protective insulating layer 1 may have a low resistance and a parasitic channel may be formed. It is important to avoid using hydrogen in the formation method so that 44 does not contain as much hydrogen as possible. is.

[0125] In addition, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. The compound semiconductor layer 140 and the protective insulating layer 144 are formed so as not to contain hydrogen, hydroxyl groups, or water. This is because.

[0126] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O) and other compounds containing hydrogen atoms are removed, The concentration of impurities contained in the layer 144 can be reduced.

[0127] The sputtering gas used when forming the protective insulating layer 144 is a gas containing hydrogen, water, and a hydroxyl group. The concentration of impurities such as compounds or hydrides is on the order of a few ppm (preferably on the order of a few ppb). It is preferable to use a high purity gas in which the concentration has been reduced to 100 ppm.

[0128] Then, a second heat treatment (preferably 20 It is desirable to carry out the heating at a temperature of 0°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. Then, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. This can reduce variations in the electrical characteristics of the transistors.

[0129] In addition, even if heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours, This heat treatment can be carried out by maintaining a constant heating temperature, or by heating from room temperature to 100°C or higher. Repeat the heating process several times to a temperature of 200°C or less and then to room temperature. This heat treatment may also be carried out under reduced pressure before the formation of the protective insulating layer. When the heat treatment is performed under reduced pressure, the heating time can be shortened. The treatment may be carried out in place of the second heat treatment, or may be carried out before or after the second heat treatment. stomach.

[0130] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 5(A)). The edge layer 146 can be formed by using a PVD method, a CVD method, or the like. silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The interlayer insulating layer 146 can be formed using a material containing an inorganic insulating material such as silica. After that, it is desirable to flatten the surface by a method such as CMP or etching. It's nice.

[0131] Next, the electrode 1 is formed on the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138. 36a, electrode 136b, electrode 136c, source or drain electrode 142a, source An opening is formed so as to reach the electrode or drain electrode 142b, and a conductive layer is formed so as to be embedded in the opening. A conductive layer 148 is formed (see FIG. 5B). The opening is formed by etching using a mask or the like. The mask can be formed by a method such as exposure using a photomask. The etching can be wet etching or dry etching. However, from the viewpoint of fine processing, it is recommended to use dry etching. The conductive layer 148 is preferably formed by a film forming method such as a PVD method or a CVD method. Materials that can be used to form the conductive layer 148 include molybdenum, titanium, and the like. Tantalum, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. Examples include any conductive material, their alloys, and compounds (e.g., nitrides).

[0132] Specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then a CVD method is applied. After forming a thin titanium nitride film by this method, a tungsten film is formed so as to fill the opening. Here, the titanium film formed by the PVD method is Electrodes (here, electrode 136a, electrode 136b, electrode 136c, source electrode or drain electrode) The oxide film formed on the surface of the electrode 142a, the source electrode or the drain electrode 142b is reduced. This has the function of reducing the contact resistance with the lower electrode. The silicon film has a barrier function that suppresses the diffusion of conductive materials. After forming a barrier film such as a copper film, a copper film may be formed by plating.

[0133] After the conductive layer 148 is formed, the conductive layer 148 is removed by a method such as etching or CMP. 150a, 150b, and 150c are removed to expose the interlayer insulating layer 146. Then, the conductive layer 50c, the electrode 150d, and the electrode 150e are formed (see FIG. 5(C)). A part of 148 is removed to form electrodes 150a, 150b, 150c, 150d, and When forming the pole 150e, it is desirable to process it so that the surface is flat. As shown, the interlayer insulating layer 146, the electrode 150a, the electrode 150b, the electrode 150c, the electrode 150d, By planarizing the surface of the electrode 150e, it is possible to obtain good electrodes, wiring, and insulation in the subsequent processes. It is possible to form an edge layer, etc.

[0134] Furthermore, an insulating layer 152 is formed, and the electrodes 150a, 150b, and 150c are attached to the insulating layer 152. 50c, the electrode 150d, and the electrode 150e are formed, and the insulating layer 150 is embedded in the opening. After forming the conductive layer as shown above, a part of the conductive layer is removed by a method such as etching or CMP. , the insulating layer 152 is exposed, and the electrodes 154a, 154b, 154c, and 154 This step is the same as that for forming the electrodes 150a and the like. Therefore, I will omit the details.

[0135] When the transistor 162 is manufactured by the above method, the hydrogen concentration in the oxide semiconductor layer 140 is Degrees are 5 x 10 19 atoms / cm 3 and the off-current of the transistor 162 is The hydrogen concentration is sufficiently reduced and the purity is increased. By using the oxide semiconductor layer 140, the transistor 162 can have excellent characteristics. In addition, a transistor 160 using a material other than an oxide semiconductor is provided in the lower portion, and A semiconductor device with excellent characteristics having a transistor 162 using an oxide semiconductor in a portion thereof is manufactured. It is possible.

[0136] In addition, examples of semiconductor materials that can be compared with oxide semiconductors include silicon carbide (e.g., 4H Oxide semiconductors and 4H-SiC have several things in common. The carrier density of an oxide semiconductor at room temperature is 10 -7 / cm 3 Process This is estimated to be 6.7 × 10 -11 / cm 3 Similar to , which is an extremely low value. The intrinsic carrier density of silicon (1.4 × 10 10 / cm 3 degree) When compared to this, it is easy to see how extraordinary the level of this is.

[0137] The energy band gap of oxide semiconductors is 3.0 to 3.5 eV, and 4H-S The energy band gap of iC is 3.26 eV, so it is called a wide-gap semiconductor. Oxide semiconductors and silicon carbide have in common this point as well.

[0138] On the other hand, there is a significant difference between oxide semiconductors and silicon carbide. The process temperature is 1500℃ to 2000℃. However, it is difficult to form a laminated structure with semiconductor elements using other semiconductor materials. This is because the semiconductor substrate and semiconductor elements are destroyed. It is made by heat treatment at 300 to 500°C (below the glass transition temperature, up to about 700°C). It is possible to form an integrated circuit using other semiconductor materials and then use an oxide semiconductor. This makes it possible to form a semiconductor element.

[0139] In addition, unlike silicon carbide, it is possible to use a substrate with low heat resistance, such as a glass substrate. Furthermore, compared to silicon carbide, it has the advantage that it does not require high-temperature heat treatment. This has the advantage that the energy cost can be sufficiently reduced.

[0140] Although much research has been done on the physical properties of oxide semiconductors, In one embodiment of the disclosed invention, the localized level itself is sufficiently reduced. By removing water and hydrogen, which can cause intrinsic levels, from the oxide semiconductor, a highly purified oxide This is to create a compound semiconductor that sufficiently reduces the localized levels in the energy gap. This is the idea that we are able to manufacture extremely excellent industrial products. This makes it possible.

[0141] Furthermore, oxygen is supplied to the dangling bonds of the metal that are generated due to oxygen deficiency, and oxygen vacancies are eliminated. By reducing the localized levels, a more highly purified (i-type) oxide semiconductor can be obtained. For example, an oxide film containing excess oxygen may be formed in contact with the channel forming region, By supplying oxygen from the oxide film, it is possible to reduce localized levels due to oxygen defects. .

[0142] Defects in oxide semiconductors include shallow levels below the conduction band due to excess hydrogen and deep levels due to a lack of oxygen. In order to eliminate these defects, hydrogen is thoroughly Remove and provide adequate oxygen.

[0143] Conduction mechanism of transistors using oxide semiconductors Next, the conduction mechanism of a transistor using an oxide semiconductor will be described with reference to FIGS. 11 to 14. In the following description, an ideal situation is assumed for ease of understanding.

[0144] FIG. 11 is a cross-sectional view of an inverted staggered transistor using an oxide semiconductor. an oxide semiconductor layer (OS) is provided on the electrode layer (GE1) via a gate insulating layer (GI); A source electrode (S) and a drain electrode (D) are provided thereon.

[0145] 12(A) and 12(B) show the energy band structure along A-A' in FIG. FIG. 12(A) shows the state where no voltage is applied to the gate electrode layer (V G =0), and When no voltage is applied to either the drain electrode or the source electrode, or when the same voltage is applied to both electrodes, This is the case (V S =V D = 0, or V S =V D ) Figure 12(B) shows the drain electrode Positive voltage (V D >0), the dashed line shows the case where no voltage is applied to the gate electrode layer (V G =0), the solid line indicates a positive voltage (V G > 0) is applied. When no voltage is applied to the electrode layer, the high potential barrier prevents the oxide semiconductor from This indicates the off state where no carriers (electrons) are injected into the body side and no current flows. When a positive voltage is applied to the electrode layer, the potential barrier decreases, indicating an on-state in which current flows.

[0146] 13(A) and 13(B) show energy band diagrams in the cross section taken along the line B-B' in FIG. 11. (schematic diagram). FIG. 13(A) shows a gate electrode layer (GE1) with a positive potential (V G >0) In a given state, carriers (electrons) flow between the source and drain electrodes. FIG. 13(B) shows the gate electrode layer (GE1) in a negative potential (V G <0) is applied and the state is off (minority carriers do not flow). show.

[0147] Figure 14 shows the relationship between the vacuum level and the work function (φ M ) and the electron affinity (χ) of the oxide semiconductor Shows.

[0148] Metals are degenerate, with the Fermi level located within the conduction band. It is n-type and its Fermi level (E f ) is the intrinsic Fermi element located in the center of the band gap. Level (E i ) and is located closer to the conduction band. It is known that some of the oxygen deficiency becomes a donor, which is one of the factors that causes n-type formation. It is known that loss is also one of the factors that cause n-type conversion.

[0149] In contrast, an oxide semiconductor according to one embodiment of the disclosed invention can convert hydrogen, which is a factor in making the oxide semiconductor n-type, into an oxide. The oxide semiconductor is made of a material that contains as few impurity elements as possible, other than the main components of the oxide semiconductor. By purifying the material so that it is not susceptible to oxygen deficiency, it is made into an intrinsic (i-type) material, or by removing the oxygen deficiency, it is made into an intrinsic (i-type) material. In other words, instead of adding impurity elements to make it i-type, By removing impurities such as hydrogen and water and oxygen vacancies as much as possible, highly purified i-type (intrinsic) This allows the Fermi level (E f ) is the intrinsic Fermi level (E i ) can be made to the same extent as

[0150] The band gap (E g ) is 3.15 eV, and the electron affinity (χ) is 4.3 e V. The work function of titanium (Ti) that makes up the source and drain electrodes is The electron affinity (χ) of the oxide semiconductor is approximately equal to the electron affinity (χ) of the metal-oxide semiconductor interface. In this case, no Schottky barrier is formed for electrons.

[0151] Metal work function (φ M When the electron affinity (χ) of the oxide semiconductor is equal to that of the oxide semiconductor, As a result, an energy band diagram (schematic diagram) such as that shown in FIG. 12(A) is obtained.

[0152] In Figure 12(B), black circles (●) represent electrons. When a positive potential is applied to the drain electrode, , electrons are injected into the oxide semiconductor across the barrier (h) and flow toward the drain electrode. The barrier height (h) depends on the gate voltage (V G ) but varies depending on the positive drain voltage When a voltage is applied to the drain electrode, the barrier height in FIG. 12(A) without voltage application, That is, the band gap (E g ) or lower.

[0153] At this time, the electrons are transported between the gate insulating layer and the highly purified oxide semiconductor, as shown in FIG. They move near the interface with the body (the lowest energetically stable part of the oxide semiconductor).

[0154] Also, as shown in FIG. 13(B), when a negative potential is applied to the gate electrode (GE1), Since the number of holes, which are minority carriers, is essentially zero, the current is close to zero. .

[0155] For example, if the off-state current at room temperature (25°C) is 10 zA / μm (1×10 -20 A / μm ) or less, or 1zA / μm (1×10 -21 A / μm) or less, and therefore, A transistor with a threshold swing value (S value) of 0.1V / dec. is obtained.

[0156] In this way, the oxide semiconductor is prepared so that impurities other than the main components of the oxide semiconductor are not included as much as possible. High purification can improve the operation of the transistor.

[0157] <Modification> 6 to 9 show modified examples of the configuration of the semiconductor device. In the following, the following modified examples are mentioned: The following describes a case where the configuration of the transistor 162 is different from that described above. The configuration of the controller 160 is the same as above.

[0158] 6, a gate electrode 136d is provided under the oxide semiconductor layer 140, and a source electrode or drain electrode The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 14. The transistor 162 has a structure in which the lower surface of the transistor 162 is in contact with the oxide semiconductor layer 140. Here, the structure of the plane can be changed appropriately according to the cross section. Only the surface will be shown.

[0159] The major difference between the configuration shown in FIG. 6 and the configuration shown in FIG. 2 is the source electrode or drain electrode. 142a or the source electrode or drain electrode 142b and the oxide semiconductor layer 140. That is, in the configuration shown in FIG. 2, the upper surface of the oxide semiconductor layer 140 has a , the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, 6, the oxide semiconductor layer 140 is in contact with the lower surface of the oxide semiconductor layer 140. The source electrode or drain electrode 142a and the source electrode or drain electrode 142b are in contact with each other. Due to this difference in contact, the arrangement of other electrodes, insulating layers, etc. may differ. The details of each component are the same as in Figure 2.

[0160] Specifically, a gate electrode 136d provided on the interlayer insulating layer 128 and a gate electrode 136 a gate insulating layer 138 provided on the gate insulating layer 138; a source or drain electrode 142a, a source or drain electrode 142b, and a source electrode or in contact with the upper surface of the drain electrode 142a, the source electrode or the drain electrode 142b. and an oxide semiconductor layer 140.

[0161] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. Similarly to the gate electrode 136d, the source electrode or The electrode 136a is in contact with the drain electrode 130a, and the source or drain electrode 130b Electrode 136b is formed in contact with electrode 130c, and electrode 136c is formed in contact with electrode 130c. do.

[0162] In addition, a protective film is formed on the transistor 162 so as to be in contact with part of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with a source electrode or a drain electrode. An opening is provided that reaches the source electrode 142a and the source or drain electrode 142b. Through the openings, the electrodes 150d and 150e are connected to the source and drain electrodes. The electrode 142a is formed in contact with the source electrode or the drain electrode 142b. As well as electrodes 150d and 150e, gate insulating layer 138, protective insulating layer 144, interlayer insulating layer The electrodes 136a, 136b, and 136c are in contact with each other through openings provided in the layer 146. Electrodes 150a, 150b, and 150c are formed.

[0163] An insulating layer 152 is provided on the interlayer insulating layer 146, and a buried insulating layer 152 is provided on the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so that the electrodes are embedded in the Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150a. b, electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 54d is in contact with electrode 150e.

[0164] FIG. 7 shows an example of a configuration in which a gate electrode 136d is provided on an oxide semiconductor layer 140. 7A shows the source or drain electrode 142a and the source or drain electrode 142b. The oxide semiconductor layer 140 is connected to the lower surface of the oxide semiconductor layer 140 by a contact electrode 142b. 7B shows an example of a configuration in which the source electrode or drain electrode 142a and the source The drain electrode 142b is formed on the upper surface of the oxide semiconductor layer 140. This is an example of a configuration in contact with the conductor layer 140.

[0165] 7 is different from the configurations shown in FIGS. 2 and 6 in that a 7A and 7B. The major difference in the configuration is the source electrode or drain electrode 142a. The drain electrode 142b is located on either the lower surface or the upper surface of the oxide semiconductor layer 140. These differences lead to the question of whether the other electrodes, insulators, The arrangement of layers is different. The details of each component are the same as in Figure 2.

[0166] Specifically, in FIG. 7A, the source electrode or the drain electrode provided on the interlayer insulating layer 128 a source or drain electrode 142a, a source or drain electrode 142b, and a The oxide semiconductor in contact with the upper surface of the electrode 142a, the source electrode or the drain electrode 142b a gate insulating layer 138 provided on the oxide semiconductor layer 140; and a gate electrode 136d in a region overlapping with the oxide semiconductor layer 140 on the gate electrode 138.

[0167] 7B, the oxide semiconductor layer 140 provided over the interlayer insulating layer 128 and the oxide semiconductor layer 140 are A source electrode or a drain electrode 1 is provided in contact with the upper surface of the compound semiconductor layer 140. 42a, a source electrode or a drain electrode 142b, an oxide semiconductor layer 140, a source electrode or drain electrode 142a and the source or drain electrode 142b. The gate insulating layer 138 overlaps with the oxide semiconductor layer 140 on the gate insulating layer 138. and a gate electrode 136d in the region.

[0168] In the configuration shown in FIG. 7, compared to the configuration shown in FIG. 2, some components can be omitted. In this case, the manufacturing process can be simplified. Of course, this is not essential in the configuration shown in FIG. It goes without saying that components can be omitted.

[0169] FIG. 8 shows a case where the size of the element is relatively large, and a gate electrode is provided below the oxide semiconductor layer 140. This is an example of a configuration having an electrode 136d. In this case, the requirements for surface flatness and coverage are met. Since the requirements are relatively gentle, wiring, electrodes, etc. can be formed by embedding them in the insulating layer. For example, the gate electrode 136 can be formed by patterning the conductive layer after it is formed. Although not shown here, it is possible to form the transistor 160 can also be fabricated in the same manner.

[0170] The major difference between the configuration shown in FIG. 8(A) and the configuration shown in FIG. 8(B) is the source electrode or drain electrode. The source electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 140. The question is whether the contact occurs on the lower or upper surface of the Due to these differences, the arrangement of other electrodes, insulating layers, etc. is also different. The details of the components are the same as those in FIG.

[0171] Specifically, in FIG. 8A, a gate electrode 136d is provided on the interlayer insulating layer 128, A gate insulating layer 138 is provided on the gate electrode 136d. The source or drain electrode 142a, the source or drain electrode 142 b, and the source or drain electrode 142a, the source or drain electrode 142b and an oxide semiconductor layer 140 in contact with the upper surface of the substrate.

[0172] In FIG. 8B, a gate electrode 136d is provided on the interlayer insulating layer 128, and a gate A gate insulating layer 138 provided on the electrode 136d, and a gate electrode on the gate insulating layer 138 The oxide semiconductor layer 140 provided in a region overlapping with the oxide semiconductor layer 136d, A source electrode or drain electrode 142a provided in contact with the upper surface, a source electrode or a drain electrode 142b.

[0173] In addition, the configuration shown in FIG. 8 also allows for elimination of components compared to the configuration shown in FIG. 2, etc. In this case, too, the effect of simplifying the manufacturing process can be obtained.

[0174] FIG. 9 shows a case where the size of the element is relatively large, in which a gate electrode is formed on the oxide semiconductor layer 140. This is an example of a configuration having an electrode 136d. In this case, too, consideration is given to the flatness of the surface and coverage. Since the requirements for this are relatively mild, wiring and electrodes can be embedded in the insulating layer. For example, by patterning after forming the conductive layer, the gate electrode 1 Although not shown here, it is possible to form transistor 1 60 can also be produced in the same manner.

[0175] The major difference between the configuration shown in FIG. 9(A) and the configuration shown in FIG. 9(B) is the source electrode or drain electrode. The source electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 140. The question is whether the contact occurs on the lower or upper surface of the Due to these differences, the arrangement of other electrodes, insulating layers, etc. is also different. The details of the components are the same as those in FIG.

[0176] Specifically, in FIG. 9A, the source electrode or the drain electrode provided on the interlayer insulating layer 128 a source or drain electrode 142a, a source or drain electrode 142b, and a The oxide semiconductor in contact with the upper surface of the electrode 142a, the source electrode or the drain electrode 142b layer 140, a source or drain electrode 142a, a source or drain electrode 1 42b, a gate insulating layer 138 provided on the oxide semiconductor layer 140, and a gate insulating layer 13 and a gate electrode 136d provided in a region overlapping with the oxide semiconductor layer 140 on the gate electrode 136. do.

[0177] 9B, the oxide semiconductor layer 140 provided over the interlayer insulating layer 128 and the oxide semiconductor layer 140 are A source electrode or a drain electrode 1 is provided in contact with the upper surface of the compound semiconductor layer 140. 42a, source or drain electrode 142b, and source or drain electrode 14 2a, a source electrode or a drain electrode 142b, a gate electrode provided on the oxide semiconductor layer 140, The gate insulating layer 138 is provided in a region overlapping with the oxide semiconductor layer 140 on the gate insulating layer 138. and a gate electrode 136d.

[0178] In addition, the configuration shown in FIG. 9 also allows for elimination of components compared to the configuration shown in FIG. 2. In this case, too, the effect of simplifying the manufacturing process can be obtained.

[0179] As described above, one embodiment of the disclosed invention realizes a semiconductor device with a novel structure. In this embodiment, the transistor 160 and the transistor 162 are stacked. However, the configuration of the semiconductor device is not limited to this example. In this configuration, the channel lengths of the transistors 160 and 162 are perpendicular to each other. The positional relationship between the transistor 160 and the transistor 162 is the same as in the above example. Furthermore, the transistor 160 and the transistor 162 may be overlapped. It may be provided.

[0180] For ease of understanding, the present embodiment will be described with reference to a semiconductor device with a minimum storage unit (1 bit). However, the configuration of the semiconductor device is not limited to this. By appropriately connecting the components, it is possible to construct a more advanced semiconductor device. By using multiple devices, it is possible to configure a NAND or NOR type semiconductor device. The configuration is not limited to that shown in FIG. 1 and can be modified as appropriate.

[0181] The semiconductor device according to this embodiment has a very low off-state current due to the low off-state current of the transistor 162. It is possible to retain information for a long time. No refresh operation is required, which reduces power consumption. It can be used as a photo-emissive semiconductor device.

[0182] In addition, since information is written by the switching operation of the transistor 162, It does not require high voltage and does not have the problem of element degradation. Therefore, since information can be written and erased, high speed operation can be easily realized. It is possible to directly rewrite information by controlling the voltage input to the transistor. Another advantage is that no action is required to erase the information.

[0183] In addition, a transistor using a material other than an oxide semiconductor is Compared to the conventional memory, it can operate at a higher speed, so by using it, the contents of the memory can be It is possible to perform reading at high speed.

[0184] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0185] (Embodiment 2) In this embodiment, a structure and a manufacturing method of a semiconductor device according to another embodiment of the disclosed invention will be described. This will be described with reference to FIG.

[0186] 15A shows an example of a circuit configuration of a semiconductor device. The difference from FIG. 1 is that a capacitor 16 15A, the presence or absence of the source electrode of the transistor 162. One of the gate and drain electrodes of the capacitor 164 and the gate of the transistor 160 are connected to each other. The first wiring (1st Line: source line) is electrically connected to the source electrode. BL) and the source electrode of the transistor 160 are electrically connected to each other, and the second wiring (2nd Line: also called bit line BL) and the drain electrode of transistor 160 , and are electrically connected. In addition, a third wiring (3rd Line: the first signal line S1) The transistor 162 is electrically connected to the other of the source electrode and the drain electrode. A fourth line (also called the second signal line S2) and a transistor The gate electrode of the fifth wiring (5th Li ne: also referred to as a word line WL) and the other electrode of the capacitor 164 are electrically connected. Note that in FIG. 15, in order to show that the transistor is formed using an oxide semiconductor, The OS code is also added.

[0187] Here, the transistor 162 is a transistor including an oxide semiconductor. A transistor including an oxide semiconductor has an extremely low off-state current. Therefore, by turning off the transistor 162, the gate of the transistor 160 The potential of the gate electrode can be maintained for an extremely long period of time. 164, the charge applied to the gate electrode of the transistor 160 is retained. This makes it easier to read the stored information.

[0188] The transistor 160 is not particularly limited. From the viewpoint of this, for example, transistors using single crystal silicon, which are switching It is preferable to use high speed transistors.

[0189] In the semiconductor device shown in FIG. 15A, the potential of the gate electrode of the transistor 160 can be maintained. By taking advantage of this feature, it is possible to write, store, and read information as follows: .

[0190] First, writing and holding of information will be explained. First, the potential of the fourth wiring is set to The transistor 162 is set to a potential that turns it on, thereby turning it on. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 160 and the capacitor 1 That is, a predetermined charge is applied to the gate electrode of the transistor 160. Here, two different potentials are applied to the charge (hereinafter, the low potential is applied). Charge Q L , the charge that gives the high potential is the charge Q H (called transistor 16) 0 gate electrode. Then, the potential of the fourth wiring may be applied to the transistor. The transistor 162 is turned off by applying a potential to the transistor 162. As a result, the charge applied to the gate electrode of the transistor 160 is retained (retained).

[0191] Since the off-state current of the transistor 162 is extremely small, the gate electrode of the transistor 160 The charge is retained for a long time.

[0192] Next, the reading of information will be described. In this state, when an appropriate potential (read potential) is applied to the fifth wire, the gate of the transistor 160 The second wiring has a different potential depending on the amount of charge held in the transistor electrode. If the transistor 160 is an n-channel type, then the gate electrode of the transistor 160 is connected to Q H is given The apparent threshold V th_H is connected to the gate electrode of transistor 160. L but The apparent threshold V for a given th_L This is because the The threshold voltage of the transistor 160 is the fifth voltage required to turn the transistor 160 "on." Therefore, the potential of the fifth wire is V th_H and V th_L By setting the potential V0 to the intermediate potential between For example, in writing, Q H If the fifth wire is given, The potential of V0 (>V th_H ), transistor 160 is in the "ON state." Q L is given, the potential of the fifth wire is V0( <V th_L ) even if The transistor 160 remains in the "off state." Therefore, the potential of the second wiring is not visible. The stored information can be read out.

[0193] When memory cells are arranged in an array, only the information of the desired memory cell is read. In this way, it is necessary to read the information of a specific memory cell and When the information of the other memory cells is not read, the first memory cell of the memory cell that is not the object of reading is read. For the wiring of 5, the transistor 160 is in the "off state" regardless of the state of the gate electrode. That is, V th_H Alternatively, a smaller potential can be applied to the gate electrode. The potential at which transistor 160 is "on" regardless of polarity, i.e., V th_L A larger potential may be applied to the fifth wiring.

[0194] Next, the rewriting of information will be described. That is, the potential of the fourth wiring is held when the transistor 162 is turned on. This turns on the transistor 162. (a potential related to new information) is applied to the gate electrode of the transistor 160 and the capacitor 164. After that, the potential of the fourth wiring is set to a potential that turns off the transistor 162. By turning off the transistor 162, the gate voltage of the transistor 160 is The poles are given a charge related to the new information.

[0195] In this way, the semiconductor device according to the disclosed invention can directly write information again. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need to extract charge from the floating gate using a high voltage, and the erase operation In other words, it is possible to suppress the decrease in operating speed caused by the above. It will be revealed.

[0196] The source electrode or drain electrode of the transistor 162 is connected to the gate of the transistor 160. By electrically connecting the gate electrode to the flow cell, the flow cell can be used as a nonvolatile memory element. This has the same effect as the floating gate of a floating gate type transistor. In the figure, the source electrode or drain electrode of the transistor 162 and the gate electrode of the transistor 160 The part where the gate electrode is electrically connected is sometimes called the floating gate part FG. When the transistor 162 is off, the floating gate portion FG is buried in an insulator. This can be seen as a charge-holding effect, and the floating gate FG holds charge. The off-state current of the transistor 162 using Since the value is less than 1 / 100,000 of the value of the transistor 162, the floating It is possible to ignore the loss of charge stored in the gate FG. The transistor 162 using the semiconductor is a nonvolatile memory that can retain information even without power supply. It is possible to realize a storage device with a high degree of accuracy.

[0197] For example, if the off-state current of the transistor 162 at room temperature (25° C.) is 10 zA (1 zA (zepto)), ampere) is 1 x 10 -21 A) or less, and the capacitance value of the capacitance element 164 is about 10 fF. In some cases, at least 10 4 It is possible to hold data for more than 10 seconds. However, it goes without saying that this will vary depending on the transistor characteristics and capacitance value.

[0198] In this case, the gate electrode, which has been pointed out in the conventional floating gate type transistor, There is no problem of deterioration of the gate insulating film (tunnel insulating film). This eliminates the degradation of the gate insulating film that occurs when electrons are injected into the floating gate. This means that there is no theoretical limit to the number of times you can write to it. In addition, the conventional floating gate transistor requires The high voltage that was previously required is no longer necessary.

[0199] The semiconductor device shown in FIG. 15A includes elements such as transistors constituting the semiconductor device. It can be considered as including resistance and capacitance as shown in Figure 15(B). In FIG. 15B, the transistor 160 and the capacitor 164 are respectively a resistor and a R1 and C1 are considered to be composed of the resistor and capacitance. The resistance value R1 is the resistance and capacitance value of the capacitance element 164. R2 and C2 correspond to the resistance of the edge layer. The resistance and capacitance of the transistor 160 are The capacitance C2 corresponds to the resistance of the insulating layer, and the capacitance C2 is the so-called gate capacitance (the capacitance between the gate electrode and the source The capacitance formed between the gate electrode or the drain electrode, and the gate electrode and the channel forming region This corresponds to the capacitance value of the capacitance formed between

[0200] The resistance between the source and drain electrodes when the transistor 162 is in the off state (actual If the gate leakage of transistor 162 is sufficiently small, then In the condition, if R1 and R2 satisfy R1 ≥ ROS and R2 ≥ ROS, the charge The retention period (which can also be called the information retention period) is mainly due to the ON state of the transistor 162. The value is determined by the off-current.

[0201] On the other hand, if this condition is not satisfied, the off-state current of the transistor 162 is not sufficiently small. In addition, it becomes difficult to secure a sufficient retention period. The leakage current (for example, the leakage current generated between the source electrode and the gate electrode) is large. For this reason, the semiconductor device disclosed in this embodiment has the above-mentioned characteristics. It is desirable that the above conditions be met.

[0202] On the other hand, it is desirable that C1 and C2 satisfy the relationship C1≧C2. When the potential of the floating gate portion FG is controlled by the fifth wiring (for example, when reading This is because the fluctuation in the potential of the fifth wiring can be kept low when the fifth wiring is opened (when the fifth wiring is opened).

[0203] By satisfying the above-mentioned relationship, it is possible to realize a more suitable semiconductor device. R1 and R2 are formed by the gate insulating layer of the transistor 160 and the insulating layer of the capacitor element 164. The same applies to C1 and C2. Therefore, the material and thickness of the gate insulating layer It is desirable to appropriately set the length etc. so as to satisfy the above-mentioned relationship.

[0204] In the semiconductor device shown in this embodiment, the floating gate portion FG is Functions similar to the floating gate of a floating gate type transistor such as a memory However, the floating gate portion FG of this embodiment is a floating gate of a flash memory or the like. In flash memory, the control gate has fundamentally different characteristics. The voltage applied to the gate is high, so the potential influence is large on the floating gate of the adjacent cell. To prevent this from reaching the cell, it is necessary to maintain a certain distance between the cells. This is one of the factors that hinder the high integration of semiconductor devices. This is due to the fundamental principle of flash memory: applying a magnetic field to generate a tunnel current. It is something.

[0205] In addition, due to the above-mentioned principle of flash memory, the insulating film deteriorates and the number of times it can be rewritten is limited. Kai (10 4 ~10 5 Another problem arises:

[0206] The semiconductor device according to the disclosed invention is a semiconductor device including a transistor including an oxide semiconductor. This operates in this way, and does not use the principle of charge injection by tunnel current as described above. Unlike flash memory, there is no need for a high electric field to inject charges. Since there is no need to consider the effect of the high electric field caused by the control gate on adjacent cells, Integration becomes easier.

[0207] In addition, since no charge is injected by tunnel current, there is no cause for deterioration of the memory cell. This means that it has higher durability and reliability than flash memory. .

[0208] In addition, the fact that a high electric field is not required and large peripheral circuits (such as a boost circuit) are not required is also an advantage of flash memory. This is an advantage over Schmemoria.

[0209] The dielectric constant of the insulating layer that constitutes C1 is εr1, and the dielectric constant of the insulating layer that constitutes C2 is εr 2, the area S1 of C1 and the area S2 of C2 must be different from each other. Preferably, it is easy to achieve C1 ≧ C2 while satisfying S2 ≧ S1. For example, in C1, a film made of a high-k material such as hafnium oxide is used. The layer structure is a layer made of a high-k material such as hafnium oxide and an oxide semiconductor. is used to set εr1 to 10 or more, preferably 15 or more, and in C2, silicon oxide By adopting this, it is possible to make εr2=3 to 4. By using this configuration in combination, Therefore, the semiconductor device according to the disclosed invention can be highly integrated.

[0210] The above explanation applies to the case where an n-type transistor (n-channel transistor) is used. However, p-type transistors can be used instead of n-type transistors. It goes without saying.

[0211] As described above, the semiconductor device according to one embodiment of the disclosed invention has a source and a drain in an off state. A write transistor with low leakage current (off-state current) between the write transistors, Nonvolatile memory including a read transistor and a capacitor element using a semiconductor material different from that of the transistor The memory cell has:

[0212] The off-state current of the writing transistor is 100 zA (1 × 10 -19 A) or less, preferably 10zA (1 x 10 -20 A) or less, more preferably 1 zA(1×10 -21 A) or less. In ordinary silicon semiconductors, the low Although it is difficult to obtain a high current, transistors obtained by processing oxide semiconductors under appropriate conditions are Therefore, the write transistor can be made of an oxide semiconductor. It is preferable to use a transistor including:

[0213] Furthermore, transistors using oxide semiconductors have a small subthreshold swing (S value). Therefore, even if the mobility is relatively low, the switching speed can be increased sufficiently. Therefore, by using the transistor as a writing transistor, This makes it possible to make the rise of the write pulse applied to the write gate FG extremely steep. In addition, since the off-current is small, the amount of charge held in the floating gate portion FG can be reduced. In other words, when a transistor including an oxide semiconductor is used for writing, By using it as a transistor, information can be rewritten at high speed.

[0214] As the readout transistor, a transistor that operates at high speed is used to increase the readout speed. It is desirable to use a transistor. For example, a switching transistor is used as a readout transistor. It is preferable to use transistors with speeds of 1 nanosecond or less.

[0215] Data is written to the memory cell by turning on the write transistor. One of the source electrode or the drain electrode of the writing transistor and the electrode of the capacitor element One of the floating gate electrodes is electrically connected to the gate electrode of the read transistor. By supplying a potential to the gate FG and then turning off the write transistor, This is done by holding a predetermined amount of charge in the floating gate portion FG. The off-current of the transistor for loading is extremely small, so the If the off-current is, for example, substantially zero, the conventional The refresh operation required for the DRAM is no longer necessary, or the refresh operation This makes it possible to reduce the frequency of such damage extremely (for example, once a month or once a year), This can significantly reduce the power consumption of the device.

[0216] In addition, information can be directly rewritten by writing information to the memory cell again. This eliminates the need for the erase operation required in flash memory, etc. This makes it possible to suppress a decrease in the operating speed due to the erase operation. In addition, writing and erasing can be performed with conventional floating gate transistors. Since the high voltage required for the semiconductor device is not required, the power consumption of the semiconductor device can be further reduced. The voltage applied to the memory cell according to this embodiment (each terminal of the memory cell) The maximum value of the difference between the maximum and minimum potentials applied simultaneously to When writing information, the voltage in one memory cell should be 5V or less, or 3V or less. It is possible.

[0217] A memory cell arranged in a semiconductor device according to the disclosed invention includes a write transistor and Since it is sufficient to include at least a read transistor, for example, one memory cell Compared to SRAM, which requires six transistors per memory cell, In other words, it is possible to form memory cells in a semiconductor device with high density. can be placed.

[0218] In addition, in conventional floating gate transistors, the gate insulating film (transistor) The charge transfer in the gate insulating film (tunnel insulating film) causes deterioration of the gate insulating film (tunnel insulating film). However, in the memory cell according to one embodiment of the present invention, Since information is written by the switching operation of the read transistor, There is no problem of film deterioration. This is because there is no theoretical limit to the number of times it can be written, and it has high rewrite durability. For example, a memory cell according to one embodiment of the present invention has 1×10 9 Even after more than 1 billion writes, the current-voltage characteristics showed no degradation. do not have.

[0219] Furthermore, a transistor using an oxide semiconductor as a writing transistor in a memory cell When using an oxide semiconductor, the energy gap is generally large (for example, In-Ga - 3.0 to 3.5 eV in the case of Zn-O system) There are very few thermally excited carriers, e.g. For example, no degradation in the current-voltage characteristics of the memory cell is observed even in high-temperature environments of 150°C.

[0220] The transistor having the above-mentioned excellent characteristics is used as a write transistor for a memory cell. By applying the present invention in this manner, it is possible to provide a semiconductor device having unprecedented features.

[0221] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0222] (Embodiment 3) In this embodiment, an application example of a semiconductor device according to one embodiment of the disclosed invention will be described with reference to FIGS. This will be explained using Figure 21.

[0223] FIG. 16 shows an outline of a semiconductor device according to this embodiment.

[0224] FIG. 16 shows the semiconductor device shown in FIG. 1 or FIG. 15(A) (hereinafter also referred to as memory cell 1200). 1 is an example of a circuit diagram of a semiconductor device formed using a plurality of

[0225] The semiconductor device shown in FIG. 16 is a memory device in which a plurality of memory cells 1200 are arranged in a matrix. The rechargeable cell array, the first driving circuit 1211, the second driving circuit 1212, and the third driving circuit The fourth driving circuit 1213, the fourth driving circuit 1214, and the first driving circuit 1211 are electrically connected to each other. In addition, a plurality of wirings L1 and a plurality of wirings L2 electrically connected to the second driving circuit 1212 a plurality of wirings L3 electrically connected to the third driving circuit 1213; and a fourth driving circuit and a plurality of wirings L4 electrically connected to the wirings 1214.

[0226] As shown in FIG. 16, each memory cell 1200 has a wiring L1, a wiring L2, a wiring L3, and The wiring L4 is electrically connected. This allows each memory cell 1200 to be connected to the first drive circuit 1. 211, the second driving circuit 1212, the third driving circuit 1213 and the fourth driving circuit 121 4 can be used to control the operation of the memory cells. The wiring L1, L2, L3, and L4 are arranged in a matrix, and the wiring L1, L2, L3, and L4 are arranged in a grid pattern in the row or column direction. By providing the memory cell 120, the write operation and the read operation of the semiconductor device can be performed. It can also be done row by row or column by column of 0s.

[0227] The memory cell 1200 shown in FIG. 16 includes the first driver circuit 1211 to the fourth driver circuit 1212. 1214 are electrically connected to each other, but the disclosed invention is However, it is not limited to this. A plurality of wirings are connected from one or more driving circuits to the memory cell 120. 0. Also, any one or more memory cells 120 0, the wiring of one or more of the drive circuits is not electrically connected. That's fine.

[0228] In the semiconductor device shown in FIG. 16, the first driver circuit 1211 and the second driver circuit 1212 The third driver circuit 1213 and the fourth driver circuit 1214 are provided independently of each other. The disclosed invention is not limited to this. In order to ensure sufficient operating speed, the drive circuit is preferably made of a single-crystal semiconductor. It is desirable to form the semiconductor device using a material such as bulk silicon (so-called silicon wafer). It is best to use something that uses the character "eha".

[0229] Next, a more specific configuration example will be described.

[0230] 17(A) and 17(B) are diagrams illustrating the semiconductor device (hereinafter referred to as memory cell) shown in FIG. 15(A). 17 is an example of a circuit diagram of a semiconductor device formed using a plurality of semiconductor devices. (A) shows the circuit of a so-called NAND type semiconductor device in which memory cells 400 are connected in series. FIG. 17B shows a so-called NOR type memory cell in which memory cells 400 are connected in parallel. FIG. 2 is a circuit diagram of the semiconductor device.

[0231] The semiconductor device shown in FIG. 17A includes a source line SL, a bit line BL, a first signal line S1, and a plurality of The memory cell array 400 includes a second signal line S2, a plurality of word lines WL, and a plurality of memory cells 400. In (A), there is one source line SL and one bit line BL. However, the present invention is not limited to this, and a configuration having a plurality of source lines SL and bit lines BL may also be used. stomach.

[0232] In each memory cell 400, the gate electrode of transistor 160 and the gate electrode of transistor 162 One of the source electrode and the drain electrode of the capacitor 164 is electrically connected to one of the electrodes of the capacitor 164. Also, the first signal line S1 and the source electrode or the drain electrode of the transistor 162 are connected. The other of the gate electrodes is electrically connected to the second signal line S2 and the gate of the transistor 162. The electrode of the capacitor 164 is electrically connected to the word line WL. The other is electrically connected.

[0233] The source electrode of the transistor 160 in the memory cell 400 is connected to the adjacent memory cell The drain electrode of the transistor 160 in the memory cell 400 is electrically connected to the drain electrode of the transistor 160 in the memory cell 400. The drain electrode of the transistor 160 is connected to the transistor of the adjacent memory cell 400. 160. However, the plurality of memory cells connected in series are electrically connected to the source electrode of the memory cell 160. The drain of the transistor 160 of the memory cell 400 provided at one end of the The electrode is electrically connected to a bit line BL. The source voltage of the transistor 160 of the memory cell 400 provided at the other end of the The electrode is electrically connected to a source line SL.

[0234] In the semiconductor device shown in FIG. 17A, writing and reading operations are performed row by row. The write operation is performed as follows: A transistor is connected to the second signal line S2 of the row to be written. A potential is applied to turn on the transistor 162 of the row to be written. As a result, the first signal line S is connected to the gate electrodes of the transistors 160 in the specified row. A potential of 1 is applied, and a predetermined charge is applied to the gate electrode. Data can be written to the memory cells in the selected row.

[0235] The read operation is performed as follows: First, the word lines WL other than the row from which the read is to be performed are connected. Therefore, regardless of the charge applied to the gate electrode of the transistor 160, the transistor 160 A potential is applied to turn on the transistors 160 other than the row to be read out. Then, the gate of the transistor 160 is connected to the word line WL of the row to be read. The charge on the electrode selects the on or off state of the transistor 160. Then, a constant potential is applied to the source line SL, and a constant potential is applied to the bit line The read circuit (not shown) connected to the source line BL is set to an operating state. The transistors 160 between the SL and the bit line BL are turned on except for the row to be read. Since the read operation is in the read state, the conductance between the source line SL and the bit line BL is The state (on or off) of the transistor 160 in the row is used to determine the readout. The charge on the gate electrodes of the transistors 160 in the row that is being sampled causes the Since the conductance is different, the potential of the bit line BL will take on different values ​​accordingly. The potential of the bit line BL is read out by the read circuit, and the memory of the specified row is read out. Information can be read from the recell.

[0236] The semiconductor device shown in FIG. 17B includes a source line SL, a bit line BL, a first signal line S1, a second The memory cell array has a plurality of signal lines S2 and word lines WL, and a plurality of memory cells 400. The gate electrode of each transistor 160 and the source electrode or drain of each transistor 162 One of the in-electrodes and one of the electrodes of the capacitor 164 are electrically connected to each other. The source line SL and the source electrode of the transistor 160 are electrically connected, and the bit line BL and the drain electrode of the transistor 160 are electrically connected. S1 and the other of the source electrode or the drain electrode of the transistor 162 are electrically connected. The second signal line S2 and the gate electrode of the transistor 162 are electrically connected. The word line WL and the other electrode of the capacitor 164 are electrically connected to each other.

[0237] In the semiconductor device shown in FIG. 17B, writing and reading operations are performed row by row. The write operation is performed in the same manner as in the semiconductor device shown in FIG. The read operation is performed as follows: First, a transistor is connected to the word line WL other than the row from which data is to be read. The transistor 160 is turned off regardless of the charge applied to the gate electrode of the transistor 160. A potential such as this is applied to turn off the transistors 160 other than the row that is being read out. Then, the word line WL of the row to be read is connected to the gate electrode of the transistor 160. The charge creates a potential ( A constant potential is applied to the source line SL, and a constant potential is applied to the bit line BL. The read circuit (not shown) connected to the source line SL-bit The conductance between the lines BL is determined by the state (on state) of the transistor 160 of the row to be read. The transistors 160 of the row to be read are determined by the on / off state. The potential of the bit line BL will take on different values ​​depending on the charge carried by the gate electrode. The potential of the bit line BL is read by the read circuit, and the memory cells in the specified row are read. Information can be read from the

[0238] In the above description, the amount of information stored in each memory cell 400 is 1 bit. The structure of the memory device described in the embodiment is not limited to this. Three or more potentials may be provided to increase the amount of information stored in each memory cell 400. For example, when four types of potentials are applied to the gate electrode of the transistor 160, Each memory cell can hold two bits of information.

[0239] Next, an example of a read circuit that can be used in the semiconductor device shown in FIG. 18 will be used to explain.

[0240] FIG. 18A shows a schematic diagram of a readout circuit. The readout circuit is composed of a transistor and a sensor. It has a sense amplifier circuit.

[0241] When reading, terminal A is connected to the bit line BL to which the memory cell to be read is connected. A bias potential Vbias is applied to the gate electrode of the transistor, and The potential of the electrode is controlled.

[0242] The memory cell 400 exhibits different resistance values ​​depending on the data stored therein. When the transistor 160 of the selected memory cell 400 is in an on state, it is in a low resistance state. When the transistor 160 of the selected memory cell 400 is in an off state, it is in a high resistance state. .

[0243] When the memory cell is in a high resistance state, the potential at terminal A becomes higher than the reference potential Vref, and the sense The amplifier outputs a potential corresponding to the potential at terminal A. On the other hand, when the memory cell is in a low resistance state, The potential of terminal A becomes lower than the reference potential Vref, and the sense amplifier circuit The corresponding voltage is output.

[0244] In this way, data can be read from the memory cell by using the read circuit. Note that the readout circuit in this embodiment is an example. Other circuits may be used. The read circuit may include a precharge circuit. The bit lines BL may be connected to the first and second bit lines BL.

[0245] FIG. 18B shows a differential sense amplifier, which is an example of a sense amplifier circuit. The amplifier has input terminals Vin(+) and Vin(-) and an output terminal Vout. The difference between the potentials of Vin(+) and Vin(-) is amplified. If the potential of Vin(+) is higher than Vin(-), Vout outputs a High signal. If the differential sense amplifier is connected to the read circuit, Vout outputs a Low signal. When used in a circuit, one of Vin(+) and Vin(-) is connected to terminal A, and Vin(+) and The other terminal of Vin(-) is supplied with a reference potential Vref.

[0246] FIG. 18C shows a latch-type sense amplifier, which is an example of a sense amplifier circuit. The sense amplifier has input / output terminals V1 and V2, and input terminals for control signals Sp and Sn. First, set signal Sp to High and signal Sn to Low, and cut off the power supply potential (Vdd). Then, apply potential V1in and V2in for comparison to V1 and V2 respectively. After that , when setting signal Sp to Low and signal Sn to High and supplying the power supply potential (Vdd), if the potentials V1in and V2in for comparison are in the relationship of V1in > V2in, the output of V1 will be High , and the output of V2 will be Low. If they are in the relationship of V1in < V2in, the output of V1 will be Low and the output of V2 will be High. Utilizing such a relationship, the difference between V1in and V2in can be amplified. When using the latch-type sense amplifier in a read circuit, one of V1 and V2 is connected to terminal A and the output terminal via a switch, and the other of V1 and V2 is given the reference potential Vref.

[0247] FIG. 19 is an example of a circuit diagram of a semiconductor device formed by using a plurality of semiconductor devices shown in FIG. 15(A). The semiconductor device shown in FIG. 19 has a storage capacity of m × n bits.

[0248] The semiconductor device according to FIG. 19 includes m word lines WL, m second signal lines S2, n bit lines BL, n source lines SL, n first signal lines S1, and a plurality of memory cells 1100 arranged in a matrix of m (rows) × n (columns) (m and n are natural numbers), and peripheral circuits such as a first drive circuit 1111, a second drive circuit 1112, a third drive circuit 1113, and a fourth drive circuit 1114. Here , as the memory cell 1100, the configuration described in the previous embodiment (for example, the configuration shown in FIG. 15(A)) is applied. ​

[0249] That is, each memory cell 1100 includes a first transistor 160, a second transistor 16 2 and a capacitor 164. The gate electrode of the first transistor 160, One of the source electrode and the drain electrode of the second transistor 162 and the One of the electrodes is connected to the source line SL and the source electrode of the first transistor 160. are connected, and the bit line BL and the drain electrode of the first transistor 160 are connected. The first signal line S1 and the source electrode or the drain electrode of the second transistor 162 are connected to each other. The other is connected to the second signal line S2, and the gate electrode of the second transistor 162 is connected to the second signal line S3. , and the word line WL and the other electrode of the capacitor element 164 are connected.

[0250] The memory cells 1100 are connected in parallel between the source line SL and the bit line BL. For example, a memory cell 1100(i,j) in the i-th row and j-th column (i is an integer between 1 and m, and j is an integer between 1 and m) is an integer between 1 and n) represents the source line SL(j), the bit line BL(j), the first signal line S 1(j), the word line WL(i), and the second signal line S2(i), respectively.

[0251] The source line SL and the bit line BL are connected to a first driving circuit 1111. The signal line S1 is connected to the second driving circuit 1112, and the signal line S2 is connected to the third driving circuit 1113. The word line WL is connected to a fourth drive circuit 1113, and the word line WL is connected to a fourth drive circuit 1114. Here, the first driver circuit 1111, the second driver circuit 1112, the third driver circuit 1113, and the The fourth driver circuit 1113 and the fourth driver circuit 1114 are provided independently. The present invention is not limited to this. A decoder having one or more of the functions may be used. stomach.

[0252] Next, the write operation of the semiconductor device shown in FIG. 19 will be described with reference to the timing chart shown in FIG. The operation and read operation will be described below.

[0253] For simplicity, the operation of a 2-row x 2-column semiconductor device will be described here. The disclosed invention is not limited to this.

[0254] 20 is a diagram for explaining the operation of the semiconductor device shown in FIG. 19. In FIG. S1(1) and S1(2) are the potentials of the first signal line S1, S2(1) and S 2(2) is the potential of the second signal line S2, BL(1) and BL(2) are the potentials of the second signal line S3, The potentials of the bit lines BL, WL(1) and WL(2), are the potential of the word line WL, SL(1). ) and SL(2) correspond to the potential of the source line SL, respectively.

[0255] First, write to memory cell (1,1) and memory cell (1,2) in the first row. When reading from the first memory cell (1,1) and the second memory cell (1,2), In the following, the data to be written to the memory cell (1,1) is assumed to be "1", A case where the data to be written to the memory cell (1, 2) is "0" will be described.

[0256] First, the write operation will be explained. During the write period for the first row, the second signal for the first row is written. A potential VH is applied to the line S2(1), and the second transistor 162 in the first row is turned on. Also, 0V is applied to the second signal line S2(2) in the second row, and the second transistor 1 62 is set to the OFF state.

[0257] Next, a potential V2 is applied to the first signal line S1(1) in the first column, and a potential V3 is applied to the first signal line S1(2) in the second column. Apply a potential of 0V.

[0258] As a result, the potential V2 is applied to the floating gate FG of the memory cell (1,1), The floating gate FG of cell (1,2) is given 0V. Here, the potential V The potential of the first transistor 160 is higher than the threshold voltage of the first transistor 160. The potential of the second signal line S2(1) is set to 0 V, and the second transistor 162 in the first row is turned off. By setting the write state to "ON", the writing is completed.

[0259] The word lines WL(1) and WL(2) are set to 0V. Before changing the potential of S1(1), the second signal line S2(1) of the first row is set to 0V. After the write operation, the terminal connected to the word line WL is used as the control gate electrode, and the first transistor 160 is used as the the source electrode of the first transistor 161 as the source electrode, the drain electrode of the second transistor 162 as the drain electrode, The threshold value of the memory element is Vw0 for data "0" and Vw1 for data "1". Here, the threshold voltage of the memory cell is Vw1. The voltage at the terminal connected to the word line WL changes the resistance between the drain electrode and the gate electrode. It is assumed that Vw0>0>Vw1.

[0260] Next, the readout will be described. During the readout period of the first row, the word line W 0V is applied to L(1), and a potential VL is applied to the word line WL(2) of the second row. If WL(1) is set to 0V, the data in the first row will be The first transistor 160 of the memory cell (1, 2) in which the data "0" is stored is in the OFF state. The first transistor 160 of the memory cell (1,1) in which data "1" is stored is turned on. If WL(2) is set to the potential VL, then in the second row, data "0" and "1" The first transistor 160 is in an off state regardless of which of the following is held in the memory cell. This becomes:

[0261] Next, a potential of 0V is applied to the source line SL(1) in the first column and the source line SL(2) in the second column.

[0262] As a result, the first line of the memory cell (1,1) is connected between the bit line BL(1) and the source line SL(1). Since the transistor is on, the resistance is low, and the bit line BL(2)-source line SL( During 2), the first transistor 160 of the memory cell (1, 2) is in an off state, and therefore, a high resistance The read circuit connected to the bit line BL(1) and the bit line BL(2) The data can be read from the difference in resistance of the wires.

[0263] Also, 0V is applied to the second signal line S2(1), and a potential VL is applied to the second signal line S2(2). , all the second transistors 162 are turned off. Since the potential of the section FG is 0V or V2, by setting the second signal line S2(1) to 0V, All the second transistors 162 in the first row can be turned off. When a potential VL is applied to the word line WL(2), the potential of the floating gate portion FG becomes The potential becomes lower than the potential immediately after writing. 2 is turned on, the second signal line S2(2) is connected to the word line WL(2 ) is set to the same low potential as that of the second transistor 162. This can be done.

[0264] Next, the output potential when the circuit shown in FIG. 21 is used as the read circuit will be described. Since the resistance between the bit line BL(1) and the source line SL(1) is low, a clocked inverter A low potential is input to the bit line BL(2) and the output D(1) goes high. Since the resistance between the lines SL(2) is high, a high potential is input to the clocked inverter, and the output D(2) becomes Low.

[0265] The operating voltages are, for example, VDD=2V, V2=1.5V, VH=2V, and VL=-2V. It is possible.

[0266] As described above, by providing a plurality of memory cells, the semiconductor device The memory capacity can be increased. The number and arrangement of the operating circuits can be designed as appropriate, and are not limited to the above configuration. isn't it.

[0267] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0268] (Fourth embodiment) In this embodiment, one embodiment of the disclosed invention, which is different from Embodiments 1 and 2, is described. The structure of the semiconductor device and a manufacturing method thereof will be described with reference to FIGS. 22 to 24. The transistor 260 described in this embodiment is the same as that described in the previous embodiment. As transistor 160 in the circuit diagram, transistor 262 is The transistor 162 in the circuit diagram is replaced by a capacitor 264 in the previous embodiment. It can be used as the capacitor element 164 in the circuit diagram.

[0269] <Cross-sectional and planar configurations of semiconductor device> 22A and 22B show an example of the configuration of the semiconductor device. 22(A) and 22(B) show a plan view of the semiconductor device. 22(B) corresponds to the cross sections taken along lines C1-C2 and D1-D2. In the figure, to avoid complication, the source electrode or drain electrode 254, Some of the components, such as the wiring 256, are omitted. The semiconductor device to be fabricated has a transistor 260 using a semiconductor material other than an oxide semiconductor in the lower part. and a transistor 262 using an oxide semiconductor thereon. Transistors using semiconductor materials other than conductors can easily operate at high speeds. A transistor using a semiconductor can retain charge for a long period of time due to its characteristics.

[0270] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that a p-channel transistor can also be used. The technical essence of the present invention is to use an oxide semiconductor as the transistor 262 to store data. The specific configuration of the semiconductor device does not need to be limited to that shown here. .

[0271] In the semiconductor device shown in FIG. 22, a transistor 262 and a capacitance element 264 are The planar layout shown in FIG. For example, if the minimum processing dimension is F, then Moricell's area is 15F 2 ~25F 2 It is possible to do so.

[0272] One of the differences between the semiconductor device shown in FIG. 22 and the semiconductor device shown in the previous embodiment is that The presence or absence of a sidewall insulating layer in the transistor 260. The semiconductor device does not have a sidewall insulating layer. As a result, the impurity region 114 (see, for example, FIG. 2) is not formed. As shown above, when no sidewall insulating layer is provided, the In addition, compared to the case where a sidewall insulating layer is provided, the fabrication is easier. The process can be simplified.

[0273] Another difference between the semiconductor device shown in FIG. 22 and the semiconductor device shown in the previous embodiment is that , which are the interlayer insulating layers in the transistor 260. That is, the semiconductor device shown in FIG. In this example, the interlayer insulating layer 225 containing hydrogen contacts the metal compound region 224 of the transistor 260. By providing the interlayer insulating layer 225 containing hydrogen so as to be in contact with the metal compound region 224, The characteristics of the transistor 260 can be improved by supplying hydrogen to the transistor 260. Such an interlayer insulating layer 225 can be formed by, for example, a plasma CVD method. Furthermore, the interlayer insulating layer 226 may include a silicon nitride layer containing hydrogen. The application of a low concentration insulating layer may deteriorate the characteristics of the transistor 262. It is possible to prevent hydrogen from entering the transistor 262. 226 is, for example, silicon nitride formed by sputtering in the absence of hydrogen. By adopting such a configuration, the transistor 260 and the transistor In FIG. 22, the substrate 200 is The element isolation insulating layer 206 is formed on the substrate 100 of the first embodiment. 06, the gate insulating layer 208 is the gate insulating layer 108 of the first embodiment, and the gate electrode 210 corresponds to the gate electrode 110 of the first embodiment, and the channel forming region 216 corresponds to the channel forming region of the first embodiment. In the hole forming region 116, the high concentration impurity region 220 is the same as the high concentration impurity region 120 of the first embodiment. The metal compound region 224 corresponds to the metal compound region 124 of the first embodiment. .

[0274] Another difference between the semiconductor device shown in FIG. 22 and the semiconductor device shown in the previous embodiment is that In the transistor 262, the insulating layer 243a and the insulating layer 243b are oxide semiconductor layers. Between the oxide semiconductor layer 244 and the source or drain electrode 242a, and between the oxide semiconductor layer 244 and the The point is provided between the source electrode or the drain electrode 242b. By providing the layer 243a and the insulating layer 243b, the gate electrode 248a and the source electrode 248b are A source or drain electrode 242a (or a gate electrode 248a) and a source or drain electrode The gate capacitance formed by the gate electrode 242b is reduced, and the operation of the transistor 262 is Speed ​​can be improved.

[0275] As in the first embodiment, the lower transistor 260 and the upper transistor 262 are The source electrode or drain electrode 242a is formed directly on the gate electrode 210. This configuration allows for a more efficient connection than when electrodes and wiring are provided separately. In comparison, the degree of integration is improved and the manufacturing process is simplified.

[0276] In this embodiment, the configuration in which the above-mentioned differences are integrated is shown. A configuration having only one of the above may be adopted.

[0277] <Method for manufacturing semiconductor device> Next, an example of a method for manufacturing the semiconductor device will be described. The process after forming the transistor 260 and the method for fabricating the upper transistor 262 are shown in FIG. 24. The lower transistor 260 is the same as that shown in the first embodiment. For details, see the description of Embodiment 1. Note that in this embodiment, a capacitor 264 is provided. In this embodiment, an interlayer insulating layer 225 and an interlayer insulating film 226 are formed to cover the transistor 260. Three types of interlayer insulating layers are formed: layer 226, interlayer insulating layer 228. In this embodiment, in the manufacturing process of the transistor 260, The source or drain electrode 130a and the source or drain electrode 130b are not formed. However, the source or drain electrode 130a and the source or drain electrode 130 For convenience, the transistor will be referred to as transistor 260 even when "b" is not formed.

[0278] First, the lower transistor 260 is formed by the method shown in the first embodiment, and then the transistor The upper part of the gate electrode 210 of 260 is removed. This removal process is performed by CMP (chemical machining). By this, the upper surface of the gate electrode 210 may be polished. The upper interlayer insulating layers 225, 226, and 228 are removed. By sufficiently flattening the surface by polishing, it is possible to obtain good electrodes and wiring in the subsequent processes. It is possible to form lines, insulating layers, semiconductor layers, etc.

[0279] Next, on the gate electrode 210, the interlayer insulating layer 225, the interlayer insulating layer 226, and the interlayer insulating layer 228, A conductive layer is formed, and the conductive layer is selectively etched to form a source electrode or a drain electrode. 242a, and a source or drain electrode 242b are formed (see FIG. 23(A)). Here, the source electrode or drain electrode 242a is directly connected to the gate electrode 210. It forms a sea urchin.

[0280] Forming a source or drain electrode 242a and a source or drain electrode 242b The conductive layer for this purpose is the same as the source or drain electrode 142a, The source electrode or drain electrode 142b can be formed using a material similar to that of the source electrode or drain electrode 142b. The conductive layer is also etched using the same method as that shown in the first embodiment. For details, the description in embodiment 1 can be referred to.

[0281] Next, the source or drain electrode 242a, the source or drain electrode 242b and forming an insulating layer to cover the source electrode or An insulating layer 243a is formed on the drain electrode 242a, and a An insulating layer 243b is formed on each of the insulating layers 243a and 243b (see FIG. 23(B)).

[0282] By providing the insulating layers 243a and 243b, the gate electrode 2 to be formed later can be 48a, a source electrode or drain electrode 242a, and a source electrode or drain It is possible to reduce the parasitic capacitance between the electrode 242b.

[0283] Next, the source or drain electrode 242a, the source or drain electrode 242b An oxide semiconductor layer 244 is formed to cover the gate insulating layer 2 46 is formed (see FIG. 23(C)).

[0284] The oxide semiconductor layer 244 can be formed using the material and the method for forming the oxide semiconductor layer 140 described in Embodiment 1. The oxide semiconductor layer 244 can be formed by heat treatment (first heat treatment) For details, please refer to the description of the first embodiment. do.

[0285] The gate insulating layer 246 is formed by the material and method for the gate insulating layer 138 shown in the first embodiment. After the gate insulating layer 246 is formed, the insulating layer 246 can be formed in an inert gas atmosphere or It is desirable to perform the heat treatment (second heat treatment) in an oxygen atmosphere. The description of Form 1 can be taken into consideration.

[0286] Next, a region to be a channel formation region of the transistor 262 is formed on the gate insulating layer 246. A gate electrode 248a is formed in a region overlapping the source or drain electrode 242. An electrode 248b is formed in the region overlapping with a (see FIG. 23(D)).

[0287] The gate electrode 248a and the electrode 248b are formed by forming a conductive layer on the gate insulating layer 246. The gate electrode can be formed by selectively etching the conductive layer. The conductive layers that become the electrodes 248a and 248b can be formed by PVD methods such as sputtering, It can be formed by using a CVD method such as a plasma CVD method. The same applies to the case of the drain electrode 242a, etc., and the descriptions therefor can be taken into consideration.

[0288] Next, an interlayer insulating layer is formed on the gate insulating layer 246, the gate electrode 248a, and the electrode 248b. 250 and an interlayer insulating layer 252 are formed (see FIG. 24(A)). The protective insulating layer 144 and the interlayer insulating layer 252 are the same as the protective insulating layer 144 and the interlayer insulating layer 146 shown in the first embodiment. For details, refer to the description of Embodiment 1. It is possible.

[0289] It is desirable that the interlayer insulating layer 252 be formed so that its surface is flat. By forming the interlayer insulating layer 252 so that the surface is flat, it is possible to Even in such a case, electrodes, wiring, and the like can be suitably formed on the interlayer insulating layer 252. The interlayer insulating layer 252 can be planarized by a method such as CMP (chemical mechanical polishing). This can be done using the method.

[0290] Next, the interlayer insulating layer 225, the interlayer insulating layer 226, the interlayer insulating layer 228, and the oxide semiconductor layer 244 , the gate insulating layer 246, the interlayer insulating layer 250, and the interlayer insulating layer 252 are selectively etched. 24(B), an opening is formed down to the metal compound region 224 of the transistor 260. )). Either dry etching or wet etching can be used. However, from the viewpoint of miniaturization, it is preferable to use dry etching.

[0291] Then, a source electrode or drain electrode 254 is formed so as to fill the opening. Then, a wiring 256 connected to the source electrode or drain electrode 254 is formed (FIG. 24 (See (C)).

[0292] The source electrode or drain electrode 254 is formed by, for example, PVD or CVD in the area including the opening. After forming a conductive layer using a method such as etching or CMP, It can be formed by removing a part of the conductive layer. A thin titanium film is formed on the area including the mouth by the PVD method, and a thin titanium nitride film is formed on the area by the CVD method. After forming the opening, a tungsten film is formed so as to fill the opening. Here, the titanium film formed by the PVD method does not form an oxide film (natural oxide film) on the surface on which it is formed. and the like) to reduce the contact resistance with the lower electrode and the like (here, the metal compound region 224). In addition, the titanium nitride film formed afterwards suppresses the diffusion of the conductive material. It also has a barrier function that prevents the formation of a barrier film made of titanium or titanium nitride. Alternatively, a copper film may be formed by plating.

[0293] The wiring 256 is formed by forming a conductive layer in contact with the source electrode or drain electrode 254. The conductive layer can be formed by selectively etching the conductive layer. It is formed using PVD methods such as sputtering and CVD methods such as plasma CVD. The details are the same as those for the source electrode or drain electrode 242a. do.

[0294] As a result, a semiconductor device including the transistor 260, the transistor 262, and the capacitor 264 is formed. The conductor device is completed.

[0295] In the semiconductor device described in this embodiment, the transistor 262 and the capacitor 264 are The transistor 260 has a structure overlapping the sidewall insulating layer. The absence of an insulating layer means that the source electrode or drain electrode 242a is directly formed on the gate electrode 210. High integration is possible due to the fact that the semiconductor device is formed in close contact with the substrate. It has been done.

[0296] In addition, in the semiconductor device described in this embodiment, an insulating layer containing hydrogen is used as the interlayer insulating layer 225. By applying an insulating layer with a low hydrogen concentration as the interlayer insulating layer 226, The characteristics of the capacitor 260 and the transistor 262 are improved. By providing the insulating layer 243b, the so-called gate capacitance is reduced, and the transistor 262 The operating speed has been improved.

[0297] The above-described features of the present embodiment provide a semiconductor device with extremely excellent characteristics. is possible.

[0298] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0299] (Embodiment 5) In this embodiment, an example of an electronic device equipped with the semiconductor device obtained in the above embodiment will be described. The semiconductor device obtained in the above embodiment is a semiconductor device that does not require power supply. Even if the data is written or erased, it is possible to retain the data. Furthermore, the operation is also fast. Therefore, it is possible to use this semiconductor device to develop new electrical circuits. It is possible to provide a sub-device. The semiconductor device is then mounted on a circuit board or the like and installed inside various electronic devices.

[0300] FIG. 10A shows a notebook personal computer including the semiconductor device according to the above embodiment. The computer is composed of a main body 301, a housing 302, a display unit 303, a keyboard 304, etc. It has been completed.

[0301] FIG. 10B shows a personal digital assistant (PDA) including the semiconductor device according to the above embodiment. The main body 311 includes a display unit 313, an external interface 315, an operation button 314, etc. Also, a stylus 312 is provided as an accessory for operation.

[0302] FIG. 10C shows an example of electronic paper including the semiconductor device according to the above embodiment. The electronic book 320 is shown. The electronic book 320 is made up of two housings, housing 321 and housing 323. The housing 321 and the housing 323 are integrated by a shaft portion 337. The opening and closing operation can be performed around the axis portion 337. The book 320 can be used like a paper book.

[0303] The housing 321 incorporates a display unit 325, and the housing 323 incorporates a display unit 327. The display unit 325 and the display unit 327 may be configured to display a continuous screen, or may be configured to display different screens. By configuring to display different screens, for example, The text is displayed on the right display unit (display unit 325 in FIG. 10(C)), and the text is displayed on the left display unit (display unit 325 in FIG. 10(C)). In (C), an image can be displayed on the display unit 327).

[0304] FIG. 10C shows an example in which an operation unit and the like are provided on the housing 321. The body 321 includes a power supply 331, operation keys 333, a speaker 335, etc. You can turn the page by pressing the arrow 333. In addition, there is a keyboard and a pointer on the same surface as the display unit of the housing. The back and sides of the housing may be provided with an external Connection terminals (earphone jack, USB terminal, AC adapter and USB cable, etc.) terminals that can be connected to various cables, a recording medium insertion section, etc. Furthermore, the electronic book 320 may be configured to have the function of an electronic dictionary.

[0305] The electronic book 320 may also be configured to be able to send and receive information wirelessly. It is also possible to purchase and download desired book data from the child book server. It is possible.

[0306] Electronic paper can be applied to any field that displays information. For example, in addition to e-books, posters, advertisements on trains and other vehicles, credit cards, etc. The present invention can be applied to displays on various cards such as gift cards.

[0307] FIG. 10D shows a mobile phone including the semiconductor device according to the above embodiment. The phone is made up of two housings, housing 340 and housing 341. Housing 341 has a front display panel 342, speaker 343, microphone 344, pointing device 3 46, a camera lens 347, an external connection terminal 348, etc. The mobile phone includes a solar cell 349 for charging the mobile phone, an external memory slot 350, etc. The antenna is also built into the housing 341.

[0308] The display panel 342 has a touch panel function, and in FIG. 10(D) an image is displayed. The multiple operation keys 345 are shown by dotted lines. A boost circuit is implemented to boost the voltage output by 9 to the voltage required for each circuit. In addition to the above configuration, it may be configured to incorporate a contactless IC chip, a small recording device, etc. It is also possible.

[0309] The display direction of the display panel 342 changes appropriately depending on the usage mode. The camera lens 347 is located on the same surface as the camera 42, making it possible to make video calls. The speaker 343 and microphone 344 are not limited to voice calls, but also video calls, recording, playback Furthermore, the housing 340 and the housing 341 can be slid, and as shown in FIG. It can be folded from the unfolded state to the overlapping state, making it possible to make it compact and portable. It is Noh.

[0310] The external connection terminal 348 can be connected to various cables such as an AC adapter or a USB cable. The external memory slot 350 can store a recording medium. It can insert and store and move larger amounts of data. In addition to the above functions, It may also be equipped with infrared communication functions, television reception functions, etc.

[0311] FIG. 10E shows a digital camera including the semiconductor device according to the previous embodiment. The digital camera comprises a main body 361, a display unit (A) 367, an eyepiece 363, and an operation switch 364. , a display unit (B) 365, a battery 366, etc.

[0312] FIG. 10F shows a television set including the semiconductor device according to the above embodiment. In the vision device 370, a display unit 373 is built into a housing 371. In this case, the stand 375 is used to hold the case in place. 371 is shown in the supporting configuration.

[0313] The television device 370 can be operated using an operation switch provided on the housing 371 or a separate remote control. This can be done by operating the operating device 380. The remote control operating device 380 has an operating key 379. This allows you to control the channel and volume, and to operate the image displayed on the display unit 373. In addition, the remote control operation device 380 can receive the output from the remote control operation device 380. A display unit 377 for displaying the information may be provided.

[0314] It is preferable that the television device 370 is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts. By connecting to a wired or wireless communication network, The purpose of this communication is to communicate information between two parties (one party) or two-way (between a sender and a receiver, or between receivers). It is possible to do this.

[0315] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. Can be used in combination [Example]

[0316] In this example, the off-state current of a transistor including a highly purified oxide semiconductor was measured. Explain the results.

[0317] First, the off-state current of a transistor using a highly purified oxide semiconductor must be sufficiently small. Considering this, we prepared a transistor with a sufficiently large channel width W of 1 m and measured the off-state current. The results of measuring the off-state current of a transistor with a channel width W of 1 m are shown in Figure 25. In FIG. 25, the horizontal axis represents the gate voltage VG, and the vertical axis represents the drain current ID. When the voltage VD is +1V or +10V, if the gate voltage VG is in the range of -5V to -20V, The off-current of the thin film transistor is 1×10, which is the detection limit. -13 It is found to be below A In addition, the off-state current of the transistor (here, the value) is 1aA / μm (1×10 -18 A / μm or less.

[0318] Next, we aimed to more accurately measure the off-state current of thin-film transistors using highly purified oxide semiconductors. The results are described below. The off-state current of the transistor is 1×10, which is the detection limit of the measuring instrument. -13 It is found to be below A Therefore, a device for characteristic evaluation was fabricated to obtain a more accurate value of the off-state current ( The results of determining the concentration of benzoquinone (a value below the detection limit of the measuring instrument) are explained below.

[0319] First, the characteristic evaluation element used in the current measurement method will be described with reference to FIG.

[0320] The characteristic evaluation element shown in FIG. 26 has three measurement systems 800 connected in parallel. 0 represents the capacitor element 802, the transistor 804, the transistor 805, and the transistor 806. , and transistor 808. A transistor including a highly purified oxide semiconductor was used for the capacitor 806.

[0321] In the measurement system 800, one of the source terminal and the drain terminal of the transistor 804, One of the terminals of the capacitor 802 and the source terminal and drain terminal of the transistor 805 One end is connected to a power supply (the power supply that provides V2). the other of the source and drain terminals of the transistor 808 One of the terminals of the capacitor 802, the other terminal of the capacitor 802, and the gate terminal of the transistor 805 are connected to each other. The other of the source terminal and the drain terminal of the transistor 808 is connected to the One of the source terminal and the drain terminal of the transistor 806 and the gate of the transistor 806 The output terminal of the transistor 805 is connected to a power supply (the power supply that provides V1). the other of the source and drain terminals of the transistor 806 The other terminal is connected to serve as an output terminal.

[0322] The gate terminal of the transistor 804 is connected to a resistor R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R A potential Vext_b2 that controls the state of the transistor 808 is supplied to the gate terminal of the transistor 808. A potential Vext_b1 that controls the on and off states of the transistor 808 is supplied. Furthermore, the potential Vout is output from the output terminal.

[0323] Next, a current measurement method using the above characteristic evaluation element will be described.

[0324] First, an outline of the initial period during which a potential difference is applied to measure the off-state current will be described. During this period, the gate terminal of the transistor 808 is connected to the ON state. A potential Vext_b1 is input to the source terminal or drain of the transistor 804. The node connected to the other of the terminals (i.e., the source terminal and drain terminal of the transistor 808) one of the terminals of the capacitor 802, the other terminal of the capacitor 802, and the gate terminal of the transistor 805. A potential V1 is applied to node A, which is a node connected to the The transistor 804 is kept in an off state.

[0325] Then, a potential that turns off the transistor 808 is applied to the gate terminal of the transistor 808. Vext_b1 is input to turn off the transistor 808. After turning off the transistor 804, the potential V1 is set to a low potential. The potential V2 is set to the same potential as the potential V1. When the initial period is over, the node A and the source terminal of the transistor 804 and A potential difference is generated between the node A and one of the drain terminals of the transistor 808. A potential difference occurs between the source terminal and the drain terminal of the transistor. A small amount of charge flows through the transistor 804 and the transistor 808. In other words, an off-current occurs. .

[0326] Next, an outline of the measurement period of the off-state current will be described. The potential of one of the source terminal or drain terminal of 804 (i.e., V2) and The potential of the other terminal of the source terminal or the drain terminal of the transistor 808 (i.e., V1) is On the other hand, during the measurement period, the potential of the node A is not fixed (flow This causes a charge to flow through the transistor 804, and over time, The amount of charge held at node A fluctuates. In other words, the output potential Vout of the output terminal also fluctuates. .

[0327] Details of the relationship between the potentials during the initial period when the potential difference is applied and the subsequent measurement period The timing chart is shown in FIG.

[0328] In the initial period, first, the potential Vext_b2 is applied when the transistor 804 is turned on. This causes the potential of node A to be V2, that is, the low potential (V After that, the potential Vext_b2 is set to a value that turns off the transistor 804. The transistor 804 is turned off by setting the potential at the potential (low potential). Vext_b1 is set to a potential (high potential) that turns on the transistor 808. This causes the potential of node A to become V1, i.e., the high potential (VDD). xt_b1 is set to a potential that turns off the transistor 808. Node A becomes floating and the initial period ends.

[0329] In the subsequent measurement period, potentials V1 and V2 are measured as charges flow into node A. Or, the potential is set so that charge flows out from node A. Here, the potential V1 and the potential V 2 is the low potential (VSS). However, at the timing when the output potential Vout is measured, In this case, it is necessary to operate the output circuit, so V1 is temporarily set to a high potential (VDD). The period when V1 is at a high potential (VDD) should be short enough so as not to affect the measurement. The period.

[0330] As described above, when a potential difference is applied and the measurement period begins, the voltage at node A increases over time. The amount of charge held changes, and the potential at node A changes accordingly. This means that the potential of the gate terminal of the transistor 805 fluctuates, so over time, the output The potential of the output potential Vout of the terminal also changes.

[0331] A method for calculating the off-state current from the obtained output potential Vout will be described below.

[0332] Before calculating the off-state current, the potential V of node A A and the output voltage Vout. This causes the output potential Vout to change to the potential V at node A. A can be obtained. From the above relationship, the potential of node A, V A is expressed as a function of the output potential Vout as follows: It is possible.

[0333]

number

[0334] Also, the charge Q at node A A is the potential V of node A A , capacitance C connected to node A A , fixed Using a constant, it is expressed as follows: CA is the sum of the capacitance of the capacitive element 802 and other capacitances.

[0335]

number

[0336] Current I at node A A is the charge flowing into (or out of) node A. Since it is a time derivative, the current I at node A A is expressed as follows:

[0337]

number

[0338] In this way, the capacitance C connected to node A A The output potential Vout of the output terminal is Current I A can be obtained.

[0339] By using the method described above, the leakage current flowing between the source and drain of the transistor in the off state can be reduced. The off-state current (off current) can be measured.

[0340] In this example, a highly purified oxide having a channel length L=10 μm and a channel width W=50 μm was used. Using semiconductors, transistors 804, 805, 806, In each of the paralleled measurement systems 800, a capacitance element 802a The capacitance values ​​of the capacitive elements 802a to 802c are set to 100 fF, and the capacitance values ​​of the capacitive elements 802b to 1 and the capacitance element 802c was set to 3 pF.

[0341] In the measurement according to this embodiment, VDD=5V and VSS=0V. In this case, the potential V1 is set to VSS as a rule, and the voltage is increased by 100 msec every 10 to 300 sec. Vout was measured as VDD for the period c. The time Δt was set to approximately 30,000 seconds.

[0342] FIG. 28 shows the relationship between the elapsed time Time in the current measurement and the output potential Vout. From FIG. 28, it can be seen that the potential changes over time.

[0343] FIG. 29 shows the off-state current at room temperature (25° C.) calculated from the above current measurement. FIG. 29 shows the relationship between the source-drain voltage V and the off-state current I. 29, the off-current is about 40zA / μm when the source-drain voltage is 4V. In addition, under the condition of a source-drain voltage of 3.1 V, the off-current It was found that the current density was 10zA / μm or less. -21 Represents A.

[0344] Furthermore, the off-state current calculated from the above current measurement in a temperature environment of 85°C was The figure shows the source-drain voltage V and the off-state voltage V under a temperature environment of 85°C. This shows the relationship between the source and drain voltage and the current I. It was found that the off-state current was 100 zA / μm or less.

[0345] As described above, in this example, in a transistor using a highly purified oxide semiconductor, It was confirmed that the flow was sufficiently small. [Example]

[0346] The number of times that a semiconductor device according to one embodiment of the disclosed invention can be rewritten was investigated. The survey results will now be explained with reference to FIG.

[0347] The semiconductor device used in the investigation has a circuit configuration shown in FIG. A transistor corresponding to the transistor 162 is formed using an oxide semiconductor. The corresponding capacitance element used had a capacitance value of 0.33 pF.

[0348] The investigation involves setting the initial memory window width and repeating the retention and writing of information a predetermined number of times. This is done by comparing the memory window width after the data is returned. The write operation is performed by applying either 0V or 5V to the wiring corresponding to the third wiring in FIG. 15(A). and the wire corresponding to the fourth wire is given either 0V or 5V. When the potential of the wiring corresponding to the fourth wiring is 0 V, the transistor 162 The corresponding transistor (write transistor) is in the off state, so that If the potential of the wiring corresponding to the fourth wiring is 5V, the transistor Since the transistor corresponding to the third wiring is turned on, the transistor corresponding to the third wiring is turned on. The potential of the line is applied to node FG.

[0349] The memory window width is one of the indicators that show the characteristics of a memory device. The potential Vcg of the wiring corresponding to the fifth wiring and the potential Vcg of the wiring corresponding to the transistor 160 during the memory state The curve ( The difference between the Vcg and Id curves is referred to as the shift ΔVcg. The state where 0V is applied to node FG (hereinafter referred to as the Low state) and the state where 5V is applied to node FG are In other words, the memory window width is the Lo This can be confirmed by sweeping the potential Vcg in the w state and the high state.

[0350] Figure 31 shows the memory window width in the initial state and the 9 After writing The horizontal axis in Figure 31 represents Vcg (V). The vertical axis shows Id(A). From Figure 31, 1×10 9 Before and after writing, It can be seen that the memory window width has not changed. 9 Before and after writing The fact that the memory window width remains unchanged means that the semiconductor device will This indicates that there is no deterioration.

[0351] As described above, the semiconductor device according to one embodiment of the disclosed invention performs storage and writing in a 1×1 0 9 Even after repeated rewriting, the characteristics do not change and the rewriting durability is extremely high. According to one embodiment of the present invention, a highly reliable semiconductor device can be achieved. [Explanation of symbols]

[0352] 100 boards 102 Protective layer 104 Semiconductor Area 106 Element isolation insulating layer 108 Gate insulating layer 110 gate electrode 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulating layer 120 High concentration impurity region 122 Metal layer 124 Metal compound area 126 Interlayer insulation layer 128 Interlayer Insulation Layer 130a Source electrode or drain electrode 130b Source electrode or drain electrode 130c electrode 132 Insulating layer 134 Conductive Layer 136a electrode 136b Electrode 136c electrode 136d Gate electrode 138 Gate insulating layer 140 Oxide semiconductor layer 142a Source electrode or drain electrode 142b Source electrode or drain electrode 144 Protective Insulation Layer 146 Interlayer insulation layer 148 Conductive Layer 150a electrode 150b electrode 150c electrode 150d electrode 150e electrode 152 Insulating layer 154a electrode 154b electrode 154c electrode 154d electrode 160 transistors 162 transistors 164 Capacitor 200 boards 206 Element isolation insulating layer 208 Gate insulating layer 210 gate electrode 216 Channel formation region 220 High concentration impurity region 224 Metal compound area 225 Interlayer insulation layer 226 Interlayer insulation layer 228 Interlayer Insulation Layer 242a Source electrode or drain electrode 242b Source or drain electrode 243a Insulating layer 243b Insulating layer 244 Oxide semiconductor layer 246 Gate insulating layer 248a Gate electrode 248b Electrode 250 Interlayer Insulation Layer 252 Interlayer insulation layer 254 Source or drain electrode 256 Wiring 260 transistors 262 transistors 264 Capacitive Element 301 Main Unit 302 Case 303 Display section 304 keyboard 311 Main Unit 312 Stylus 313 Display section 314 Operation Button 315 External Interface 320 e-books 321 Case 323 Case 325 Display section 327 Display section 331 Power supply 333 Operation Key 335 Speaker 337 Shaft 340 Case 341 Case 342 Display Panel 343 Speaker 344 Microphone 345 Operation Key 346 Pointing Device 347 Camera Lenses 348 External connection terminal 349 Solar Cells 350 external memory slot 361 Main Unit 363 Eyepiece 364 Operation Switch 365 Display section (B) 366 Battery 367 Display section (A) 370 Television Equipment 371 Case 373 Display section 375 Stand 377 Display section 379 Operation Key 380 Remote Controlled Device 400 memory cells 800 measurement system 802 Capacitor element 802a Capacitive element 802b Capacitive element 802c Capacitive Element 804 transistor 805 transistor 806 Transistor 808 Transistor 1100 memory cells 1111 drive circuit 1112 Drive circuit 1113 Drive circuit 1114 Drive circuit 1200 memory cells 1211 Drive circuit 1212 drive circuit 1213 Drive circuit 1214 drive circuit

Claims

1. a first transistor and a second transistor; a source or a drain of the first transistor is electrically connected to a gate electrode of the second transistor; the first transistor has a channel formation region in an oxide semiconductor layer; the oxide semiconductor layer is an In—Ga—Zn—O-based, In—Sn—Zn—O-based, In—Al—Zn—O-based, Sn—Ga—Zn—O-based, Al—Ga—Zn—O-based, Sn—Al—Zn—O-based, In—Zn—O-based, Sn—Zn—O-based, Al—Zn—O-based, In—O-based, Sn—O-based, or Zn—O-based oxide semiconductor layer, the oxide semiconductor layer has crystallinity, the first transistor has an off-state current of 1×10 A / μm or less; a potential is applied to the gate electrode of the second transistor by turning on the first transistor, and then the potential of the gate electrode of the second transistor is maintained by turning off the first transistor; Semiconductor device.

2. a first transistor, a second transistor, and a capacitor; a source or a drain of the first transistor is electrically connected to a gate electrode of the second transistor and one electrode of the capacitor element; the first transistor has a channel formation region in an oxide semiconductor layer; the oxide semiconductor layer is an In—Ga—Zn—O-based, In—Sn—Zn—O-based, In—Al—Zn—O-based, Sn—Ga—Zn—O-based, Al—Ga—Zn—O-based, Sn—Al—Zn—O-based, In—Zn—O-based, Sn—Zn—O-based, Al—Zn—O-based, In—O-based, Sn—O-based, or Zn—O-based oxide semiconductor layer, the oxide semiconductor layer has crystallinity, the first transistor has an off-state current of 1×10 A / μm or less; a potential is applied to the gate electrode of the second transistor by turning on the first transistor, and then the potential of the gate electrode of the second transistor is maintained by turning off the first transistor; Semiconductor device.

3. a first transistor and a second transistor; a source or a drain of the first transistor is electrically connected to a gate electrode of the second transistor; the first transistor has a channel formation region in an oxide semiconductor layer; the oxide semiconductor layer is an In—Ga—Zn—O-based, In—Sn—Zn—O-based, In—Al—Zn—O-based, Sn—Ga—Zn—O-based, Al—Ga—Zn—O-based, Sn—Al—Zn—O-based, In—Zn—O-based, Sn—Zn—O-based, Al—Zn—O-based, In—O-based, Sn—O-based, or Zn—O-based oxide semiconductor layer, the oxide semiconductor layer has crystallinity, the first transistor has an off-state current of 1×10 A / μm or less; a floating gate portion in which the source or drain of the first transistor and the gate electrode of the second transistor are electrically connected; a potential is applied to the gate electrode of the second transistor by turning on the first transistor, and then the potential of the gate electrode of the second transistor is maintained by turning off the first transistor; Semiconductor device.

4. a first transistor, a second transistor, and a capacitor; a source or a drain of the first transistor is electrically connected to a gate electrode of the second transistor and one electrode of the capacitor element; the first transistor has a channel formation region in an oxide semiconductor layer; the oxide semiconductor layer is an In—Ga—Zn—O-based, In—Sn—Zn—O-based, In—Al—Zn—O-based, Sn—Ga—Zn—O-based, Al—Ga—Zn—O-based, Sn—Al—Zn—O-based, In—Zn—O-based, Sn—Zn—O-based, Al—Zn—O-based, In—O-based, Sn—O-based, or Zn—O-based oxide semiconductor layer, the oxide semiconductor layer has crystallinity, the first transistor has an off-state current of 1×10 A / μm or less; a floating gate portion in which the source or drain of the first transistor and the gate electrode of the second transistor are electrically connected; a potential is applied to the gate electrode of the second transistor by turning on the first transistor, and then the potential of the gate electrode of the second transistor is maintained by turning off the first transistor; Semiconductor device.

5. a first transistor and a second transistor; a source or a drain of the first transistor is electrically connected to a gate electrode of the second transistor; the first transistor has a channel formation region in an oxide semiconductor layer; the oxide semiconductor layer is an In—Ga—Zn—O-based, In—Sn—Zn—O-based, In—Al—Zn—O-based, Sn—Ga—Zn—O-based, Al—Ga—Zn—O-based, Sn—Al—Zn—O-based, In—Zn—O-based, Sn—Zn—O-based, Al—Zn—O-based, In—O-based, Sn—O-based, or Zn—O-based oxide semiconductor layer, the oxide semiconductor layer has crystallinity, the first transistor has an off-state current of 1×10 A / μm or less; a floating gate portion in which the source or drain of the first transistor and the gate electrode of the second transistor are electrically connected; the floating gate portion is buried in an insulator, a potential is applied to the gate electrode of the second transistor by turning on the first transistor, and then the potential of the gate electrode of the second transistor is maintained by turning off the first transistor; Semiconductor device.

6. a first transistor, a second transistor, and a capacitor; a source or a drain of the first transistor is electrically connected to a gate electrode of the second transistor and one electrode of the capacitor element; the first transistor has a channel formation region in an oxide semiconductor layer; the oxide semiconductor layer is an In—Ga—Zn—O-based, In—Sn—Zn—O-based, In—Al—Zn—O-based, Sn—Ga—Zn—O-based, Al—Ga—Zn—O-based, Sn—Al—Zn—O-based, In—Zn—O-based, Sn—Zn—O-based, Al—Zn—O-based, In—O-based, Sn—O-based, or Zn—O-based oxide semiconductor layer, the oxide semiconductor layer has crystallinity, the first transistor has an off-state current of 1×10 A / μm or less; a floating gate portion in which the source or drain of the first transistor and the gate electrode of the second transistor are electrically connected; the floating gate portion is buried in an insulator, a potential is applied to the gate electrode of the second transistor by turning on the first transistor, and then the potential of the gate electrode of the second transistor is maintained by turning off the first transistor; Semiconductor device.

7. In any one of claims 1 to 6, the oxide semiconductor layer has an i-type or substantially i-type region; Semiconductor device.

8. In any one of claims 1 to 7, The oxide semiconductor layer has a hydrogen concentration of 5×10 measured by secondary ion mass spectrometry. １９ atoms / cm ３ Below is the Semiconductor device.

9. In any one of claims 1 to 8, the second transistor has silicon in a channel formation region; Semiconductor device.

10. In any one of claims 1 to 9, an insulating layer disposed above the gate electrode of the second transistor; the oxide semiconductor layer is disposed above the insulating layer; the oxide semiconductor layer is disposed at a position spaced apart from the gate electrode of the second transistor in a plan view; Semiconductor device.

Images