Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device capable of suppressing ionic migration in a peripheral region of a pad wiring layer and reducing a stress to the pad wiring layer.SOLUTION: A semiconductor device includes: a chip body 21 including an element formation surface 3; a passivation layer 2 formed on the element formation surface 3 of the chip body 21; a pad wiring layer 29 including a first conductive layer 56 formed on the passivation layer 2 and including a Cu conducive layer 49, a second conductive layer 51 formed on the first conductive layer 56 and including a Ni layer 54 and a Pd layer 55, and an eaves 57; a joining member 22 joined to the pad wiring layer 29; and a covering insulation film 58 selectively formed below the eaves 57 on the passivation layer 2, exposing an upper surface 23 of the passivation layer 2 to a peripheral region of the pad wiring layer 29, and covering a side surface 49c of the first conductive layer 56.SELECTED DRAWING: Figure 18

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate, Cu wiring formed on the semiconductor substrate, a plating layer covering the surface and side surfaces of the Cu wiring, and Cu wires wire-bonded onto the Cu wiring via the plating layer. The plating layer has a Ni / Pd / Au laminated structure. The manufacturing process of this semiconductor device includes, for example, a step of forming Cu wiring via a barrier metal film on an insulating film covering a semiconductor substrate. The barrier metal film includes a Ti / Cu seed layer formed by sputtering. The Cu wiring is formed on the barrier metal film by electroplating using a resist film on the barrier metal film as a mask. After plating the Cu wiring, the resist film is removed, and the exposed Ti / Cu seed layer is then removed by wet etching. For example, the Cu seed layer is first removed with a mixture of hydrogen peroxide and nitric acid, and then the Ti film is removed with a mixture of hydrogen peroxide and ammonia. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-171386 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of a semiconductor device according to an embodiment of the present disclosure is to suppress ion migration in the region surrounding a pad wiring layer and reduce stress on the pad wiring layer. [Means for solving the problem]

[0005] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor chip having an element forming surface, an insulating layer formed on the element forming surface of the semiconductor chip, a pad wiring layer having a first conductive layer formed on the insulating layer and including a first conductive material, and a second conductive layer formed on the first conductive layer and including a second conductive material different from the first conductive material, the pad wiring layer having an eave portion formed by the second conductive layer protruding outward from an end face of the first conductive layer, a bonding member bonded to the pad wiring layer and supplying power to elements on the element forming surface, and a covering insulating film selectively formed on the insulating layer below the eave portion, exposing an upper surface of the insulating layer in a region surrounding the pad wiring layer and covering the end face of the first conductive layer. [Effects of the Invention]

[0006] According to the semiconductor device according to the embodiment of the present disclosure, it is possible to suppress ion migration in the region surrounding the pad wiring layer and reduce stress on the pad wiring layer. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view (through the sealing resin) of the semiconductor device shown in FIG. [Figure 3] FIG. 3 is a plan view of the semiconductor device shown in FIG. 1 (with the semiconductor element and sealing resin transparent). [Figure 4] FIG. 4 is a bottom view of the semiconductor device shown in FIG. [Figure 5] FIG. 5 is a front view of the semiconductor device shown in FIG. [Figure 6] FIG. 6 is a rear view of the semiconductor device shown in FIG. [Figure 7] FIG. 7 is a right side view of the semiconductor device shown in FIG. [Figure 8] FIG. 8 is a left side view of the semiconductor device shown in FIG. [Figure 9] FIG. 9 is a partially enlarged view of FIG. [Figure 10] FIG. 10 is a partially enlarged view of FIG. [Figure 11] FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. [Figure 12] FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. [Figure 13] FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. [Figure 14] FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. [Figure 15] FIG. 15 is a partially enlarged view (near the first electrode) of FIG. [Figure 16] FIG. 16 is a partially enlarged view of FIG. 11 (near the second electrode). [Figure 17] FIG. 17 is a schematic plan view for explaining the wiring structure of the element chip. [Figure 18] FIG. 18 is a schematic cross-sectional view of the element chip, taken along line XVIII-XVIII in FIG. [Figure 19] FIG. 19 is an enlarged view of the portion surrounded by the two-dot chain line A in FIG. 18, and shows a first form of the insulating coating film. [Figure 20] FIG. 20 is an enlarged view of the portion surrounded by the two-dot chain line A in FIG. 18, showing a second form of the insulating coating film. [Figure 21] FIG. 21 is an enlarged view of the portion surrounded by the two-dot chain line A in FIG. 18, showing a third form of the insulating coating film. [Figure 22] FIG. 22 is an enlarged view of the portion surrounded by the two-dot chain line A in FIG. 18, showing a fourth embodiment of the insulating coating film. [Figure 23A] FIG. 23A is a diagram for explaining a part of the manufacturing process of the semiconductor device. [Figure 23B] FIG. 23B shows the next step in FIG. 23A. [Figure 23C] FIG. 23C shows the next step in FIG. 23B. [Figure 23D] FIG. 23D shows the next step in FIG. 23C. [Figure 23E] FIG. 23E shows the next step of FIG. 23D. [Figure 23F] FIG. 23F shows the next step in FIG. 23E. [Figure 23G] FIG. 23G shows the next step in FIG. 23F. [Figure 23H] FIG. 23H shows the next step of FIG. 23G. [Figure 23I] FIG. 23I shows the next step in FIG. 23H. [Figure 23J] FIG. 23J shows the next step in FIG. 23I. [Figure 23K] FIG. 23K shows the next step in FIG. 23J. [Figure 23L] FIG. 23L shows the next step in FIG. 23K. [Figure 23M] FIG. 23M shows the next step in FIG. 23L. [Figure 23N] FIG. 23N shows the next step of FIG. 23M. [Figure 23O] FIG. 23O shows the next step of FIG. 23N. [Figure 23P] FIG. 23P shows the next step in FIG. 23O. [Figure 24] 24A and 24B are diagrams showing steps involved in forming the insulating coating film. [Figure 25] 25A and 25B are diagrams showing steps involved in forming the insulating coating film. [Figure 26] FIG. 26 is a schematic cross-sectional view showing a reference example of the element chip. [Figure 27] FIG. 27 is a schematic cross-sectional view showing another embodiment of the element chip. DETAILED DESCRIPTION OF THE INVENTION

[0008] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following detailed description, there are a plurality of components with names each having an ordinal number, but the ordinal numbers do not necessarily match the ordinal numbers of the components described in the claims. A semiconductor device A10 according to a first embodiment of the present disclosure will be described with reference to FIGS.

[0009] The semiconductor device A10 includes a conductive member 10, an element chip 20, a bonding layer 30, and a sealing resin 40. As shown in FIG. 1, the semiconductor device A10 is packaged in a QFN (Quad For Non-Lead Package) format. The element chip 20 is a flip-chip type LSI. The element chip 20 includes therein a switching circuit 212A and a control circuit 212B (each of which will be described in detail later).

[0010] In the semiconductor device A10, DC power (voltage) is converted into AC power (voltage) by the switching circuit 212A. The semiconductor device A10 is used, for example, as one element constituting a circuit of a DC / DC converter. Here, for ease of understanding, FIG. 2 shows a perspective view through the sealing resin 40. For ease of understanding, FIG. 3 shows a perspective view through the element chip 20 and the sealing resin 40. In these figures, the transparent element chip 20 and the sealing resin 40 are respectively indicated by imaginary lines (two-dot chain lines).

[0011] In the description of the semiconductor device A10, the thickness direction Z of the conductive member 10 is referred to as the "thickness direction Z." A direction perpendicular to the thickness direction Z is referred to as the "first direction x." A direction perpendicular to both the thickness direction Z and the first direction x is referred to as the "second direction y." 1 and 2, the semiconductor device A10 has a square shape when viewed along the thickness direction Z. In addition, in the description of the semiconductor device A10, for convenience, the side in the second direction y on which the plurality of second leads 12 (described in detail later) are located will be referred to as "one side in the second direction y." The side in the second direction y on which the plurality of first leads 11 (described in detail later) are located will be referred to as "the other side in the second direction y."

[0012] As shown in Fig. 2, the conductive member 10 supports the element chip 20 and also serves as a terminal for mounting the semiconductor device A10 on a wiring board. As shown in Figs. 11 to 14, the conductive member 10 is partially covered with a sealing resin 40. The conductive member 10 has a main surface 101 (first surface) and a back surface 102 (second surface) that face opposite each other in the thickness direction Z. The main surface 101 faces one side in the thickness direction Z and faces the element chip 20.

[0013] The element chip 20 is supported on a main surface 101. The main surface 101 is covered with a sealing resin 40. The back surface 102 faces the other side in the thickness direction Z. The conductive member 10 is composed of a single lead frame. The lead frame is made of, for example, copper (Cu) or a copper alloy. The conductive member 10 includes a plurality of first leads 11, a plurality of second leads 12, and a pair of third leads 13.

[0014] 3 and 4, the multiple first leads 11 are strip-shaped and extend in the second direction y when viewed along the thickness direction Z. The multiple first leads 11 are arranged along the second direction y. In the example of the semiconductor device A10, the multiple first leads 11 are configured with three terminals: a first input terminal 111A, a second input terminal 11B, and an output terminal 11C. The multiple first leads 11 are arranged in the order of the first input terminal 11A, the output terminal 11C, and the second input terminal 11B from one side to the other side in the second direction y. The first input terminal 11A and the second input terminal 11B receive DC power (voltage) to be converted into power in the semiconductor device A10. The first input terminal 11A is a positive terminal (P terminal). The second input terminal 11B is a negative terminal (N terminal). The output terminal 11C outputs AC power (voltage) converted by the switching circuit 212A configured in the element chip 20.

[0015] As shown in FIG. 3, the first input terminal 11A is located between the multiple second leads 12 and the output terminal 11C in the second direction y. The output terminal 11C is located between the first input terminal 11A and the second input terminal 11B in the second direction y. Each of the first input terminal 11A and the output terminal 11C includes a main portion 111 and a pair of side portions 112. As shown in FIGS. 3 and 4, the main portion 111 extends in the first direction x. In the multiple first leads 11, the component chip 20 is supported on the main surface 101 of the main portion 111.

[0016] The pair of side portions 112 are connected to both ends of the main portion 111 in the first direction x. As shown in FIGS. 3, 4, 12, and 13, each of the pair of side portions 112 has a first end surface 112A. The first end surface 112A is connected to both the main surface 101 and the back surface 102 of the first lead 11, and faces the first direction x. The first end surface 112A is exposed from the sealing resin 40. 9, a constricted portion 112B is formed on each of a pair of side portions 112 of the first input terminal 11A and the output terminal 11C. The constricted portion 112B extends from the main surface 101 to the back surface 102 of the first lead 11, and is recessed inward from both sides in the second direction y into the side portions 112. The constricted portion 112B is in contact with the sealing resin 40. Due to the constricted portion 112B, in the first input terminal 11A and the output terminal 11C, the dimension b in the second direction y of each of the pair of first end faces 112A is smaller than the dimension B in the second direction y of the back surface 102 of the main portion 111.

[0017] 3, the second input terminal 11B is located on the other side in the second direction y than the output terminal 11C. Therefore, the second input terminal 11B is located on the other side in the second direction y among the multiple first leads 11. The second input terminal 11B includes a main portion 111, a pair of side portions 112, and multiple protrusions 113. The multiple protrusions 113 protrude from the other side of the main portion 111 in the second direction y. Sealing resin 40 is filled between two adjacent protrusions 113. As shown in FIG. 11, each of the multiple protrusions 113 has a minor end face 113A. The minor end face 113A is connected to both the main surface 101 and the back surface 102 of the second input terminal 11B and faces the other side in the second direction y. The minor end face 113A is exposed from the sealing resin 40. As shown in FIG. 7, the multiple minor end faces 113A are arranged at predetermined intervals along the first direction x.

[0018] As shown in FIG. 10, a notch 112C is formed in each of the pair of side portions 112 of the second input terminal 11B. The notch 112C extends from the main surface 101 to the back surface 102 of the second input terminal 11B and is recessed in the first direction x from the first end surface 112A. This divides the first end surface 112A into two regions spaced apart in the second direction y. Due to the notch 112C, in the second input terminal 11B, the dimension b in the second direction y of each of the pair of first end surfaces 112A is smaller than the dimension B in the second direction y of the back surface 102 of the main portion 111. Note that the dimension b here is the sum of the dimension b1 in the second direction y of one region of the first end surface 112A and the dimension b2 in the second direction y of the other region of the first end surface 112A (b=b1+b2). The notch 112C is filled with sealing resin 40.

[0019] 3 and 4, in each of the multiple first leads 11, the area of ​​the main surface 101 is larger than the area of ​​the back surface 102. In the example illustrated by semiconductor device A10, the areas of the back surfaces 102 of the first input terminal 11A and the output terminal 11C are equal. The area of ​​the back surface 102 of the second input terminal 11B is larger than the areas of the back surfaces 102 of the first input terminal 11A and the output terminal 11C.

[0020] In each of the first input terminal 11A, the second input terminal 11B, and the output terminal 11C, the main surface 101 of the main portion 111 on which the element chip 20 is supported may be plated with, for example, silver (Ag). Furthermore, in each of the first input terminal 11A, the second input terminal 11B, and the output terminal 11C, the back surface 102 exposed from the sealing resin 40, the pair of first end faces 112A, and the plurality of sub-end faces 113A may be plated with, for example, tin (Sn). Note that instead of tin plating, multiple metal platings may be employed, for example, in which nickel (Ni), palladium (Pd), and gold (Au) are layered in this order.

[0021] As shown in FIG. 3, the second leads 12 are located on one side of the first leads 11 in the second direction y. One of the second leads 12 is a ground terminal of a control circuit 212B configured on the element chip 20. Each of the other second leads 12 receives power (voltage) for driving the control circuit 212B or an electrical signal for transmission to the control circuit 212B. As shown in FIGS. 3, 4, and 11, each of the second leads 12 has a second end surface 121. The second end surface 121 is connected to both the main surface 101 and the back surface 102 of the second lead 12 and faces one side in the second direction y. The second end surface 121 is exposed from the sealing resin 40. As shown in FIG. 8, the second end surfaces 121 are arranged at predetermined intervals along the first direction x.

[0022] As shown in FIGS. 3 and 4, the area of ​​the main surface 101 of each of the multiple second leads 12 is larger than the area of ​​the back surface 102. The areas of the back surfaces 102 of the multiple second leads 12 are all equal. The back surfaces 102 of the multiple second leads 12 on which the element chip 20 is supported may be plated with silver, for example. Furthermore, the back surfaces 102 and second end surfaces 121 of the multiple second leads 12 exposed from the sealing resin 40 may be plated with tin, for example. Instead of tin plating, multiple metal platings may be used, for example, in which nickel, palladium, and gold are layered in this order.

[0023] 3, the pair of third leads 13 are located between the first lead 11 (first input terminal 11A) and the plurality of second leads 12 in the second direction y. The pair of third leads 13 are spaced apart from each other in the first direction x. An electrical signal or the like is input to each of the pair of third leads 13 to be transmitted to the control circuit 212B configured in the element chip 20. 3, 4, and 14, each of the pair of third leads 13 has a third end surface 131. The third end surface 131 is connected to both the main surface 101 and the back surface 102 and faces the first direction x. The third end surface 131 is exposed from the sealing resin 40. The third end surface 131, together with the first end surfaces 112A of the multiple first leads 11, is arranged along the second direction y.

[0024] 3 and 4, the area of ​​the main surface 101 of each of the pair of third leads 13 is larger than the area of ​​the back surface 102. The main surfaces 101 of the pair of third leads 13 on which the element chip 20 is supported may be plated with silver, for example. Furthermore, the back surfaces 102 and third end surfaces 131 of the pair of third leads 13 exposed from the sealing resin 40 may be plated with tin, for example. Note that instead of tin plating, multiple metal platings may be used, for example, in which nickel, palladium, and gold are layered in this order.

[0025] As shown in Figures 11 to 14, the element chip 20 is electrically joined to and supported by the conductive member 10 (plurality of first leads 11, plural second leads 12, and a pair of third leads 13) by flip-chip bonding. The element chip 20 is covered with a sealing resin 40. As shown in Figures 12 to 16, the element chip 20 has a chip body 21, a pad wiring layer 29, and plural bonding members 22.

[0026] The chip body 21 forms the main part of the element chip 20. As shown in Figures 15 and 16, the chip body 21 has a semiconductor substrate 211 and a semiconductor layer 212. 15 and 16, the semiconductor substrate 211 supports therebelow a semiconductor layer 212, a pad wiring layer 29, and a plurality of bonding members 22. The constituent material of the semiconductor substrate 211 is, for example, Si (silicon) or silicon carbide (SiC).

[0027] 11 to 14, semiconductor layer 212 is laminated on the side of semiconductor substrate 211 facing main surface 101 of conductive member 10. Semiconductor layer 212 includes multiple types of p-type semiconductors and n-type semiconductors based on differences in the amounts of doped elements. Semiconductor layer 212 includes switching circuit 212A and control circuit 212B that is electrically connected to switching circuit 212A. Switching circuit 212A is a semiconductor element such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor).

[0028] In the example of the semiconductor device A10, the switching circuit 212A is divided into two regions: a high-voltage region (upper arm circuit) and a low-voltage region (lower arm circuit). Each region is configured with one n-channel MOSFET. The control circuit 212B includes a gate driver for driving the switching circuit 212A, a bootstrap circuit corresponding to the high-voltage region of the switching circuit 212A, and the like, and performs control for normally driving the switching circuit 212A. A wiring layer (described later) is configured in the semiconductor layer 212. The switching circuit 212A and the control circuit 212B are mutually conductive via the wiring layer.

[0029] 11 to 14, the multiple bonding members 22 protrude from the side of the chip body 21 facing the main surface 101 of the conductive member 10 toward the main surface 101 of the conductive member 10. The multiple bonding members 22 are electrically bonded to the main surface 101 of the conductive member 10. The multiple bonding members 22 include multiple first bonding members 22A and multiple second bonding members 22B. The multiple first bonding members 22A are electrically connected to the switching circuit 212A of the semiconductor layer 212. In addition, the multiple first bonding members 22A are electrically connected to the main surface 101 of the multiple first leads 11. As a result, the multiple first leads 11 are electrically connected to the switching circuit 212A. In addition, the multiple second bonding members 22B are electrically connected to the control circuit 212B of the semiconductor layer 212. In addition, most of the multiple second bonding members 22B are electrically connected to the main surface 101 of the multiple second leads 12. The remaining second joint members 22B are electrically joined to the main surfaces 101 of the pair of third leads 13. As a result, the plurality of second leads 12 and the pair of third leads 13 are electrically connected to the control circuit 212B.

[0030] As shown in FIGS. 15 and 16 , each of the multiple bonding members 22 is formed on a pad wiring layer 29 formed on a semiconductor layer 212. The pad wiring layer 29 is electrically connected to either a switching circuit 212A or a control circuit 212B of the semiconductor layer 212. The bonding members 22 are formed as pillars 222 protruding from the pad wiring layer 29 toward the main surface 101 of the conductive member 10. The pillars 222 have a tip surface 222A and a side surface 222B. The tip surface 222A faces the main surface 101 of the conductive member 10. The side surface 222B is connected to the tip surface 222A and faces a direction perpendicular to the thickness direction Z. In the semiconductor device A10, the pillars 222 may have recesses 222C recessed from the tip surface 222A toward the chip body 21. The pillars 222 supply power via the pad wiring layer 29 to the switching circuit 212A and the control circuit 212B formed in the semiconductor layer 212.

[0031] As shown in FIGS. 15 and 16 , the bonding layer 30 is in contact with both the main surface 101 of the conductive member 10 and the plurality of bonding members 22. The bonding layer 30 is conductive. As a result, the plurality of bonding members 22 are electrically bonded to the main surface 101 of the conductive member 10. In each of the plurality of bonding members 22, the bonding layer 30 is in contact with both the tip surface 222A and the side surface 222B of the pillar 222. In the semiconductor device A10, the bonding layer 30 is also in contact with the recess 222C of the pillar 222. Furthermore, the pillar 222 of the element chip 20 is embedded in the bonding layer 30. As a result, not only the tip surface 222A and the recess 222C of the pillar 222 but also part of the side surface is covered with the bonding layer 30.

[0032] 5 to 8, the sealing resin 40 has a top surface 41, a bottom surface 42, a pair of first side surfaces 431, and a pair of second side surfaces 432. The sealing resin 40 is made of, for example, a black epoxy resin. 11 to 14, the top surface 41 faces the same side as the main surface 101 of the conductive member 10 in the thickness direction Z. As shown in FIGS. 5 to 8, the bottom surface 42 faces the opposite side to the top surface 41. As shown in FIG. 4, the back surfaces 102 of the multiple first leads 11, the back surfaces 102 of the multiple second leads 12, and the back surfaces 102 of the pair of third leads 13 are exposed from the bottom surface 42.

[0033] 7 and 8, the pair of first side surfaces 431 are connected to both the top surface 41 and the bottom surface 42 and face the first direction x. The pair of first side surfaces 431 are spaced apart from each other in the second direction y. As shown in FIGS. 12 to 14, the first end surfaces 112A of the multiple first leads 11 and the third end surface 131 of the third lead 13 are exposed from each of the pair of first side surfaces 431 so as to be flush with the first side surfaces 431.

[0034] As shown in FIGS. 5 and 6, the pair of second side surfaces 432 are connected to all of the top surface 41, the bottom surface 42, and the pair of first side surfaces 431, and face the second direction y. The pair of second side surfaces 432 are spaced apart in the first direction x. As shown in FIG. 11, the second end surfaces 121 of the plurality of second leads 12 are exposed from the second side surface 432 located on one side in the second direction y so as to be flush with the second side surface 432. The plurality of minor end surfaces 113A of the second input terminal 11B (first lead 11) are exposed from the second side surface 432 located on the other side in the second direction y so as to be flush with the second side surface 432.

[0035] The semiconductor device A10 includes a conductive member 10 having a main surface 101, an element chip 20 having a chip body 21 and a plurality of bonding members 22 electrically bonded to the main surface 101, and a bonding layer 30 in contact with both the main surface 101 and the plurality of bonding members 22. Each of the plurality of bonding members 22 includes a columnar body 222 that protrudes toward the main surface 101 from a pad wiring layer 29 in contact with the side of the chip body 21 facing the main surface 101 and is in contact with the bonding layer 30. As a result, the element chip 20 is electrically bonded to the conductive member 10 by flip-chip bonding.

[0036] Fig. 17 is a schematic plan view for explaining the wiring structure of the element chip 20. Fig. 18 is a cross-sectional view taken along line XVIII-XVIII in Fig. 17. 17 shows a part of the planar structure of the element chip 20, more specifically, the first bonding members 22A and the pad wiring layer 29 that supports the first bonding members 22A. Explanation of the second bonding members 22B and the pad wiring layer 29 that supports the second bonding members 22B will be omitted, but they have the same structures as the first bonding members 22A and the pad wiring layer 29 shown in FIG. 17. FIG. 18 shows the element chip 20 before it is bonded to the conductive member 10 by flip-chip bonding. FIG. 18 also shows the element chip 20 in a state where the columnar bodies 222 (first bonding members 22A) protrude upward. Therefore, the above-mentioned FIGS. 11 to 16 and FIG. 18 are upside down.

[0037] The element chip 20 includes a multilayer wiring structure 1, a passivation layer 2, a pad wiring layer 29, a covering insulating film 58, a columnar body 222 (bonding member 22), and a bonding layer 30. Note that Fig. 18 shows only one bonding member 22 out of the multiple bonding members 22. The multilayer wiring structure 1 includes a plurality of interlayer insulating films 4 to 7 formed on the element forming surface 3 of the semiconductor layer 212, and a plurality of wiring layers 14 to 16 formed in the plurality of interlayer insulating films 4 to 7. Since the wiring layers 14 to 16 form the multilayer wiring structure 1, they may also be referred to as wiring layers 14 to 16, respectively.

[0038] The multiple interlayer insulating films 4 to 7 include a first interlayer insulating film 4 formed on the element forming surface 3 of the semiconductor layer 212, a second interlayer insulating film 5 formed on the first interlayer insulating film 4, a third interlayer insulating film 6 formed on the second interlayer insulating film 5, and a fourth interlayer insulating film 7 formed on the third interlayer insulating film 6. The first interlayer insulating film 4, the second interlayer insulating film 5, the third interlayer insulating film 6, and the fourth interlayer insulating film 7 may each include an oxide film (SiO2 film) or a nitride film (SiN film).

[0039] The plurality of wiring layers 14 to 16 are electrically connected to a switching circuit 212A and a control circuit 212B formed in the semiconductor layer 212 (only the switching circuit 212A is shown in FIG. 18). The multiple wiring layers 14 to 16 include a first wiring layer 14 formed on the first interlayer insulating film 4 and covered with a second interlayer insulating film 5, a second wiring layer 15 formed on the second interlayer insulating film 5 and covered with a third interlayer insulating film 6, and a third wiring layer 16 formed on the third interlayer insulating film 6 and covered with a fourth interlayer insulating film 7. The first wiring layer 14, the second wiring layer 15, and the third wiring layer 16 may each contain copper or aluminum.

[0040] A first barrier layer 31 is formed on the lower surface of the first wiring layer 14. The first barrier layer 31 prevents the electrode material constituting the first wiring layer 14 from diffusing into the first interlayer insulating film 4. A first barrier layer 32 is formed on the upper surface of the first wiring layer 14. The first barrier layer 32 prevents the electrode material constituting the first wiring layer 14 from diffusing into the second interlayer insulating film 5. A second barrier layer 33 is formed on the lower surface of the second wiring layer 15. The second barrier layer 33 prevents the electrode material constituting the second wiring layer 15 from diffusing into the second interlayer insulating film 5.

[0041] A second barrier layer 34 is formed on the upper surface of the second wiring layer 15. The second barrier layer 34 prevents the electrode material constituting the second wiring layer 15 from diffusing into the third interlayer insulating film 6. A third barrier layer 35 is formed on the lower surface of the third wiring layer 16. The third barrier layer 35 prevents the electrode material constituting the third wiring layer 16 from diffusing into the third interlayer insulating film 6. A third barrier layer 36 is formed on the upper surface of the third wiring layer 16. The third barrier layer 36 prevents the electrode material constituting the third wiring layer 16 from diffusing into the fourth interlayer insulating film 7.

[0042] Each of the barrier layers 31-36 may have a single layer structure made of a titanium nitride layer or a titanium layer, or may have a multilayer structure including a titanium nitride layer and a titanium layer formed on the titanium nitride layer. The barrier layers 31-36 may be made of the same material or different materials. The passivation layer 2 is formed on the multilayer wiring structure 1 so as to cover the multilayer wiring structure 1. More specifically, the passivation layer 2 covers the fourth interlayer insulating film .

[0043] The passivation layer 2 may include an oxide film (SiO2 film), a BPSG (Boron Phosphorus Silicon Glass) film, or a nitride film (SiN film). In this embodiment, the passivation layer 2 is formed of a nitride film (SiN film). The passivation layer 2 may be called the uppermost insulating layer of the multilayer wiring structure 1, or may be called a surface protection layer. A first via 39 penetrating the second interlayer insulating film 5 is formed in the second interlayer insulating film 5 between the upper surface of the first wiring layer 14 and the lower surface of the second wiring layer 15. The first wiring layer 14 is electrically connected to the second wiring layer 15 through the first via 39.

[0044] A first via barrier film 43 is formed between the first via 39 and the second interlayer insulating film 5. The first via 39 may contain tungsten. The first via barrier film 43 may contain titanium nitride. A second via 44 penetrating the third interlayer insulating film 6 is formed in the third interlayer insulating film 6 between the upper surface of the second wiring layer 15 and the lower surface of the third wiring layer 16. The second wiring layer 15 is electrically connected to the third wiring layer 16 through the second via 44.

[0045] A second via barrier film 45 is formed between the second via 44 and the third interlayer insulating film 6. The second via 44 may contain tungsten. The second via barrier film 45 may contain titanium nitride. A third via 46 is formed in the passivation layer 2 and the fourth interlayer insulating film 7 on the third wiring layer 16, penetrating the passivation layer 2 and the fourth interlayer insulating film 7. The third via 46 is exposed from the passivation layer 2 and is electrically connected to the third wiring layer 16.

[0046] The exposed surface of the third via 46 is formed flush with the upper surface 23 of the passivation layer 2. A third via barrier film 47 is formed between the third via 46 and the fourth interlayer insulating film 7, and between the third via 46 and the passivation layer 2. The third via 46 may contain tungsten. The third via barrier film 47 may contain titanium nitride. The pad wiring layer 29 is formed on the upper surface 23 of the passivation layer 2 so as to cover the third via 46. As shown in FIG. 17 , the pad wiring layer 29 is formed in a strip shape in a plan view, and may support a plurality of pillars 222. In this embodiment, a plurality of pad wiring layers 29 are formed at intervals from each other. The pad wiring layer 29 is wiring formed on the top surface of the multilayer wiring structure 1, and therefore may also be referred to as the top-layer wiring layer, the top-layer wiring, the top metal wiring layer, etc. The pad wiring layer 29 has a layered structure including a barrier conductive layer 48 formed on the passivation layer 2 and a first conductive layer 56 containing a metal mainly composed of copper and formed on the main surface of the barrier conductive layer 48. Since the first conductive layer 56 contains a metal mainly composed of copper, it may also be referred to as a Cu conductive layer 49. The barrier conductive layer 48 prevents the electrode material constituting the Cu conductive layer 49 from diffusing into the passivation layer 2.

[0047] Here, the term "metal containing copper as a main component" refers to a metal in which the mass ratio (mass %) of copper constituting the Cu conductive layer 49 is the highest relative to the other components constituting the Cu conductive layer 49 (the same applies hereinafter). When the Cu conductive layer 49 is made of an aluminum-copper alloy (Al-Cu alloy), the mass ratio R Cu is the mass ratio of aluminum R Al Higher than (R Cu >R Al ). When the Cu conductive layer 49 is made of an aluminum-silicon-copper alloy (Al-Si-Cu alloy), the mass ratio R Cu is the mass ratio of aluminum R Al and the mass ratio of silicon, R Si Higher than (R Cu >R Al , and R Cu >R Si ).

[0048] "Metals primarily composed of copper" may contain trace amounts of impurities, but also include high-purity copper with a purity of 99.9999% (6N) or more, and high-purity copper with a purity of 99.99% (4N) or more. The barrier conductive layer 48 is formed on the passivation layer 2 so as to cover the third via 46. The barrier conductive layer 48 is electrically connected to the first wiring layer 14, the second wiring layer 15, and the third wiring layer 16 through the third via 46.

[0049] The barrier conductive layer 48 may have a thickness of 100 nm or more and 500 nm or less (approximately 100 nm in this embodiment). The barrier conductive layer 48 may have a single-layer structure made of a single metal layer. The barrier conductive layer 48 may have a layered structure in which multiple metal layers are stacked. The barrier conductive layer 48 preferably has a thermal expansion coefficient smaller than that of the Cu conductive layer 49. In addition, the barrier conductive layer 48 preferably has a rigidity coefficient larger than that of the Cu conductive layer 49.

[0050] The barrier conductive layer 48 may contain at least one of titanium, titanium nitride, tantalum, tungsten, molybdenum, chromium, and ruthenium. These metal materials can provide the barrier conductive layer 48 with a thermal expansion coefficient (4 μm / m·K or more and 9 μm / m·K or less) smaller than that of the Cu conductive layer 49. When the Cu conductive layer 49 is made of high-purity copper, the thermal expansion coefficient of the Cu conductive layer 49 is approximately 16.5 μm / m·K.

[0051] The barrier conductive layer 48 may contain at least one of tantalum, tungsten, molybdenum, chromium, and ruthenium. These metal materials allow the barrier conductive layer 48 to have a thermal expansion coefficient (4 μm / m·K or more and 7 μm / m·K or less) smaller than that of the Cu conductive layer 49. Furthermore, these metal materials can realize barrier conductive layer 48 having a modulus of rigidity (50 Gpa or more and 180 Gpa or less) greater than that of Cu conductive layer 49. When Cu conductive layer 49 is made of high-purity copper, the modulus of rigidity of Cu conductive layer 49 is approximately 48 Gpa.

[0052] The Cu conductive layer 49 occupies a large portion of the pad wiring layer 29. The Cu conductive layer 49 may have a thickness of 2 μm or more and 6 μm or less. The Cu conductive layer 49 has an upper surface 49a (first surface), a lower surface 49b (second surface) located opposite the upper surface 49a, and a side surface 49c (end surface) connecting the upper surface 49a and the lower surface 49b. The lower surface 49b of the Cu conductive layer 49 is mechanically and electrically connected to the barrier conductive layer 48.

[0053] The periphery of the lower surface 49b of the Cu conductive layer 49 is spaced inward from the periphery of the barrier conductive layer 48. The lower surface 49b of the Cu conductive layer 49 is formed narrower than the upper surface 49a of the Cu conductive layer 49 in the direction along the upper surface 23 of the passivation layer 2. More specifically, in the Cu conductive layer 49, a recess 50 is formed in the region on the lower surface 49b side of the side surface 49c, which recesses inward of the Cu conductive layer 49 and exposes the upper surface of the edge of the barrier conductive layer 48.

[0054] The recess 50 is formed in a convex curved shape that bulges obliquely upward from the Cu conductive layer 49. This makes the inner surface of the recess 50 a convex curved surface. Due to this recess 50, the lower surface 49b of the Cu conductive layer 49 is formed narrower than the upper surface 49a of the Cu conductive layer 49. In this embodiment, the side surface 49c of the Cu conductive layer 49 is located outside the periphery (side surface) of the barrier conductive layer 48. Therefore, in this embodiment, the periphery (side surface) of the barrier conductive layer 48 is located in the region between the periphery of the lower surface 49b of the Cu conductive layer 49 and the side surface 49c of the Cu conductive layer 49. The side surface 49c of the Cu conductive layer 49 may be located inside the periphery (side surface) of the barrier conductive layer 48.

[0055] The pad wiring layer 29 includes a second conductive layer 51 formed on an upper surface 49a of the Cu conductive layer 49. The second conductive layer 51 is formed on the upper surface 49a of the Cu conductive layer 49 so as to cover the upper surface 49a of the Cu conductive layer 49. The second conductive layer 51 includes a first portion 52 mechanically and electrically connected to the upper surface 49a of the Cu conductive layer 49, and a second portion 53 protruding outward from the first portion 52 beyond the side surface 49c of the Cu conductive layer 49. The second portion 53 has an eave shape formed on the upper portion of the pad wiring layer 29 in the thickness direction, and may therefore be referred to as an eave portion 57.

[0056] The second conductive layer 51 has an upper surface 51a (first surface), a lower surface 51b (second surface) located opposite the upper surface 51a, and a side surface 51c (end surface) connecting the upper surface 51a and the lower surface 51b. The lower surface 51b of the second conductive layer 51 is mechanically and electrically connected to the Cu conductive layer 49 (first conductive layer 56). The side surface 51c of the second conductive layer 51 is disposed further outward from the pad wiring layer 29 than the side surface 49c of the Cu conductive layer 49. As a result, a recess 59 is formed below the overhang portion 57 due to a step between the side surface 51c of the second conductive layer 51 and the side surface 49c of the Cu conductive layer 49. In this embodiment, as shown in FIG. 17 , the overhang portion 57 is formed in an annular shape around the entire outer periphery of the pad wiring layer 29 in a plan view. As a result, the recess 59 is formed in an annular shape around the entire periphery below the annular overhang portion 57. The recess 59 may be a portion surrounded by the upper surface 23 of the passivation layer 2, the side surface 49c of the first conductive layer 56, and the overhang portion 57.

[0057] In this embodiment, the second conductive layer 51 has a laminated structure including a first layer 54 formed on the upper surface 49a of the Cu conductive layer 49 and a second layer 55 formed on the first layer 54. The first layer 54 and the second layer 55 are made of a material having a linear expansion coefficient smaller than that of the Cu conductive layer 49 and the Cu columnar members 18 (described later). For example, the linear expansion coefficient of the Cu conductive layer 49 and the Cu columnar members 18 is set to 16.0 or more and 18.0 (10 -6 / °C) or less, and the linear expansion coefficient of the first layer 54 and the second layer 55 is 10.0 or more and 15.0 (10 -6 / °C) or less.

[0058] The material used for the first layer 54 and the second layer 55 is, for example, Ni=13.3(10-6 / ℃), Pd=11.8(10 -6 / ℃), Au=14.2(10 -6 / ℃) degree, W=4.3(10 -6 / ℃), Pt=8.9(10 -6 / ° C.) etc. In this embodiment, the first layer 54 is formed of a nickel (Ni) layer, and the second layer 55 is formed of a palladium (Pd) layer.

[0059] The second layer 55 is formed to a thickness smaller than that of the first layer 54. The second layer 55 may be a metal in which the mass ratio (mass %) of palladium constituting the second layer 55 is the highest relative to the other components constituting the second layer 55. In other words, the second layer 55 may be a metal containing palladium as a main component. The first layer 54 may be a metal in which the mass ratio (mass %) of nickel constituting the first layer 54 is the highest relative to the other components constituting the first layer 54. In other words, the first layer 54 may be a metal in which nickel is the main component.

[0060] The thickness of the first layer 54 may be 0.5 μm or more and 5 μm or less, and the thickness of the second layer 55 may be 0.05 μm or more and 0.5 μm or less. The insulating cover film 58 is formed on the passivation layer 2. The insulating cover film 58 will be described in detail with reference to FIGS. 19, the coated insulating film 58 is selectively formed in a recess 59 below the overhanging portion 57 on the passivation layer 2. In this embodiment, since the recess 59 is formed in a ring shape in a plan view (see FIG. 17), the coated insulating film 58 is also formed in a ring shape. The ring-shaped coated insulating film 58 laterally surrounds the first conductive layer 56 within the recess 59, thereby covering the side surface 49c of the first conductive layer 56.

[0061] Here, "selectively formed in the recess 59" may mean, for example, that all or most of the coating insulating film 58 is formed in the region within the recess 59 among the regions of the upper surface 23 of the passivation layer 2. For example, if the amount S of the coating insulating film 58 protruding outside the side surface 51c of the second conductive layer 51 is in a range (S < T3) smaller than the first thickness T3 of the coating insulating film 58 in the thickness direction of the pad wiring layer 29 (see FIGS. 21 and 22), it may be defined that "the coating insulating film 58 is selectively formed in the recess 59". Thereby, the coating insulating film 58 may be substantially hidden below the eaves portion 57 in a plan view.

[0062] The coating insulating film 58 has a side surface 58c along the side surface 51c of the second conductive layer 51 in the thickness direction of the pad wiring layer 29. The "side surface 58c along the side surface 51c of the second conductive layer 51" may be defined as a side surface 58c formed substantially parallel to the side surface 51c of the second conductive layer 51 in a region within a width W1 (width W1 < thickness T2 of the second conductive layer 51) from the side surface 51c of the second conductive layer 51 to the inside and outside. The "surface substantially parallel to the side surface 51c" may include a surface parallel to the side surface 51c and a surface inclined at about ±5° with respect to the side surface 51c.

[0063] 19, the coated insulating film 58 has a side surface 58c that is located more inward of the pad wiring layer 29 than the side surface 51c of the second conductive layer 51 in a region within a width W1 extending inward from the side surface 51c. The entire side surface 58c of the coated insulating film 58 may be substantially parallel to the side surface 51c, or a portion of the side surface 58c may be substantially parallel to the side surface 51c and the remainder may not be substantially parallel to the side surface 51c. For example, as shown in FIG. 19, consider a case in which the side surface 58c is divided in the thickness direction of the first conductive layer 56 into a first region 581c that is substantially parallel to the side surface 51c and a second region 582c that is substantially not parallel to the side surface 51c. In this case, the first region 581c may occupy more than 50% (preferably, 70% to 90%) of the side surface 58c, and the second region 582c may occupy less than 50% (preferably, 10% to 30%) of the side surface 58c. 19, first region 581c may be formed on the lower side of side surface 58c relative to second region 582c. Second region 582c may be linear in cross section, or may be formed in an arc shape as shown in FIG.

[0064] The coated insulating film 58 has a first thickness T3 in the thickness direction of the pad wiring layer 29 and a second thickness T4 in a direction intersecting the thickness direction of the pad wiring layer 29. The second thickness T4 of the coated insulating film 58 is smaller than the first thickness T3. For example, the first thickness T3 may be the same as the thickness T1 of the first conductive layer 56 (for example, approximately 2 μm or more and 6 μm or less). In a peripheral region 60 of the pad wiring layer 29, the upper surface 23 of the passivation layer 2 is exposed from the insulating coating film 58. For example, in FIG. 17 , a region 61 between adjacent pad wiring layers may be the peripheral region 60, and the upper surface 23 of the passivation layer 2 may be exposed in this region 61.

[0065] Since the insulating film 58 is selectively formed in the recess 59, the upper surface 51a and the side surface 51c of the second conductive layer 51 are exposed from the insulating film 58. In other words, the insulating film 58 is a film that selectively covers the first conductive layer 56 of the pad wiring layer 29, and the second conductive layer 51 is not covered by the insulating film 58. Therefore, the upper surface 51a and the side surface 51c of the second conductive layer 51 are exposed from the insulating film 58 as continuous exposed surfaces via a boundary portion 51d between the upper surface 51a and the side surface 51c (in this embodiment, an upper corner portion of the second conductive layer 51). In particular, the entire upper surface 51a of the second conductive layer 51 is exposed from the insulating film 58. Therefore, the entire upper surface 51a of the second conductive layer 51 is used as a pad region to which the bonding member 22 can be bonded.

[0066] The insulating coating film 58 is made of an electrically insulating film and may be, for example, a resin film. Examples of the resin film include a polyimide resin film and a phenolic resin film. The insulating coating film 58 may also be an insulating film other than a resin film (for example, a silicon oxide film, a silicon nitride film, etc.). 20, the coated insulating film 58 may have a side surface 58c that is flush with the side surface 51c of the second conductive layer 51. Also, with reference to FIGS. 21 and 22, the coated insulating film 58 may have a side surface 58c that is arranged further outward from the pad wiring layer 29 than the side surface 51c in a region within a range of width W1 extending outward from the side surface 51c of the second conductive layer 51. In this case, as shown in FIG. 22, the lower portion of the side surface 51c of the second conductive layer 51 may be selectively coated with the coated insulating film 58.

[0067] 17 and 18, the bonding members 22 (columnar bodies 222) are bonded to an upper surface 51a of the second conductive layer 51 and protrude from the upper surface 51a. In this embodiment, a plurality of bonding members 22 are bonded to one pad wiring layer 29. Referring to Fig. 17, the plurality of bonding members 22 may be arranged at intervals from one another in the longitudinal direction of the pad wiring layer 29.

[0068] The bonding member 22 has a layered structure including a barrier layer 17 and Cu pillars 18, which contain a metal mainly composed of copper and are formed on the main surfaces of the barrier layer 17. Here, the "metal mainly composed of copper" constituting the Cu pillars 18 is defined in the same way as the Cu conductive layer 49 described above. The barrier layer 17 is mechanically and electrically connected to the pad wiring layer 29. The barrier layer 17 may have a thickness of 100 nm or more and 500 nm or less (approximately 100 nm in this embodiment). The barrier layer 17 may have a single-layer structure made of a single metal layer. The barrier layer 17 may also have a laminated structure in which multiple metal layers are laminated.

[0069] The Cu pillars 18 may have a thickness of 20 μm or more and 60 μm or less. In addition, the Cu pillars 18 may be replaced by pillars made of a material other than Cu. The bonding layer 30 is formed on the tip end surface 222A of the columnar body 222 of the bonding member 22. The bonding layer 30 has a protruding portion 19 that partially protrudes laterally beyond the side surface 222B of the columnar body 222.

[0070] The bonding layer 30 may have, in a portion in contact with the Cu columns 18, a layer made of a material having a linear expansion coefficient smaller than that of the Cu columns 18. In this embodiment, the bonding layer 30 has a layered structure including a first layer 24 formed on the columns 222 (Cu columns 18) and a second layer 25 formed on the first layer 24. The first layer 24 is made of a material having a linear expansion coefficient smaller than that of the Cu columns 18. More specifically, the first layer 24 may include a nickel layer, and the second layer 25 may include a solder layer.

[0071] The nickel layer may be a metal having the highest mass ratio (mass %) of nickel relative to the other components constituting the nickel layer. In other words, the first layer 24 may be any metal containing nickel as its main component. The solder layer is preferably a lead-free solder containing no or almost no lead. Examples of suitable lead-free solder include SnAgCu, SnZnBi, SnCu, SnAgInBi, and SnZnAl. The second layer 25 may be formed in a generally spherical shape before flip-chip bonding, as shown in FIG. 18 .

[0072] 23A to 23P are diagrams for explaining part of the manufacturing process of the semiconductor device A10 in the order of steps. FIGS. 24A and 24B are diagrams showing steps related to the formation of the coated insulating film 58. FIGS. 25A and 25B are diagrams showing steps related to the formation of the coated insulating film 58. In the following, an example will be described in which the Cu conductive layer 49 is made of high-purity copper. In manufacturing the semiconductor device A10, first, the element chip 20 is manufactured. Referring to FIG. 23A, a wafer-shaped semiconductor substrate (semiconductor layer 212) having a passivation layer 2 formed on a multilayer wiring structure 1 is prepared. A third via 46 is formed in the passivation layer 2 and the fourth interlayer insulating film 7 so as to penetrate them. Next, a barrier conductive layer 48 is formed on the passivation layer 2. The barrier conductive layer 48 may be formed by, for example, a sputtering method.

[0073] 23B , a Cu seed layer 9 is formed on the barrier conductive layer 48. The Cu seed layer 9 may be formed by, for example, a sputtering method. Next, a mask 26 having a predetermined pattern is formed on the Cu seed layer 9. The mask 26 selectively has openings 26a that expose regions of the Cu seed layer 9 where a Cu conductive layer 49 is to be formed.

[0074] Next, referring to FIG. 23C, a Cu conductive layer 49 (first conductive layer 56) is formed. The Cu conductive layer 49 is formed on the surface of the Cu seed layer 9 exposed from the opening 26a of the mask 26. The Cu conductive layer 49 may be formed by electrolytic copper plating. The Cu conductive layer 49 is formed to a depth partway through the opening 26a of the mask 26. The Cu conductive layer 49 is formed integrally with the Cu seed layer 9.

[0075] 23D , a first layer 54 and a second layer 55 are formed in this order on the upper surface 49a of the Cu conductive layer 49. The first layer 54 and the second layer 55 are each formed on the upper surface 49a of the Cu conductive layer 49 exposed through the opening 26a of the mask 26. The first layer 54 and the second layer 55 may each be formed by electroless plating. Next, referring to Figure 23E, the mask 26 is removed.

[0076] Next, referring to FIG. 23F, unnecessary portions of the Cu seed layer 9 are removed. The Cu seed layer 9 may be removed by wet etching. In this process, a portion of the Cu conductive layer 49 is side-etched. Therefore, a side surface 49c of the Cu conductive layer 49 is formed to be located more inward than the side surface of the second conductive layer 51. The side etching occurs, for example, due to a battery effect between the first conductive layer 56 and the second conductive layer 51, which are made of different conductive materials. The "battery effect" may be defined as, for example, a phenomenon in which, when different conductive materials are immersed in an aqueous solution such as an etching solution while conducting with each other, a voltage is generated between the two conductive materials, causing corrosion of the material with a relatively low ionization tendency.

[0077] This forms the second conductive layer 51. The second conductive layer 51 includes a first portion 52 mechanically and electrically connected to the upper surface 49a of the Cu conductive layer 49, and a second portion 53 (eave portion 57) that protrudes from the first portion 52 to the side of the barrier conductive layer 48. In addition, a recess 59 is formed below the eave portion 57. 23G, unnecessary portions of the barrier conductive layer 48 are removed. The barrier conductive layer 48 may be removed by wet etching. In this step, the portion of the barrier conductive layer 48 located directly below the Cu conductive layer 49 is removed by an amount corresponding to the thickness of the barrier conductive layer 48. Therefore, the side surface of the barrier conductive layer 48 is formed so as to be located inward from the side surface 49c of the Cu conductive layer 49.

[0078] 23H , a corner portion of the Cu conductive layer 49 connecting the lower surface 49b and the side surface 49c is removed. The corner portion of the Cu conductive layer 49 may be removed by wet etching. The wet etching process is performed until the main surface of the barrier conductive layer 48 is exposed. As a result, a recess 50 is formed in a region of the Cu conductive layer 49 on the lower surface 49b side of the side surface 49c, exposing the upper surface of the edge portion of the barrier conductive layer 48.

[0079] 23I, 24A, and 25A, an insulating layer 62 is formed on the passivation layer 2 so as to cover the pad wiring layer 29. The insulating layer 62 may be a photosensitive resin layer (e.g., a polyimide resin film, a phenolic resin film, etc.), or an insulating layer other than a resin layer (e.g., a silicon oxide film, a silicon nitride film, etc.). The insulating layer 62 may be formed on the entire surface of the semiconductor wafer (semiconductor layer 212) by, for example, a spin coating method. A portion of the insulating layer 62 enters the recess 59 as a first portion 621 (the portion painted gray in FIG. 24A), and the remainder of the insulating layer 62 is exposed outside the recess 59 as a second portion 622.

[0080] When the insulating layer 62 is a resin layer, as shown in FIG. 24A, the entire surface of the insulating layer 62 is exposed to light. At this time, a first portion 621 of the insulating layer 62 is covered by the overhanging portion 57 and is not exposed, becoming a non-exposed portion. On the other hand, a second portion 622 of the insulating layer 62 is not covered by the overhanging portion 57 and is therefore exposed, becoming a photoexposed portion. In other words, the overhanging portion 57 of the second conductive layer 51 is used as a mask to prevent the first portion 621 of the insulating layer 62 from being exposed to light. Next, as shown in FIG. 24B, the exposed insulating layer 62 is developed, so that the first portion 621 of the insulating layer 62, which is the non-exposed portion, remains as the coated insulating film 58, and the second portion 622 of the insulating layer 62, which is the photoexposed portion, is selectively removed.

[0081] 25A and 25B, the insulating layer 62 may be patterned by etching back. For example, the insulating layer 62 may be formed over the entire surface of the semiconductor wafer (semiconductor layer 212), and then anisotropic etching back may be performed. In this case, the first portion 621 of the insulating layer 62 is hidden by the overhanging portion 57 in the direction normal to the upper surface 23 and is not exposed to the etching solution, and can be left as the coated insulating film 58.

[0082] 23J, a barrier layer 17 is formed on the passivation layer 2 so as to cover the pad wiring layer 29. The barrier layer 17 may be formed by, for example, a sputtering method. Next, a Cu seed layer 27 is formed on the barrier layer 17. The Cu seed layer 27 may be formed by, for example, a sputtering method. Next, a mask 28 having a predetermined pattern is formed on the Cu seed layer 27. The mask 28 selectively has openings 28a that expose regions of the Cu seed layer 27 where the Cu columns 18 are to be formed.

[0083] Next, referring to FIG. 23K, Cu pillars 18 are formed on the surface of Cu seed layer 27 exposed through openings 28a in mask 28. Cu pillars 18 may be formed by electrolytic copper plating. Cu pillars 18 are formed to the middle of openings 28a in mask 28 in the depth direction. Next, referring to FIG. 23L, a first layer 24 (nickel layer) is formed on the Cu columnar bodies 18. The first layer 24 is formed on the upper surfaces of the Cu columnar bodies 18 exposed from the openings 28a of the mask 28. The first layer 24 may be formed by electroless plating. Next, a second layer 25 (solder layer) is formed on the first layer 24. This forms the bonding layer 30.

[0084] Next, referring to Figure 23M, the mask 28 is removed. 23N, unnecessary portions of the Cu seed layer 27 are removed. The Cu seed layer 27 may be removed by wet etching. In this process, parts of the Cu columnar bodies 18 are side-etched. Therefore, the side surfaces 222B of the Cu columnar bodies 18 are formed so as to be located more inward than the side surfaces of the first layer 24.

[0085] 23O, unnecessary portions of the barrier layer 17 are removed. The barrier layer 17 may be removed by wet etching. Next, referring to FIG. 23P, second layer 25 is formed into a spherical shape, for example, by heat treatment. Thereafter, the element chip 20 is flip-bonded to the conductive member 10. Next, the element chip 20 is sealed together with the conductive member 10 by the sealing resin 40. Then, a dicing process is performed on the sealing resin 40, and the semiconductor device A10 is cut out. Through the above processes, the semiconductor device A10 is manufactured.

[0086] 18 to 22, in the element chip 20, the side surface 49c of the first conductive layer 56 is covered with the insulating coating film 58, which makes it possible to suppress the migration of Cu-derived ions along the upper surface 23 of the passivation layer 2. This makes it possible to suppress ion migration in the surrounding region 60 of the pad wiring layer 29. More specifically, it is possible to suppress the migration of ions in the region 61 between adjacent pad wiring layers 29, thereby suppressing ion migration.

[0087] On the other hand, the insulating coating film 58 is selectively formed below the overhanging portion 57 of the pad wiring layer 29. Therefore, the upper surface 51a of the pad wiring layer 29 and the upper portions of the side surfaces 51c of the pad wiring layer 29 near the upper surface 51a are not covered with the insulating coating film 58. This reduces the portion of the pad wiring layer 29 covered by the insulating coating film 58, thereby reducing stress on the pad wiring layer 29.

[0088] For example, this will be compared with the reference example of FIG. 26 , in which the upper surface 51 a and the side surface 51 c of the pad wiring layer 29 are covered with a resin film 63 and the contact hole 64 of the bonding member 22 is formed in the resin film 63. In this reference example, because the pad wiring layer 29 is covered with the resin film 63, stress is likely to be applied in the directions indicated by arrows 65 and 66, for example, near the boundary portion 51 d and the contact hole 64. Furthermore, because the adhesion between Ni and Pd and the resin is poor, there is a concern that this stress may cause the resin film 63 to peel off. In contrast, in this embodiment, the upper surface 51 a and the side surface 51 c of the pad wiring layer 29 are exposed from the insulating coating 58, so that at least the stress indicated by the arrows 65 and 66 in FIG. 26 can be eliminated.

[0089] In the element chip 20 according to this embodiment, the entire upper surface 51a of the pad wiring layer 29 is exposed from the insulating coating film 58. Therefore, the bonding member 22 can be bonded to the upper surface 51a under more relaxed conditions (e.g., dimensional conditions, misalignment conditions, etc.) compared to the case in which only a part of the upper surface 51a of the pad wiring layer 29 is exposed as a pad 67 from the contact hole 64 as shown in FIG.

[0090] Furthermore, when forming the covering insulating film 58 selectively filled in the recess 59, the eaves portion 57 of the pad wiring layer 29 is used as a mask when patterning the insulating layer 62, thereby preventing an increase in costs due to the addition of a mask. Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms. For example, in the above-described embodiment, only the form in which the element chip 20 is flip-chip bonded has been shown, but the element chip 20 may have the back surface of the semiconductor substrate 211 bonded to the conductive member 10, and the second conductive layer 51 and each lead of the conductive member 10 bonded by wire bonding. In this case, as shown in Fig. 27, a bonding wire 68 may be bonded to the upper surface 51a of the pad wiring layer 29.

[0091] The embodiments of the present disclosure are to be considered as illustrative in all respects and not restrictive, and are intended to include modifications in all respects. The following characteristics can be extracted from the description of this specification and the drawings. [Appendix 1-1] a semiconductor chip (21) having an element forming surface (3); an insulating layer (2) formed on the element forming surface (3) of the semiconductor chip (21); a pad wiring layer (29) having a first conductive layer (49, 56) formed on the insulating layer (2) and containing a first conductive material, and a second conductive layer (51, 54, 55) formed on the first conductive layer (49, 56) and containing a second conductive material different from the first conductive material, the pad wiring layer (29) having an overhang portion (57) formed by the second conductive layer (51, 54, 55) protruding outward from an end face (49c) of the first conductive layer (49, 56); a bonding member (22) bonded to the pad wiring layer (29) and supplying power to the elements (212A, 212B) on the element forming surface (3); a covering insulating film (58) selectively formed on the insulating layer (2) below the overhanging portion (57), exposing an upper surface (23) of the insulating layer (2) in a peripheral region (60) of the pad wiring layer (29), and covering an end surface (49c) of the first conductive layer (49, 56).

[0092] With this configuration, the end surface (49c) of the first conductive layer (49, 56) is covered with the insulating film (58), which prevents ions from the first conductive material from migrating along the upper surface (23) of the insulating layer (2). This prevents ion migration in the peripheral region (60) of the pad wiring layer (29). Meanwhile, the insulating film (58) is selectively formed below the overhanging portion (57) of the pad wiring layer (29). Therefore, the upper surface (51a) of the pad wiring layer (29) and the upper portion of the end surface (51c) of the pad wiring layer (29) near the upper surface (51a) are not covered with the insulating film (58). This reduces the portion of the pad wiring layer (29) covered by the insulating film (58), thereby reducing stress on the pad wiring layer (29). [Appendix 1-2] The overhanging portion (57) is formed in a ring shape along the outer periphery of the pad wiring layer (29) in a plan view, The semiconductor device (A10) described in Appendix 1-1, wherein the covering insulating film (58) is formed around the entire circumference of the recess (59) below the annular overhang portion (57) and includes an annular insulating film (58) that covers the first conductive layer (49, 56) from the side.

[0093] According to this configuration, the end face (49c) of the first conductive layer (49, 56) is covered over the entire periphery of the recess (59), thereby suppressing ion migration over the entire periphery of the peripheral region (60) of the pad wiring layer (29). [Appendix 1-3] a plurality of the pad wiring layers (29) arranged at intervals on the insulating layer (2); The semiconductor device (A10) according to Appendix 1-1 or Appendix 1-2, wherein the peripheral region (60) of the pad wiring layer (29) includes a region (61) between adjacent ones of the pad wiring layers (29).

[0094] This configuration makes it possible to suppress the movement of ions between adjacent pad wiring layers (29), thereby suppressing ion migration. [Appendix 1-4] The semiconductor device (A10) according to any one of Appendices 1-1 to 1-3, wherein the second conductive layer (51, 54, 55) has a bonding surface (51a) to which the bonding member (22) is bonded and which is an exposed surface that is entirely exposed from the covering insulating film (58).

[0095] According to this configuration, the entire bonding surface (51 a) of the second conductive layer (51, 54, 55) is exposed from the insulating film (58). Therefore, it is possible to prevent stress from being directly applied from the insulating film (58) to the bonding surface (51 a) of the second conductive layer (51, 54, 55). Furthermore, because the entire bonding surface (51 a) of the second conductive layer (51, 54, 55) is exposed, the bonding member (22) can be bonded to the bonding surface (51 a) under more relaxed conditions (e.g., dimensional conditions, misalignment conditions, etc.) than when only a portion of the second conductive layer (51, 54, 55) is exposed as a pad through an opening of a predetermined shape. [Appendix 1-5] The semiconductor device (A10) according to any one of Supplementary Notes 1-1 to 1-4, wherein the insulating cover film (58) is substantially hidden below the overhanging portion (57) in plan view. [Appendix 1-6] A semiconductor device (A10) according to any one of Appendices 1-1 to 1-5, wherein the covering insulating film (58) has an end surface (58c) that is aligned with an end surface (51c) of the second conductive layer (51, 54, 55) in the thickness direction of the pad wiring layer (29). [Appendix 1-7] A semiconductor device (A10) described in Appendix 1-6, wherein an end surface (58c) of the covering insulating film (58) is positioned inside the pad wiring layer (29) more than an end surface (51c) of the second conductive layer (51, 54, 55). [Appendix 1-8] The semiconductor device (A10) according to appendix 1-6, wherein an end surface (58c) of the insulating cover layer (58) is flush with an end surface (51c) of the second conductive layer (51, 54, 55). [Appendix 1-9] A semiconductor device (A10) described in Appendix 1-6, wherein an end surface (58c) of the covering insulating film (58) is positioned outside the pad wiring layer (29) more than an end surface (51c) of the second conductive layer (51, 54, 55). [Appendix 1-10] A semiconductor device (A10) described in any one of Appendices 1-1 to 1-9, wherein the covering insulating film (58) has a first thickness (T3) in the thickness direction of the pad wiring layer (29) and a second thickness (T4) in a direction intersecting the thickness direction of the pad wiring layer (29), the second thickness (T4) being smaller than the first thickness (T3). [Appendix 1-11] The semiconductor device (A10) according to any one of Appendix 1-1 to Appendix 1-10, wherein the insulating coating film (58) includes a resin film (58). [Appendix 1-12] The semiconductor device (A10) according to Appendix 1-11, wherein the resin film (58) includes at least one of a polyimide resin film and a phenolic resin film. [Appendix 1-13] the first conductive layer (49, 56) includes a Cu conductive layer (49); The semiconductor device (A10) according to any one of Appendices 1-1 to 1-12, wherein the second conductive layer (51, 54, 55) includes a Ni conductive layer (54) on the Cu conductive layer (49) and a Pd conductive layer (55) on the Ni conductive layer (54). [Appendix 1-14] The semiconductor device (A10) according to any one of Supplementary Notes 1-1 to 1-13, wherein the bonding member (22) includes a columnar body (222) extending in a thickness direction of the pad wiring layer (29). [Appendix 1-15] The semiconductor device (A10) according to any one of Supplementary Notes 1-1 to 1-13, wherein the joining member (22) includes a bonding wire (68). [Appendix 1-16] a conductive member (10) that supports the semiconductor chip (21); The semiconductor device (A10) according to any one of Supplementary Notes 1-1 to 1-15, further comprising a sealing resin (40) that covers a part of the conductive member and the semiconductor chip (21). [Appendix 1-17] A step of forming an insulating layer (2) on an element forming surface (3) of a semiconductor substrate (20) having the element forming surface (3); forming a pad wiring layer (29) by sequentially stacking, on the insulating layer (2), first conductive layers (49, 56) containing a first conductive material and second conductive layers (51, 54, 55) containing a second conductive material different from the first conductive material; a step of selectively side-etching the first conductive layer (49, 56) of the pad wiring layer (29) to form an eave portion (57) on the pad wiring layer (29) that is made of a part of the second conductive layer (51, 54, 55) and that protrudes outward from an end face (49c) of the first conductive layer (49, 56); forming a second insulating layer (62) on the insulating layer (2) so as to cover the pad wiring layer (29); and a step of selectively removing a second portion (622) of the second insulating layer (62) that is not covered by the overhanging portion (57) by patterning using the overhanging portion (57) as a mask, thereby leaving a first portion (621) of the second insulating layer (62) that is covered by the overhanging portion (57) as a coated insulating film (58) that covers an end face (49c) of the first conductive layer (49, 56).

[0096] This method allows the insulating coating film 58 to be selectively left on the insulating layer 2 below the overhanging portion 57. Furthermore, at least the upper surface 51 a of the pad wiring layer 29 and the upper portion of the end surface 51 c of the pad wiring layer 29 near the upper surface 51 a can be exposed from the insulating coating film 58. This makes it possible to provide a semiconductor device A10 that can suppress ion migration in the peripheral region 60 of the pad wiring layer 29 and reduce stress on the pad wiring layer 29.

[0097] Furthermore, since the eaves portion (57) of the pad wiring layer (29) is used as a mask when patterning the second insulating layer (62), it is possible to prevent an increase in cost due to the addition of a mask. [Appendix 1-18] the second insulating layer (62) includes a photosensitive resin layer (62), The method for manufacturing a semiconductor device (A10) described in Appendix 1-17, wherein the patterning using the overhang portion (57) as a mask includes a process of performing full-surface exposure on the resin layer (62), and a process of performing a development process after the exposure to leave the first portion (621), which is a non-photosensitive portion of the resin layer (62), as a resin film (58), and selectively remove the second portion (622), which is a photosensitive portion of the resin layer (62). [Appendix 1-19] A method for manufacturing a semiconductor device (A10) according to Appendix 1-17, wherein the patterning using the overhang portion (57) as a mask includes a step of etching back the second insulating layer (62) to leave the first portion (621) of the second insulating layer (62) as a coating resin film (58) and selectively remove the second portion (622) of the second insulating layer (2). [Explanation of symbols]

[0098] 1: Multilayer wiring structure 2: Passivation layer 3: Element formation surface 4: First interlayer insulating film 5: Second interlayer insulating film 6: Third interlayer insulating film 7: Fourth interlayer insulating film 9: Cu seed layer 10: Conductive material 11: First lead 11A: First input terminal 11B: Second input terminal 11C: Output terminal 12: Second lead 13: Third lead 14: 1st wiring layer 15: 2nd wiring layer 16: 3rd wiring layer 17: Barrier layer 18:Cu columnar body 19: Overhang 20: Element chip 21: Chip body 22: Joint material 22A: First joining member 22B: Second joining member 23:Top surface 24 :1st layer 25: 2nd layer 26: Mask 26a:Aperture 27: Cu seed layer 28: Mask 28a:Aperture 29: Pad wiring layer 30: Bonding layer 31: First barrier layer 32: First barrier layer 33: Second barrier layer 34: Second barrier layer 35: Third barrier layer 36: Third barrier layer 39: First via 40: Sealing resin 41:Top surface 42: Bottom 43: First via barrier film 44: Second via 45: Second via barrier film 46: Third via 47: Third via barrier film 48: Barrier conductive layer 49:Cu conductive layer 49a:Top surface 49b: Bottom surface 49c: Side 50: Recess 51: Second conductive layer 51a:Top surface 51b: Bottom surface 51c: Side 51d: Boundary part 52 :1st part 53:Second part 54: 1st layer (Ni layer) 55: 2nd layer (Pd layer) 56: First conductive layer 57: Eave 58: Covered insulation film 58c: Side 59: Recess 60: Surrounding area 61 :Area 62: Insulating layer 63: Resin film 64: Contact hole 65: Arrow 66: Arrow 67: Pad 68: Bonding wire 101: Main surface 102: Back side 111: Main section 111A: First input terminal 112: Side 112A: 1st end surface 112B : Department 112C: Notch 113:Protrusion 113A: Minor end face 121: 2nd end face 131: Third end surface 211: Semiconductor substrate 212: Semiconductor layer 212A: Switching circuit 212B: Control circuit 222: Column 222A: Tip surface 222B: Side 222C: Recess 431 :1st side 432:Second side 581c: 1st area 582c:Second area 621 :1st part 622 :Second part A10: Semiconductor device S: Amount of overhang T1: Thickness T2: Thickness T3: First thickness T4: Second thickness W1: Width

Claims

1. a semiconductor chip having an element formation surface; an insulating layer formed on the element forming surface of the semiconductor chip; a pad wiring layer having a first conductive layer formed on the insulating layer and containing a first conductive material, and a second conductive layer formed on the first conductive layer and containing a second conductive material different from the first conductive material, the second conductive layer protruding outward from an end face of the first conductive layer to form an overhanging portion; a bonding member bonded to the pad wiring layer and configured to supply power to the elements on the element forming surface; a covering insulating film selectively formed on the insulating layer below the overhanging portion, exposing an upper surface of the insulating layer in a peripheral region of the pad wiring layer, and covering an end face of the first conductive layer; The semiconductor device, wherein the insulating coating film includes a resin film.

2. the overhanging portion is formed in a ring shape along the outer periphery of the pad wiring layer in a plan view, 2. The semiconductor device according to claim 1, wherein said insulating cover includes an annular insulating film formed around the entire periphery of the recess below said annular overhang portion and covering said first conductive layer from the side.

3. a plurality of the pad wiring layers arranged on the insulating layer at intervals from each other; 3. The semiconductor device according to claim 1, wherein the peripheral region of the pad wiring layer includes a region between adjacent ones of the pad wiring layers.

4. 4. The semiconductor device according to claim 1, wherein the second conductive layer has a bonding surface to which the bonding member is bonded and which is an exposed surface that is entirely exposed from the insulating coating film.

5. 5. The semiconductor device according to claim 1, wherein said insulating cover film is substantially hidden below said overhanging portion in plan view.

6. 6. The semiconductor device according to claim 1, wherein the insulating cover layer has an end face that is aligned with an end face of the second conductive layer in a thickness direction of the pad wiring layer.

7. 7. The semiconductor device according to claim 6, wherein an end face of said insulating cover layer is located inside said pad wiring layer with respect to an end face of said second conductive layer.

8. The semiconductor device according to claim 6 , wherein an end face of said insulating cover film is flush with an end face of said second conductive layer.

9. 7. The semiconductor device according to claim 6, wherein an end face of said insulating cover layer is disposed outside said pad wiring layer with respect to an end face of said second conductive layer.

10. The semiconductor device according to any one of claims 1 to 9, wherein the coated insulating film has a first thickness in the thickness direction of the pad wiring layer and a second thickness in a direction intersecting the thickness direction of the pad wiring layer, the second thickness being smaller than the first thickness.

11. A semiconductor chip having an element formation surface; an insulating layer formed on the element forming surface of the semiconductor chip; a pad wiring layer having a barrier conductive layer formed on the insulating layer, a first conductive layer formed on the barrier conductive layer and containing a first conductive material, and a second conductive layer formed on the first conductive layer and containing a second conductive material different from the first conductive material, the second conductive layer protruding outward from an end face of the first conductive layer; a bonding member bonded to the pad wiring layer and configured to supply power to the elements on the element forming surface; a covering insulating film selectively formed on the insulating layer below the overhanging portion, exposing an upper surface of the insulating layer in a peripheral region of the pad wiring layer, and covering an end face of the first conductive layer; the insulating coating film covers both the top surface and the side surface of the barrier conductive layer at an end of the barrier conductive layer; The semiconductor device, wherein the insulating coating film includes a resin film.

12. 12. The semiconductor device according to claim 1, wherein the resin film includes at least one of a polyimide resin film and a phenolic resin film.

13. the first conductive layer includes a Cu conductive layer; 13. The semiconductor device according to claim 1, wherein the second conductive layer includes a Ni conductive layer on the Cu conductive layer, and a Pd conductive layer on the Ni conductive layer.

14. 14. The semiconductor device according to claim 1, wherein the bonding member includes a columnar body extending in a thickness direction of the pad wiring layer.

15. 14. The semiconductor device according to claim 1, wherein the bonding member includes a bonding wire.

16. a conductive member supporting the semiconductor chip; 16. The semiconductor device according to claim 1, further comprising a sealing resin that covers a portion of said conductive member and said semiconductor chip.

17. forming an insulating layer on a device formation surface of a semiconductor substrate having the device formation surface; forming a pad wiring layer by sequentially stacking a first conductive layer including a first conductive material and a second conductive layer including a second conductive material different from the first conductive material on the insulating layer; forming an eave portion on the pad wiring layer, the eave portion being made of a part of the second conductive layer and protruding outward from an end face of the first conductive layer, by selectively side-etching the first conductive layer of the pad wiring layer; forming a second insulating layer on the insulating layer so as to cover the pad wiring layer; and selectively removing a second portion of the second insulating layer that is not covered by the overhanging portion by patterning using the overhanging portion as a mask, thereby leaving a first portion of the second insulating layer that is covered by the overhanging portion as a coated insulating film that covers an end face of the first conductive layer.

18. the second insulating layer includes a photosensitive resin layer, 18. The method for manufacturing a semiconductor device according to claim 17, wherein the patterning using the overhanging portion as a mask includes a step of performing a full-surface exposure on the resin layer, and a step of performing a development process after the exposure to leave the first portion, which is a non-photoexposed portion of the resin layer, as a resin film and selectively removing the second portion, which is a photoexposed portion of the resin layer.

19. 18. The method for manufacturing a semiconductor device according to claim 17, wherein the patterning using the overhanging portion as a mask includes a step of etching back the second insulating layer to leave the first portion of the second insulating layer as a covering insulating film and selectively remove the second portion of the second insulating layer.

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