Memory device

Abstract

To provide a highly reliable storage device.SOLUTION: At a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided sequentially when viewed from the first conductor side. The first conductor is provided with: a first region overlapping with a second conductor through the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator; and a second region overlapping with a third conductor through the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above-mentioned technical fields. The technical fields of the inventions disclosed in this specification relate to products, methods, or manufacturing methods. Alternatively, one aspect of the present invention relates to processes, machines, manufactures, or compositions of matter.

[0003] In this specification and the like, a semiconductor device generally refers to anything that can function by utilizing semiconductor characteristics. Therefore, semiconductor elements such as transistors and diodes, and circuits including semiconductor elements are semiconductor devices. Furthermore, display devices, light-emitting devices, lighting devices, electro-optical devices, memory devices, imaging devices, communication devices, and electronic devices may include semiconductor elements and semiconductor circuits. Furthermore, display devices, light-emitting devices, lighting devices, electro-optical devices, memory devices, imaging devices, communication devices, and electronic devices may also be called semiconductor devices. [Background technology]

[0004] In recent years, with the increase in the amount of data handled, there has been a demand for semiconductor devices with larger storage capacities. Stacking memory cells is an effective way to increase the storage capacity per unit area (see Patent Documents 1 and 2). Stacking memory cells makes it possible to increase the storage capacity per unit area in accordance with the number of stacked memory cells. Patent Documents 3 and 4 disclose memory devices using oxide semiconductors. Patent Document 5 discloses a semiconductor memory using an oxide semiconductor as a charge storage layer.

[0005] Furthermore, Non-Patent Document 1 discloses CAAC-IGZO as a crystalline oxide semiconductor, and also discloses the growth mechanism of CAAC-IGZO. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] US Patent Publication No. 2011 / 0065270A1 [Patent Document 2] U.S. Patent Publication No. 9634097B2 [Patent Document 3] Patent Publication No. 2018-207038 [Patent Document 4] JP-A-2019-8862 [Patent Document 5] Patent Publication No. 2018-157205 [Non-patent literature]

[0007] [Non-Patent Document 1] Noboru Kimizuka and Shunpei Yamazaki, “PHYSICS AND TECHNOLOGY OF CRYSTALLINE OXIDE SEMICONDUCTOR CAAC-IGZO” FUNDAMENTALS (USA), Wiley-SID Series in Display Technology, 2017, p.94-97 Summary of the Invention [Problem to be solved by the invention]

[0008] In Patent Documents 1 and 2, a plurality of storage elements (also called memory cells) are stacked and connected in series to form a three-dimensional memory cell array (also called memory string).

[0009] In Patent Document 1, a columnar semiconductor is in contact with an insulator having a charge storage layer. In Patent Document 2, a columnar semiconductor is in contact with an insulator that functions as a tunnel dielectric. In both Patent Documents 1 and 2, writing information to a memory cell is performed by extracting and injecting charges through the insulator. In this case, trap centers may be formed at the interface where the semiconductor and insulator meet. The trap centers may capture electrons and cause the threshold voltage of the transistor to fluctuate. This may adversely affect the reliability of the memory device.

[0010] An object of one embodiment of the present invention is to provide a highly reliable memory device.Another object of one embodiment of the present invention is to provide a memory device with a large storage capacity.Another object of one embodiment of the present invention is to provide a memory device with a small occupation area.Another object of one embodiment of the present invention is to provide a memory device with low manufacturing costs.Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device.Another object of one embodiment of the present invention is to provide a semiconductor device with low manufacturing costs.Another object of one embodiment of the present invention is to provide a novel semiconductor device.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc. [Means for solving the problem]

[0012] One aspect of the present invention is a semiconductor device in which a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order on a side surface of a first conductor extending in a first direction, as viewed from the first conductor side. The first conductor has a first region overlapping the second conductor via the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator, and a second region overlapping the third conductor via the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.

[0013] Another aspect of the present invention is a memory device having a first conductor, a second conductor, a third conductor, a fourth conductor, a first insulator, a second insulator, a third insulator, a first semiconductor, and a second semiconductor, wherein the first conductor extends in a first direction, and on a side of the first conductor extending in the first direction, the first insulator is provided adjacent to the first conductor, the first semiconductor is provided adjacent to the first insulator, the second insulator is provided adjacent to the first semiconductor, the second semiconductor is provided adjacent to the second insulator, and the third insulator is provided adjacent to the second semiconductor, and the first conductor has a first region and a second region, and in the first region, the second conductor is provided adjacent to the third insulator, and in the second region, the fourth conductor is provided between the first insulator and the first semiconductor.

[0014] In the first region, the first insulator, the second insulator, the third insulator, the first semiconductor, and the second semiconductor are preferably arranged concentrically, and in the second region, the first insulator, the second insulator, the third insulator, the first semiconductor, the second semiconductor, and the fourth conductor are preferably arranged concentrically.

[0015] The first region can function as a first transistor. The second region can function as a second transistor. The first semiconductor is preferably an oxide semiconductor. The second semiconductor is preferably an oxide semiconductor.

[0016] Another aspect of the present invention is a memory device having a first conductor extending in a first direction, a second conductor extending in a second direction, a third conductor extending in the second direction, a fourth conductor, a first insulator, a second insulator, a third insulator, a first semiconductor, and a second semiconductor, wherein at a first intersection where the first conductor and the second conductor intersect and a second intersection where the first conductor and the third conductor intersect, the first insulator overlaps the first conductor, the first semiconductor overlaps the first insulator, the second insulator overlaps the first semiconductor, the second semiconductor overlaps the second insulator, and the third insulator overlaps the second semiconductor, and at the second intersection, the first semiconductor overlaps the first insulator via the fourth conductor.

[0017] At the first intersection, the first insulator, the second insulator, the third insulator, the first semiconductor, and the second semiconductor are preferably arranged concentrically.At the second intersection, the first insulator, the second insulator, the third insulator, the first semiconductor, the second semiconductor, and the fourth conductor are preferably arranged concentrically.

[0018] Additionally, the first intersection can function as a first transistor, and the second intersection can function as a second transistor. [Effects of the Invention]

[0019] According to one embodiment of the present invention, a highly reliable memory device can be provided. According to another embodiment of the present invention, a memory device with a large memory capacity can be provided. According to one embodiment of the present invention, a memory device with a small occupation area can be provided. According to one embodiment of the present invention, a memory device with low manufacturing costs can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with low manufacturing costs can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided.

[0020] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 is a perspective view of a storage device. [Figure 2] FIG. 2 is a cross-sectional view of the storage device. [Figure 3] FIG. 3 is a cross-sectional view of a memory string. [Figure 4] FIG. 4 is a cross-sectional view of a memory string. [Figure 5] 5A and 5B are cross-sectional views of a memory string. [Figure 6] 6A and 6B are cross-sectional views of a memory string. [Figure 7] 7A and 7B are cross-sectional and perspective views of a memory element. [Figure 8] 8A and 8B are cross-sectional views of a memory string. [Figure 9] 9A to 9F are cross-sectional views of memory strings. [Figure 10] 10A and 10B are cross-sectional views of a memory string. [Figure 11] Figure 11A is a diagram explaining the classification of IGZO crystal structures, Figure 11B is a diagram explaining the XRD spectrum of a CAAC-IGZO film, and Figure 11C is a diagram explaining the electron microbeam diffraction pattern of a CAAC-IGZO film. [Figure 12] 12A to 12C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 13] 13A to 13C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 14] 14A to 14C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 15] 15A to 15C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 16] 16A to 16C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 17] 17A to 17C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 18] 18A to 18C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 19] 19A to 19D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 20] 20A to 20C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 21] 21A to 21C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 22] 22A to 22C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 23] 23A to 23C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 24] 24A to 24C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 25] 25A to 25C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 26] 26A to 26C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 27] 27A to 27C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 28]28A to 28C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 29] FIG. 29 is a perspective view of a storage device. [Figure 30] FIG. 30 is a cross-sectional view of the storage device. [Figure 31] FIG. 31 is a cross-sectional view of a memory string. [Figure 32] 32A to 32C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 33] 33A to 33C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 34] 34A to 34C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 35] 35A to 35C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 36] 36A to 36C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 37] 37A to 37C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 38] 38A to 38C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 39] 39A to 39C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 40] 40A to 40C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 41] 41A to 41C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 42] 42A to 42C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 43]43A to 43D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 44] 44A to 44C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 45] 45A to 45C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 46] 46A to 46C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 47] 47A to 47C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 48] 48A to 48C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 49] 49A to 49C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 50] 50A to 50C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 51] FIG. 51 is a diagram illustrating an example of the configuration of an MOCVD apparatus. [Figure 52] Fig. 52A is a schematic diagram of a multi-chamber film forming apparatus, and Fig. 52B is a cross-sectional view of a film forming chamber. [Figure 53] FIG. 53 is a diagram illustrating an example of the circuit configuration of a memory string. [Figure 54] FIG. 54 is an equivalent circuit diagram of a memory element MC. [Figure 55] FIG. 55 is a diagram illustrating an example of the circuit configuration of a memory string. [Figure 56] FIG. 56 is a diagram illustrating an example of the circuit configuration of a memory string. [Figure 57] FIG. 57 is a diagram illustrating an example of the circuit configuration of a memory string. [Figure 58] FIG. 58 is a timing chart illustrating an example of a write operation of a memory string. [Figure 59] 59A and 59B are circuit diagrams illustrating an example of a write operation of a memory string. [Figure 60] 60A and 60B are circuit diagrams illustrating an example of a write operation of a memory string. [Figure 61] 61A and 61B are circuit diagrams illustrating an example of a write operation of a memory string. [Figure 62] 62A and 62B are circuit diagrams illustrating an example of a write operation of a memory string. [Figure 63] 63A and 63B are timing charts illustrating an example of a read operation of a memory string. [Figure 64] 64A and 64B are circuit diagrams illustrating an example of a read operation of a memory string. [Figure 65] 65A and 65B are circuit diagrams illustrating an example of a read operation of a memory string. [Figure 66] 66A and 66B are diagrams illustrating the Id-Vg characteristics of a transistor. [Figure 67] FIG. 67 is a diagram illustrating an example of the circuit configuration of a memory string. [Figure 68] FIG. 68 is a timing chart illustrating an example of a write operation of a memory string. [Figure 69] FIG. 69 is a timing chart illustrating an example of a read operation of a memory string. [Figure 70] FIG. 70 is a diagram illustrating an example of the circuit configuration of a memory string. [Figure 71] FIG. 71 is a diagram illustrating an example of the circuit configuration of a memory string. [Figure 72] FIG. 72 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 73] 73A to 73C are perspective views for explaining configuration examples of a semiconductor device. [Figure 74] FIG. 74 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 75] FIG. 75 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 76] Figure 76A is a schematic diagram of a semiconductor device, and Figure 76B is a perspective view of the semiconductor device. [Figure 77] 77A to 77E are diagrams for explaining an example of a storage device. [Figure 78] 78A to 78G are diagrams for explaining an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0022] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications in form and detail can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions will be denoted by the same reference numerals in different drawings, and repeated descriptions thereof will be omitted.

[0023] Furthermore, the position, size, range, etc. of each component shown in the drawings, etc. may not represent the actual position, size, range, etc. in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc. For example, in an actual manufacturing process, a resist mask, etc. may be unintentionally eroded by a process such as etching, but this may not be reflected in the drawings in order to facilitate understanding.

[0024] In addition, in the drawings and the like, the illustration of some components may be omitted in order to make the explanation easier to understand.

[0025] Furthermore, the terms "electrode" and "wiring" used in this specification and elsewhere do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0026] In this specification, a "terminal" in an electric circuit refers to a portion where a current is input or output, a voltage is input or output, or a signal is received or transmitted. Therefore, a part of a wiring or an electrode may function as a terminal.

[0027] In this specification, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below, and being in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not necessarily mean that electrode B is formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0028] In addition, the functions of the source and drain are interchangeable depending on operating conditions, such as when transistors of different polarities are used or when the direction of current changes during circuit operation, making it difficult to define which is the source and which is the drain. For this reason, the terms source and drain can be used interchangeably in this specification.

[0029] Furthermore, in this specification, "electrically connected" includes both direct connection and connection via "something that has some kind of electrical effect." Here, "something that has some kind of electrical effect" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. Therefore, even when the expression "electrically connected" is used, in an actual circuit, there may be no physical connection and only wiring may be extended.

[0030] Furthermore, in this specification and elsewhere, "parallel" refers to, for example, a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases in which the angle is -5° or more and 5° or less. Furthermore, "perpendicular" and "orthogonal" refer to, for example, a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases in which the angle is 85° or more and 95° or less.

[0031] In this specification and elsewhere, when referring to counting values ​​and measurement values, or to objects, methods, and events that can be converted into counting values ​​or measurement values, terms such as "identical," "same," "equal," or "uniform" are intended to include an error of plus or minus 20%, unless otherwise specified.

[0032] Furthermore, in this specification, the terms "adjacent" and "close to" do not necessarily mean that components are in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" does not require that insulating layer A and electrode B are in direct contact with each other, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0033] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be used interchangeably. In this specification and elsewhere, unless otherwise specified, voltage and potential can be used interchangeably.

[0034] It should be noted that even when written as "semiconductor," if the conductivity is sufficiently low, it will have the properties of an "insulator." Therefore, it is also possible to use "semiconductor" instead of "insulator." In this case, the boundary between "semiconductor" and "insulator" is vague, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "insulator" described in this specification may be read interchangeably.

[0035] Furthermore, even when written as "semiconductor," if the conductivity is sufficiently high, it will have the properties of a "conductor." Therefore, it is also possible to use "semiconductor" instead of "conductor." In this case, the boundary between "semiconductor" and "conductor" is vague, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "conductor" described in this specification may be read interchangeably.

[0036] Note that ordinal numbers such as "first" and "second" used in this specification are used to avoid confusion between components, and do not indicate any order or ranking, such as the order of processes or stacking. Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Furthermore, even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Furthermore, even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0037] In this specification and the like, the "on state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically short-circuited (also referred to as a "conductive state"). The "off state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically disconnected (also referred to as a "non-conductive state").

[0038] In this specification, the term "on-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is on, and the term "off-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is off.

[0039] In this specification, the high power supply potential VDD (hereinafter simply referred to as "VDD," "H potential," or "H") refers to a power supply potential that is higher than the low power supply potential VSS (hereinafter simply referred to as "VSS," "L potential," or "L"). VSS refers to a power supply potential that is lower than VDD. Ground potential (hereinafter simply referred to as "GND" or "GND potential") can also be used as VDD or VSS. For example, when VDD is the ground potential, VSS is a potential lower than the ground potential, and when VSS is the ground potential, VDD is a potential higher than the ground potential.

[0040] Unless otherwise specified, the transistors described in this specification and the like are enhancement-type (normally-off) n-channel field-effect transistors. Therefore, their threshold voltages (also referred to as "Vth") are assumed to be greater than 0 V. Unless otherwise specified, "supplying an H potential to the gate of a transistor" may be synonymous with "turning the transistor on." Unless otherwise specified, "supplying an L potential to the gate of a transistor" may be synonymous with "turning the transistor off."

[0041] In this specification and the like, a gate refers to a gate electrode and a part or all of a gate wiring, and a gate wiring refers to a wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.

[0042] In this specification, the term "source" refers to a source region, a source electrode, and part or all of a source wiring. The term "source region" refers to a region of a semiconductor layer whose resistivity is equal to or less than a certain value. The term "source electrode" refers to a conductive layer connected to the source region. The term "source wiring" refers to wiring that electrically connects the source electrode of at least one transistor to another electrode or wiring.

[0043] In this specification, the term "drain" refers to a part or all of the drain region, drain electrode, and drain wiring. The term "drain region" refers to a region of the semiconductor layer whose resistivity is equal to or less than a certain value. The term "drain electrode" refers to a conductive layer connected to the drain region. The term "drain wiring" refers to wiring that electrically connects the drain electrode of at least one transistor to another electrode or wiring.

[0044] In addition, in drawings and the like, to make it easier to understand the potential of a wiring, electrode, conductor, etc., an "H" indicating an H potential or an "L" indicating an L potential may be written next to the wiring, electrode, conductor, etc. Furthermore, a wiring, electrode, conductor, etc. in which a potential change has occurred may be written with "H" or "L" enclosed in letters. Furthermore, when a transistor is in an off state, an "x" symbol may be written over the transistor.

[0045] Generally, a "capacitance" has a configuration in which two electrodes face each other via an insulator (dielectric). In this specification, etc., the term "capacitance element" includes the above-mentioned "capacitance." That is, in this specification, etc., the term "capacitance element" includes a configuration in which two electrodes face each other via an insulator, a configuration in which two wires face each other via an insulator, or a configuration in which two wires are arranged via an insulator.

[0046] Furthermore, in this specification and the like, when the same reference numeral is used for multiple elements, and when it is particularly necessary to distinguish between them, the reference numeral may be accompanied by an identifying symbol such as "_1", "_2", "[n]", "[m,n]", etc. For example, the second wiring GL may be described as wiring GL[2].

[0047] (Embodiment 1) FIG. 1 shows a perspective view of a storage device 100 according to one embodiment of the present invention. The storage device 100 is a storage device having a three-dimensional stacked structure. FIG. 2 is a cross-sectional view of a portion A1-A2 indicated by a dashed line in FIG. 1. Note that in FIG. 1 and other figures, arrows indicating the X, Y, and Z directions may be added. The X, Y, and Z directions are mutually orthogonal. In this specification and other figures, one of the X, Y, and Z directions may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0048] Fig. 2 shows a cross section of the XZ plane. As mentioned above, some components may be omitted from Fig. 1 and Fig. 2 for ease of explanation.

[0049] <Storage device configuration example> A memory device 100 according to one embodiment of the present invention includes a memory cell array 110. The memory cell array 110 includes a plurality of memory strings 120. The memory strings 120 extend in the Z direction and are arranged in a matrix on the XY plane.

[0050] 3 shows an example cross-sectional structure of a memory string 120 according to one embodiment of the present invention. The memory string 120 has a configuration in which multiple storage elements MC (also referred to as "memory cells") are connected in series. Although this embodiment illustrates the case in which five storage elements MC are connected in series, the number of storage elements MC included in the memory string 120 is not limited to five. When the number of storage elements MC included in the memory string 120 is n, n may be an integer of 2 or greater.

[0051] The memory string 120 also has a plurality of conductors WWL, a plurality of conductors RWL, and a conductor SG. In the memory cell array 110, the conductors WWL, RWL, and conductor SG extend in the X direction. The plurality of conductors WWL and the plurality of conductors RWL are alternately stacked with insulators 123 interposed therebetween. The conductor SG is provided in a lower layer than the plurality of conductors WWL and the plurality of conductors RWL.

[0052] 3, the five storage elements MC are denoted as storage elements MC[1] to MC[5]. Note that when describing matters common to the storage elements MC[1] to MC[5], they are simply referred to as "storage element MC." The same applies to other components such as the conductor WWL, the conductor RWL, and the insulator 123.

[0053] The memory string 120 includes a transistor STr1 electrically connected to the storage element MC[1] and a transistor STr2 electrically connected to the storage element MC[5].

[0054] The conductors WWL, RWL, and SG have regions that extend beyond the memory cell array 110. Furthermore, the conductors WWL, RWL, and SG are stacked in a stepped manner outside the memory cell array 110 (see FIGS. 1 and 2).

[0055] Figure 5A shows a cross section of the region B1-B2 indicated by the dashed-dotted line in Figure 3, as seen from the Z direction. Figure 5B shows a cross section of the region C1-C2 indicated by the dashed-dotted line in Figure 3, as seen from the Z direction. Figure 7A shows an enlarged view of region 105 indicated by the two-dot-dash line in Figure 3. Figure 7A corresponds to a cross section of memory element MC.

[0056] The memory string 120 has a conductor 122 on a base 121. The base 121 may be made of, for example, an insulator. Also, on the conductor 122, there are insulator 123[1], conductor SG, insulator 123[2], conductor RWL[1], insulator 123[3], conductor WWL[1], insulator 123[4], conductor RWL[2], insulator 123[5], conductor WWL[2], insulator 123[6], conductor RWL[3], insulator 123[7], conductor WWL[3], insulator 123[8], conductor RWL[4], insulator 123[9], conductor WWL[4], insulator 123

[10] , conductor RWL[5], insulator 123

[11] , conductor WWL[5], and insulator 123

[12] (see Figure 3).

[0057] The memory string 120 also has openings 141 (see FIG. 4) formed by removing portions of the insulator 123[1], conductor SG, insulator 123[2], conductor RWL[1], insulator 123[3], conductor WWL[1], insulator 123[4], conductor RWL[2], insulator 123[5], conductor WWL[2], insulator 123[6], conductor RWL[3], insulator 123[7], conductor WWL[3], insulator 123[8], conductor RWL[4], insulator 123[9], conductor WWL[4], insulator 123

[10] , conductor RWL[5], insulator 123

[11] , conductor WWL[5], and insulator 123

[12] . FIG. 4 is the same cross-sectional view as FIG. 3. However, in order to make the cross-sectional shape of the opening 141 easier to recognize, components provided within the opening 141 are shown by dashed lines in FIG.

[0058] The opening 141 extends in the Z direction and reaches the conductor 122. In the opening 141, the diameter of a region 142 overlapping with the conductor RWL is larger than the diameter of a region 143 overlapping with the conductor WWL. Therefore, the side surface of the opening 141 has an uneven shape.

[0059] Further, an insulator 124, a semiconductor 125, an insulator 126, and a semiconductor 127 are provided along the side surface of the opening 141. The semiconductor 125 has a region that overlaps with the side surface of the opening 141 with the insulator 124 interposed therebetween. The insulator 126 has a region that overlaps with the side surface of the opening 141 with the semiconductor 125 and the insulator 124 interposed therebetween. The semiconductor 127 has a region that overlaps with the side surface of the opening 141 with the insulator 126, the semiconductor 125, and the insulator 124 interposed therebetween. Further, at the bottom of the opening 141, the semiconductor 125 has a region that is electrically connected to the conductor 122.

[0060] The memory string 120 also has a conductor 130 extending in the Z direction. The conductor 130 is provided at or near the center of the opening 141. An insulator 129 is provided in a region of the conductor 130 that overlaps with the opening 141. At the bottom of the opening 141, the conductor 130 has a region that overlaps with the conductor 122, with the insulator 129, semiconductor 127, insulator 126, and semiconductor 125 interposed therebetween. A conductor 128 is provided between the semiconductor 127 and the insulator 129 in a region that overlaps with the conductor RWL.

[0061] Between the conductor WWL and the conductor 130, an insulator 124, a semiconductor 125, an insulator 126, a semiconductor 127, and an insulator 129 are provided in this order from the conductor WWL side (see FIG. 5A). Between the conductor RWL and the conductor 130, an insulator 124, a semiconductor 125, an insulator 126, a semiconductor 127, a conductor 128, and an insulator 129 are provided in this order from the conductor RWL side (see FIG. 5B).

[0062] 5A and 5B show a cross section (XY cross section) of one memory string 120, while Figures 6A and 6B show an example in which multiple memory strings 120 are provided. The multiple memory strings 120 may be arranged side by side in the X-axis direction, or in the Y-axis direction, or may be arranged in a matrix.

[0063] The memory element MC has a transistor WTr and a transistor RTr (see FIG. 7A). The region where the conductor WWL and the conductor 130 overlap functions as the transistor WTr. In other words, the intersection of the conductor WWL and the conductor 130 functions as the transistor WTr. At the intersection of the conductor WWL and the conductor 130, the insulator 129 is adjacent to the conductor 130, and the semiconductor 127 is adjacent to the insulator 129. Furthermore, the insulator 126 is adjacent to the semiconductor 127, and the semiconductor 125 is adjacent to the insulator 126. Furthermore, the insulator 124 is adjacent to the semiconductor 125.

[0064] The conductor WWL functions as the gate electrode of the transistor WTr, and the conductor 130 functions as the backgate electrode of the transistor WTr. A part of the semiconductor 127 functions as a semiconductor layer in which the channel of the transistor WTr is formed. The semiconductor layer in which the channel of the transistor WTr is formed overlaps with the gate electrode (conductor WWL) via parts of the insulator 126, the semiconductor 125, and the insulator 124. Note that in the present embodiment and the like, an example is shown in which a part of the conductor WWL functions as the gate electrode, but the gate electrode and the conductor WWL may be provided independently and electrically connected to each other.

[0065] The region where the conductor RWL and the conductor 130 overlap functions as the transistor RTr. In other words, the intersection of the conductor RWL and the conductor 130 functions as the transistor RTr. Furthermore, a conductor 128 is provided at the intersection of the conductor RWL and the conductor 130. Similar to the intersection of the conductor WWL and the conductor 130, the intersection of the conductor RWL and the conductor 130 also has an overlapping region in a direction perpendicular to the Z direction among the insulator 129, the semiconductor 127, the insulator 126, the semiconductor 125, and the insulator 124. However, the intersection of the conductor RWL and the conductor 130 differs from the intersection of the conductor WWL and the conductor 130 in that the conductor 128 is provided between the insulator 129 and the semiconductor 127.

[0066] The conductor 128 functions as the gate electrode of the transistor RTr. The conductor RWL functions as the back gate electrode of the transistor RTr. A part of the semiconductor 125 functions as a semiconductor layer in which the channel of the transistor RTr is formed. The semiconductor layer in which the channel of the transistor RTr is formed overlaps with the gate electrode (conductor 128) via a part of the insulator 126. The semiconductor layer in which the channel of the transistor RTr is formed overlaps with the back gate electrode (conductor RWL) via a part of the insulator 124. Note that in the present embodiment and the like, an example is shown in which a part of the conductor RWL functions as the back gate electrode, but the back gate electrode and the conductor RWL may be provided independently and electrically connected to each other.

[0067] Moreover, dividing the memory string 120 along the Z-axis direction is preferable because it increases the number of memory cells provided in the opening 141. When dividing the memory string 120 along the Z-axis direction, the conductors WWL and RWL may also be divided.

[0068] FIG. 8A shows how the conductor WWL and the memory string 120 are divided by the insulator 153 provided along the XZ plane, and FIG. 8B shows how the conductor RWL and the memory string 120 are divided by the insulator 153 provided along the XZ plane. Note that FIG. 8A corresponds to a modified example of the cross section shown in FIG. 5A. FIG. 8B corresponds to a modified example of the cross section shown in FIG. 5B. In FIG. 8 and other figures, the symbols of the divided components are suffixed with "a" or "b."

[0069] As shown in FIG. 8A, the region where the conductor WWLa and the conductor 130a overlap functions as the transistor WTra. Specifically, the region where the conductor WWLa, the insulator 124a, the semiconductor 125a, the insulator 126a, the semiconductor 127a, the insulator 129a, and the conductor 130a overlap functions as the transistor WTra. The conductor WWLa functions as the gate electrode of the transistor WTra, and the conductor 130a functions as the backgate electrode of the transistor WTra. A portion of the semiconductor 127a functions as a semiconductor layer in which the channel of the transistor WTra is formed. The semiconductor layer in which the channel of the transistor WTra is formed overlaps with the gate electrode (conductor WWLa) via a portion of the insulator 124a, a portion of the semiconductor 125a, and a portion of the insulator 126a.

[0070] Furthermore, the region where the conductor WWLb and the conductor 130b overlap functions as the transistor WTrb. Specifically, the region where the conductor WWLb, the insulator 124b, the semiconductor 125b, the insulator 126b, the semiconductor 127b, the insulator 129b, and the conductor 130b overlap functions as the transistor WTrb. The conductor WWLb functions as the gate electrode of the transistor WTrb, and the conductor 130b functions as the backgate electrode of the transistor WTrb. Furthermore, a portion of the semiconductor 127b functions as a semiconductor layer in which the channel of the transistor WTrb is formed. The semiconductor layer in which the channel of the transistor WTrb is formed overlaps with the gate electrode (conductor WWLb) via a portion of the insulator 124b, a portion of the semiconductor 125b, and a portion of the insulator 126b.

[0071] As shown in FIG. 8B, the region where the conductor RWLa and the conductor 130a overlap functions as the transistor RTra. Specifically, RWLa, the insulator 124a, the semiconductor 125a, the insulator 126a, the semiconductor 127a, the conductor 128a, the insulator 129a, and the conductor 130a function as the transistor RTra. The conductor RWLa functions as the gate electrode of the transistor RTra. The conductor 130a functions as the back gate electrode of the transistor RTra. A portion of the semiconductor 125a functions as a semiconductor layer in which the channel of the transistor RTra is formed. The semiconductor layer in which the channel of the transistor RTra is formed overlaps with the gate electrode (conductor RWLa) via the insulator 124a. The semiconductor layer in which the channel of the transistor RTra is formed overlaps with the back gate electrode (conductor 130a) via a portion of the insulator 126a, a portion of the semiconductor 127a, a portion of the conductor 128a, and a portion of the insulator 129a.

[0072] Furthermore, the region where the conductor RWLb and the conductor 130b overlap functions as the transistor RTrb. Specifically, RWLb, the insulator 124b, the semiconductor 125b, the insulator 126b, the semiconductor 127b, the conductor 128b, the insulator 129b, and the conductor 130b function as the transistor RTrb. The conductor RWLb functions as the gate electrode of the transistor RTrb. The conductor 130b functions as the back gate electrode of the transistor RTrb. A portion of the semiconductor 125b functions as a semiconductor layer in which the channel of the transistor RTrb is formed. The semiconductor layer in which the channel of the transistor RTrb is formed overlaps with the gate electrode (conductor RWLb) via the insulator 124b. The semiconductor layer in which the channel of the transistor RTrb is formed overlaps with the back gate electrode (conductor 130b) via a portion of the insulator 126b, a portion of the semiconductor 127b, a portion of the conductor 128b, and a portion of the insulator 129b.

[0073] As described above, by dividing the conductors WWL, RWL, and memory strings 120, the number of memory cells provided in the opening 141 can be doubled. The method of dividing the memory strings 120 is not limited to the above. In FIGS. 8A and 8B, the memory strings 120 are divided by insulators 153 extending in the X-axis direction. However, as shown in FIGS. 9A and 9B, the insulators 153 may extend in a direction different from the X-axis direction. Furthermore, as shown in FIGS. 9C to 9F, the memory strings 120 may be divided into three or more parts. FIGS. 9C and 9D show an example of a memory string 120 divided into three parts, and FIGS. 9E and 9F show an example of a memory string 120 divided into four parts. In this case, the number of memory cells provided in the opening 141 can be tripled and quadrupled, respectively.

[0074] 9A to 9F, the insulator 153 is preferably arranged so as not to interfere with the conduction of the conductors WWL and RWL in the X-axis direction.

[0075] Here, we will explain the back gate. The gate and back gate are arranged so that they overlap with each other via the channel formation region of the semiconductor layer. The back gate can function in the same way as the gate. In addition, by changing the potential of the back gate, the threshold voltage of the transistor can be changed. Either the gate or the back gate may be called the "first gate" or "first gate," and the other may be called the "second gate" or "second gate."

[0076] The gate and back gate are formed from conductive layers or semiconductor layers with low resistivity, and therefore have the function of preventing external electric fields from acting on the semiconductor layer where the channel is formed (particularly, electrostatic shielding against static electricity). In other words, it is possible to prevent fluctuations in the electrical characteristics of the transistor due to the influence of external electric fields such as static electricity.

[0077] The threshold voltage of the transistor can be controlled by controlling the potential of the back gate, which may be the same potential as the gate, a ground potential (GND potential), or any other potential.

[0078] The semiconductor layers in which the channels of the transistors WTr and RTr are formed can be made of single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, amorphous semiconductors, or the like, either singly or in combination. Examples of semiconductor materials that can be used include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors can also be used. The same applies to the transistors STr1 and STr2.

[0079] Note that the semiconductor layers used in the transistor may be stacked. When the semiconductor layers are stacked, semiconductors having different crystal states or different semiconductor materials may be used for the respective layers.

[0080] The semiconductor layers used in the transistors WTr, RTr, STr1, and STr2 are preferably oxide semiconductors containing metal oxide. Transistors using metal oxide in their semiconductor layers have higher field-effect mobility than transistors using amorphous silicon in their semiconductor layers. Furthermore, transistors using polycrystalline silicon in their semiconductor layers may have grain boundaries in their semiconductor layers. Carriers are likely to be captured at the grain boundaries, resulting in a decrease in the on-state current and field-effect mobility of the transistor. On the other hand, as will be described in detail later, oxide semiconductors can achieve a crystal structure with no clear grain boundaries or with very few grain boundaries. Using such oxide semiconductors in the semiconductor layers is advantageous because it enables the realization of transistors with favorable electrical characteristics, such as high on-state current and field-effect mobility.

[0081] Furthermore, oxide semiconductors, particularly the crystalline oxide semiconductor CAAC-IGZO, have a characteristic structure in which nanoclusters of a few nanometers (e.g., 1 to 3 nm) are connected together, with their c-axes oriented perpendicular to the surface on which they are formed. This makes it possible to form a crystalline structure in which no clear grain boundaries are visible, even within openings extending in the Z direction.

[0082] In particular, the transistor WTr is preferably a transistor (also referred to as an "OS transistor") that uses an oxide semiconductor, which is a type of metal oxide, in a semiconductor layer in which a channel is formed. An oxide semiconductor has a band gap of 2 eV or more, and therefore has a significantly low off-state current. When an OS transistor is used as the transistor WTr, charge written to the node ND can be held for a long period of time. When an OS transistor is used as a transistor constituting the memory element MC, the memory element MC can be called an "OS memory." The memory string 120 including the memory element MC can also be called an "OS memory." The memory device 100 can also be called an "OS memory."

[0083] OS memory can retain written information for more than one year, or even more than ten years, even if the power supply is cut off, so OS memory can also be considered non-volatile memory.

[0084] Furthermore, since the amount of charge written into the OS memory is unlikely to change over a long period of time, the OS memory can hold not only binary (1-bit) information but also multi-value (multi-bit) information.

[0085] Furthermore, because OS memory writes charge to nodes via transistors, it does not require the high voltages required by conventional flash memory, enabling high-speed write operations. Furthermore, OS memory does not require the erase operation required by flash memory before rewriting data. Furthermore, because no charge is injected or extracted from the floating gate or charge trapping layer, OS memory allows for virtually unlimited data write and read operations. OS memory is less susceptible to degradation than conventional flash memory, making it highly reliable.

[0086] In addition, OS memory does not involve atomic-level structural changes like magnetoresistive random access memory (MRAM) or resistive random access memory (ReRAM), and therefore has better rewrite endurance than magnetoresistive random access memory and resistive random access memory.

[0087] Furthermore, the off-state current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an ambient temperature range of room temperature to 200°C. Furthermore, the on-state current is unlikely to decrease even in a high-temperature environment. A storage device including an OS memory operates stably and has high reliability even in a high-temperature environment. Furthermore, an OS transistor has a high withstand voltage between the source and drain. By using an OS transistor as a transistor constituting a semiconductor device, a semiconductor device that operates stably and has high reliability even in a high-temperature environment can be realized.

[0088] The semiconductor 125 is preferably an n-type semiconductor. Also, the region of the semiconductor 127 that overlaps with the conductor WWL is preferably an i-type or substantially i-type semiconductor. In this case, the transistor WTr is an enhancement type (normally off type) transistor, and the transistor RTr is a depletion type (normally on type) transistor.

[0089] Note that the semiconductor 125 and the semiconductor 127 may be made of the same material or different materials. For example, the semiconductor 125 and the semiconductor 127 may each be an oxide semiconductor. Alternatively, the semiconductor 125 and the semiconductor 127 may each be a semiconductor containing silicon. Alternatively, the semiconductor 125 may be an oxide semiconductor, and the semiconductor 127 may be a semiconductor containing silicon. Alternatively, the semiconductor 125 may be a semiconductor containing silicon, and the semiconductor 127 may be an oxide semiconductor.

[0090] 7B shows a perspective cross-sectional view of the memory element MC. Note that, in order to make the structure of the memory element MC easier to understand, the insulator 123 is omitted in FIG.

[0091] 5A corresponds to the XY plane at or near the center of the transistor WTr, and FIG. 5B corresponds to the XY plane at or near the center of the transistor RTr. In FIG. 5A and FIG. 5B, when the cross-sectional shape of the conductor 130 is circular, the insulator 129 is provided concentrically outside the conductor 130, the semiconductor 127 is provided concentrically outside the insulator 129, the insulator 126 is provided concentrically outside the semiconductor 127, the semiconductor 125 is provided concentrically outside the insulator 126, and the insulator 124 is provided concentrically outside the semiconductor 125. The conductor 128 is provided concentrically between the insulator 129 and the semiconductor 127.

[0092] Furthermore, the cross-sectional shape of the conductor 130 is not limited to a circle. As shown in Fig. 10A, the cross-sectional shape of the conductor 130 may be rectangular. As shown in Fig. 10B, the cross-sectional shape of the conductor 130 may be triangular. Note that Figs. 10A and 10B correspond to cross sections of the portion B1-B2 indicated by the dashed dotted line in Fig. 3 as viewed from the Z direction.

[0093] The memory string 120 can also be called a storage device, and the storage element MC can also be called a storage device.

[0094] [Constituent materials of semiconductor device] Next, constituent materials that can be used for the storage device 100 will be described.

[0095] [substrate] The memory device 100 can be provided on a substrate. Examples of the substrate include an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria-stabilized zirconia substrate), and a resin substrate. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride or a metal oxide. Examples of other substrates include a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, or the like.

[0096] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0097] In this specification and the like, the term "oxynitride" refers to a material that contains more oxygen than nitrogen. For example, "silicon oxynitride" refers to a silicon material that contains more oxygen than nitrogen. In this specification and the like, the term "nitride oxide" refers to a material that contains more nitrogen than oxygen, and the term "aluminum nitride oxide" refers to an aluminum material that contains more nitrogen than oxygen.

[0098] For example, as transistors become more miniaturized and highly integrated, thinner gate insulators can cause problems such as leakage current. Using a high-k material for the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the interlayer insulator can reduce the parasitic capacitance between wiring. Therefore, it is best to select materials based on the insulator's function.

[0099] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0100] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, or resin.

[0101] Furthermore, the electrical characteristics of an OS transistor can be stabilized by surrounding it with an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0102] When an oxide semiconductor is used for the semiconductor 125 and / or the semiconductor 127, the insulator functioning as a gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the semiconductor 125 and / or the semiconductor 127, oxygen vacancies in the semiconductor 125 and / or the semiconductor 127 can be compensated for.

[0103] [conductor] The conductor is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0104] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0105] When an oxide semiconductor, which is a type of metal oxide, is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0106] In particular, a conductive material containing oxygen and a metal element contained in the oxide semiconductor in which a channel is formed is preferably used as a conductor functioning as a gate electrode. Alternatively, a conductive material containing the above-described metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon is added may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the oxide semiconductor in which a channel is formed may be captured. Alternatively, hydrogen introduced from an external insulator may be captured.

[0107] [Oxide semiconductor] A metal oxide (oxide semiconductor) that functions as a semiconductor is preferably used as the semiconductor 125 and the semiconductor 127. Oxide semiconductors that can be used for the semiconductor 125 and the semiconductor 127 will be described below.

[0108] The oxide semiconductor preferably contains at least one of indium and zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0109] Here, we consider a case where the oxide semiconductor is an In-M-Zn oxide containing indium, an element M, and zinc. The element M is one or more selected from aluminum, gallium, yttrium, and tin. Other elements that can be used as the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, a combination of two or more of the above elements may be used as the element M.

[0110] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0111] [Classification of crystal structures] First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 11A. Fig. 11A is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0112] As shown in FIG. 11A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). The "Crystalline" classification excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0113] The structure within the bold frame in Figure 11A is an intermediate state between "amorphous" and "crystal," and is a structure that belongs to a new boundary region (new crystalline phase). In other words, this structure can be said to be completely different from the energetically unstable "amorphous" and "crystal."

[0114] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 11B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 11B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 11B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 11B is 500 nm.

[0115] As shown in Figure 11B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. As shown in Figure 11B, the peak near 2θ = 31° is asymmetrical with respect to the angle at which the peak intensity is detected.

[0116] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 11C. Figure 11C shows a diffraction pattern observed by NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 11C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0117] As shown in Figure 11C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0118] [Oxide semiconductor structure] Note that oxide semiconductors may be classified differently from those shown in FIG. 11A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0119] Next, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be explained in detail.

[0120] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0121] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0122] In the In-M-Zn oxide, the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain the element M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0123] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0124] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0125] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0126] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0127] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by impurities or defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0128] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD system, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0129] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0130] [Oxide semiconductor composition] Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0131] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0132] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0133] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0134] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0135] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0136] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0137] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0138] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0139] [Transistor Having an Oxide Semiconductor] Next, a case where the oxide semiconductor is used in a transistor will be described.

[0140] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0141] An oxide semiconductor with a low carrier concentration is preferably used for a channel formation region of a transistor. For example, the carrier concentration of the channel formation region of an oxide semiconductor is preferably 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm-3 It is more preferable that the carrier concentration of the oxide semiconductor film is less than 1000 . Note that in order to reduce the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. In addition, being highly purified intrinsic or substantially highly purified intrinsic may be referred to as an i-type or substantially i-type.

[0142] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0143] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0144] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0145] 〔impurities〕 Here, the influence of each impurity in an oxide semiconductor will be described.

[0146] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the channel formation region of the oxide semiconductor and the silicon and carbon near the interface with the channel formation region of the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0147] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect states may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0148] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of an oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm3 Do the following:

[0149] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration measured by SIMS in the channel formation region of the oxide semiconductor is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0150] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0151] [Other semiconductor materials] The semiconductor material that can be used for the semiconductor 125 and the semiconductor 127 is not limited to the oxide semiconductors described above. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the semiconductor 125 and the semiconductor 127. For example, a semiconductor of an element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material that functions as a semiconductor (also referred to as an atomic layer material, a two-dimensional material, or the like) may also be used as the semiconductor material. In particular, it is preferable to use a layered material that functions as a semiconductor as the semiconductor material.

[0152] In this specification, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0153] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements in Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides.

[0154] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as semiconductor 125 and semiconductor 127. Specific examples of transition metal chalcogenides that can be used as semiconductor 125 and semiconductor 127 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0155] <Example of how to make a memory device> Next, an example of a method for fabricating a memory device according to the present invention will be described with reference to FIGS. 12A to 28C. In each of FIGS. 12A to 28C, A is a top view seen from the Z direction, and B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in A. In each of FIGS. 12A to 28C, C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in A. FIG. 19D is an enlarged cross-sectional view of the portion surrounded by the dashed-dotted line in FIG. 19B. While this fabrication method illustrates one memory string 120 having two (also referred to as "two stages") memory elements MC, this embodiment is not limited to this. The memory string 120 may have three or more stages of memory elements MC. For example, the memory string 120 preferably has 32 or more stages, preferably 64 or more stages, more preferably 128 or more stages, and even more preferably 256 or more stages of memory elements MC.

[0156] First, a conductor 122 is formed on a substrate 121 having an insulating surface, and an insulator 132 is formed around the conductor 122 (see FIGS. 12A to 12C).

[0157] First, a conductive film is formed and then processed using lithography to form the conductor 122. Next, an insulating film is formed on the substrate 121 so as to cover the conductor 122. Next, a planarization treatment is preferably performed on the insulating film. In the planarization treatment, the insulating film is preferably polished until the surface of the conductor 122 is exposed. The insulator 132 can be formed by the above method, but the method for forming the conductor 122 and the insulator 132 is not limited to this. The insulator 132 may be formed on the substrate 121, and unnecessary portions of the insulator 132 may be removed to form grooves or openings, and the conductor 122 may be embedded in the grooves or openings. This method for forming a conductor is sometimes called a damascene method (single damascene method, dual damascene method). The above method can obtain the structure of the conductor 122 and the insulator 132 shown in Figures 12A to 12C.

[0158] The conductor 122 and the insulator 132 can be formed by sputtering, CVD, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), ALD, or the like.

[0159] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (Photo-CVD), which uses light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD), depending on the source gas used.

[0160] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can minimize plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, because the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0161] The ALD method is also a film formation method that can reduce plasma damage to the workpiece, and because no plasma damage occurs during film formation, the ALD method also produces films with fewer defects.

[0162] Unlike film formation methods in which particles emitted from a target or the like are deposited, CVD and ALD are film formation methods in which a film is formed by a reaction on the surface of the workpiece. Therefore, these film formation methods are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of openings with high aspect ratios. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which has a faster film formation rate.

[0163] The CVD method and the ALD method can control the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, the CVD method and the ALD method can form a film of any composition by adjusting the flow rate ratio of the source gases. Furthermore, for example, the CVD method and the ALD method can form a film with a continuously changing composition by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened by the time required for transportation and pressure adjustment compared to when forming a film using multiple film formation chambers. Therefore, the productivity of semiconductor devices can sometimes be improved.

[0164] In the lithography method, first, a resist is exposed through a photomask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, a conductor, semiconductor, insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. Alternatively, an electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, a photomask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0165] Alternatively, a hard mask made of an insulator or a conductor may be used instead of the resist mask. In the case of using a hard mask, an insulating film or a conductive film that serves as a hard mask material is formed on a conductive film, a resist mask is formed thereon, and the hard mask material is etched, whereby a hard mask having a desired shape can be formed.

[0166] This processing can be performed by dry etching or wet etching, and dry etching is suitable for fine processing.

[0167] The dry etching apparatus may be a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power supply to one of the parallel plate electrodes. Alternatively, it may be configured to apply multiple different high frequency power supplies to one of the parallel plate electrodes. Alternatively, it may be configured to apply a high frequency power supply of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply a high frequency power supply of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high density plasma source may be used. For example, an inductively coupled plasma (ICP) etching apparatus may be used as the dry etching apparatus having a high density plasma source.

[0168] When a hard mask is used for etching a conductive film, the etching process may be performed after removing the resist mask used for forming the hard mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the conductive film. On the other hand, if the material of the hard mask does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0169] The conductive film to be the conductor 122 is preferably formed by a sputtering method using a conductive film containing a metal element. Alternatively, the conductive film can also be formed by a CVD method.

[0170] If necessary, the surface of the insulator 132 is preferably subjected to planarization treatment, which can be performed by chemical mechanical polishing (CMP) or reflow.

[0171] An insulating film 123A, a conductive film 134A, and a conductive film 136A are alternately stacked over the conductor 122 and the insulator 132. In this embodiment, an example is shown in which the insulating film 123A is formed over the insulator 132, the conductive film 134A is formed over the insulating film 123A, the insulating film 123A is formed over the conductive film 134A, and the conductive film 136A is formed over the insulating film 123A (see FIGS. 12A to 12C). The conductive film 134A, the conductive film 136A, and the insulating film 123A can be formed by a CVD method. Alternatively, a sputtering method may be used.

[0172] The conductor 122, the conductive film 134A, and the conductive film 136A can be made of a conductive material such as silicon doped with impurities or a metal. The conductive film 136A is preferably made of a different material from the conductor 122 and the conductive film 134A because selective etching must be performed on the conductor 122 and the conductive film 134A in a later step. The conductor 122 and the conductive film 134A may be made of the same material or different materials. When silicon is used for the conductor 122, the conductive film 134A, or the conductive film 136A, amorphous silicon or polysilicon can be used. To provide conductivity to silicon, p-type impurities or n-type impurities may be added. As a conductive material containing silicon, silicide containing titanium, cobalt, or nickel can be used for the conductor 122, the conductive film 134A, or the conductive film 136A. Furthermore, when a metal material is used for the conductor 122, the conductive film 134A, or the conductive film 136A, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. can be used.

[0173] For the insulator 132 and the insulating film 123A, an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, metal nitride oxide, or the like can be used. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide or resin having pores, aluminum oxide, gallium oxide, hafnium oxide, zirconium oxide, oxide containing aluminum and hafnium, oxynitride containing aluminum and hafnium, oxide containing silicon and hafnium, oxynitride containing silicon and hafnium, nitride containing silicon and hafnium, or the like can be used.

[0174] Although the present embodiment has shown an example in which six insulating films 123A, three conductive films 134A, and two conductive films 136A are formed, the number of stacked layers is not limited to this. Each of these layers can be formed depending on the desired performance of the semiconductor device. If the number of stacked conductive films 134A is m (m is an integer of 2 or more), the number of stacked insulating films 123A is 2×m, and the number of stacked conductive films 136A is m−1. For example, m can be 33 or more, preferably 65 or more, more preferably 129 or more, and even more preferably 257 or more.

[0175] Next, a mask (not shown) is formed on the insulating film 123A, and the insulating film 123A, the conductive film 134A, and the conductive film 136A are processed using lithography to form a first opening to expose the conductor 122 (see Figures 13A to 13C).

[0176] Next, isotropic etching is performed on the conductive film 136A to recess the side surfaces of the conductive film 136A in the first opening from the side surfaces of the insulating film 123A and the conductive film 134A (see FIGS. 14A to 14C). This process makes the diameter of the first opening overlapping the conductive film 136A larger than the diameters of the first opening overlapping the insulating film 123A and the conductive film 134A. Therefore, unevenness is formed on the side surfaces of the first opening. For this process, isotropic etching by dry etching using gas, radicals, plasma, or the like, or isotropic etching by wet etching using a liquid can be used. The liquid used in wet etching is sometimes called an etchant. When isotropic etching is performed using dry etching, gas, radicals, plasma, or the like containing at least one of chlorine, bromine, and fluorine can be used. It is preferable to perform isotropic etching without removing the mask used to form the first opening. The first opening obtained by the above process corresponds to the opening 141 shown in FIG. 4.

[0177] Next, an insulating film 124A is formed on the insulating film 123A and inside the first opening (see FIGS. 15A to 15C). Although the insulating film 124A has a single-layer structure in FIGS. 15B and 15C, it may have a multilayer structure. The insulating film 124A can be formed using a CVD method or an ALD method. In particular, the ALD method is preferable because it allows a film of uniform thickness to be formed even in grooves or openings with a high aspect ratio. Alternatively, the insulating film 124A may be formed by combining an ALD method and a CVD method. When the insulating film 124A has a multilayer structure, each insulating film may be formed using the same film formation apparatus or different film formation apparatuses.

[0178] The insulating film 124A formed by the above method has good coverage and can be formed even on the uneven shape of the side surface of the first opening. That is, the insulating film 124A can be formed so as to contact not only the side surfaces of the insulating film 123A, the conductive film 134A, and the conductive film 136A, but also part of the upper surface and part of the lower surface of the insulating film 123A.

[0179] Next, the insulating film 124A formed on the bottom of the first opening is removed to obtain the insulator 124. Anisotropic etching is preferably used to remove the insulating film 124A. At this time, the insulating film 124A on the insulating film 123A is also removed, so that the insulator 124 is provided only on the sidewall of the first opening (see FIGS. 16A to 16C). By removing the insulating film 124A on the bottom of the first opening, the conductor 122 is exposed again.

[0180] Next, a semiconductor film 125A, an insulating film 126A, and a semiconductor film 127A are formed inside the first opening (see FIGS. 17A to 17C).

[0181] The semiconductor film 125A, insulating film 126A, and semiconductor film 127A can be formed using a CVD method or an ALD method. The ALD method is particularly preferable because it allows for the formation of films with uniform thickness even in grooves and openings with a large aspect ratio. Alternatively, the semiconductor film 125A, insulating film 126A, and semiconductor film 127A may be formed by combining an ALD method and a CVD method. Different film formation methods and film formation apparatuses may also be used for each film to be formed. For example, the semiconductor film 125A and semiconductor film 127A are preferably formed by an MOCVD method.

[0182] Next, a conductive film 128A is formed inside the first opening (see FIGS. 17A to 17C). The conductive film 128A need only be formed so as to fill the recesses of the conductive film 136A via at least the insulator 124, the semiconductor film 125A, the insulating film 126A, and the semiconductor film 127A, and does not necessarily have to fill the entire inside of the first opening. The conductive film 128A can be formed using a CVD method or an ALD method. In particular, the ALD method is preferable because it allows a film of uniform thickness to be formed even in grooves or openings with a high aspect ratio. Alternatively, the conductive film 128A may be formed by combining the ALD method and the CVD method.

[0183] The semiconductor film 125A and the semiconductor film 127A are preferably oxide semiconductors having a CAAC structure. When the semiconductor film 125A and the semiconductor film 127A are oxide semiconductors having a CAAC structure, the c-axis of the semiconductor film 125A is aligned in the normal direction to the formation surface inside the first opening. In this case, the c-axes of the semiconductor film 125A and the semiconductor film 127A located on the side surfaces of the insulating film 123A, the conductive film 134A, and the conductive film 136A, via the insulator 124, are aligned from the formation surface toward the axis 182 shown in FIGS. 17A to 17C . The axis 182 can be referred to as the central axis of the first opening. As a result, the c-axes of the semiconductors 125 and 127 located above are aligned from the formation surface toward the axis 182.

[0184] Next, the conductive film 128A is processed to form the conductor 128 (see FIGS. 18A to 18C). The conductive film 128A can be processed by isotropic etching or anisotropic etching. When forming the conductive film 128A, if the conductive film 128A fills the recess and does not completely fill the first opening, as shown in FIGS. 17A to 17C, it is preferable to use isotropic etching to process the conductive film 128A. On the other hand, if the conductive film 128A is formed so as to fill the recess and the first opening, it is preferable to use anisotropic etching. By the above processing, the conductor 128 can be formed inside the recess.

[0185] Next, an insulating film 129A is formed inside the semiconductor film 127A and the conductor 128. Subsequently, using the conductor 128 as a mask, a part of the semiconductor film 127A is made highly resistive to form a high-resistance region (I-type region). The high-resistance region can be formed by irradiating the semiconductor film 127A with microwaves 144 through the insulating film 129A to remove hydrogen contained in the semiconductor film 127A. Furthermore, it is preferable to irradiate the semiconductor film 127A with microwaves 144 in an oxygen-containing atmosphere, since oxygen is supplied to the semiconductor film 127A. In this embodiment, a part of the semiconductor film 127A is irradiated with microwaves 144 through the insulating film 129A in an atmosphere containing oxygen and argon to make a region 146 of the semiconductor film 127A highly resistive (see FIGS. 19A to 19D).

[0186] Here, heat treatment may be performed. The heat treatment is preferably performed in a nitrogen-containing atmosphere at a temperature of 200°C to 500°C, preferably 300°C to 400°C. The atmosphere in which the heat treatment is performed is not limited to the above, and the heat treatment may be performed in an atmosphere containing at least one of nitrogen, oxygen, and argon. The heat treatment may be performed in a reduced pressure atmosphere or an atmospheric pressure atmosphere.

[0187] Heat treatment reduces the resistance of the semiconductor film 127A in contact with the conductor 128, thereby forming a low-resistance region (n-type region) in the region 148. By performing heat treatment while the semiconductor film 127A and the conductor 128 are in contact with each other, a metal compound layer containing a metal element contained in the conductor 128 and a component of the semiconductor film 127A may be formed at the interface between the conductor 128 and the semiconductor film 127A. Forming the metal compound layer is preferable because it reduces the resistance of the semiconductor film 127A in the region in contact with the conductor 128. Furthermore, the conductor 128 may absorb oxygen contained in the semiconductor film 127A. By performing heat treatment while the semiconductor film 127A and the conductor 128 are in contact with each other, the resistance of the semiconductor film 127A can be further reduced. The heat treatment may be performed before the microwave treatment. The region 148 whose resistance has been reduced by the heat treatment is covered with the conductor 128, and therefore is not affected by the microwave 144, and can maintain a low resistance value even after the microwave treatment.

[0188] The carrier concentration of the region 146 after the microwave treatment and heat treatment is 1×10 18 / cm 3 Less than 1 x 10, preferably 17 / cm 3 or less, more preferably 1×10 16 / cm 3 The carrier concentration of the region 148 is preferably 1×10 18 / cm 3 More than 1×10 19 / cm 3 More preferably, 1×10 20 / cm 3 It is preferable that this is equal to or greater than this.

[0189] Next, the conductive film 130A is formed (see FIGS. 20A to 20C). The conductive film 130A can be formed using a CVD method or an ALD method. In particular, the ALD method is preferable because it allows a film of uniform thickness to be formed even in grooves or openings with a large aspect ratio. Alternatively, the conductive film 130A may be formed by combining the ALD method and the CVD method.

[0190] Next, heat treatment is performed. The heat treatment is preferably performed in a nitrogen-containing atmosphere at a temperature of 200°C to 500°C, preferably 300°C to 400°C. The atmosphere in which the heat treatment is performed is not limited to the above, and the heat treatment may be performed in an atmosphere containing at least one of nitrogen, oxygen, and argon. The heat treatment may be performed in a reduced pressure atmosphere or an atmospheric pressure atmosphere.

[0191] Next, the conductive film 130A is removed by CMP or the like until the surface of the insulating film 129A is exposed, thereby obtaining the conductor 130 (see FIGS. 21A to 21C). Note that the heat treatment described above may be performed after the conductor 130 is formed.

[0192] Next, the semiconductor film 125A, the insulating film 126A, the semiconductor film 127A, and the insulating film 129A are processed to obtain the semiconductor 125, the insulator 126, the oxide film 127B, and the insulating film 129B (see FIGS. 22A to 22C). This processing can be performed by dry etching or wet etching.

[0193] Next, the insulating film 123A, the conductive film 134A, and the conductive film 136A are processed to form the stepped insulator 123B, the conductor 134B, and the conductor 136B as shown in FIG. 23B (see FIGS. 23A to 23C). In processing the insulating film 123A, the conductive film 134A, and the conductive film 136A, etching of the insulating film 123A, the conductive film 134A, and the conductive film 136A and slimming of a mask are alternately performed, thereby forming the stepped insulator 123B, the conductor 134B, and the conductor 136B.

[0194] Next, the insulator 150 is formed (see FIGS. 23A to 23C). The insulator 150 can be formed using a CVD method. The insulator 150 is preferably subjected to a planarization process using a CMP method or a reflow method.

[0195] Next, the insulator 150, the insulator 123B, the conductor 134B, and the conductor 136B are processed to obtain the insulator 123, the conductor 134, and the conductor 136 (see FIGS. 24A to 24C).

[0196] Next, an insulator 152 is formed so as to fill the portion removed by the above processing (see FIGS. 24A to 24C). The insulator 152 can be formed using a CVD method or an ALD method. In particular, the ALD method is preferable because it allows a film of uniform thickness to be formed even in grooves or openings with a large aspect ratio. Alternatively, the insulator 152 may be formed by combining the ALD method and the CVD method. The insulator 152 is preferably planarized using a CMP method or a reflow method.

[0197] Next, the oxide film 127B and the insulating film 129B are processed using lithography to obtain the semiconductor 127 and the insulator 129 (see FIGS. 25A to 25C). This processing can be performed by dry etching or wet etching.

[0198] Next, the conductor 154 is formed so as to overlap with part of the semiconductor 125 with the insulator 126 interposed therebetween (see FIGS. 26A to 26C). The conductor 154 is obtained by forming a conductive film over the insulators 126, 150, and 152, and processing the conductive film using lithography. Note that in FIG. 26A, the conductor 154 does not exist on the dashed dotted line A1-A2, but in FIG. 26B, the conductor 154 is illustrated by the dashed dotted line.

[0199] Next, the insulator 156 is formed to cover the conductor 154, the insulator 126, the insulator 150, and the insulator 152 (see FIGS. 27A to 27C). The insulator 156 can be formed by a CVD method, an ALD method, a sputtering method, or the like.

[0200] Next, insulator 156, insulator 126, insulator 129, semiconductor 127, and insulator 150 are processed using lithography to form second openings so as to expose conductor 134, conductor 136, conductor 130, conductor 154, and semiconductor 125. Second openings are formed for conductor 134 and conductor 136, which are formed in a stepped shape (see FIGS. 27A to 27C).

[0201] Next, conductor 161 electrically connected to conductor 134, conductor 162 electrically connected to conductor 136, conductor 163 electrically connected to conductor 130, conductor 164 electrically connected to conductor 154, conductor 165 electrically connected to semiconductor 125, and conductor 166 electrically connected to semiconductor 125 and semiconductor 127 are formed so as to fill the second opening (see FIGS. 28A to 28C). Conductors 161, 162, 163, conductor 164, conductor 165, and conductor 166 can be formed using a CVD method or an ALD method. ALD is particularly preferable because it allows for the formation of a film with a uniform thickness even in grooves and openings with a large aspect ratio. Alternatively, the conductors may be formed by combining ALD and CVD. Furthermore, the conductors 161, 162, 163, 164, 165, and 166 may have a layered structure made up of multiple layers. The conductors 161, 162, 163, 164, 165, and 166 can be formed by forming a conductive film on the insulator 156 and inside the second opening, and then removing unnecessary conductive film using CMP or the like.

[0202] Next, a conductor 171 electrically connected to the conductor 161, a conductor 172 electrically connected to the conductor 162, a conductor 173 electrically connected to the conductor 163, a conductor 174 electrically connected to the conductor 164, and a conductor 175 electrically connected to the conductor 165 are formed (see FIGS. 28A to 28C). The conductors 171, 172, 173, 174, and 175 can be formed by forming a conductive film on the insulator 156 and processing it using a lithography method. Dry etching or wet etching can be used for this processing.

[0203] Conductor 171, conductor 161, and conductor 134 function as conductor SG or conductor WWL. Conductor 172, conductor 162, and conductor 136 function as conductor RWL. Conductor 173, conductor 163, and conductor 130 function as conductor BG. Conductor 174, conductor 164, and conductor 154 function as conductor SEL. Conductor 175 and conductor 165 function as BL. A memory device can be manufactured by the above process.

[0204] (Embodiment 2) In this embodiment, a memory device 100A that is a modified example of the memory device 100 shown in embodiment 1 will be described. FIG. 29 shows a perspective view of the memory device 100A according to one embodiment of the present invention. FIG. 30 is a cross-sectional view of the region A1-A2 indicated by the dashed dotted line in FIG. 29. Note that for matters not described in this embodiment, other embodiments may be referred to.

[0205] <Storage device configuration example> The memory device 100A has a memory string 120s. The memory string 120s differs from the memory string 120 in the configuration of the transistor STr2. FIG. 31 shows an example of a cross-sectional configuration of the memory string 120s. In the memory string 120s, a conductor SEL that functions as the gate electrode of the transistor STr2 is provided on an insulator 123

[12] . Also, an insulator 138 is provided on the conductor SEL. A part of the conductor 130 functions as the back gate electrode of the transistor STr2.

[0206] <Example of how to make a memory device> Next, another exemplary method for fabricating the memory device 100A will be described with reference to FIGS. 32A to 50C. In each of FIGS. 32A to 50C, A is a top view seen from the Z direction, B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in A, and C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in A. FIG. 43D is an enlarged cross-sectional view of the portion surrounded by the dashed-dotted line in FIG. 43B. While this fabrication method illustrates one memory string 120s having two stages of memory elements MC, this embodiment is not limited to this. The memory string 120s may have three or more stages of memory elements MC. For example, the memory string 120s preferably has 32 or more stages of memory elements MC, preferably 64 or more stages, more preferably 128 or more stages, and even more preferably 256 or more stages.

[0207] First, similarly to the example of the method for manufacturing the memory device 100, a conductor 122, an insulator 132, an insulating film 123A, a conductive film 134A, and a conductive film 136A are formed over a base 121 having an insulating surface (see FIGS. 32A to 32C).

[0208] Next, a conductive film 137A is formed on the uppermost insulating film 123A, and an insulating film 138A is formed on the conductive film 137A. The conductive film 137A can be formed using the same method and from the same material as the conductive film 134A. The insulating film 138A can be formed using the same method and from the same material as the insulating film 123A.

[0209] Next, a mask (not shown) is formed on the insulating film 138A, and the insulating film 138A, the conductive film 137A, the insulating film 123A, the conductive film 134A, and the conductive film 136A are processed using lithography to form a first opening to expose the conductor 122 (see Figures 33A to 33C).

[0210] Next, isotropic etching is performed on the conductive film 136A to recess the side surface of the conductive film 136A in the first opening relative to the side surfaces of the insulating film 123A, the conductive film 134A, the conductive film 137A, and the insulating film 138A (see FIGS. 34A to 34C). This process makes the diameter of the first opening overlapping the conductive film 136A larger than the diameters of the first openings overlapping the insulating film 123A, the conductive film 134A, the conductive film 137A, and the insulating film 138A. As a result, unevenness is formed on the side surface of the first opening.

[0211] Next, the insulating film 124A is formed on the insulating film 138A and inside the first opening (see FIGS. 35A to 35C). Note that although the insulating film 124A has a single-layer structure in FIGS. 35B and 35C, it may have a multilayer structure. The insulating film 124A can be formed using a CVD method or an ALD method. In particular, the ALD method is preferable because it allows a film of uniform thickness to be formed even in grooves or openings with a high aspect ratio. Alternatively, the insulating film 124A may be formed by combining the ALD method and the CVD method. When the insulating film 124A has a multilayer structure, each insulating film may be formed using the same film formation apparatus or different film formation apparatuses.

[0212] The insulating film 124A formed by the above method has good coverage and can be formed even on the uneven shape of the side surface of the first opening. That is, the insulating film 124A can be formed so as to contact not only the side surfaces of the insulating film 123A, the conductive film 134A, and the conductive film 136A, but also part of the upper surface and part of the lower surface of the insulating film 123A.

[0213] Next, the insulating film 124A formed on the bottom of the first opening is removed to obtain the insulator 124. Anisotropic etching is preferably used to remove the insulating film 124A. At this time, the insulating film 124A on the insulating film 138A is also removed, so that the insulator 124 is provided only on the sidewall of the first opening (see FIGS. 36A to 36C). By removing the insulating film 124A on the bottom of the first opening, the conductor 122 is exposed again.

[0214] Next, a semiconductor film 125A and an insulating film 126A are formed inside the first opening (see FIGS. 37A to 37C).

[0215] The semiconductor film 125A and the insulating film 126A can be formed using a CVD method or an ALD method. The ALD method is particularly preferable because it allows for the formation of a film with a uniform thickness even in trenches or openings with a large aspect ratio. Alternatively, the semiconductor film 125A and the insulating film 126A may be formed by combining the ALD method and the CVD method. Also, different film formation methods and film formation apparatuses may be used for each film to be formed.

[0216] The semiconductor film 125A is preferably an oxide semiconductor having a CAAC structure. When the semiconductor film 125A is an oxide semiconductor having a CAAC structure, the c-axis of the semiconductor film 125A is aligned in the normal direction to the formation surface inside the first opening. In this case, the c-axis of the semiconductor film 125A located on the side surfaces of the insulating film 138A, the conductive film 137A, the insulating film 123A, the conductive film 134A, and the conductive film 136A via the insulator 124 is aligned toward the axis 182 shown in FIGS. 37A to 37C . As a result, the c-axis of the semiconductor 125A located above is aligned toward the axis 182 from the formation surface.

[0217] Next, the regions of the insulating film 126A and the semiconductor film 125A that overlap with the conductive film 137A are removed when viewed from the Z direction. To remove the insulating film 126A and the semiconductor film 125A in these regions, a material 180 (also called a sacrificial layer) that can be easily removed in a subsequent process is first formed inside the first opening so as to fill it, and a portion of the material 180 is then removed by etching or the like to a desired depth inside the first opening (see FIGS. 38A to 38C). Next, using the remaining material 180 as a mask, the insulating film 126A and the semiconductor film 125A exposed by the etching are sequentially removed, yielding the insulator 126 and the semiconductor 125 (see FIGS. 39A to 39C). Then, the material 180 is removed (see FIGS. 40A to 40C).

[0218] If the transistor STr2 can be formed in the region without removing a portion of the insulating film 126A and the semiconductor film 125A, the process of removing the insulating film 126A and the semiconductor film 125A using the material 180 can be omitted. At this time, the transistor STr2 is formed in which the semiconductor 125 is provided between the conductor 137 and the semiconductor 127 with the insulator 124 and the insulator 126 interposed therebetween.

[0219] Next, a semiconductor film 127A and a conductive film 128A are formed inside the first opening (see FIGS. 41A to 41C).

[0220] First, the semiconductor film 127A is formed. The semiconductor film 127A can be formed using a CVD method or an ALD method. In particular, the ALD method is preferable because it allows a film of uniform thickness to be formed even in grooves or openings with a large aspect ratio. Alternatively, the semiconductor film 127A may be formed by combining the ALD method and the CVD method.

[0221] The semiconductor film 127A is preferably an oxide semiconductor having a CAAC structure. When the semiconductor film 127A is an oxide semiconductor having a CAAC structure, the c-axis of the semiconductor film 127A is aligned in the normal direction to the formation surface inside the first opening. In this case, the c-axis of the semiconductor film 127A located on the side surfaces of the insulating film 138A, the conductive film 137A, the insulating film 123A, the conductive film 134A, and the conductive film 136A via the insulator 124, the semiconductor 125, the insulator 126, etc. is aligned from the formation surface toward the axis 182 shown in FIGS. 41A to 41C . As a result, the c-axis of the semiconductor 127A located above is aligned from the formation surface toward the axis 182.

[0222] Next, the conductive film 128A is formed (see FIGS. 41A to 41C). The conductive film 128A only needs to be formed so as to fill the recessed portion of the conductive film 136A via at least the insulator 124, the semiconductor film 125, the insulating film 126, and the semiconductor film 127A, and does not necessarily need to fill the entire inside of the second opening. The conductive film 128A can be formed using a CVD method or an ALD method. In particular, the ALD method is preferable because it allows a film of uniform thickness to be formed even in grooves or openings with a high aspect ratio. Alternatively, the conductive film 128A may be formed by combining the ALD method and the CVD method.

[0223] Next, the conductive film 128A is processed to form the conductor 128 (see FIGS. 42A to 42C). Isotropic etching or anisotropic etching can be used to process the conductive film 128A. In forming the conductive film 128A, if the conductive film 128A fills the recesses but does not completely fill the openings, as shown in FIGS. 41A to 41C, it is preferable to use isotropic etching to process the conductive film 128A. On the other hand, if the conductive film 128A is formed so as to fill the recesses and the openings, it is preferable to use anisotropic etching. By the above processing, the conductor 128 can be formed inside the recesses.

[0224] Next, using the conductor 128 as a mask, a portion of the semiconductor film 127A is made to have high resistance, thereby forming a high-resistance region (I-type region). The high-resistance region can be formed by irradiating the semiconductor film 127A with microwaves 144 to remove hydrogen contained in the semiconductor film 127A. Furthermore, irradiating the semiconductor film 127A with microwaves 144 in an atmosphere containing oxygen is preferable because oxygen is supplied to the semiconductor film 127A. In this embodiment, a portion of the semiconductor film 127A is irradiated with microwaves 144 in an atmosphere containing oxygen and argon, thereby making a region of the semiconductor film 127A that does not overlap with the conductor 128 (region 146) highly resistive (see FIGS. 43A to 43D).

[0225] Here, heat treatment may be performed. The heat treatment is preferably performed in a nitrogen-containing atmosphere at a temperature of 200°C to 500°C, preferably 300°C to 400°C. The atmosphere in which the heat treatment is performed is not limited to the above, and the heat treatment may be performed in an atmosphere containing at least one of nitrogen, oxygen, and argon. The heat treatment may be performed in a reduced pressure atmosphere or an atmospheric pressure atmosphere.

[0226] Heat treatment reduces the resistance of a region (region 148) of the semiconductor film 127A that is in contact with the conductor 128, thereby forming a low-resistance region (n-type region). By performing heat treatment while the semiconductor film 127A and the conductor 128 are in contact with each other, a metal compound layer containing a metal element of the conductor 128 and a component of the semiconductor film 127A may be formed at the interface between the conductor 128 and the semiconductor film 127A. Forming the metal compound layer is preferable because it reduces the resistance of the semiconductor film 127A in the region where the conductor 128 and the semiconductor film 127A are in contact with each other. Furthermore, the conductor 128 may absorb oxygen contained in the semiconductor film 127A. By performing heat treatment while the semiconductor film 127A and the conductor 128 are in contact with each other, the resistance of the region 148 of the semiconductor film 127A becomes even lower. The heat treatment may be performed before the microwave treatment. The region 148 whose resistance has been reduced by the heat treatment is covered with the conductor 128, and therefore is not affected by the microwave 144, and can maintain a low resistance value even after the microwave treatment.

[0227] The carrier concentration of the region 146 after the microwave treatment and heat treatment is 1×10 18 / cm 3 Less than 1 x 10, preferably 17 / cm 3 or less, more preferably 1×10 16 / cm 3 The carrier concentration of the region 148 is preferably 1×10 18 / cm 3 More than 1×10 19 / cm 3 More preferably, 1×10 20 / cm 3 It is preferable that this is equal to or greater than this.

[0228] Next, an insulating film 129A is formed to cover the semiconductor film 127A and the conductor 128, and a conductive film 130A is formed to cover the insulating film 129A (see FIGS. 44A to 44C). The insulating film 129A and the conductive film 130A can be formed using a CVD method or an ALD method. In particular, the ALD method is preferable because it allows a film of uniform thickness to be formed even in grooves or openings with a large aspect ratio. Alternatively, the ALD method and the CVD method may be combined to form the films.

[0229] Note that the formation of the high-resistance region by the microwave treatment and the heat treatment may be performed after the insulating film 129A is formed and before the conductive film 130A is formed.

[0230] Next, heat treatment is performed. The heat treatment is preferably performed in a nitrogen-containing atmosphere at a temperature of 200°C to 500°C, preferably 300°C to 400°C. The atmosphere in which the heat treatment is performed is not limited to the above, and the heat treatment may be performed in an atmosphere containing at least one of nitrogen, oxygen, and argon. The heat treatment may be performed in a reduced pressure atmosphere or an atmospheric pressure atmosphere.

[0231] Next, the conductive film 130A is removed by CMP or the like until the surface of the insulating film 129A is exposed, thereby obtaining the conductor 130 (see FIGS. 45A to 45C). Note that the heat treatment described above may be performed after the conductor 130 is formed.

[0232] Next, the semiconductor film 127A and the insulating film 129A are processed to obtain the semiconductor 127 and the insulator 129 (see FIGS. 46A to 46C). This processing can be performed by dry etching or wet etching. At this time, the semiconductor 127 that is electrically connected to the semiconductor 125 can be formed.

[0233] Next, the insulating film 138A, the conductive film 137A, the insulating film 123A, the conductive film 134A, and the conductive film 136A are processed to form the stepped insulator 138B, the conductor 137B, the insulator 123B, the conductor 134B, and the conductor 136B as shown in FIG. 47B (see FIGS. 47A to 47C). In processing the insulating film 138A, the conductive film 137A, the insulating film 123A, the conductive film 134A, and the conductive film 136A, etching of the insulating film 138A, the conductive film 137A, the insulating film 123A, the conductive film 134A, and the conductive film 136A and slimming of the mask are alternately performed, thereby forming the stepped insulator 138B, the conductor 137B, the insulator 123B, the conductor 134B, and the conductor 136B.

[0234] Next, the insulator 150 is formed (see FIGS. 47A to 47C). The insulator 150 can be formed using a CVD method. The insulator 150 is preferably subjected to a planarization process using a CMP method or a reflow method.

[0235] Next, insulator 150, insulator 138B, conductor 137B, insulator 123B, conductor 134B, and conductor 136B are processed to obtain insulator 138, conductor 137, insulator 123, conductor 134, and conductor 136 (see FIGS. 48A to 48C).

[0236] Next, an insulator 152 is formed so as to fill in the portions removed by the above processing (see FIGS. 48A to 48C). The insulator 152 can be formed using a CVD method or an ALD method. In particular, the ALD method is preferable because it allows a film of uniform thickness to be formed even in grooves or openings with a large aspect ratio. Alternatively, the insulator 152 may be formed by combining the ALD method and the CVD method. The insulator 152 is preferably planarized using a CMP method or a reflow method.

[0237] Next, the insulator 156 is formed to cover the conductor 130, the insulator 129, the insulator 150, and the insulator 152 (see FIGS. 49A to 49C). The insulator 156 can be formed by a CVD method, an ALD method, a sputtering method, or the like.

[0238] Next, insulator 156, insulator 150, insulator 129, and insulator 138 are processed using lithography to form second openings so as to expose conductor 134, conductor 136, conductor 130, conductor 137, and semiconductor 127. The second openings are formed for conductor 134 and conductor 136, which are formed in a stepped shape (see FIGS. 49A to 49C).

[0239] Next, conductor 161 electrically connected to conductor 134, conductor 162 electrically connected to conductor 136, conductor 163 electrically connected to conductor 130, conductor 164 electrically connected to conductor 137, and conductor 165 electrically connected to semiconductor 127 are formed so as to fill the second opening (see FIGS. 50A to 50C). Conductors 161, 162, 163, 164, and 165 can be formed using a CVD method or an ALD method. ALD is particularly preferred because it allows for the formation of a film with a uniform thickness even in grooves or openings with a high aspect ratio. Alternatively, the conductors may be formed by combining an ALD method and a CVD method. Conductors 161, 162, 163, 164, and 165 may have a multilayer structure consisting of multiple layers. Conductor 161, conductor 162, conductor 163, conductor 164, and conductor 165 can be formed by forming a conductive film on insulator 156 and inside the second opening, and removing unnecessary conductive film using CMP or the like.

[0240] Next, conductors 171 electrically connected to conductor 161, conductor 172 electrically connected to conductor 162, conductor 173 electrically connected to conductor 163, conductor 174 electrically connected to conductor 164, and conductor 175 electrically connected to conductor 165 are formed (see FIGS. 50A to 50C). Conductors 171, 172, 173, 174, and 175 can be formed by forming a conductive film on insulator 156 and processing it using a lithography method. For this processing, a dry etching method or a wet etching method can be used.

[0241] Conductors 171, conductor 161, and conductor 134 function as conductor SG or conductor WWL. Conductors 172, conductor 162, and conductor 136 function as conductor RWL. Conductors 173, conductor 163, and conductor 130 function as conductor BG. Conductors 174, conductor 164, and conductor 137 function as conductor SEL. Conductors 175 and conductor 165 function as BL. Through the above steps, semiconductor device 200A can be fabricated.

[0242] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0243] (Embodiment 3) In this embodiment, a MOCVD apparatus that can be used for forming oxides and the like, and a film formation method using the MOCVD method will be described with reference to FIGS. 51 and 52.

[0244] <Film Formation Method Using MOCVD Apparatus and MOCVD Method> In the MOCVD method, a liquid raw material (also called a precursor or metal precursor) is vaporized using a vaporizer and introduced into a chamber to form a film. The liquid precursor is held in a cylinder 1041 (cylinders 1041A to 1041D) for each precursor. A gas 1042 is supplied into the cylinder 1041 holding the precursor to be used for film formation. An inert gas such as helium, argon, or nitrogen can be used as the gas 1042. The supply of the gas 1042 can be controlled by a valve 1043, and the desired cylinder 1041 can be pressurized. Pressurizing the cylinder 1041 allows the liquid precursor to be supplied to the vaporizer 1044. The gas 1042 can be supplied to one cylinder 1041 or to two or more cylinders 1041 simultaneously. Although FIG. 51 shows an example in which four cylinders 1041 are connected to the MOCVD apparatus, this embodiment is not limited to this. There may be one or more cylinders 1041.

[0245] By using multiple precursors for film formation, films with different compositions can be formed. For example, by holding a precursor containing indium in cylinder 1041A, a precursor containing gallium in cylinder 1041B, and a precursor containing zinc in cylinder 1041C, and simultaneously supplying gas 1042 to cylinders 1041A to 1041C, a film containing indium, gallium, and zinc can be formed. Furthermore, as will be described in detail later, by mixing the vaporized precursor with a reactive gas containing oxygen and supplying the mixture to film formation chamber 1008 or 1009, an oxide containing indium, gallium, and zinc can be formed on wafer 1012 held in film formation chamber 1008 or 1009.

[0246] The precursor supplied to the vaporizer 1044 is first supplied to the dispersion section 1045. When multiple types of precursors are used for film formation, these precursors are mixed in the dispersion section 1045. At this time, it is preferable that a gas 1046 is supplied to the dispersion section. The gas 1046 may be called a primary carrier gas. The gas 1046 is used to supply the precursor or the mixed precursor from the dispersion section 1045 to the vaporization section 1048. The gas 1046 may be an inert gas such as helium, argon, or nitrogen.

[0247] The precursor or the mixed precursor is heated and vaporized in vaporizer 1048. The vaporized precursor is supplied to valve 1049 by gas 1047. Gas 1047 may be called a secondary carrier gas. An inert gas such as helium, argon, or nitrogen can be used as gas 1047.

[0248] It is preferable to exhaust the vaporized precursor and secondary carrier gas without supplying them to the deposition chamber 1008 or 1009 until the supply of the vaporized precursor and secondary carrier gas is stabilized. At this time, the precursor and secondary carrier gas can be exhausted by closing valve 1049a and opening valve 1049b.

[0249] Once the supply of the vaporized precursor and secondary carrier gas has stabilized, valve 1049a is opened and valve 1049b is closed. The precursor and secondary carrier gas are supplied to film formation chamber 1008 or 1009, whereby a desired film can be formed on wafer 1012.

[0250] As described above, by exhausting the precursor and secondary carrier gas before they become stable, it is possible to supply a desired amount of precursor or precursors in a desired mixture ratio to the film formation chamber 1008 or 1009. By exhausting the precursor and secondary carrier gas before they become stable, it is possible to form a film of a desired quality or thickness on the wafer 1012. This also improves the uniformity of the formed film, which is preferable.

[0251] Furthermore, the precursor and secondary carrier gas that have passed through valve 1049a may be mixed with gas 1050. It is preferable to use a reactive gas such as an oxidizing gas or a nitriding gas as gas 1050. Oxygen, ozone, or the like may be used as the oxidizing gas. Nitrogen, nitrous oxide, nitrogen dioxide, ammonia, or the like may be used as the nitriding gas. The supply of gas 1050 can be controlled by valve 1051. A mass flow controller or the like may be provided as appropriate to control the supply amount of gas 1050.

[0252] Here, the precursor vaporized by the vaporizer 1048 may liquefy or solidify due to temperature changes. For example, solidification may produce powder of components contained in the precursor. Therefore, it is preferable to heat the piping from the vaporizer 1048 to the film formation chamber 1008 or 1009, the film formation chamber 1008, the film formation chamber 1009, and the exhaust piping. The heating temperature of the piping and the exhaust piping is preferably equal to or higher than the heating temperature of the vaporizer. The heating temperature of the film formation chamber 1008 and the film formation chamber 1009 can be determined appropriately by the practitioner, taking into consideration the quality of the film to be formed, the uniformity of the film, the film formation rate, etc.

[0253] As described above, the film formation method using a vaporized precursor can form a film with high uniformity in film thickness and quality. It also has a high surface coverage rate even on uneven surfaces. In particular, in openings with a large aspect ratio, a film with high uniformity in quality and thickness can be formed on the bottom and sides of the opening.

[0254] Here, as an example of an apparatus capable of forming a film by the MOCVD method, a configuration example of a film formation apparatus 1000 will be described with reference to Figures 52A and 52B. Figure 52A is a schematic diagram of a multi-chamber type film formation apparatus 1000, and Figure 52B is a cross-sectional view of a film formation chamber 1008.

[0255] <Configuration example of film formation equipment> The film formation apparatus 1000 includes a cassette chamber 1002, an alignment chamber 1004, a transfer chamber 1006, film formation chambers 1008 and 1009, a cooling chamber 1010, and a transfer arm 1014. A wafer 1012 can be transferred by the transfer arm 1014. The cassette chamber 1002, the alignment chamber 1004, the film formation chambers 1008 and 1009, and the cooling chamber 1010 are connected to the transfer chamber 1006. This allows continuous film formation in the film formation chambers 1008 and 1009 without exposure to the atmosphere, preventing impurities from being mixed into the films. Furthermore, contamination of the interfaces between the substrate and the film and between the films is reduced, resulting in clean interfaces.

[0256] A cassette having a plurality of wafers 1012 can be placed in the cassette chamber 1002. One or more cassettes can be placed. The wafers 1012 are removed from the cassette by a transfer arm 1014, and after processing such as film formation, are returned to the desired cassette in the cassette chamber 1002.

[0257] In the alignment chamber 1004, the position of the wafer 1012 on the transfer arm 1014 is adjusted. It is preferable to adjust the position before the wafer 1012 taken out of the cassette chamber 1002 is transferred to the film formation chamber 1008 or 1009. Alternatively, the position may be adjusted before the wafer 1012 is returned to the cassette chamber 1002 after processing such as film formation.

[0258] In the film-forming chamber 1008 and the film-forming chamber 1009, a film is formed on the wafer 1012.

[0259] The cooling chamber 1010 adjusts the temperature of the wafer 1012 processed in the film formation chamber 1008 or the film formation chamber 1009. For example, when the processing in the film formation chamber 1008 or the film formation chamber 1009 is performed in a heated atmosphere, it is preferable to carry out the wafer 1012 into the cassette chamber 1002 after adjusting the temperature in the cooling chamber 1010 in order to prevent the heated wafer 1012 from being cooled rapidly.

[0260] In addition, in order to prevent adhesion of moisture and the like, the cassette chamber 1002, the alignment chamber 1004, the transfer chamber 1006, the film forming chamber 1008, the film forming chamber 1009, and the cooling chamber 1010 are preferably filled with an inert gas (such as nitrogen gas) with a controlled dew point, and it is desirable to maintain a reduced pressure.

[0261] In addition, an MOCVD apparatus can be used in the film forming chamber 1008 and the film forming chamber 1009. Also, a configuration may be adopted in which a film forming apparatus other than the ALD apparatus is used in either the film forming chamber 1008 or the film forming chamber 1009. Examples of the film forming apparatus used in the film forming chamber 1008 and the film forming chamber 1009 include a sputtering apparatus, a PECVD apparatus, a TCVD apparatus, an ALD apparatus, and the like.

[0262] Further, although the film forming apparatus 1000 is configured to include the cassette chamber 1002, the alignment chamber 1004, the transfer chamber 1006, the film forming chamber 1008, the film forming chamber 1009, and the cooling chamber 1010, the present invention is not limited thereto. The film forming apparatus 1000 may be configured to have three or more film forming chambers, or may be configured to add a processing chamber for performing heat treatment or plasma treatment. Also, the film forming apparatus 1000 may be a single wafer type or a batch type for simultaneously forming films on a plurality of substrates.

[0263] <MOCVD apparatus> Next, a configuration in which an MOCVD apparatus is used as the film formation chamber 1008 will be described with reference to FIG. 52B. The film formation chamber 1008 has a bottom outer wall 1021, side outer walls 1022, and an upper outer wall 1023. The upper outer wall 1023 is provided with a raw material inlet 1025 and a shower plate 1024. The side outer wall 1022 is provided with a gate valve 1028 for loading and unloading the wafer 1012. The bottom outer wall 1021 is provided with an exhaust unit 1026, an exhaust valve 1027, and a stage 1029. It is preferable that the bottom outer wall 1021, side outer wall 1022, and upper outer wall 1023 be provided with heaters for controlling the temperature during film formation. It is not necessary that the bottom outer wall 1021, side outer wall 1022, and upper outer wall 1023 be provided independently. For example, the bottom outer wall 1021, the side outer wall 1022, and the top outer wall 1023 may be integrally formed. Alternatively, the bottom outer wall 1021 and the side outer wall 1022 may be integrally formed, with the top outer wall 1023 functioning as a lid.

[0264] The gas containing the precursor vaporized by the vaporization unit 1048 is introduced into the film formation chamber 1008 from the raw material inlet 1025 and supplied to the wafer 1012 on the stage 1029 via the shower plate 1024. The supplied gas is deposited on the wafer 1012 to form a film. Meanwhile, the gas not used in forming the film, or excess gas, is exhausted to the outside of the film formation chamber 1008 from the exhaust unit 1026.

[0265] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0266] (Fourth embodiment) In this embodiment, the circuit configuration and operation of a memory string 120, which is a memory device, will be described. FIG. 53 shows an example of the circuit configuration of the memory string 120. Note that the circuit configuration example shown in this embodiment can also be applied to the memory string 120s. Therefore, in this embodiment, "memory string 120" can be read as "memory string 120s."

[0267] <Memory string circuit configuration example> 53 shows an example of a circuit configuration in which the number n of storage elements MC included in the memory string 120 is 5. As described in the above embodiment, the storage element MC has a transistor WTr and a transistor RTr.

[0268] In an equivalent circuit diagram, the symbol "OS" may be added to the circuit symbol of a transistor to indicate that the transistor is an OS transistor. Similarly, the symbol "Si" may be added to the circuit symbol of a transistor to indicate that the transistor is a Si transistor (a transistor that uses silicon in the semiconductor layer in which the channel is formed). In Figure 53, the transistors WTr and RTr are shown to be OS transistors.

[0269] An equivalent circuit diagram of the memory element MC is shown in Fig. 54. As shown in Fig. 54, the transistor WTr can be represented by replacing it with a capacitance Cs and a transistor Tr. The gate of the transistor Tr is electrically connected to the conductor WWL via the capacitance Cs.

[0270] In FIG. 53, the transistor WTr included in the memory element MC[1] is shown as transistor WTr[1], and the transistor RTr included in the memory element MC[1] is shown as transistor RTr[1]. Therefore, the memory string 120 shown in FIG. 53 has transistors WTr[1] to WTr[5] and transistors RTr[1] to RTr[5]. The memory string 120 shown in FIG. 53 also has transistors STr1 and STr2. The memory string 120 is a NAND-type memory device.

[0271] A NAND-type storage device that includes an OS memory is also called an "OS NAND type" or "OS NAND type storage device." Additionally, an OS NAND type storage device with multiple OS memories stacked in the Z direction is also called a "3D OS NAND type" or "3D OS NAND type storage device."

[0272] One of the source or drain of transistor RTr[1] is electrically connected to one of the source or drain of transistor STr1, and the other is electrically connected to one of the source or drain of transistor RTr[2]. One of the source or drain of transistor WTr[1] is electrically connected to the gate of transistor RTr[1], and the other is electrically connected to one of the source or drain of transistor WTr[2]. The back gate of transistor RTr[1] is electrically connected to conductor RWL[1]. The gate of transistor WTr[1] is electrically connected to conductor WWL[1]. The back gate of transistor WTr[1] is electrically connected to conductor BG. The other of the source or drain of transistor STr1 is electrically connected to conductor 122, and the gate is electrically connected to conductor SG.

[0273] In addition, one of the source or drain of transistor RTr[5] is electrically connected to the other of the source or drain of transistor RTr[4], and the other is electrically connected to one of the source or drain of transistor STr2. The gate of transistor RTr[5] is electrically connected to one of the source or drain of transistor WTr[5]. The other of the source or drain of transistor WTr[5] is electrically connected to one of the source or drain of transistor STr2. The back gate of transistor RTr[5] is electrically connected to conductor RWL[5]. The gate of transistor WTr[5] is electrically connected to conductor WWL[5]. In addition, the back gate of transistor WTr[5] is electrically connected to conductor BG. In addition, the other of the source or drain of transistor STr2 is electrically connected to conductor BL, and the gate is electrically connected to conductor SEL.

[0274] When the memory string 120 includes n memory elements MC, in the i-th memory element MC[i] (i is an integer between 1 and n) excluding the first and n-th memory elements MC, one of the source or drain of the transistor RTr[i] is electrically connected to the other of the source or drain of the transistor RTr[i-1], and the other is electrically connected to one of the source or drain of the transistor RTr[i+1]. The gate of the transistor RTr[i] is electrically connected to one of the source or drain of the transistor WTr[i]. The other of the source or drain of the transistor WTr[i] is electrically connected to one of the source or drain of the transistor WTr[i+1]. The back gate of the transistor RTr[i] is electrically connected to the conductor RWL[i]. The gate of the transistor WTr[i] is electrically connected to the conductor WWL[i]. The back gate of the transistor WTr[i] is electrically connected to the conductor BG.

[0275] Also, the node where the gate of the transistor RTr is electrically connected to either the source or the drain of the transistor WTr is referred to as a node ND. That is, the node where the gate of the transistor RTr[i] is electrically connected to either the source or the drain of the transistor WTr[i] is referred to as a node ND[i]. In FIG. 53, the node ND included in the memory element MC[1] is referred to as a node ND[1].

[0276] The transistors STr1 and STr2 may be, for example, OS transistors or Si transistors. One of the transistors STr1 and STr2 may be an OS transistor and the other may be a Si transistor. When both the transistors WTr and RTr are formed of OS transistors, it is preferable that the transistors STr1 and STr2 are also formed of OS transistors. By using the same semiconductor material for the transistors, the productivity of the semiconductor device can be improved.

[0277] Alternatively, an OS transistor may be used as the transistor WTr and a Si transistor may be used as the transistor RTr. An equivalent circuit diagram of the memory string 120 in the case where an OS transistor is used as the transistor WTr and a Si transistor is used as the transistor RTr is shown in FIG.

[0278] When the transistor RTr is a Si transistor, polycrystalline silicon, for example, may be used for the semiconductor 125. When the transistor WTr is an OS transistor, CAAC-IGZO, for example, may be used for the semiconductor 127.

[0279] Note that, depending on the purpose or application, a Si transistor may be used as the transistor WTr and an OS transistor may be used as the transistor RTr, as shown in Fig. 56. Also, depending on the purpose or application, a Si transistor may be used for both the transistor WTr and the transistor RTr, as shown in Fig. 57. When Si transistors are used for both the transistor WTr and the transistor RTr, it is preferable to use Si transistors also for the transistors STr1 and STr2.

[0280] <Memory string operation example> Next, an example of the operation of the memory string 120 shown in FIG. 53 will be described.

[0281] [Write operation] In this embodiment, an example of an operation in which an H potential is written to the memory element MC[1] and the memory element MC[3] and an L potential is written to the other memory elements MC will be described. FIG. 58 is a timing chart illustrating the write operation. FIGS. 59A to 62B are circuit diagrams illustrating the write operation. Note that reference numerals and the like not shown in FIGS. 59A to 62B may be referred to in FIG. 53 and the like.

[0282] In an initial state, an L potential is written to the memory elements MC[1] to MC[5]. Also, an L potential is supplied to the conductors WWL[1] to WWL[5], the conductors RWL[1] to RWL[5], the conductor SEL, the conductor BG, the conductor BL, the conductor SG, and the conductor 122. The threshold value of the transistor RTr can be controlled by adjusting the potential supplied to the conductor BG. The potential supplied to the conductor BG may be appropriately adjusted so that the transistor RTr becomes a desired normally-on transistor.

[0283] [Period T1] In a period T1, an H potential is supplied to the conductors WWL[1] to WWL[5], the conductor BL, and the conductor SEL (see FIG. 59A). As a result, the potentials of the nodes ND[1] to ND[5] become H potentials.

[0284] [Period T2] In period T2, an L potential is supplied to the conductor WWL[1] (see FIG. 59B). Then, the transistor WTr[1] is turned off, and the charge written to the node ND[1] is retained. Here, a charge equivalent to an H potential is retained.

[0285] [Period T3] In the period T3, an L potential is supplied to the conductor BL (see FIG. 59B). Then, the potentials of the nodes ND[2] to ND[5] become L potential. In this case, the gates of the transistors RTr[2] to RTr[5] also become L potential. However, because the transistors RTr are normally-on transistors, the transistors RTr[2] to RTr[5] do not turn off.

[0286] [Period T4] In period T4, the conductor WWL[2] is supplied with an L potential (see FIG. 60A). This turns off the transistor WTr[2], and the charge written to the node ND[2] is retained. Here, a charge equivalent to the L potential is retained.

[0287] [Period T5] In a period T5, an H potential is supplied to the conductor BL (see FIG. 60B). As a result, the potentials of the nodes [3] to [5] become H potentials.

[0288] [Period T6] In period T6, an L potential is supplied to the conductor WWL[3] (see FIG. 61A). Then, the transistor WTr[3] is turned off, and the charge written to the node ND[3] is retained. Here, a charge equivalent to an H potential is retained.

[0289] [Period T7] In a period T7, an L potential is supplied to the conductor BL (see FIG. 61B), causing the potentials of the nodes ND[4] and ND[5] to become L potential.

[0290] [Period T8] In period T8, the conductor WWL[4] is supplied with an L potential (see FIG. 62A). This turns off the transistor WTr[4], and the charge written to the node ND[4] is retained. Here, a charge equivalent to the L potential is retained.

[0291] [Period T9] In the period T9, the conductor BL remains at the L potential, so the potential of the node ND[5] also remains at the L potential.

[0292] [Period T10] In period T10, an L potential is supplied to the conductor WWL[5] (see FIG. 62B). Then, the transistor WTr[5] is turned off, and the charge written to the node ND[5] is retained. Here, a charge equivalent to the L potential is retained. Also, an L potential is supplied to the conductor SEL.

[0293] In this way, information can be written to the memory element MC.

[0294] Note that when writing data to the i-th memory element MC (excluding i=1) among the multiple memory elements MC, the data write operation to the i-1th memory elements MC can be omitted. For example, when writing data to the memory element MC[4], it is not necessary to write data to the memory elements MC[1] to MC[3]. In other words, the data write operation from the period T1 to the period T6 described in this embodiment can be omitted. Therefore, the time and power consumption required for the write operation of the memory device can be reduced.

[0295] [Read operation] An example of a read operation of the memory string 120 having the above circuit configuration will be described. As an initial state, assume that an H potential is held in the memory elements MC[1] and MC[3], and an L potential is held in the memory elements MC[2], MC[4], and MC[5]. Also assume that an L potential is supplied to conductors WWL[1] to WWL[5], conductors RWL[1] to RWL[5], conductor SEL, conductor BG, conductor BL, conductor SG, and conductor 122. Figures 63A and 63B are timing charts illustrating the read operation. Figures 64A, 64B, 65A, and 65B are circuit diagrams illustrating the read operation. Note that reference numerals and other symbols not shown in Figures 64A, 64B, 65A, and 65B may refer to Figure 53, etc.

[0296] <When the holding potential is H potential> First, the read operation of the memory element MC[3] in which the H potential is held will be described.

[0297] [Period T11] In period T11, an H potential is supplied to the conductors RWL[1] to RWL[5] and the conductor SEL (see FIG. 64A). This turns on the transistor STr2, and the semiconductor 125 and the conductor BL of the transistor RTr are brought into a conductive state. In this state, the conductor BL and the semiconductor 125 are precharged with an H potential, bringing them into a floating state.

[0298] Here, the Id-Vg characteristics of a transistor will be explained. Figures 66A and 66B are diagrams illustrating the Id-Vg characteristics of a transistor. The horizontal axis of Figures 66A and 66B represents gate voltage (Vg), and the vertical axis represents drain current (Id). Figure 66A shows the Id-Vg characteristics of a normally-off transistor, and Figure 66B shows the Id-Vg characteristics of a normally-on transistor.

[0299] The H potential is a potential higher than the L potential. If the L potential is 0V, the H potential is a positive voltage. In a normally-off transistor, when Vg is at the L potential (0V), the channel resistance (resistance between the source and drain) is extremely large, and Id hardly flows. Furthermore, when Vg becomes the H potential, the channel resistance decreases and Id increases (see Figure 66A).

[0300] In a normally-on transistor, the channel resistance is small even when Vg is at a low potential, and a larger Id flows than in a normally-off transistor. When Vg becomes a high potential, the channel resistance becomes even smaller, and Id increases even more (see Figure 66B).

[0301] Because the transistor RTr is a normally-on transistor, the semiconductor 125 can be precharged even if the potential of the conductor RWL remains at L potential. However, supplying H potential to the conductor RWL further reduces the channel resistance of the transistor RTr. This reduces the time and power consumption required for precharging.

[0302] [Period T12] In period T12, an L potential is supplied to the conductor RWL[3] (see FIG. 64B). The node ND[3] is held at an H potential. Therefore, even if the potential of the conductor RWL[3] becomes an L potential, the channel resistance value of the transistor RTr[3] is smaller than when the node ND[3] is held at an L potential.

[0303] [Period T13] During period T13, an H potential is supplied to conductor SG, turning on transistor STr1 (see FIG. 65A). This causes conductor BL and conductor 122 to become conductive. At this time, because an H potential is supplied to conductors RWL[1], RWL[2], RWL[4], and RWL[5], the channel resistance values ​​of transistors RTr[1], RTr[2], RTr[4], and RTr[5] become small regardless of the potential of node ND. As mentioned above, although an L potential is supplied to conductor RWL[3], because an H potential is maintained at node ND[3], the channel resistance value of transistor RTr[3] becomes small. Therefore, the potential of conductor BL, which is in a floating state, suddenly changes from an H potential to an L potential (see FIG. 63A).

[0304] [T14 period] In a period T14, an L potential is supplied to the conductor SEL, the conductor RWL, and the conductor SG (see FIG. 65B).

[0305] <When the holding potential is L potential> Next, the read operation of the memory element MC[2] holding an L potential will be described. When reading the information (potential) held in the memory element MC[2], the potential of the conductor RWL[2] is set to an L potential during period T12 (see FIG. 63B). At this time, since the L potential is held at the node ND[2], the channel resistance value of the transistor RTr[2] is larger than when the H potential is held at the node ND[2].

[0306] Subsequently, in period T13, an H potential is supplied to the conductor SG, bringing the conductor BL and the conductor 122 into a conductive state. At this time, since the channel resistance value of the transistor RTr[2] is large, the potential of the conductor BL changes gradually from the H potential to the L potential.

[0307] In this way, in the period T13, the potential of the conductor RWL corresponding to the memory element MC to be read is set to the L potential, and the change in the potential of the conductor BL is detected, thereby making it possible to know the information stored in the memory element MC.

[0308] <Modification> 67 shows an example of the circuit configuration of a memory string 120A, which is a modified example of the memory string 120. The memory string 120A has a circuit configuration in which a transistor STr3 is added to the memory string 120.

[0309] In the memory string 120A shown in FIG. 67, the other of the source or drain of transistor RTr[5] is electrically connected to the source or drain of transistor STr3, not the source or drain of transistor STr2. The other of the source or drain of transistor STr3 is electrically connected to conductor BL. The gate of transistor STr2 is electrically connected to conductor WSEL, and the gate of transistor STr3 is electrically connected to conductor RSEL.

[0310] Fig. 68 is a timing chart illustrating a write operation of the memory string 120A. Fig. 69 is a timing chart illustrating a read operation of the memory string 120A.

[0311] In the memory string 120A, during a write operation, an H potential is supplied to the conductor WSEL, and an L potential is supplied to the conductor RSEL. Also, during a read operation, an L potential is supplied to the conductor WSEL, and an H potential is supplied to the conductor RSEL. Therefore, during a write operation, the transistor STr2 is turned on, and the transistor STr3 is turned off. During a read operation, the transistor STr2 is turned off, and the transistor STr3 is turned on. When writing or reading information via the conductor BL, the information transmission path can be switched using the respective dedicated transistors. This stabilizes the operation of the memory device, and improves the reliability of the memory device.

[0312] Furthermore, in the memory string 120, the memory string 120A, and the memory string 120B described later, it is preferable to supply a potential (also referred to as an "LL potential") lower than the L potential to the conductor BG during operations other than the write operation. By supplying the LL potential to the conductor BG, the transistor WTr can be turned off more reliably. Therefore, the data written to the node ND can be retained for a longer period of time.

[0313] Furthermore, in the memory string 120, the memory string 120A, and the memory string 120B described below, a potential higher than the L potential may be supplied to the conductor BG during a write operation. For example, an H potential may be supplied to the conductor BG during a write operation. By supplying an H potential to the conductor BG during a write operation, the resistance value of the semiconductor 127 decreases, and the write speed can be increased.

[0314] 70, the other of the source or drain of transistor STr2 may be electrically connected to a conductor WBL, and the other of the source or drain of transistor STr3 may be electrically connected to a conductor RBL. During a write operation, information is written via the conductor WBL, and during a read operation, information is read via the conductor RBL. By providing dedicated conductors BL for both the write operation and the read operation, the operation of the memory device can be stabilized and the reliability of the memory device can be improved.

[0315] The memory string 120B shown in Figure 71 has a circuit configuration in which a transistor STr4 is added to the memory string 120A. One of the source or drain of the transistor STr4 is electrically connected to one of the source or drain of the transistor WTr[1], and the other is electrically connected to the conductor WBL[2]. The gate of the transistor STr4 is electrically connected to the conductor WSEL[2].

[0316] In the memory string 120B, the gate of the transistor STr2 is electrically connected to the conductor WSEL[1], and the other of the source and drain of the transistor STr2 is electrically connected to the conductor WBL[1]. Note that, as shown in FIG. 67, the circuit configuration may be such that the transistors STr2 and STr3 are electrically connected to the conductor BL.

[0317] In the memory string 120B, information can be written from both the conductor WBL[1] and the conductor WBL[2]. This increases the speed at which information can be written. In addition, the supply of charge corresponding to the information to be written can be more reliably achieved.

[0318] Furthermore, when writing information to the i-th memory element MC, if i is close to n, the information is written from the conductor WBL[1] side, thereby eliminating the operation of writing information to the 1st to (i-1)th memory elements MC. Furthermore, if i is close to 1, the information is written from the conductor WBL[2] side, thereby eliminating the operation of writing information to the (i+1)th to nth memory elements MC. In the memory string 120B, the time and power consumption required for the write operation can be further reduced.

[0319] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0320] (Embodiment 5) In this embodiment, a configuration example of a semiconductor device 200 including a memory device 100 will be described. Note that a memory device 100A may be used instead of the memory device 100. In this embodiment and the like, it is assumed that the memory device 100A can be used instead of the memory device 100 unless otherwise specified.

[0321] 72 is a block diagram illustrating a configuration example of a semiconductor device 200 according to one embodiment of the present invention. The semiconductor device 200 illustrated in FIG. 72 includes a driver circuit 210 and a memory array 220. The memory array 220 includes one or more memory devices 100. FIG. 72 illustrates an example in which the memory array 220 includes a plurality of memory devices 100 arranged in a matrix.

[0322] The drive circuit 210 has a PSW 241 (power switch), a PSW 242, and a peripheral circuit 215. The peripheral circuit 215 has a peripheral circuit 211 (row decoder), a control circuit 212, and a voltage generation circuit 228. The semiconductor device 200 has elements or circuits having various functions, such as a memory array 220, PSWs 241 and 242, the peripheral circuit 211, the control circuit 212, and the voltage generation circuit 228. Therefore, the semiconductor device 200 may be referred to as a system or a subsystem.

[0323] In the semiconductor device 200, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0324] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 212.

[0325] The control circuit 212 is a logic circuit having a function of controlling the overall operation of the semiconductor device 200. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 200. Alternatively, the control circuit 212 generates a control signal for the peripheral circuit 211 so that this operation mode is executed.

[0326] The voltage generation circuit 228 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 228. For example, when an H-level signal is given to the signal WAKE, the signal CLK is input to the voltage generation circuit 228, and the voltage generation circuit 228 generates a negative voltage.

[0327] The peripheral circuit 211 is a circuit for writing and reading data to and from the memory device 100. The peripheral circuit 211 has a row decoder 221, a column decoder 222, a row driver 223, a column driver 224, an input circuit 225, an output circuit 226, and a sense amplifier 227.

[0328] The row decoder 221 and the column decoder 222 have the function of decoding the signal ADDR. The row decoder 221 is a circuit for specifying a row to be accessed, and the column decoder 222 is a circuit for specifying a column to be accessed. The row driver 223 has the function of selecting the wiring WL specified by the row decoder 221. The column driver 224 has the function of writing data to the memory device 100, reading data from the memory device 100, and retaining the read data.

[0329] The input circuit 225 has a function of holding a signal WDA. The data held by the input circuit 225 is output to the column driver 224. The output data of the input circuit 225 is data (Din) to be written to the memory device 100. The data (Dout) read from the memory device 100 by the column driver 224 is output to the output circuit 226. The output circuit 226 has a function of holding Dout. In addition, the output circuit 226 has a function of outputting Dout to the outside of the semiconductor device 200. The data output from the output circuit 226 is a signal RDA.

[0330] The PSW 241 has a function of controlling the supply of VDD to the peripheral circuit 215. The PSW 242 has a function of controlling the supply of VHM to the row driver 223. In this example, the high power supply voltage of the semiconductor device 200 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of the PSW 241 is controlled by a signal PON1, and the on / off of the PSW 242 is controlled by a signal PON2. In FIG. 72, the number of power domains to which VDD is supplied in the peripheral circuit 215 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0331] The drive circuit 210 and the memory array 220 may be provided on the same plane. Alternatively, as shown in FIG. 73A, the drive circuit 210 and the memory array 220 may be provided overlapping each other. By providing the drive circuit 210 and the memory array 220 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 73B, the memory array 220 may be provided in multiple layers on the drive circuit 210.

[0332] Furthermore, as shown in FIG. 73C , memory arrays 220 may be provided above and below the drive circuit 210. FIG. 73C shows an example in which one memory array 220 is provided above and one memory array 220 below the drive circuit 210. By arranging the drive circuit 210 so that the multiple memory arrays 220 sandwich the drive circuit 210, the signal propagation distance can be further shortened. Note that the number of memory arrays 220 stacked above the drive circuit 210 and the number of memory arrays 220 stacked below the drive circuit 210 may each be one or more. It is preferable that the number of memory arrays 220 stacked above the drive circuit 210 is equal to the number of memory arrays 220 stacked below the drive circuit 210.

[0333] <Example of cross-sectional structure of semiconductor device> Fig. 74 shows an example of a cross-sectional configuration of the semiconductor device 200 shown in Fig. 73A. Fig. 74 shows a part of the semiconductor device 200 shown in Fig. 73A. Fig. 75 shows an example of a cross-sectional configuration when the semiconductor device 200 shown in Fig. 73A is replaced with a semiconductor device 200A. Fig. 75 also shows a part of the semiconductor device 200A.

[0334] FIG. 74 shows transistors 301, 302, and 303 included in the driver circuit 210. The transistors 301 and 302 function as part of a sense amplifier 304. The transistor 303 functions as a column selection switch. Specifically, a conductor BL included in the memory array 220 is electrically connected to one of the source and drain of the transistor 301, the gate of the transistor 301 is electrically connected to one of the source and drain of the transistor 302, and the gate of the transistor 302 is electrically connected to the other of the source and drain of the transistor 301. The one of the source and drain of the transistor 301 and the other of the source and drain of the transistor 302 are electrically connected to one of the source and drain of the transistor 303, which functions as a column selection switch. This enables the layout area of ​​the semiconductor device 200 to be reduced. FIG. 74 shows an example in which seven memory elements MC are provided per memory string. However, the number of memory elements MC provided in one memory string is not limited to this. For example, the number of storage elements MC provided in one memory string may be 32, 64, 128, or 200 or more.

[0335] The conductor BL of the memory array 220 is electrically connected to the sense amplifier 304 and the transistor 303 functioning as a column selection switch via a conductor 752 formed so as to be embedded in the insulators 726 and 722, a conductor 705, a conductor 714, and a conductor 715. Note that the circuits and transistors included in the driver circuit 210 are merely examples, and the circuit configuration and transistor structure are not limited thereto. In addition to the above, appropriate circuits and transistors, such as a control circuit, a row decoder, a row driver, a source line driver, and an input / output circuit, can be provided depending on the configuration of the semiconductor device 200 and its driving method.

[0336] The transistors 301, 302, and 303 are provided on a substrate 311, and each includes a conductor 316, an insulator 315, a semiconductor region 313 made of part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b functioning as a source region or a drain region. As shown in FIG. 74, one low-resistance region may be shared by the transistors 301 and 302 as both the source region or the drain region of one and the source region or the drain region of the other.

[0337] In the transistors 301, 302, and 303, a semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. The conductor 316 may be made of a material that adjusts the work function. The transistors 301, 302, and 303 are also called FIN transistors because they utilize the convex portions of the semiconductor substrate. An insulator that functions as a mask for forming the convex portions may be provided in contact with the tops of the convex portions. While the case where the convex portions are formed by processing a part of the semiconductor substrate has been described here, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0338] The transistors 301, 302, and 303 may each be either a p-channel type or an n-channel type, but it is preferable that the transistors 301 and 302 have opposite conductivity types.

[0339] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as the source region or the drain region, and the low-resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single-crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, by using GaAs and GaAlAs, the transistors 301, 302, and 303 may be configured as HEMTs (High Electron Mobility Transistors).

[0340] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0341] The insulator 315 functions as a gate insulating film for the transistor 301 , the transistor 302 , and the transistor 303 .

[0342] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0343] Since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride and tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use metal materials such as tungsten and aluminum as a laminate for the conductor, and tungsten is particularly preferable in terms of heat resistance.

[0344] An insulator 317, which functions as an etch stopper, is preferably provided above the conductor 316. An insulator 318, which functions as a spacer, is preferably provided on the side of the insulator 315. By providing the insulators 317 and 318, the regions where the low-resistance regions 314a and 314b are electrically connected to the conductor 328 can be determined in a self-aligned manner. Therefore, even if misalignment occurs when forming openings to expose portions of the low-resistance regions 314a and 314b, openings can be formed to expose the intended regions. Forming the conductor 328 in the openings thus formed results in good contact with the conductor 328, with reduced contact resistance, and thus a contact between the low-resistance regions 314a and 314b and the conductor 328. The contact formed in this manner between the low-resistance regions 314a and 314b and the conductor 328 is sometimes referred to as a self-aligned contact. In addition, a conductor 329 electrically connected to the conductor 316 may be provided so as to be embedded in the insulator 317 and the insulator 322 .

[0345] An insulator 320, an insulator 322, an insulator 324, an insulator 326, and an insulator 327 are stacked in this order to cover the transistor 301, the transistor 302, and the transistor 303.

[0346] The insulators 320, 322, 324, 326, and 327 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride.

[0347] The insulator 322 may function as a planarizing film that flattens steps caused by the transistor 301 or the like provided thereunder. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the flatness.

[0348] The insulator 324 is preferably a film having a barrier property that prevents hydrogen or impurities from diffusing from the substrate 311 or the transistor 301 to a region where the memory array 220 is provided.

[0349] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the memory element MC, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the memory element MC and the transistor 301 or the like. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0350] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0351] Note that the insulators 326 and 327 preferably have a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulators 326 and 327 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulators 326 and 327 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0352] Furthermore, conductors 328, 329, 330, etc., which are electrically connected to the memory array 220, are embedded in the insulators 320, 322, 324, 326, and 327. The conductors 328, 329, and 330 function as plugs or wiring. Furthermore, for conductors that function as plugs or wiring, multiple structures may be collectively assigned the same reference numeral. Furthermore, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a portion of the conductor functions as wiring, and cases where a portion of the conductor functions as a plug.

[0353] The materials for each plug and wiring (such as conductor 328, conductor 329, and conductor 330) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a laminated layer. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and conductivity, are preferably used, and tungsten is preferred. Alternatively, they are preferably formed from a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce the wiring resistance.

[0354] A wiring layer may be provided over the insulator 327 and the conductor 330. For example, in FIG. 74, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring. The conductor 356 can be formed using a material similar to that of the conductors 328, 329, and 330.

[0355] Note that, for example, the insulator 350 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 301 and the like can be separated from the memory element MC by a barrier layer, and diffusion of hydrogen from the transistor 301 and the like to the memory element MC can be suppressed.

[0356] Note that, for example, tantalum nitride or the like is preferably used as a conductor having a barrier property against hydrogen. Stacking tantalum nitride and highly conductive tungsten can suppress diffusion of hydrogen from the transistor 301 and the like while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0357] A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 74, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. The conductor 366 can be formed using a material similar to that of the conductors 328, 329, and 330.

[0358] Note that, for example, the insulator 360 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 301 and the like can be separated from the memory element MC by a barrier layer, and diffusion of hydrogen from the transistor 301 and the like to the memory element MC can be suppressed.

[0359] An insulator 722 is provided on the insulator 364 and the conductor 366, and the memory array 220 is provided above the insulator 722. A barrier film made of a material similar to that of the insulator 324 may be provided between the insulator 364 and the insulator 722.

[0360] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0361] (Embodiment 6) In this embodiment, an example of a chip 1200, which is a type of semiconductor device on which a memory device of the present invention is mounted, is shown using Figures 76A and 76B. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this way is sometimes called a system on chip (SoC).

[0362] As shown in FIG. 76A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0363] Chip 1200 is provided with bumps (not shown), which are connected to a first surface of a printed circuit board (PCB) 1201 as shown in Fig. 76B. In addition, a plurality of bumps 1202 are provided on the backside of the first surface of PCB 1201, which is connected to a motherboard 1203.

[0364] The motherboard 1203 may be provided with a storage device such as a DRAM 1221 or a flash memory 1222. The semiconductor device described in the above embodiment is preferably used as the flash memory 1222. By using the semiconductor device described in the above embodiment for the flash memory 1222, the storage capacity of the flash memory 1222 can be increased.

[0365] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. The GPU 1212 is suitable for parallel calculation of a large amount of data, and can be used for image processing and multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit and a multiply-and-accumulate operation circuit, it becomes possible to perform image processing and multiply-and-accumulate operations with low power consumption.

[0366] Furthermore, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, enabling high-speed data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of the calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212.

[0367] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0368] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0369] The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include a mouse, keyboard, game controller, etc. As such an interface, a USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0370] The network circuit 1216 includes a network circuit for connecting to a LAN (Local Area Network), etc. It may also include a circuit for network security.

[0371] The above circuits (systems) can be formed in the same manufacturing process on the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0372] A PCB 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided can be called a GPU module 1204.

[0373] The GPU module 1204 includes the chip 1200 using SoC technology, allowing for a small size. Furthermore, due to its superior image processing capabilities, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, a multiply-and-accumulate circuit using the GPU 1212 can execute techniques such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0374] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0375] (Embodiment 7) In this embodiment, an application example of a semiconductor device using the storage device described in the previous embodiment will be described. The storage device described in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid state drives). Figures 77A to 77E schematically show several configuration examples of removable storage devices. For example, the semiconductor device described in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0376] 77A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The memory chip 1105 or the like can be incorporated with the storage device or semiconductor device described in the above embodiments.

[0377] FIG. 77B is a schematic diagram of the appearance of an SD card, and FIG. 77C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. The capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the substrate 1113. Furthermore, a wireless chip with a wireless communication function may be provided on the substrate 1113. This enables reading and writing of data from and to the memory chip 1114 through wireless communication between a host device and the SD card 1110. The memory device or semiconductor device described in the above embodiments can be incorporated into the memory chip 1114 or the like.

[0378] FIG. 77D is a schematic diagram of the appearance of an SSD, and FIG. 77E is a schematic diagram of the internal structure of the SSD. SSD 1150 has a housing 1151, a connector 1152, and a board 1153. Board 1153 is housed in housing 1151. For example, memory chips 1154, 1155, and a controller chip 1156 are attached to board 1153. Memory chip 1155 is a work memory for controller chip 1156, and may be, for example, a DOSRAM chip. By providing a memory chip 1154 on the back side of board 1153, the capacity of SSD 1150 can be increased. The storage device or semiconductor device described in the previous embodiments can be incorporated into memory chip 1154 or the like.

[0379] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0380] (Embodiment 8) 78A to 78G illustrate specific examples of electronic devices equipped with a memory device or a semiconductor device according to one embodiment of the present invention.

[0381] <Electronic devices and systems> The memory device or semiconductor device according to one embodiment of the present invention can be incorporated into various electronic devices. Examples of the electronic devices include information terminals, computers, smartphones, e-book readers, televisions, digital signage, large game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, recording and playback devices, navigation systems, and audio playback devices. Note that the term "computer" as used herein includes tablet computers, notebook computers, desktop computers, and large computers such as server systems.

[0382] The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0383] An electronic device according to one embodiment of the present invention may have a sensor (including a function for measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0384] The electronic device of one embodiment of the present invention can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display portion, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, etc.

[0385] [Information terminal] A memory device for storing programs of a microcontroller can be formed using a memory device or a semiconductor device according to one embodiment of the present invention, and therefore, according to one embodiment of the present invention, the size of a microcontroller chip can be reduced.

[0386] FIG. 78A illustrates a mobile phone (smartphone), which is one type of information terminal. The information terminal 5100 includes a housing 5101 and a display portion 5102. As input interfaces, a touch panel is provided on the display portion 5102 and buttons are provided on the housing 5101. By using a miniaturized microcontroller according to one embodiment of the present invention, the limited space inside the mobile phone can be effectively utilized. Furthermore, a storage device according to one embodiment of the present invention may be used for storage of the mobile phone. This allows the storage capacity per unit area of ​​the storage to be increased.

[0387] FIG. 78B illustrates a notebook information terminal 5200. The notebook information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203. By using a miniaturized microcontroller according to one embodiment of the present invention, the limited space inside the notebook information terminal can be effectively utilized. Furthermore, a storage device according to one embodiment of the present invention may be used for storage of the notebook information terminal. This allows the storage capacity per unit area of ​​the storage to be increased.

[0388] In the above description, a smartphone and a notebook type information terminal are illustrated as examples of electronic devices in Figures 78A and 78B, but information terminals other than smartphones and notebook type information terminals can also be applied. Examples of information terminals other than smartphones and notebook type information terminals include PDAs (Personal Digital Assistants), desktop type information terminals, and workstations.

[0389] [Game consoles] FIG. 78C illustrates a portable game console 5300, which is an example of a game console. The portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display portion 5304, a connection portion 5305, operation keys 5306, and the like. The housings 5302 and 5303 can be detached from the housing 5301. By attaching the connection portion 5305 of the housing 5301 to another housing (not shown), the video displayed on the display portion 5304 can be output to another video device (not shown). In this case, the housings 5302 and 5303 can each function as an operation portion. This allows multiple players to play a game simultaneously. A memory device or a semiconductor device according to one embodiment of the present invention can be incorporated into chips or the like provided on the substrates of the housings 5301, 5302, and 5303.

[0390] 78D shows an example of a game machine, a stationary game machine 5400. A controller 5402 is connected to the stationary game machine 5400 wirelessly or via a wire.

[0391] By using a miniaturized microcontroller according to one embodiment of the present invention in a game console such as a portable game console 5300 or a stationary game console 5400, it is possible to effectively utilize the limited space inside the game console. Furthermore, a storage device or a semiconductor device according to one embodiment of the present invention may be used for storage in the portable game console. This allows the storage capacity per unit area of ​​the storage to be increased.

[0392] 78C and 78D show a portable game machine and a stationary game machine as examples of game machines, but game machines to which the microcontroller of one embodiment of the present invention is applied are not limited to these. Examples of game machines to which the microcontroller of one embodiment of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0393] [Mainframe Computer] A memory device or a semiconductor device according to one embodiment of the present invention can be applied to a large-scale computer.

[0394] 78E is a diagram showing a supercomputer 5500, which is an example of a mainframe computer. FIG. 78F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.

[0395] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. The computer 5502 is provided with a plurality of boards 5504, and a microcontroller according to one embodiment of the present invention can be mounted on the board. By using a miniaturized microcontroller according to one embodiment of the present invention, the limited space of a large computer can be effectively utilized. Furthermore, a storage device or a semiconductor device according to one embodiment of the present invention may be used for storage of the large computer. This allows the storage capacity per unit area of ​​the storage to be increased.

[0396] 78E and 78F illustrate a supercomputer as an example of a mainframe computer, but the mainframe computer to which the microcontroller according to an embodiment of the present invention is applied is not limited to this. Examples of mainframe computers to which the microcontroller according to an embodiment of the present invention is applied include computers that provide services (servers) and large general-purpose computers (mainframes).

[0397] [electric appliances] 78G shows an example of an electric appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0398] A memory device or a semiconductor device according to one embodiment of the present invention can also be applied to an electric refrigerator-freezer 5800. For example, by applying a miniaturized microcontroller according to one embodiment of the present invention to the electric refrigerator-freezer 5800, the limited space of the electric refrigerator-freezer can be effectively utilized.

[0399] Although electric refrigerator-freezers have been described as an example of electrical appliances, other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0400] The electronic devices, functions, effects, and the like described in this embodiment can be combined as appropriate with descriptions of other electronic devices.

[0401] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes. [Explanation of symbols]

[0402] 100: memory device, 105: region, 110: memory cell array, 120: memory string, 121: substrate, 122: conductor, 123: insulator, 124: insulator, 125: semiconductor, 126: insulator, 127: semiconductor, 128: conductor, 129: insulator, 130: conductor, 141: opening, 142: region, 143: region

Claims

1. a first conductor having a region that functions as a first gate electrode of a first transistor; a second conductor having a region that functions as a first electrode of the capacitor; a third conductor having a region that functions as a first gate electrode of the second transistor; a fourth conductor having a region that functions as a second gate electrode of the second transistor; a first insulator having a region that functions as a first gate insulating film of the first transistor; a second insulator having a region that functions as a second gate insulating film of the first transistor and a region that functions as a second gate insulating film of the second transistor; a third insulator having a region that functions as a first gate insulating film of the second transistor; a fourth insulator; and a first semiconductor having a channel formation region of the first transistor; a second semiconductor having a region that functions as a second gate electrode of the first transistor and a second electrode of the capacitance element, and a channel formation region of the second transistor; the first conductor extends in a first direction; On a side surface of the first conductor extending in the first direction, The first insulator has a region in contact with the first conductor; The first semiconductor has a region in contact with the first insulator; The second insulator has a region in contact with the first semiconductor; The second semiconductor has a region in contact with the second insulator; The third insulator has a region in contact with the second semiconductor, the first conductor has a first region and a second region; In the first region, the second conductor has a region in contact with the third insulator, In the second region, the third conductor has a region in contact with the third insulator, In the second region, the fourth conductor has a region located between the first insulator and the first semiconductor, A memory device, wherein on a side of the fourth insulator extending in the first direction, the fourth insulator has a region in contact with the first conductor, a region in contact with the first insulator, a region in contact with the first semiconductor, a region in contact with the second insulator, a region in contact with the second semiconductor, a region in contact with the third insulator, a region in contact with the second conductor, a region in contact with the third conductor, and a region in contact with the fourth conductor.

2. the first semiconductor is an oxide semiconductor, the second semiconductor is an oxide semiconductor; The storage device according to claim 1 .

3. the first semiconductor includes at least one of indium and zinc; the second semiconductor contains at least one of indium and zinc; The storage device according to claim 2 .

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