Integration of variable rate shading and supersampling shading

Abstract

Provided herein is a technique for performing rasterization and pixel shading at decoupled resolutions. The technique involves performing normal rasterization to generate quads. Accumulating the quads in a tile buffer. Determining a shading rate for the contents of the tile buffer. Downsampling the quads in the tile buffer if the shading rate is a subsampling shading rate reduces the work performed by the pixel shader. The shaded, downsampled quads are then restored to the resolution of the render target. If the shading rate is a supersampling shading rate, upsample the quads in the tile buffer. Writing the resulting shaded, downsampled quads or upsampled quads to a render target.

Description

Technical Field

[0001] (Cross - reference to Related Applications) This application claims the benefit of U.S. Patent Application No. 16 / 228,692, filed on December 20, 2018, the content of which is incorporated herein by reference.

Background Art

[0002] A three - dimensional (3D) graphics processing pipeline performs a series of steps to convert an input geometric shape into a two - dimensional (2D) image for display on a screen. Some of these steps include rasterization and pixel shading. Rasterization involves identifying pixels (or sub - pixel samples) covered by triangles provided by a stage of the pipeline before the rasterizer. The output of rasterization includes quads (2×2 pixel blocks) and coverage data indicating the samples covered by the pixels of the quad. The pixel shader shades the pixels of the quad and writes the pixels of the quad into the frame buffer. Pixel shading is very resource - intensive, so techniques for improving the efficiency of pixel shading are constantly being developed.

[0003] A more detailed understanding can be obtained from the following description given by way of example together with the accompanying drawings.

Brief Description of the Drawings

[0004] [Figure 1] It is a block diagram of an exemplary device capable of implementing one or more features of the present disclosure. [Figure 2] It is a diagram showing details of the device of FIG. 1 according to an example. [Figure 3] It is a block diagram showing further details of the graphics processing pipeline shown in FIG. 2. [Figure 4A] This figure illustrates a technique for performing rasterization at a different resolution than pixel shading, as an example. [Figure 4B] This figure illustrates a technique for performing rasterization at a different resolution than pixel shading, as an example. [Figure 4C] This figure illustrates a technique for performing rasterization at a different resolution than pixel shading, as an example. [Figure 4D] This figure illustrates a technique for performing rasterization at a different resolution than pixel shading, as an example. [Modes for carrying out the invention]

[0005] This specification provides a technique for performing rasterization and pixel shading at a decoupled resolution. This technique includes performing normal rasterization to generate quads. The quads are stored in a tile buffer. The shading rate of the contents of the tile buffer is determined. If the shading rate is a subsampling shading rate, the quads in the tile buffer are downsampled, reducing the amount of work performed by the pixel shader. The shaded and downsampled quads are then restored to the resolution of the render target. If the shading rate is a supersampling shading rate, the quads in the tile buffer are upsampled. The result of the shaded and downsampled or upsampled quads is written to the render target.

[0006] Figure 1 is a block diagram of an exemplary device 100 that can implement one or more features of the present disclosure. Device 100 may be, but is not limited to, a computer, a gaming device, a handheld device, a set-top box, a television, a mobile phone, a tablet computer, or other computing device. Device 100 includes a processor 102, memory 104, storage 106, one or more input devices 108, and one or more output devices 110. Device 100 also includes one or more input drivers 112 and one or more output drivers 114. Any of the input drivers 112 may be embodied as hardware, a combination of hardware and software, or software, and serve the purpose of controlling the input device 108 (e.g., controlling its operation, receiving input from the input driver 112, and providing data to the input driver 112). Similarly, the output driver 114 may be embodied as hardware, a combination of hardware and software, or software, and serve the purpose of controlling the output device 110 (for example, controlling its operation, receiving input from the output driver 114, and providing data to the output driver 114). It should be understood that device 100 may include additional components not shown in Figure 1.

[0007] In various alternatives, the processor 102 includes a central processing unit (CPU), a graphics processing unit (GPU), a CPU and a GPU located on the same die, or one or more processor cores, each of which may be a CPU or a GPU. In various alternatives, the memory 104 may be located on the same die as the processor 102, or it may be located separately from the processor 102. The memory 104 includes volatile memory or non-volatile memory (e.g., random access memory (RAM), dynamic RAM, cache, etc.).

[0008] Storage 106 includes fixed or removable storage (e.g., hard disk drives, solid-state drives, optical discs, or flash drives, etc.). Input device 108 includes, but is not limited to, a keyboard, keypad, touchscreen, touchpad, detector, microphone, accelerometer, gyroscope, biometric scanner, or network connectivity (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE 802 signals). Output device 110 includes, but is not limited to, a display, speaker, printer, haptic feedback device, one or more lights, antenna, or network connectivity (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE 802 signals).

[0009] The input driver 112 and output driver 114 include one or more hardware, software, and / or firmware components configured to interface with and drive the input device 108 and output device 110. The input driver 112 communicates with the processor 102 and the input device 108, enabling the processor 102 to receive input from the input device 108. The output driver 114 communicates with the processor 102 and the output device 110, enabling the processor 102 to send output to the output device 110. The output driver 114 includes an accelerated processing device (APD) 116, which in some examples is connected to a display device 118, which is a physical display device or a simulated device that uses the Remote Display Protocol to display the output. The APD 116 is configured to receive calculation commands and graphic rendering commands from the processor 102, process these calculation commands and graphic rendering commands, and provide pixel output to the display device 118 for display. As will be described in more detail below, the APD116 includes one or more parallel processing units configured to perform computations according to a single-instruction multiple-data (SIMD) paradigm. Thus, although various functions are described herein as being performed by or with the APD116, in various alternative examples, the functions described as being performed by the APD116 are not driven by a host processor (e.g., processor 102) and are additionally or alternatively performed by other computing devices having similar functions, configured to provide graphical output to the display device 118. For example, any processing system that performs processing tasks according to a SIMD paradigm may be configured to perform the functions described herein. Alternatively, a computing system that does not perform processing tasks according to a SIMD paradigm may perform the functions described herein.

[0010] Figure 2 shows details of device 100 and APD 116 in an example. Processor 102 (Figure 1) runs the operating system 120, driver 122, and application 126, and may run other software alternatively or additionally. The operating system 120 controls various aspects of device 100 (e.g., managing hardware resources, processing service requests, scheduling and controlling process execution, and other operations). The APD driver 122 controls the operation of APD 116 and sends tasks such as graphics rendering tasks and other operations to APD 116 for processing. The APD driver 122 also includes a just-in-time compiler that compiles programs for execution by the processing components of APD 116 (such as the SIMD unit 138, which will be described in more detail below).

[0011] The APD116 executes commands and programs for selected functions, such as graphics operations and non-graphics operations, that are suitable for parallel processing. Based on commands received from the processor 102, the APD116 is used to perform graphics pipeline operations, such as pixel manipulation and geometric calculations, and to render images to the display device 118. The APD116 also performs computational processing operations that are not directly related to graphics operations, such as video, physical simulations, computational fluid dynamics, or other tasks, based on commands received from the processor 102.

[0012] The APD116 includes a compute unit 132 which includes one or more SIMD units 138 configured to execute operations in parallel in response to requests from the processor 102 (or another unit) according to the SIMD paradigm. The SIMD paradigm allows multiple processing elements to share a single program control flow unit and program counter, thereby enabling them to execute the same program but with different data. In one example, each SIMD unit 138 includes 16 lanes, and each lane can execute the same instruction simultaneously with other lanes in the SIMD unit 138, but with different data. If not all lanes need to execute a given instruction, lanes may be turned off using predication. Predication may be used to execute a program with branching control flows. More specifically, in the case of a program with conditional branches or other instructions where the control flow is based on calculations performed by individual lanes, predication of lanes corresponding to control flow paths not currently being executed, and sequential execution of different control flow paths, enables arbitrary control flows.

[0013] The basic unit of execution in the compute unit 132 is a work item. Each work item represents a single instance of a program to be executed in parallel on a specific lane. Work items may be executed simultaneously (or partially simultaneously and partially sequentially) as a "wavefront" on a single SIMD processing unit 138. One or more wavefronts are part of a "workgroup" which contains a set of work items designated to run the same program. A workgroup is executed by executing each of the wavefronts that make up the workgroup. In an alternative example, a wavefront may be executed on a single SIMD unit 138 or on different SIMD units 138. A wavefront may be thought of as the largest set of work items that can be executed simultaneously (or pseudo-simultaneously) on a single SIMD unit 138. "Pseudo-simultaneous" execution occurs when there are more wavefronts than there are lanes in the SIMD unit 138. In such a situation, the wavefront is executed over multiple cycles, and different sets of work items are executed in different cycles. The APD scheduler 136 is configured to perform various workgroup and wavefront scheduling operations on the compute unit 132 and the SIMD unit 138.

[0014] The parallelism provided by the computing unit 132 is suitable for graphics-related operations such as pixel value calculation, vertex transformation, and other graphics operations. Therefore, in some examples, the graphics pipeline 134, which receives graphics processing commands from the processor 102, provides the computing unit 132 with computation tasks to be executed in parallel.

[0015] The compute unit 132 is also used to perform computational tasks that are not related to graphics, or computational tasks that are not performed as part of the "normal" operation of the graphics pipeline 134 (for example, custom operations performed to supplement the processing performed for the operation of the graphics pipeline 134). An application 126 or other software running on the processor 102 sends a program that defines such computational tasks to the APD 116 for execution.

[0016] Figure 3 is a block diagram showing further details of the graphics processing pipeline 134 shown in Figure 2. The graphics processing pipeline 134 includes stages, each performing a specific function of the graphics processing pipeline 134. Each stage is partially or completely implemented as a shader program executed on a programmable computing unit 132, or partially or completely implemented as non-programmable hardware of fixed functions outside the computing unit 132.

[0017] The input assembler stage 302 reads primitive data from a user-filled buffer (for example, a buffer filled at the request of software executed by processor 102, such as application 126) and assembles this data into primitives to be used by the rest of the pipeline. The input assembler stage 302 can generate different types of primitives based on the primitive data contained in the user-filled buffer. The input assembler stage 302 formats the assembled primitives for use by the rest of the pipeline.

[0018] The vertex shader stage 304 processes the vertices of the primitive assembled by the input assembler stage 302. The vertex shader stage 304 performs various per-vertex operations, such as transformations, skinning, morphing, and per-vertex lighting. Transformation operations include various operations for transforming vertex coordinates. These operations include one or more of the following: modeling transformations, view transformations, projection transformations, perspective divisions, and viewport transformations that change vertex coordinates, as well as other operations that change attributes other than coordinates.

[0019] The vertex shader stage 304 is partially or completely implemented as a vertex shader program that runs on one or more computing units 132. The vertex shader program is provided by the processor 102 and is based on a program pre-written by a computer programmer. The driver 122 compiles such a computer program to generate a vertex shader program in a format suitable for execution within the computing units 132.

[0020] The hull shader stage 306, tessellator stage 308, and domain shader stage 310 work together to perform tessellation, transforming simple primitives into more complex ones by subdividing them. The hull shader stage 306 generates patches for tessellation based on the input primitives. The tessellator stage 308 generates a sample set for the patches. The domain shader stage 310 calculates the vertex positions of the vertices corresponding to the samples for the patches. The hull shader stage 306 and domain shader stage 310, like the vertex shader stage 304, can be implemented as shader programs that run on the compute unit 132, which is compiled by the driver 122.

[0021] The geometry shader stage 312 performs vertex operations for each primitive. The geometry shader stage 312 can perform various different types of operations, including, for example, point sprite expansion, dynamic particle system operations, fur-fin generation, shadow volume generation, single-pass rendering to a cubemap, per-primitive material swapping, per-primitive material setting, etc. In some examples, a geometry shader program compiled by the driver 122 and executed on the compute unit 132 performs the operations of the geometry shader stage 312.

[0022] The rasterizer stage 314 accepts and rasterizes the simple primitives (triangles) generated upstream of the rasterizer stage 314. Rasterization consists of determining which screen pixels (or sub-pixel samples) are covered by a particular primitive. Rasterization is performed by fixed-function hardware.

[0023] The pixel shader stage 316 calculates the output values of the screen pixels based on the primitives generated upstream and the results of rasterization. The pixel shader stage 316 may apply textures from texture memory. The operations of the pixel shader stage 316 are performed by a pixel shader program compiled by the driver 122 and executed on the compute unit 132.

[0024] The output merger stage 318 accepts the output from the pixel shader stage 316, merges these outputs into the frame buffer, and determines the final color of the screen pixels by performing operations such as z-test (z-test) and alpha blending.

[0025] In one operating mode, the rasterization performed by the rasterizer stage 314 is performed at the same resolution as the pixel shading performed by the pixel shader stage 316. As background, the rasterizer stage 314 receives triangles from the previous stage and performs a scan transformation on these triangles to generate fragments. These fragments are data about individual pixels of the render target, including information such as position, depth, coverage data, and shading data (e.g., color) after the subsequent pixel shader stage. The render target is the destination image being rendered (i.e., having color or other values ​​written to it).

[0026] Generally, fragments are grouped into quads, and each quad contains fragments corresponding to four adjacent pixel positions (i.e., 2x2 fragments). The triangle scan transform involves generating a fragment for each pixel position covered by the triangle. If the render target is a multisample image, each pixel has multiple sample positions, and each of the sample positions is tested for coverage. The fragments record coverage data for the samples of that fragment. The fragments generated by the rasterizer stage 314 are sent to the pixel shader stage 316, which shades the fragments (determines the color values ​​of these fragments) and may also determine other values.

[0027] Performing rasterization and pixel shading at the same resolution means that for each fragment generated by the rasterizer, the pixel shader 316 performs a calculation to determine the color of that fragment. In other words, the area of ​​screen space occupied by a pixel is the same area as the precision required to determine the color. For example, in the SIMD-based hardware of the computing unit 132, each fragment generated by the rasterizer stage 314 is shaded by a different work item. Therefore, there is a one-to-one correspondence between the generated fragments and the work items spawned to shade those fragments. Generally, note that the rasterizer stage 314 performs depth tests and culling fragments occupied by previously rendered fragments. Therefore, there is a one-to-one correspondence between the fragments that remain after this depth culling and the work items spawned to color these remaining fragments, although additional work items may be spawned to render helper fragments of quads that are ultimately discarded. Helper fragments are fragments that are not covered by triangles but are generated as part of a quad in some way to assist in calculating the derivatives of texture sampling. Another way to understand the operating mode in which rasterization is performed at the same resolution as shading is that the resolution at which the edges of a triangle can be defined is equal to the resolution at which the color of that triangle can be defined.

[0028] One problem with the above operating modes is that for triangles with fixed or infrequently changing colors, rasterization occurs at the same resolution as pixel shading. In such triangles, the pixel shading operations of nearby fragments produce the same or similar colors, resulting in substantial redundancy. Therefore, a similar result can be obtained by significantly reducing the number of pixel shader operations. Thus, it is advantageous to reduce the shading resolution relative to the rasterization resolution, according to a technique referred to herein as Variable Rate Shading (VRS). The advantage of such a technique is that the number of pixel shader operations is reduced, thereby reducing the processing load and improving performance. VRS will be discussed in more detail later.

[0029] One issue with VRS is the integration of this technology with supersampling anti-aliasing (SSAA). SSAA is a technique in which each pixel of the render target has multiple coverages and color samples. More specifically, in this technique, the graphics processing pipeline 134 performs both rasterization and shading at a resolution higher than the resolution of the render target to generate a supersampling image. The graphics processing pipeline 134 then "resolves" this supersampling image using anti-aliasing technology to generate an image at the resolution of the render target.

[0030] The problem arises in systems capable of performing both VRS and SSAA. Specifically, in one embodiment, it is possible to switch both VRS and SSAA so that VRS operates to reduce the shading resolution relative to the render target resolution, and SSAA operates to increase the shading resolution relative to the render target resolution. This mode of operation may be undesirable because it can lead to undefined or unexpected results. Therefore, techniques for integrating SSAA and VRS into a graphics processing pipeline 134 are described herein.

[0031] Figure 4 illustrates a technique for rasterizing, shading, and outputting a rendered image using either SSAA, VRS, or neither. This technique begins in step 402, where the rasterizer stage 314 rasterizes triangles received from previous stages in the graphics processing pipeline 134 to determine the covered samples and generate fragments containing indicators of these covered samples. Rasterization generates one fragment for each pixel within the render target enclosed by triangles. A fragment is a group of data corresponding to a single pixel, containing information such as sample coverage, per-sample color data (after the pixel shader stage), per-sample depth data, and possibly other types of data. The fragments are used to color the pixels in the frame buffer within the output merger stage 318. A sample is a point within a screen pixel, and information such as coverage, depth, and color information for this point can be individually determined. In some operating modes, there are multiple samples per pixel in the render target. Generally, the purpose of including multiple samples per pixel of the render target is to perform anti-aliasing, which improves the appearance of hard edges in the image. In other operating modes, there is only one sample per pixel of the render target.

[0032] In step 402, the rasterizer stage 314 determines which samples are covered and which are not covered by the received primitive. Generally, the rasterizer stage 314 receives triangles from the previous stage of the graphics processing pipeline 134 and rasterizes these triangles to generate fragments. Rasterizing triangles involves determining which pixels of the render target are covered by the triangles, and, if there are multiple samples per pixel, determining which samples within those covered pixels are covered by the triangles. Any technically feasible technique can be used to rasterize triangles. A fragment is generated for each pixel covered by one sample.

[0033] In step 402, the rasterizer stage 314 also performs a depth test. For example, the depth test includes checking the depth value for each sample covered by a triangle and comparing these depth values ​​to the depth values ​​of already processed triangles stored in the depth buffer. The depth value of a particular sample is compared to the depth value stored in the depth buffer for the same location as this particular sample. If the depth buffer indicates that the sample is occluded, the sample is marked as uncovered; if the depth buffer indicates that the sample is not occluded, the sample remains. For subsequent processing, as described elsewhere in this description, data indicating the covered and unoccluded sample locations is passed to other parts of the graphics processing pipeline 134. In this specification, the term “covered” where a sample is applied means that the sample is covered by a triangle and passes the depth test; the terms “uncovered” or “uncovered” mean that the sample is not covered by a triangle or is covered by a triangle but does not pass the depth test.

[0034] Rasterization outputs 2x2 groups of fragments known as quads. More specifically, rasterizer stage 314 generates a fragment for each pixel of the render target, containing at least one sample covered by a triangle. Rasterizer 314 generates quads from these fragments. A quad contains fragments from adjacent sections of 2x2 pixels, even if one or more such fragments are not completely covered by a triangle (where "not completely covered" means that the sample of the fragment is not covered and occluded by a triangle). Fragments that are not completely covered are called helper fragments. Helper fragments are used by pixel shader stage 316 to calculate spatial derivatives of the shading. Often, these spatial derivatives are used for texture mipmap selection and texture filtering, but spatial derivatives can be used for other purposes.

[0035] Furthermore, in step 402, the rasterizer stage 314 determines one or more shading rates for the triangular samples. The shading rate may be a subsampling shading rate, a one-to-one shading rate, or a supersampling shading rate. A subsampling shading rate means that the resolution of the pixel shading is lower than the resolution of the render target (excluding the sample resolution). A one-to-one shading rate means that the resolution of the pixel shading is the same as the resolution of the render target. A supersampling shading rate means that the resolution of the pixel shading is higher than the resolution of the render target. Note that the resolution of the pixel shading may differ from the resolution of the rasterization (coverage determination), even when using a supersampling shading rate. Specifically, the rasterizer determines sample coverage for a specific number of samples per pixel, and pixel shading can occur at a rate lower than that number of samples. For example, rasterization may occur for four samples per fragment, but pixel shading may occur only twice per fragment.

[0036] Pixel shading resolution, also known as shading rate, defines the number of fragments that are shaded together in the pixel shader stage 316. More specifically, in the case of subsampling, the pixel shading resolution determines how many pixel positions in the render target are given a color determined by a single work item in the pixel shader stage 316. For example, if the shading rate is 1 / 4, the work item in the pixel shader stage 316 determines the color for 4 pixel positions in the render target. In supersampling, the pixel shading resolution determines the number of samples in a given fragment to which the color determined by a single work item is given. For example, if the pixel shading resolution is "4x", four different work items determine the color for 4 different samples per fragment generated by the rasterizer stage 314.

[0037] The shading rate can be determined per triangle, per shading rate tile, or per shading rate tile for individual triangles. In the case of per-triangle shading, a unit in the graphics processing pipeline 134 upstream of the pixel shader determines the shading rate of the triangles sent to the rasterizer stage 314. In one example, the vertex shader stage 304 determines the shading rate of the triangles processed at that stage. In another example, the geometry shader stage 312 determines the shading rate of the triangles output at that stage. In the case of per-shading rate tile shading, the rasterizer stage 314 determines the shading rates of different shading rate tiles of the render target. The render target is divided into shading rate tiles, each containing multiple pixels of the render target. More specifically, the render target is "tiled" into shading rate tiles, each tile may have a different shading rate. Any technically feasible technique can be used to determine the shading rate of a shading rate tile. In one example, a shading rate tile image is used. A shading rate tile image contains information about different shading rate tiles for a render target, indicating the shading rate of the shading rate tile. Shading rate images can be specified explicitly by the application or by algorithm.

[0038] In tile-based shading for individual triangles, a combination of tile-based and triangle-based shading rate information is used to determine the shading rate for a given quad. Specifically, each triangle is associated with a triangle shading rate image that defines the shading rates for different parts of the triangle.

[0039] The size of the shading rate tiles can be the same as the number of pixels of the render target covered by the tile buffer, or it can be larger than the buffer. However, the contents of the tile buffer at any given time will have the same shading rate.

[0040] In step 404, the rasterizer stage 314 stores the quads generated as a result of rasterization in step 402 in the tile buffer 510. The tile buffer can store any number of quads that is technically feasible. For example, the tile buffer stores four adjacent quads in a 2x2 array. The quads in the tile buffer correspond to contiguous portions of the render target. This allows for downsampling of quads to fewer quads when using VRS. After storing the quads in the tile buffer, the rasterizer stage 314 triggers step 406. Note that this trigger may occur even if at least a portion of the tile buffer 510 is empty. More specifically, the tile buffer 510 stores quads from contiguous portions of screen space from the same triangle. Coverage may exist in different parts of that contiguous portion, but coverage of a particular triangle may not exist in at least some parts of that contiguous portion. In this situation, step 406 uses a non-full tile buffer 510 (to generate a quad with a modified rate based on the shading rate).

[0041] In step 406, the rasterizer stage 314 inspects the contents of the tile buffer 510 and generates a modified-rate quad based on the shading rate. There are three ways this can happen. As mentioned above, for any specific instance of the contents of the tile buffer, a shading rate is defined for all of its contents. This shading rate may be a subsampling rate, a 1:1 rate, or a supersampling rate. If the shading rate is a subsampling rate, the rasterizer stage 314 downsamples the quad of the tile buffer 510 to generate a modified-rate quad. The resulting downsampled quad contains coarser fragments that are larger than the pixels of the render target. The purpose of downsampling the quad is to reduce the number of pixel shader work items generated to shade the fragment. Specifically, since the pixel shader invokes one work item per fragment, larger fragments result in fewer work items being generated, and the shading workload is completed faster.

[0042] At subsampling shading rates, the amount of coverage information available to the downsampled quad may be insufficient to represent the full resolution of the quad's coverage data in the tile buffer 510. In such cases, downsampling also involves compressing the coverage data.

[0043] If the shading rate is 1:1, the rasterizer stage 314 simply outputs the quads of the unchanged tile buffer 510 as quads of the changed rate.

[0044] If the shading rate is the supersampling rate, the rasterizer stage 314 upsamples the quads in the tile buffer 510 to generate quads at the modified rate. The resulting upsampled quads contain more quads than the quads in the tile buffer 510. The coefficient by which the number of quads increases is equal to the supersampling rate.

[0045] In step 408, the rasterizer stage 314 assigns a centroid position to the quad fragment. This method depends on several factors, including the shading rate, the number and position of samples in the quad's tile buffer, and other factors. This centroid is the position where pixel attributes, such as texture coordinates, are evaluated.

[0046] In step 410, the pixel shader stage 316 shades the quad fragments. One work item is generated for each fragment, as described elsewhere in this specification. The pixel shader shades the fragments using the centroid determined in step 408. The pixel shader can also change the coverage for any particular fragment by, for example, switching one or more samples of the fragment from covered to uncovered, or from uncovered to covered. In one example, the pixel shader sets a particular covered sample to be uncovered by determining that the alpha value corresponding to that sample is completely transparent (e.g., has an alpha value of 0). The above is just an example, and it should be understood that a pixel shader program that an application developer can write may change the coverage in a way that is technically feasible.

[0047] In step 412, if the quads have been downsampled, the output merger stage 318 restores the original resolution of these quads, including applying finer coverage data from the rasterizer stage 314. Further details are provided in relation to Figure 4D.

[0048] In step 414, the output merger stage 318 performs the second half of the pixel operations and writes the quad samples to the framebuffer. If the shaded quad was downsampled (i.e., VRS was used), the output merger stage 318 writes the quad data restored in step 412. If the shaded quad was upsampled, or if a 1:1 shading rate was used, the render target is shaded using the quad data output by the pixel shader 316.

[0049] Figure 4B illustrates the operation of generating a modified shading rate quad based on the contents of a tile buffer 510 at a supersampling shading rate, as an example. In other words, Figure 4B represents the operation of step 406 with respect to the supersampling shading rate. The tile buffer 510 is shown in its state after accumulating the quads generated in rasterizer stage 314 (step 404). The shading rate determined for the contents of the tile buffer is the supersampling shading rate. This means that pixel shading is performed at a resolution higher than the resolution of the render target. In the example in Figure 4B, the shading rate is 4x, but the teachings herein apply to any supersampling shading rate.

[0050] As illustrated, the tile buffer 510 contains three quads (the space for quad 1 is empty because there were no covered samples for that quad), each containing four fragments. Each fragment in the tile buffer 510 contains four coverage samples. To generate quads 422 with the modified shading rate, the rasterizer stage 314 generates a number of quads equal to the shading rate for each quad in the tile buffer 510 that has at least one sample covered. Each fragment in the generated quads contains a sample subset of the fragments in the tile buffer 510.

[0051] The ratio of the number of samples in the fragments in the tile buffer 510 to the number of samples in the generated fragments is equal to the shading rate. For a 4x shading rate, the fragments in the tile buffer 510 contain four times the number of samples as the fragments for the changed shading rate. Fragments in a particular generated quad contain samples from the same sample position as the fragments in the corresponding quad in the tile buffer. In one example, each fragment in a generated quad contains a sample at the position of "sample a" in the illustrated pixel template 420. In this example, each generated quad contains a fragment with a sample at the same sample position, and four quads are generated for every quad with at least one covered sample, so that the samples assigned to different quads are different (one per sample). In the illustrated example, quad 1 is empty and no quads for the changed shading rate are generated. Quad 2 generates quads 2a, 2b, 2c, and 2d. The fragment in quad 2a contains sample a from the fragment in quad 2. The fragment of quad2b includes sample b from the fragment of quad2. The fragment of quad2c includes sample c from the fragment of quad2. The fragment of quad2d includes sample d from the fragment of quad2. Quads 3a-3d and 4a-4d derive their samples from quads 3 and quad 4 in a similar manner. Note that the number of coverage samples per fragment may differ from the shading rate. In this case, the fragment of a quad with a modified shading rate will obtain multiple samples from the quad in the tile buffer.

[0052] As illustrated in Figure 4A, after generating the Quad 422 with the modified shading rate, step 408 assigns the centroids of the quad's fragments. These centroids are the positions where attributes such as texture coordinates are evaluated. The centroids of the fragments are assigned based on the sample positions assigned to these fragments. For example, the fragments of quads 2a, 3a, and 4a get their centroids at the position of sample a. Similarly, the fragments of quads 2b, 3b, and 4b get their centroids at the position of sample b, quads 2c, 3c, and 4c get their centroids at the position of sample c, and quads 2d, 3d, and 4d get their centroids at the position of sample d. If the Quad 422 with the modified shading rate contains multiple samples, the centroids are placed at positions representing these samples. In one example, the centroids are at the position of one of the covered samples, midway between the covered samples, or at other positions representing the samples.

[0053] As illustrated with reference to Figure 4A, in step 410, the quad 422 with the modified shading rate is shaded. By shading each fragment of each quad 422 with the modified shading rate using different work items, different colors can be given to samples resulting from a single fragment in the tile buffer 510. The pixel shader stage 316 can also modify coverage, for example, by marking covered samples as uncovered. In step 414, the output merger stage 318 writes the shaded fragments to the render target. Details regarding writing shaded samples to the render target are generally known and are not described in detail herein. Generally, this operation includes performing a z-test to determine whether a sample is occluded by older samples, and, if blending is enabled, mixing the sample's color with the color in the render target. Other operations can also be performed.

[0054] Figure 4C shows an example of the operation of downsampling quads in the tile buffer 510 when a subsampling shading rate (VRS) is used. The downsampling operation involves converting the quads in the tile buffer 510 into one or more quads 440 of a smaller number of modified shading rates. The number of generated quads is equal to the number of quads in the tile buffer 510 multiplied by the shading rate (however, fewer quads may be generated if the tile buffer 510 is not completely filled with quads or if quads with no coverage are generated). In this example, the shading rate is 1 / 4, the number of quads in the tile buffer 510 is 4, and the number of quads generated from these quads is 1 (4 × 1 / 4 = 1).

[0055] Each generated quad contains four fragments. The coverage assigned to each of these fragments is an amalgamation of the coverage assigned to the quad's fragments in the tile buffer 510. In some situations, such amalgamation can result in the fragments of the quad 440 with a modified shading rate containing excessive coverage data. More specifically, the graphics processing pipeline 134 may have a limit on the number of bits that can be used to specify the coverage data of a fragment. In this situation, when the coverage data is amalgamated with the coverage data of the generated quad's fragments, the data loses fidelity (is compressed). The remaining coverage data geometrically represents the coverage of the quad's fragments in the tile buffer 510.

[0056] In the example in Figure 4C, each fragment of the quad in the tile buffer 510 contains four samples. Furthermore, the shading rate is 1 / 4, which means that in the pixel shader stage 316, four of the fragments in the tile buffer 510 are shaded together as a single fragment. Additionally, the pixel shading hardware has a limit on the number of samples that can be processed per fragment, which is eight. Due to these factors, the downsampling operation 442 generates the quad 440 with the modified shading rate in the following way: As a result of the 1 / 4 shading rate, each quad in the tile buffer 510 is converted into a single fragment in the quad 440 with the modified shading rate. Specifically, since each quad contains four fragments and the shading rate is 1 / 4, the four fragments of the quad are converted into a single fragment. Since the tile buffer 510 contains four quads, the contents of the tile buffer 510 are converted into a single quad. Each of the quad's coarse fragments corresponds to four fragments in tile buffer 510.

[0057] Furthermore, since the pixel shader 316 can only process 8 samples per fragment, the 16 samples in each quad in the tile buffer 510 are compressed to 8 samples per coarse fragment. Each sample geometrically represents two samples in the tile buffer 510. Moreover, this compression operation is conservative in that if one or both of the samples corresponding to the compressed sample are covered in the tile buffer 510, then the samples of the coarse fragment are also covered, but if neither sample is covered, then the samples of the coarse fragment are not covered. In the example in Figure 4C, dotted lines are provided in the quad 440 with the modified shading rate to indicate the corresponding areas of the fragments in the tile buffer 510. It can be seen that each sample in these corresponding areas corresponds to two samples in the tile buffer 510. Furthermore, the top-left sample of the coarse fragment portion corresponding to a "fine fragment" corresponds to the two top samples of that fine fragment, and the bottom-right sample of the coarse fragment portion corresponding to a fine fragment corresponds to the two bottom samples of that fine fragment. Note that compression will not occur if the number of samples fused into a single coarse fragment does not exceed the sample limit of that fragment. Also note that while a 1 / 4 shading rate is shown, other shading rates may be used (e.g., 1 / 2 horizontal (rows of two fragments in tile buffer 510 form a quad coarse fragment of the modified shading rate), 1 / 2 vertical (columns of two fragments in tile buffer 510 form a quad coarse fragment of the modified shading rate), or other rates).

[0058] After step 406, a centroid is assigned to the generated quad fragment. The centroid is set for each coarse fragment in a technically feasible way. In one example, the centroid represents the location of the covered sample of the coarse fragment. In another example, the location of any fragment is selected. In yet another example, the center of the coarse fragment is used as the centroid. As mentioned above, the centroid is used as the location where pixel shader stage 316 calculates attributes such as texture coordinates.

[0059] In step 410, the pixel shader stage 316 shades the generated quad fragments. Specifically, one work item is activated for each coarse fragment, and the color (and other attributes) determined for each coarse fragment is applied to each covered sample of that fragment. The pixel shader stage 316 can also change the coverage of the coarse fragments by setting covered samples as uncovered, or uncovered samples as covered, etc.

[0060] In step 412, the output merger stage 318 applies the fine coverage data from the rasterizer stage 314 to the shaded quad to generate fragments at the resolution of the render target. Figure 4D shows an example of this operation. First, the output merger stage 318 upsamples the shaded coarse quad to generate a shaded upsampled quad. To do this, the output merger stage 318 divides each of the coarse fragments into upsampled fragments based on the shading rate. At a shading rate of 1 / 4, each of the coarse fragments is converted into four upsampled fragments. Each sample of the upsampled fragments obtains the color of the original coarse fragment from which these samples originated. Furthermore, if the samples were originally compressed, the sample resolution is restored, and each restored sample obtains the color of the corresponding sample of the coarse fragment. The coverage (covered or uncovered) of each restored sample is the same as the coverage of the corresponding sample of the coarse fragment.

[0061] In Figure 4D, upsampling proceeds as follows: Coarse fragment 1 has no coverage. Therefore, the quad generated from this fragment has no coverage and is discarded. Coarse fragment 2 has color 1, as shown in the figure, and contains 6 covered fragments. The corresponding upsampled quad (quad 2) contains 3 fragments, each with 4 samples covered, and 1 fragment with no covered samples. Each sample in quad 2 has the color of coarse fragment 2. Similarly, quads 3 and quad 4 are generated using the coverage and color of coarse fragments 3 and 4.

[0062] At this point, the coverage data generated by the upsampling operation is modulated using the original coverage data generated by the rasterization stage 314. This modulation is an "AND" operation, in which the output sample is considered covered if both copies of the sample are covered by both the original coverage data and the coverage data from the upsampling operation, and uncovered if one or both samples are not covered in the original coverage data. As a result, the set of quads has the modulated coverage and the colors generated by the pixel shader 316. These quads are written to the render target as usual (e.g., performing depth tests, blending, and other operations to combine the colors of these output quads with the colors in the render target).

[0063] It should be understood that many modifications are possible based on the disclosures herein. While features and elements are described above in specific combinations, each feature or element may be used alone without other features and elements, or in various combinations with or without other features and elements. One example is an alternative technique for populating the tile buffer 510 described above. More specifically, in the technique described above, the rasterizer stage 314 first generates quads and then accumulates these quads in the tile buffer 510. In another technique, the rasterizer stage 314 directly generates quads within the tile buffer 510, thereby eliminating the need to perform two separate steps: generating the quads and then accumulating these quads within the tile buffer 510.

[0064] The provided method may be implemented in a general-purpose computer, processor, or processor core. Suitable processors include, by example, general-purpose processors, dedicated processors, conventional processors, digital signal processors (DSPs), multiple microprocessors, one or more microprocessors associated with a DSP core, controllers, microcontrollers, application-specific integrated circuits (ASICs), field-programmable gate array (FPGA) circuits, any other type of integrated circuit (IC), and / or state machines. Such processors may be manufactured by configuring a manufacturing process using the results of processed hardware description language (HDL) instructions and other intermediate data, including netlists (such instructions may be stored in a computer-readable medium). The results of such processing may be maskwork used in a semiconductor manufacturing process to manufacture a processor implementing an aspect of this embodiment.

[0065] The methods or flowcharts provided herein may be implemented in computer programs, software, or firmware embedded on non-temporary computer-readable storage media for execution by a general-purpose computer or processor. Examples of non-temporary computer-readable storage media include read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as built-in hard disks and removable disks, magneto-optical media, optical media (such as CD-ROM discs), and digital multi-purpose discs (DVDs).

Claims

1. A method for performing pixel shading and rasterization at different resolutions, The first set of quads is stored in the tile buffer, The process involves generating a first set of quads with a modified shading rate at a subsampling rate from a first set of quads stored in the tile buffer, wherein the number of quads with a modified shading rate generated from the first set is equal to the number of quads in the first set of quads stored in the tile buffer multiplied by the subsampling rate. The second set of quads is stored in the tile buffer, The process involves generating a second set of quads with a modified shading rate from a second set of quads stored in the tile buffer, wherein the number of quads in the second set of quads with a modified shading rate generated from the second set is equal to the number of quads in the second set of quads stored in the tile buffer multiplied by the supersampling rate. Shading a first set of the modified shading rate quads, wherein the shading is performed at a shading rate corresponding to the subsampling rate. Shading a second set of the modified shading rate quads, wherein the shading is performed at a shading rate corresponding to the supersampling rate, method.

2. The third set of the quads will be shaded at a 1:1 shading rate, The third set of the quads is further shaded without generating a set of quads with a modified shading rate. The method according to claim 1.

3. The method further includes determining whether the first set of the modified quad of shading rates has a subsampling shading rate and the second set of the modified quad of shading rates has a supersampling shading rate, on a triangle-by-triangle basis, on a shading rate tile basis, and on a shading rate tile basis for an individual triangle. The method according to claim 1.

4. For each triangle, it is determined whether the first set of the modified shading rate quads has the subsampling shading rate, or whether the second set of the modified shading rate quads has the supersampling shading rate. The above decision is, Identifying the shading rate of a triangle, Rasterizing the aforementioned triangle to generate the first set of the quad or the second set of the quad, This includes assigning the shading rate of the triangle to the first set of the quad or the second set of the quad, The method according to claim 3.

5. For each shading rate tile, it is determined whether the first set of the modified shading rate quad has the subsampling shading rate, or whether the second set of the modified shading rate quad has the supersampling shading rate. The above decision is, Identifying the shading rate of the shading rate tile corresponding to the first set of the quad or the second set of the quad, This includes assigning the shading rate of the shading rate tile to the first set of the quad or the second set of the quad, The method according to claim 3.

6. Identifying the shading rate of the shading rate tile includes performing a lookup in the shading rate tile image. The method of claim 5.

7. For each individual triangular shading rate tile, it is determined whether the first set of the modified shading rate quads has the subsampling shading rate, or whether the second set of the modified shading rate quads has the supersampling shading rate. The above decision is, Identifying the shading rate of a triangle, Rasterizing the aforementioned triangle to generate the first set of the quad or the second set of the quad, Identifying the shading rate of the shading rate tile corresponding to the first set of the quad or the second set of the quad, This includes assigning the shading rate of the shading rate tile to the first set of the quad or the second set of the quad, The method according to claim 3.

8. The process further includes writing a second set of shaded quads with the modified shading rate to a render target. The method according to claim 1.

9. The process further includes upsampling a first set of shaded quads of the modified shading rate, and modulating the resulting upsampled quads. The method according to claim 1.

10. A graphics processing pipeline that performs pixel shading and rasterization at different resolutions, tile buffer and Rasterizer Stage and It includes a pixel shader stage, The aforementioned rasterizer stage is The first set of quads is stored in the tile buffer, The process involves generating a first set of quads with a modified shading rate at a subsampling rate from a first set of quads stored in the tile buffer, wherein the number of quads with a modified shading rate generated from the first set is equal to the number of quads in the first set of quads stored in the tile buffer multiplied by the subsampling rate. The second set of quads is stored in the tile buffer, The process involves generating a second set of quads with a modified shading rate from a second set of quads stored in the tile buffer, wherein the number of quads in the second set of quads with a modified shading rate generated from the second set is equal to the number of quads in the second set of quads stored in the tile buffer multiplied by the supersampling rate. It is configured to do the following: The aforementioned pixel shader stage is Shading a first set of the modified shading rate quads, wherein the shading is performed at a shading rate corresponding to the subsampling rate. Shading a second set of the modified shading rate quad, wherein the shading is performed at a shading rate corresponding to the supersampling rate. It is configured to do the following: Graphics processing pipeline.

11. The aforementioned rasterizer stage is The third set of the quads will be shaded at a 1:1 shading rate, With respect to the third set of the quads, the third set of the quads is shaded without generating a set of quads with a modified shading rate. It is configured to do the following: A graphics processing pipeline according to claim 10.

12. The aforementioned rasterizer stage is The system is further configured to determine, on a triangle-by-triangle basis, on a shading rate tile basis, and on a shading rate tile basis for individual triangles, that the first set of the modified shading rate quads has a subsampling shading rate and the second set of the modified shading rate quads has a supersampling shading rate. A graphics processing pipeline according to claim 10.

13. For each triangle, it is determined whether the first set of the modified shading rate quads has the subsampling shading rate, or whether the second set of the modified shading rate quads has the supersampling shading rate. The above decision is, Identifying the shading rate of a triangle, Rasterizing the aforementioned triangle to generate the first set of the quad or the second set of the quad, This includes assigning the shading rate of the triangle to the first set of the quad or the second set of the quad, A graphics processing pipeline according to claim 12.

14. For each shading rate tile, it is determined whether the first set of the modified shading rate quad has the subsampling shading rate, or whether the second set of the modified shading rate quad has the supersampling shading rate. The above decision is, Identifying the shading rate of the shading rate tile corresponding to the first set of the quad or the second set of the quad, This includes assigning the shading rate of the shading rate tile to the first set of the quad or the second set of the quad, A graphics processing pipeline according to claim 12.

15. Identifying the shading rate of the shading rate tile includes performing a lookup in the shading rate tile image. A graphics processing pipeline according to claim 14.

16. For each individual triangular shading rate tile, it is determined whether the first set of the modified shading rate quads has the subsampling shading rate, or whether the second set of the modified shading rate quads has the supersampling shading rate. The above decision is, Identifying the shading rate of a triangle, Rasterizing the aforementioned triangle to generate the first set of the quad or the second set of the quad, Identifying the shading rate of the shading rate tile corresponding to the first set of the quad or the second set of the quad, This includes assigning the shading rate of the shading rate tile to the first set of the quad or the second set of the quad, A graphics processing pipeline according to claim 12.

17. The system further comprises an output merger stage configured to write a second set of shaded quads of the modified shading rates to a render target. A graphics processing pipeline according to claim 10.

18. The system further comprises an output merger stage configured to upsample a first set of shaded quads of the modified shading rate and to modulate the resulting upsampled quads. A graphics processing pipeline according to claim 10.

19. A processing unit configured to execute a pixel shader program, A graphics processing pipeline that performs pixel shading and rasterization at different resolutions, An accelerated processing device (APD) comprising, The graphics processing pipeline is as follows: tile buffer and Rasterizer Stage and It includes a pixel shader stage, The aforementioned rasterizer stage is The first set of quads is stored in the tile buffer, The process involves generating a first set of quads with a modified shading rate at a subsampling rate from a first set of quads stored in the tile buffer, wherein the number of quads with a modified shading rate generated from the first set is equal to the number of quads in the first set of quads stored in the tile buffer multiplied by the subsampling rate. The second set of quads is stored in the tile buffer, The process involves generating a second set of quads with a modified shading rate from a second set of quads stored in the tile buffer, wherein the number of quads in the second set of quads with a modified shading rate generated from the second set is equal to the number of quads in the second set of quads stored in the tile buffer multiplied by the supersampling rate. It is configured to do the following: The aforementioned pixel shader stage is Shading a first set of the modified shading rate quads, wherein the shading is performed at a shading rate corresponding to the subsampling rate. Shading a second set of the modified shading rate quad, wherein the shading is performed at a shading rate corresponding to the supersampling rate. It is configured to do the following: Accelerated Processing Device (APD).

20. The aforementioned rasterizer stage is It is decided that the third set of the quad will be shaded at a 1:1 shading rate, With respect to the third set of the quads, the third set of the quads is shaded without generating a set of quads with a modified shading rate. It is configured to do the following: APD according to claim 19.

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