Silicon carbide power diode device and method for manufacturing the same

Abstract

A silicon carbide power diode device is provided having a SiC substrate formed by a first surface on which a SiC epitaxial layer including an active region is provided, and a second surface. A Schottky metal layer is provided on the active region, and a first electrode layer is provided on the Schottky metal layer. A first ohmic contact metal layer is provided on the SiC substrate, and a second electrode layer is provided on the first ohmic contact metal layer. The active region of the SiC epitaxial layer includes a plurality of first P-type regions, a plurality of second P-type regions, and an N-type region. The first P-type regions and the second P-type region not provided with the ohmic contact metal layer are spaced apart to minimize the size of the second P-type region and maximize the N-type region for a given size of the first P-type region. The second ohmic contact metal layer is disposed between the first P-type region and the Schottky metal layer.

Description

[Technical Field]

[0001] The present invention relates to the technical field of semiconductor devices, and more particularly to silicon carbide power diode devices and methods for manufacturing silicon carbide power diode devices. [Background technology]

[0002] Compared to conventional Si-based devices, SiC devices offer characteristics such as higher operating frequencies, lower operating losses, and higher operating temperatures. As a representative example of SiC power devices, SiC diodes are widely used in power supplies, new energy vehicles, and other fields.

[0003] SiC SBDs (Schottky Barrier Diodes) have low forward voltage and high operating frequency. PiN diodes have no reverse recovery time or losses. However, due to their inferior reverse blocking characteristics, their operating voltage can only reach less than 200V, which is unsatisfactory. There is demand for them in high-voltage applications of 650V / 1200V.

[0004] As an improved structure for SiC SBDs, SiC JBS (Junction Barrier Schottky) incorporates P-type injection into the active region based on the SBD device structure. By adjusting parameters such as the PN ratio, injection doping concentration, and injection amount, leakage current can be significantly reduced, improving the inverse element characteristics of the JBS device and enhancing device reliability. However, JBS has inferior surge withstand capability and stability, which may prevent it from meeting customer needs in outdoor surge and lightning protection testing environments.

[0005] SiC MPS (Merged PiN Schottky) is a novel diode structure that combines the characteristics of JBS and PiN diodes. It forms ohmic contacts on the P-type injection region of the active area. Under high-current conditions, the potential barrier of the PiN diode turns on, further increasing the inrush current of the device, thus meeting the needs of higher-end applications.

[0006] In conventional SiC MPS, multiple P-type injection regions are typically formed in the active region, and ohmic contact metal is grown on each P-type injection region. However, due to the limitations of existing equipment (lithography equipment) and etching processes, in order to better etch the P-type injection regions and promote the growth of ohmic contact metal, it is necessary to appropriately enlarge the area of ​​the P-type injection regions to achieve a better process window. Otherwise, etching-related processes such as etching and metal growth become difficult due to an excessively high aspect ratio. Furthermore, while it is necessary to set a sufficient number of P-type injection regions to ensure that the inrush current of the device is sufficiently large and the current is sufficiently stable, this directly leads to a reduction in the N-type conductive region, resulting in a larger drop in forward voltage and increased conduction loss in the device. Therefore, when ensuring the size of the N-type conductive region, there is a conflict between the numerical requirements for the P-type injection regions and the design direction of miniaturization. [Overview of the project] [Problems that the invention aims to solve]

[0007] The object of the present invention is to provide a silicon carbide power diode device and a method for manufacturing the same, which overcomes the shortcomings of the current technology and provides an MPS device with good forward surge withstand capability and forward conduction characteristics while avoiding the problem of ohmic contact processes due to narrow windows. [Means for solving the problem]

[0008] The technical solution of the present invention is as follows: Silicon carbide power diode devices are The system comprises at least a SiC substrate and a SiC epitaxial layer disposed on the first surface of the SiC substrate, which has an active region.

[0009] A Schottky metal layer is provided on the surface of the active region of the SiC epitaxial layer. A first electrode layer is provided on the surface of the Schottky metal layer. A first ohmic contact metal layer is provided on the second surface of the SiC substrate.

[0010] A second electrode layer is provided on the surface of the first ohmic contact metal layer. The active region includes at least one or more first P-type regions, a plurality of second P-type regions, and an N-type region. The first P-type regions and the second P-type regions are separated, and a second ohmic contact metal layer A is provided on the surface of the first P-type regions, with the second ohmic contact metal layer positioned between the first P-type regions and the Schottky metal layer. The second P-type regions do not have an ohmic contact metal layer.

[0011] Among these, the active region of the silicon carbide epitaxial layer is given a size (including but not limited to the surface area) of the first P-type region, a size (including but not limited to the surface area) of the second P-type region being minimized, and (including but not limited to the maximum size of the N-type region).

[0012] Here, the given size of the first P-type region (including but not limited to its surface area) is greater than the set size of the second P-type region (including but not limited to its width) (including but not limited to its surface area).

[0013] Among these, the second ohmic contact metal layer completely covers the first P-type region. The second ohmic contact metal layer is a bulk metal layer that does not completely cover the first P-type region. Both the first P-type region and the second P-type region are strip-like, and the surface width of any first P-type region is greater than the width of any second P-type region.

[0014] Here, each of the first P-type regions has the same width and is arranged at equal intervals. Among them, the width of the first P-type region is not the same in all cases. Here, the distance between adjacent edges in adjacent first-type P regions is the same; that is, the distance between opposite edges in first-type P regions is the same between adjacent first-type P regions.

[0015] Among these, the first P-type region and the second P-type region are block regions. Here, the surface area of ​​any one first P-type region is greater than the surface area of ​​any one second P-type region.

[0016] The first P-type region and the second P-type region are rectangular, trapezoidal, regular polygonal (such as a regular hexagon), circular, irregularly shaped, or a combination thereof. Here, the first P-type region and the second P-type region are combinations of stripe and block regions (for example, square regions).

[0017] Here, at least one first P-type region is strip-shaped, and at least one second P-type region is block-shaped, and the surface area of ​​the first P-type region is greater than the surface area of ​​the second P-type region.

[0018] Here, at least one first P-type region is block-shaped, and at least one second P-type region is bar-shaped, and the radial width of the surface of the first P-type region in any direction is greater than the width of the surface of the second P-type region.

[0019] The total surface area of ​​the N-type region is 1 to 10 times the total surface area of ​​the first P-type region and the second P-type region. Among these, the surface width of any given first-type P region is between 1 and 10 μm, and the number of such regions is 2 or greater.

[0020] Among these, the width of the surface of any second P-type region is 0.1 μm or more. The first ohmic contact metal layer and the second ohmic contact metal layer are any one of Ti, Ni, Al, Au, Ta, or W, or a combination of these.

[0021] Here, the Schottky metal layer is any one of Ti, W, Ta, Ni, Mo, or Pt, or a combination of these. A method for manufacturing a silicon carbide power diode device is (1) a step of growing a SiC epitaxial layer including an N-type active region on a first surface of a SiC substrate; (2) depositing a protective film on the surface of the SiC epitaxial layer, opening a plurality of spaced injection windows in the N-type active region by etching, and performing ion implantation in the injection windows of the N-type active region, and by activation at high temperature, the N-type active region forms at least one first P-type region and a plurality of second P-type regions arranged at intervals.

[0022] (3) The surface of the first P-type region is entirely or partially covered by a metal layer, the surface of the second P-type region is not covered by a metal layer, and by high-temperature annealing, a second ohmic contact metal layer is formed on the surface of the first P-type region.

[0023] (4) The SiC epitaxial layer is covered by a metal layer that forms a Schottky metal layer by annealing at high temperature, and a first electrode layer is deposited on the Schottky metal layer. Among these, in step (2), the injection region in the terminal region is opened by etching, ion implantation is performed in the injection region of the terminal region, and by activation (such as high-temperature activation), the terminal region forms a terminal structure.

[0024] Among these, (5) further includes the step of growing a first passivation layer on the surface of the terminal structure and forming a second passivation layer on the surface of the first passivation layer, thereby obtaining a contact region for the first electrode layer by etching, and the second electrode layer is deposited on the surface of the first ohmic contact metal layer.

[0025] Here, step (3) or step (5) further includes covering the second layer of the SiC substrate with a metal layer and forming a first ohmic contact metal layer on the second surface of the SiC substrate by high-temperature annealing, wherein the second electrode layer is deposited on the surface of the first ohmic contact metal layer.

[0026] Among these, the high-temperature annealing process for forming the first ohmic contact metal layer and the second ohmic contact metal layer is at 800°C, 1100°C, and 1100°C for a duration of 60 to 300 seconds, while the high-temperature annealing process for forming the Schottky metal layer is at a temperature of 300°C to 500°C for a duration of 60 to 300 seconds.

[0027] Among these, the thickness of the first electrode layer is 25 μm, the thickness of the first passivation layer is 0.5-3 μm, and the thickness of the second electrode layer is 2-5 μm. Here, the first ohmic contact metal layer and the second ohmic contact metal layer are one of Ti, Ni, Al, Au, Ta, or W, or a combination thereof.

[0028] Here, the Schottky metal layer is one of Ti, W, Ta, Ni, Mo, or Pt, or a combination thereof. Among these, both the first P-type region and the second P-type region are strip-shaped, and the surface area of ​​one first P-type region is larger than the surface area of ​​one second P-type region.

[0029] Among these, both the first P-type region and the second P-type region are block regions, and the surface area of ​​one first P-type region is larger than the surface area of ​​one second P-type region. Among these, the first P-type region and the second P-type region are combinations of a strip region and a block region. When the first P-type region is a strip and the second P-type region is a block region, the surface area of ​​the first P-type region is larger than the surface area of ​​the second P-type region. When the first P-type region is a block region and the second P-type region is a strip, the radial width of the surface of the first P-type region in any direction and the width of the second P-type surface.

[0030] The beneficial effects of the present invention are as follows: The silicon carbide power diode device of the present invention is provided with two types of P-type regions. The surface of the first P-type region, which has a larger surface area and a wider range, is covered with an ohmic contact metal, while the surface of the second P-type region, which has a smaller and narrower surface area, does not have an ohmic contact metal. Under low current conditions, the current passes through the active N-type region, and under high current conditions, the forward voltage of the diode increases, and the PiN diode barrier formed by the surface of the first P-type region covered with ohmic contacts turns on. Because current can pass through this region, the surge current withstand capability of the diode is improved.

[0031] The silicon carbide power diode device manufacturing method of the present invention is used to manufacture the silicon carbide power diode device of the present invention. Under low current conditions, the N-type region of the diode is the region that transmits current. Theoretically, assuming the same surface area of ​​the P-type region, the larger the surface area of ​​the N-type region, the stronger the forward current withstand capability of the diode. Under high current conditions, theoretically, assuming the same surface area of ​​the N-type region, the larger the surface area of ​​the P-type region covered by the ohmic contact metal, the stronger the surge withstand capability of the diode. Therefore, selecting the forward current withstand capability and surge withstand capability of the diode is the focus and difficulty of device structural design. Due to limitations in semiconductor equipment and process capabilities, the precision of the etching process required to construct ohmic metal contacts on each P-type injection region is too high. To accommodate process stability and mass-producible types, the surface width of the P-type region covered by the ohmic metal is greater than 0.3 μm, and therefore a portion of the surface area of ​​the N-type region is wasted. The silicon carbide power diode device of the present invention uses two P-type regions with different specifications: the surface of the first P-type region, which has a larger surface area and a wider range, is covered with an ohmic contact metal, while the surface of the second P-type region, which has a smaller surface area and a narrower range, does not have an ohmic contact metal. This combination allows for a higher current density of the diode and suppression of on-voltage drop while maintaining the same surge withstand capability of the diode. [Brief explanation of the drawing]

[0032] [Figure 1] This is a schematic diagram of the active region in the first embodiment (the second ohmic contact metal layer completely covers the first P-type region). [Figure 2] A schematic cross-sectional view of the first embodiment (the second ohmic contact metal layer completely covers the first P-type region). [Figure 3] This is a schematic diagram of the active region according to the first embodiment (the second ohmic contact metal layer is a bulk metal layer). [Figure 4] This is a schematic diagram of the structure of the active region in the example. [Figure 5]This is a schematic cross-sectional view of a reference example. [Figure 6] This is a schematic diagram comparing the I-V characteristic curve of the present invention with a reference example. [Figure 7] This is a schematic diagram of the active region in the second embodiment. [Figure 8] This is a schematic diagram of the active region in the third embodiment. [Modes for carrying out the invention]

[0033] In the figure, 10 is the SiC substrate, 20 is the SiC epitaxial layer, 21 is the active region, 22 is the first P-type region, 23 is the second P-type region, 24 is the N-type region, 25 is the terminal region, 26 is the terminal structure, 30 is the Schottky metal layer, 40 is the first electrode layer, 50 is the first ohmic contact metal layer, 60 is the second electrode layer, 70 is the second ohmic contact metal layer, 81 is the first passivation layer, and 82 is the second passivation layer.

[0034] The present invention will be described in more detail below with reference to the drawings and embodiments. The present invention provides silicon carbide to solve the shortcomings of existing MPS devices of the prior art, such as forward surge withstand capability and forward conductivity characteristics, and the inability to sufficiently narrow the ohmic process window (due to the need to consider the effects of ohmic metal deposition). Power diode devices and methods for manufacturing them, in particular MPS devices, enable improved process compatibility, simplification of complex processes, and the realization of characteristics such as suppressed forward voltage drop, high reverse voltage, and large surge current.

[0035] First Embodiment As shown in Figures 1 and 2, the silicon carbide power diode device, or MPS device, of the present invention is The system comprises at least a SiC substrate 10, A SiC epitaxial layer 20 is provided on the first surface of the SiC substrate 10, and an active region 21 is provided in this SiC epitaxial layer 20. A Schottky metal layer 30 is provided on the surface of the active region 21 of the SiC epitaxial layer 20. A first electrode layer 40 is disposed on the surface of the Schottky metal layer 30. A first ohmic contact metal layer 50 is provided on the second surface of the SiC substrate 10. A second electrode layer 60 is disposed on the surface of the first ohmic contact metal layer 50. The active region 21 includes a plurality of first P-type regions 22, a plurality of second P-type regions 23, and an N-type region 24, wherein a second ohmic contact metal layer 70 is provided on the surface of the first P-type region 22, i.e., the first P-type region 22. The second ohmic contact metal layer 70 is ohmic contact. The second ohmic contact metal layer 70 is positioned between the first P-type region 22 and the Schottky metal layer 30. The second P-type region 23 does not have an ohmic contact metal layer provided; i.e., it is directly covered by the Schottky metal layer 30. This is based on a structure in which the second P-type region 22 has a second ohmic contact metal layer 70, and the second P-type region 23 does not have an ohmic contact metal layer. In this configuration, the active region of the SiC epitaxial layer 20 is given a size (including but not limited to the surface area) of the first P-type region 22, and the size (including but not limited to the surface area) of the second P-type region 23 is the minimum area, maximizing the size (including but not limited to the surface area) of the N-type region 24. Furthermore, in the given configuration, the size (including but not limited to the surface area) of the first P-type region 22 is larger than the size (including but not limited to the surface area) of the second P-type region 23 (including but not limited to the width of the surface area).

[0036] In the present invention, under the condition that the size of the active region 21 is fixed, the total surface area of ​​the first P-type region 22 and the second P-type region 23 can be reduced so as to increase the surface area of ​​the N-type region 24, and the width of the second P-type region 23 may be made as narrow as possible. This suppresses the drop in forward voltage and improves forward conductivity without increasing the total area of ​​the device. In the present invention, the size of the effective range for current flow within the first P-type region 22 is actually determined by the size of the superimposed area between the first P-type region 22 and the second ohmic contact metal layer 70. Based on the fact that the first P-type region 22 is sufficiently large, the shape of the second ohmic contact metal layer 70 can be diversified, satisfying good forward surge withstand capability while simultaneously making the second P-type region 23 as narrow as possible. In the present invention, the size relationship between the first P-type region 22 and the second P-type region 23 can be selected according to the following principle. In other words, if the surface of any first P-type region 22 covers all or part of the ohmic contact, then assuming that the surface of any one second P-type region 23 completely covers the ohmic contact, the amount of current passing through the first P-type region 22 must be greater than that passing through the second P-type region 23.

[0037] In certain embodiments, the second ohmic contact metal layer 70 can be mounted to cover beyond the range of the first P-type region 22, to substantially coincide with the first P-type region 22, to be slightly smaller than the first P-type region 22, or to cover only the first portion of the P-type region 22.

[0038] In this embodiment, both the first P-type region 22 and the second P-type region 23 are strip-shaped, and the surface area of ​​any first P-type region 22 is larger than the surface area of ​​any second P-type region 23. When both the first P-type region 22 and the second P-type region 23 are strip-shaped and the difference in length between the first P-type region 22 and the second P-type region 23 is small, the first P can be determined by expressing the width value. Relationship between the difference in surface area between the P-type region 22 and the second P-type region 23. In the present invention, the first P-type region 22 and the second P-type region 23 are arranged alternately in order to avoid the device becoming unstable due to the heat generated by the operation of adjacent second ohmic contact metal layers 70 mutually influencing each other and affecting the overall heat dissipation of the device.

[0039] In this embodiment, the widths of the first P-type regions 22 are the same and they are arranged at equal intervals, or the widths of the first P-type regions 22 are not all the same, and the distance between the opposing sides of adjacent first P-type regions 22 is the same. Furthermore, the uniform distribution of heat generated by the second ohmic contact metal layer 70 during operation improves heat dissipation and effectively controls the overall temperature rise, thereby ensuring the stability of the device. In a particular embodiment, the geometric center distance between adjacent first P-type regions 22 is 10 μm to 300 μm.

[0040] In certain embodiments, the first P-type region 22 and the second P-type region 23 may be implemented as rectangular strips, trapezoidal strips, regular hexagonal strips, irregularly shaped strips (wedge-shaped or other irregularly shaped strips with long sides), or combinations thereof. In this embodiment, the second ohmic contact metal layer 70 completely covers the first P-type region 22 and is implemented as a rectangular strip.

[0041] In another embodiment, as shown in Figure 3, the second ohmic contact metal layer 70 is a block-shaped metal layer that does not completely cover the first P-type region 22. Each of the first P-type regions is covered by at least one second ohmic contact metal layer 70. When the second ohmic contact metal layer 70 is a block-shaped metal layer, the distance between the centers of adjacent second ohmic contact metal layers 70 is 10 μm to 300 μm, and the second ohmic contact metal layers 70 are uniformly arranged, which is advantageous for uniform heat dissipation and can effectively control the overall temperature rise to ensure the stability of the device.

[0042] In order to balance the good forward surge resistance and forward conductivity characteristics according to the present invention, the total surface area of ​​the N-type region 24 is 1 to 10 times the total surface area of ​​the first P-type region 22 and the second P-type region 23. Preferably, the total surface area of ​​the N-type region 24 is 3 times the total surface area of ​​the first P-type region 22 and the second P-type region 23. Furthermore, the surface width of any one first P-type region 22 is 1 to 10 μm, and the number of such regions is 2 or more, and the surface width of any one second P-type region 23 is 0.1 μm or more.

[0043] As an effective region defining the active region 21, the SiC epitaxial layer 20 is further provided with a terminal region 25 surrounding the active region 21, and a first passivation layer 81 is provided on the surface of the terminal region 25, and the first passivation layer 81 covers the surface edge of the first electrode layer 40. Furthermore, the surface of the first passivation layer 81 covers the second passivation layer 82. In this embodiment, the first passivation layer 81 is a dielectric layer made of silicon oxide or silicon nitride, and the second passivation layer 82 is a PI layer made of polyimide.

[0044] To ensure good ohmic properties between the first ohmic contact metal layer 50 and the SiC substrate 10, and between the second ohmic contact metal layer 70 and the first P-type region 22, the first ohmic contact metal layer 50 and the second ohmic contact metal layer 70 are one of Ti, Ni, Al, Au, Ta, or W, or a combination thereof. In this embodiment, the first ohmic contact metal layer 50 and the second ohmic contact metal layer 70 are Ti / Ni combination multilayers.

[0045] To ensure good Schottky properties between the Schottky metal and the N-type region 24, the Schottky metal layer 30 is one of Ti, W, Ta, Ni, Mo, or Pt, or a combination thereof. In this embodiment, the Schottky metal layer 30 is a Ti / Ni / Ag combination multilayer metal.

[0046] Compared to a reference example based on the prior art (shown in Figures 4 and 5), the present invention is assumed to have the same area as the active region 21 of the reference example and to have the same number of P-type regions. All of these regions cover the ohmic contact metal layer. In the present invention, only the first P-type region 22 is covered by the second ohmic contact metal layer 70, and the second P-type region 23 is covered by the second ohmic contact metal layer 70.

[0047] In the present invention, in order to guarantee the same forward surge resistance as in the reference example, the area of ​​the first P-type region 22 and the second P-type region 23 is smaller than the total area of ​​the P-type region in the reference example, and the area of ​​the N-type region 24 in the present invention is larger than the area of ​​the N-type region 24 in the reference example, so that the present invention has superior forward conductivity characteristics compared to the reference example.

[0048] Experiments have shown that when a large forward current is passed through, the P-type region and N-type region 24 of the reference example can conduct a large current. The total surface area of ​​the second ohmic contact metal layer 70 and the N-type region 24 of the present invention allows for the passage of a large current, and the present invention has the same forward surge withstand capability as the reference example.

[0049] When a small forward current is passed through, both the reference example and the N-type region 24 of the present invention can pass through a small current. Since the planar area of ​​the N-type region 24 of the present invention is larger than that of the reference example, the current density is higher, and therefore the present invention has superior forward conductivity characteristics compared to the reference example.

[0050] As shown in Figure 6, in the present invention, under low current conditions, the current passes through the N-type region of the active area, and under high current conditions, the forward voltage of the diode increases, the PiN diode barrier formed by the first P-type region covered by ohmic contact is opened, and the current can pass through this region, improving the surge current withstand capability of the diode.

[0051] Second Embodiment A difference between this embodiment and the first embodiment is that the surface shapes of the first P-type region 22 and the second P-type region 23 are different. As shown in Figure 7, in this embodiment, the first P-type region 22 and the second P-type region 23 area 23 are block regions. Similar to the above embodiment, in this embodiment, the planar area of ​​any first P-type region 22 is larger than the planar area of ​​any one of the surfaces of the second P-type region 23.

[0052] In certain embodiments, the first P-type region 22 and the second P-type region 23 are rectangular, regular polygonal, circular, irregularly shaped, or a combination thereof, and the second ohmic contact metal layer 70 typically completely covers the first P-type region 22, and the shape of the second ohmic contact metal layer 70 is consistent with that of the first P-type region 22.

[0053] The remaining parts are the same as in the first embodiment. Third Embodiment A difference between this embodiment and the first embodiment is that the surface shapes of the first P-type region 22 and the second P-type region 23 are different. As shown in Figure 8, in this embodiment, the first P-type region 22 and the second P-type region 23. Area 23 is a combination of stripe and block regions. Similar to the above embodiment, in this embodiment, when the first P-type region 22 is strip-shaped and the second P-type region 23 is bulk region, the surface area of ​​the first P-type region 22 is larger than the surface area of ​​the second P-type region 23. Regarding the surface area, when the first P-type region 22 is block region and the second P-type region 23 is strip, the radial width of the surface of the first P-type region 22 in any direction is larger than the surface width of the second P-type region 23.

[0054] In a particular embodiment, the first P-type region 22 and the second P-type region 23 are rectangular strips, trapezoidal strips, irregular strips, rectangular regions, regular polygonal regions, circular regions, irregular regions, or combinations thereof. In this embodiment, the first P-type region 22 is a rectangular region, the second P-type region 23 is a rectangular strip, and the second ohmic contact metal layer 70 typically completely covers the first P-type region 22, with the shape of the second ohmic contact metal layer 70 being the same as that of the first P-type region 22.

[0055] The remaining parts are the same as in the first embodiment. Fourth Embodiment The present invention also provides a method for manufacturing a silicon carbide power diode device used in the fabrication of a silicon carbide power diode device, the steps of which are as follows.

[0056] (1) A SiC epitaxial layer 20 having an N-type active region 21 is grown on the first surface of the SiC substrate 10 (specifically, an RCA cleaning process is performed on the SiC substrate 10), the SiC substrate 10 having a crystal form of 4H-SiC, a thickness of 350 μm, and a doping concentration of 1 × 10 19 ~1 × 10 20 / cm 3Therefore, using MOCVD, an N-type SiC epitaxial layer 20 is grown on the first surface of an N-type SiC substrate 10, and the SiC epitaxial layer 20 has a thickness of 5 to 80 μm and a doping concentration of 1 × 10⁻¹⁶ 14 ~5×10 16 / cm 3 That is the case.

[0057] (2) A protective film is deposited on the surface of the SiC epitaxial layer 20 (PVD or CVD can be used as the deposition method). Multiple spaced implantation windows are opened in the implantation areas of the terminal region 25 and the N-type active region 21 using dry etching, ion implantation is performed in the implantation areas of the terminal region 25 and the active region 21, and after activation at high temperature, the terminal region 25 forms a terminal structure 26, and the N-type active region 21 forms multiple spaced first P-type regions 22 and multiple second P-type regions 23.

[0058] (3) The second surface of the SiC substrate 10 is covered with a metal layer, all or part of the surface of the first P-type region 22 is covered with a metal layer, the surface of the second P-type region is not covered with a metal layer, the first ohmic contact metal layer 50 is formed on the second surface of the SiC substrate 10, and the second ohmic contact metal layer 70 is formed on the surface of the first P-type region 22.

[0059] Here, a metal layer is formed on the second surface of the SiC substrate 10 by deposition or sputtering, a metal layer is formed on the first P-type region 22 by deposition or sputtering to form the first ohmic contact metal layer 50, and a first high-temperature annealing process of the 2-ohmic contact metal layer 70 is performed, with a temperature of 800°C to 1100°C and a time of 60 seconds to 300 seconds.

[0060] (4) The metal layer is coated onto the surface of the SiC epitaxial layer 20, a Schottky metal layer 30 is formed by high-temperature annealing, and the first electrode layer 40 is deposited on the Schottky metal layer 30.

[0061] In a high-temperature annealing process where the temperature is 300°C to 500°C and the time is 60 seconds to 300 seconds, a metal layer is formed on the SiC epitaxial layer 20, and a Schottky metal layer 30 is formed by deposition or sputtering. Subsequently, a first electrode layer 40 with a thickness of 2 to 5 μm is deposited as an anode electrode on the Schottky metal layer 30, and the Schottky metal layer 30 and the first electrode layer 40 covering the terminal structure 26 are removed by an etching method (that is, in the manufacturing process, the Schottky metal layer 30 and the first electrode layer 40 inevitably remain on the metal surface of the terminal structure 26).

[0062] (5) By CVD or PVD, a dielectric layer with a thickness of 0.5 to 3 μm is grown as the first passivation layer 81 on the surface of the terminal structure 26, 2 to 5 μm of polyimide is coated as the second purification layer on the surface of the first passivation layer 81, the contact area of the first electrode layer 40 is etched using a wet method or a dry etching method, and a second electrode layer 60 with a thickness of 2 to 5 μm is deposited as a cathode electrode on the surface of the first ohmic contact metal layer 50.

[0063] <​​​​​​​​​​​​​​​​In step (3), it is preferable that the first ohmic contact metal layer 50 and the second ohmic contact metal layer 70 are Ti / Ni combined multilayer metals, the process temperature is preferably 950°C, and the time is preferably 100 seconds.

[0066] In step (4), it is preferable that the Schottky metal layer 30 is Ti, the process temperature is preferably 450°C, the time is preferably 100 seconds, and the first electrode layer 40 is preferably Al with a thickness of 4 μm.

[0067] In step (5), the first passivation layer 81 is preferably silicon oxide SiO2 with a thickness of 1.2 μm, the second passivation layer 82 is preferably 5 μm thick, and the second electrode layer 60 is preferably a combination of Ti / Ni / Ag for the metal layer with a thickness of 2 μm.

[0068] Based on the manufacturing method described in this embodiment, silicon carbide power diode devices according to the first, second, and third embodiments can be manufactured according to the structures described in the first, second, and third embodiments.

[0069] The embodiments described above are used solely for illustrative purposes and are not intended to limit the invention. Modifications, improvements, etc., to the extent that they are based on the technical essence of the invention are included in the claims of the present invention.

Claims

1. A silicon carbide power diode device, wherein at least, A SiC substrate formed by a first surface and a second surface, on which a SiC epitaxial layer including an active region is provided, A Schottky metal layer is provided on the surface of the active region of the SiC epitaxial layer, A first electrode layer provided on the surface of the Schottky metal layer, A first ohmic contact metal layer is provided on the second surface of the SiC substrate, A second electrode layer provided on the surface of the first ohmic contact metal layer, A second ohmic contact metal layer is provided, The active region of the SiC epitaxial layer includes a plurality of first P-type regions, a plurality of second P-type regions, and an N-type region. The first P-type region and the second P-type region are spaced apart, minimizing the size of the second P-type region while maximizing the N-type region in accordance with the given size of the first P-type region. The second ohmic contact metal layer is positioned between the first P-type region and the Schottky metal layer, and is coated on the surface of the first P-type region. The second P-type region does not have an ohmic contact metal layer. The second ohmic contact metal layer is a block-shaped metal layer that does not completely cover the first P-type region. Each of the first P-type regions is covered by a plurality of the second ohmic contact metal layers. The multiple second ohmic contact metal layers in each of the first P-type regions are uniformly arranged with spacing between them. Furthermore, the distance between the centers of adjacent second ohmic contact metal layers in each of the first P-type regions is 10 μm to 300 μm. A silicon carbide power diode device in which the size relationship between the first P-type region and the second P-type region is such that, assuming that the surface of any one of the second P-type regions is completely covered by the second ohmic contact metal layer, the amount of current passing through the first P-type region is greater than the amount of current passing through the second P-type region.

2. A silicon carbide power diode device according to claim 1, wherein both the first P-type region and the second P-type region are strip-shaped, and the width of the first P-type region is greater than the width of the second P-type region.

3. A silicon carbide power diode device according to claim 2, wherein the widths of the first P-type regions are all the same, and the first P-type regions are arranged at equal intervals.

4. A silicon carbide power diode device according to claim 2, wherein the widths of the first P-type regions are not all the same.

5. A silicon carbide power diode device according to claim 4, wherein the distance between opposing sides of the first P-type region is the same between adjacent first P-type regions.

6. A silicon carbide power diode device according to claim 1, wherein the first P-type region and the second P-type region are block-shaped regions.

7. A silicon carbide power diode apparatus according to claim 6, wherein the surface area of ​​any one of the first P-type regions is greater than the surface area of ​​any one of the second P-type regions.

8. A silicon carbide power diode device according to claim 7, wherein the first P-type region and the second P-type region consist of a rectangular region, a trapezoidal region, a regular polygonal region, a circular region, an irregularly shaped region, or a combination thereof.

9. A silicon carbide power diode device according to claim 1, wherein the first P-type region and the second P-type region consist of a combination of a stripe-shaped region and a block-shaped region.

10. A silicon carbide power diode device according to claim 9, wherein at least one of the first P-type regions is strip-shaped, at least one of the second P-type regions is block-shaped, and the surface area of ​​one of the first P-type regions is larger than the surface area of ​​one of the second P-type regions.

11. A silicon carbide power diode apparatus according to claim 9, wherein at least one of the first P-type regions is block-shaped, at least one of the second P-type regions is strip-shaped, and the radial width of one of the first P-type regions is greater than the surface width of one of the second P-type regions.

12. A silicon carbide power diode device according to claim 1, wherein the total surface area of ​​the N-type region is 1 to 10 times the total surface area of ​​the region formed by combining the first P-type region and the second P-type region.

13. A silicon carbide power diode apparatus according to claim 12, wherein the surface width of the first P-type region is 1 to 10 μm, and two or more of the first P-type regions are present.

14. A silicon carbide power diode apparatus according to claim 12, wherein the surface width of the second P-type region is 0.1 μm or more.

15. A silicon carbide power diode apparatus according to claim 1, wherein the first ohmic contact metal layer and the second ohmic contact metal layer are one of titanium, nickel, aluminum, gold, tantalum, or tungsten, or a combination thereof.

16. A silicon carbide power diode apparatus according to claim 1, wherein the Schottky metal layer is one of titanium, tungsten, tantalum, nickel, molybdenum, or platinum, or a combination thereof.

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