Indication device

Abstract

To provide: a display device with suppressed consumption power; a display device of a self-light-emitting type with suppressed consumption power; and a display device of a self-light-emitting type with suppressed consumption power, capable of being usable for a long time even in a dark place.SOLUTION: A circuit is formed using a thin film transistor including a highly purified oxide semiconductor, so that a pixel can be kept in a constant state (state in which a video signal is written). As a result, stable operation is facilitated even in the case of displaying a still image. In addition, since the operation intervals of a driving circuit can be made long, the consumption power of the display device can be reduced. Moreover, when a luminous material is used for a pixel portion of a display device of a self-light-emitting type and light of a light-emitting element is accumulated, the use for a long time becomes possible even in a dark place.SELECTED DRAWING: Figure 15

Description

Technical Field

[0001] One embodiment of the present invention relates to a display device and an electronic device having the display device. In particular, it relates to a display device composed of a field-effect transistor using an oxide semiconductor and a light-emitting element, and an electronic device having the display device.

Background Art

[0002] Techniques for constructing thin-film transistors (TFTs) using semiconductor thin films formed on substrates having insulating surfaces have attracted attention. Thin-film transistors are used in display devices such as liquid crystal televisions. Silicon-based semiconductor materials are known as semiconductor thin films applicable to thin-film transistors, but oxide semiconductors are attracting attention as other materials. <00,00089>

[0003]

[0004] As materials for oxide semiconductors, zinc oxide or those containing zinc oxide as a component are known. And thin-film transistors formed of amorphous oxides (oxide semiconductors) having an electron carrier concentration of less than 10 / cm are disclosed (Patent Documents 1 to 3). 3

[0005]

[0006] Field-effect transistors using oxide semiconductors can be applied to, for example, display devices. Display devices include self-emitting display devices that emit light to display images, transmissive display devices that selectively transmit light from a backlight to display images, and reflective display devices that reflect external light to display images.

[0007]

[0008] [[ID=]] [[ID=]]

[0009] A key feature of reflective display devices is that they do not require a built-in light source, making it easier to reduce power consumption. Of course, since the displayed image can be rewritten, electronic paper can replace printed media. As such, it is attracting attention in a society aiming for resource conservation.

[0007] However, in environments with little ambient light, reflective displays have reduced visibility, which is a disadvantage. Lighting is required for its use. When lighting is used, reflective display devices consume less power. The characteristics of this device would be lost. Therefore, while suppressing power consumption, visibility in dark places would be improved. To achieve this, materials that store ambient light, such as phosphorescent fluorescent materials and phosphorescent materials, are applied to reflective display devices. Inventions that do this are disclosed (Patent Documents 4 and 5). [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Publication No. 2006-165527 [Patent Document 2] Japanese Patent Publication No. 2006-165528 [Patent Document 3] Japanese Patent Publication No. 2006-165529 [Patent Document 4] Japanese Patent Publication No. 2006-3924 [Patent Document 5] Japanese Patent Publication No. 2008-116855 [Overview of the Initiative] [Problems that the invention aims to solve]

[0009] Oxide semiconductors can deviate from their stoichiometric composition during the thin-film formation process. For example, The electrical conductivity of oxide semiconductors changes depending on whether there is an excess or deficiency of oxygen. Hydrogen introduced during the formation of the body's thin film forms oxygen (O)-hydrogen (H) bonds and acts as an electron donor. Furthermore, it becomes a factor that changes electrical conductivity. In addition, since OH is a polar molecule, it is an oxide semiconductor. For active devices such as thin-film transistors fabricated by this method, it becomes a factor in the variation of characteristics. ru.

[0010] Electron carrier concentration is 10 18 / cm 3 Even if it is less than, in the case of oxide semiconductors, It is an n-type, and the on / off ratio of the thin-film transistor disclosed in the aforementioned patent document is 10 3 Only It has not been done. The reason why the on / off ratio of such thin-film transistors is low is that the off-current is high. This is due to the following.

[0011] When a thin-film transistor with a high off-current is used in the pixel section of a display device, the signal applied to the pixel It becomes necessary to add capacitance to maintain the voltage. Adding capacitance to a pixel means that the pixel One challenge is that the aperture ratio decreases, leading to increased power consumption of the display device.

[0012] Furthermore, in order to reduce the power consumption of self-emissive and transmissive display devices, the display device has Reducing the energy supplied to the light-emitting element can cause the display to dim or even disappear. The impact on the quality of the labeling is significant.

[0013] Furthermore, the reflective display device using the phosphorescent material disclosed in the aforementioned patent document is suitable for use in areas with little ambient light. Even at the border, it is possible to display with low power consumption, but by first irradiating the phosphorescent material with ambient light, the phosphorescent light is charged. The material needs to store light, making it unsuitable for long-term use in dark places.

[0014] This invention was made under such technical background. Therefore, its purpose is, One of the problems is to provide a display device with reduced power consumption. Also, reduced power consumption Another problem is to provide a self-emitting display device with reduced power consumption. Also, long-term use is possible even in a dark place Another problem is to provide a self-emitting display device with reduced power consumption that can be used for a long time even in a dark place .

Means for Solving the Problems

[0015] One embodiment of the present invention is a self-emitting display device to which a thin film transistor having stable electrical characteristics (for example, extremely reduced off-current) is applied. Specifically, by removing impurities that become electron donors (donors) in an oxide semiconductor, a pure or substantially pure semiconductor, an oxide semiconductor having a larger energy gap than a silicon semiconductor, forms a channel region, and constitutes a drive circuit for a light-emitting element by a thin film transistor at the end .

[0016] That is, in one embodiment of the present invention, the hydrogen contained in the oxide semiconductor is 5×10 19 / cm 3 or less , preferably 5×10 18 / cm 3 or less, more preferably 5×10 17 / cm 3 or less , and the hydrogen or OH bond contained in the oxide semiconductor is removed, and the carrier concentration is 1×10 1 4 / cm 3 less, preferably 1×10 12 / cm 3 or less, and a drive circuit for a light-emitting element is constituted by a thin film transistor in which a channel region is formed of an oxide semiconductor film .

[0017] ​The energy gap is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or less. As a result, impurities such as hydrogen that form the donor are reduced as much as possible, and the carrier concentration is 1 × 10⁻⁶ 14 / cm 3 Less than 1 × 10 12 / cm 3 The following should be achieved.

[0018] This highly purified oxide semiconductor is used in the channel formation region of thin-film transistors. This means that even when the channel width is 10mm, the drain voltage is 1V and 10V. In this configuration, when the gate voltage is in the range of -5V to -20V, the drain current is 1 × 10⁻¹⁰ - 13 It acts in such a way that the result is less than or equal to A.

[0019] Furthermore, one aspect of the present invention focuses on the power consumed by the drive circuit of a self-illuminating display device. In other words, by reducing the frequency with which the drive circuit operates, the power consumed by the display device is reduced. It is sufficient to control it. Also, a phosphorescent layer is provided in the pixel part of a self-emissive display device, and the light-emitting element is placed in the phosphorescent layer. The phosphorescent layer stores the light it emits, and while the light emitted by the phosphorescent layer is displaying an image, it supplies energy to the light-emitting element. The solution is to suppress ghee and reduce the power consumption of the display device.

[0020] In other words, one aspect of the present invention is a power line that supplies pulsed DC power to a pixel, and the power line A first circuit controls the opening and closing of a circuit that connects a power line to a light-emitting element that is supplied with power. It has a thin-film transistor. It also has a signal line that supplies video signals, and the signal line and the first thin film It has a second thin-film transistor that controls the opening and closing of the circuit connecting the transistors. The channel formation region of the second thin-film transistor has a band gap of 2 eV or more, and water The elementary concentration is 5 × 10 19 / cm 3 It is formed from the following oxide semiconductor. Channel width 1 Off-current per μm is 1 × 10 -16 Second thin film transient suppressed to A / μm or less The first thin-film transistor maintains the ON state, and the power line and the light-emitting element are connected. It is a display device that shows still images.

[0021] Furthermore, in one aspect of the present invention, the carrier concentration of the oxide semiconductor layer is 1 × 10 14 / cm 3 Less than This is a certain display device.

[0022] Furthermore, in one aspect of the present invention, during the display period of a still image, the period during which the output of the scan line signal is stopped is The above-mentioned display device is possessed.

[0023] Furthermore, in one aspect of the present invention, the light-emitting element comprises a pair of electrodes and a light-emitting organic material between the pair of electrodes. The above-mentioned display device has a layer containing a component.

[0024] Furthermore, one aspect of the present invention is the above-described display device having a phosphorescent layer on the pixels.

[0025] Furthermore, one aspect of the present invention is an electronic device equipped with the above-mentioned display device.

[0026] In this specification, phosphorescent materials are defined as materials that absorb energy from external sources such as ambient light. A material that generates relatively stable and long-lived excitons, wherein the excitons have a relatively long lifetime. This refers to all materials that deactivate with luminescence over a period of time. It also includes phosphorescent materials that store long-lived excitons. The material continues to emit light even after the external energy supply is cut off.

[0027] In this specification, "pixel" refers to each element provided in each pixel of a display device, such as a thin film. The display is controlled by electrical signals from transistors, electrodes that function as pixel electrodes, and wiring. This refers to a group of elements composed of components for control. A pixel, for example, is a color filter, etc. It may include elements, and each pixel may represent a single color element that can control brightness. Therefore, as an example, in the case of a color display device consisting of RGB color elements, the image is most A small unit consists of three pixels: an R pixel, a G pixel, and a B pixel. This allows us to obtain an image using pixels.

[0028] In this specification, when it is stated that A and B are connected, it means that A and B are electrically connected. This includes cases where A and B are connected by air, and cases where A and B are directly connected. Here, A and B are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers). (etc.)

[0029] In this specification, the term "EL layer" refers to the layer provided between a pair of electrodes of a light-emitting element. Therefore, the light-emitting layer containing an organic compound, which is a light-emitting material sandwiched between electrodes, is one of the EL layers. It is a manner.

[0030] Furthermore, in this specification, when substance A is dispersed in a matrix consisting of other substance B, The substance B that makes up the trix is ​​called the host material, and the substance A dispersed in the matrix is ​​called the guess These materials shall be referred to as "materials." Note that even if substance A and substance B are single substances, It is acceptable, and a mixture of two or more substances is also acceptable.

[0031] In this specification, "light-emitting device" refers to an image display device, a light-emitting device, or a light source. This refers to the light source (including the lighting device). It also refers to the connector on the light-emitting device, such as an FPC (Flexible Printed Circuit). (printed circuit) or TAB (Tape Automate d Bonding) Tape or TCP (Tape Carrier Packaging) e) A module to which a TAB tape or TCP has been attached, with a printed circuit board at the end. A module or substrate on which light-emitting elements are formed is coated with COG (Chip On Glas s) All modules with ICs (integrated circuits) directly mounted using this method are also included as light-emitting devices. Let's assume that. [Effects of the Invention]

[0032] According to one embodiment of the present invention, a thin-film transistor using a highly purified oxide semiconductor is used in a circuit By configuring this, the operation of the circuitry in the display device can be stabilized. The current is 1 × 10 -13 By reducing it to A or less, the signal applied to the pixels of the display device This eliminates the need to provide additional capacitance to maintain the voltage. In other words, each pixel does not need to have a holding capacitance. Since this is not necessary, the aperture ratio can be improved. A higher aperture ratio allows for... The driving voltage is suppressed, and the power consumption of the display device is reduced.

[0033] Furthermore, a pixel using a thin-film transistor according to one embodiment of the present invention is in a certain state (when the video signal is Since it is possible to maintain the written state, it is stable even when displaying still images. It can perform the operation. Also, because the operating interval of the drive circuit can be made longer, the display device can be turned off. It can reduce power consumption.

[0034] Furthermore, according to one embodiment of the present invention, a display device that can be used even in environments with weak ambient light can be provided. Furthermore, it is possible to provide a display device that can display images while suppressing power consumption. [Brief explanation of the drawing]

[0035] [Figure 1] A top view and a cross-sectional view of a pixel according to the embodiment. [Figure 2] A diagram illustrating the configuration of a display device according to the embodiment. [Figure 3] A diagram illustrating the writing period and retention period to pixels according to the embodiment. [Figure 4] A top view and a cross-sectional view of a pixel according to the embodiment. [Figure 5] A top view and a cross-sectional view of a thin-film transistor according to an embodiment. [Figure 6] A diagram illustrating the fabrication process of a thin-film transistor according to the embodiment. [Figure 7] A top view and a cross-sectional view of a thin-film transistor according to an embodiment. [Figure 8] A diagram illustrating the fabrication process of a thin-film transistor according to the embodiment. [Figure 9] Cross-sectional view of a thin-film transistor according to the embodiment. [Figure 10] A diagram illustrating the fabrication process of a thin-film transistor according to the embodiment. [Figure 11] A diagram illustrating the fabrication process of a thin-film transistor according to the embodiment. [Figure 12] A diagram illustrating the fabrication process of a thin-film transistor according to the embodiment. [Figure 13] A diagram illustrating the fabrication process of a thin-film transistor according to the embodiment. [Figure 14] Cross-sectional view of a thin-film transistor according to the embodiment. [Figure 15] A diagram illustrating the equivalent circuit of a pixel according to the embodiment. [Figure 16] A cross-sectional view of a pixel according to the embodiment. [Figure 17] Cross-sectional view of a light-emitting device according to an embodiment. [Figure 18]A cross-sectional view of a pixel according to the embodiment. [Figure 19] A diagram illustrating an electronic device according to an embodiment. [Figure 20] A diagram illustrating an electronic device according to an embodiment. [Figure 21] A longitudinal cross-sectional view of an inverse staggered thin-film transistor using an oxide semiconductor. [Figure 22] Figure 21 shows the energy band diagram (schematic diagram) in the A-A' section. [Figure 23] (A) shows the state where a positive potential (+VG) is applied to the gate (G1), and (B) shows the state where a negative potential (-VG) is applied to the gate (G1). [Figure 24] This diagram shows the relationship between the vacuum level, the work function (φM) of metals, and the electron affinity (χ) of oxide semiconductors. [Figure 25] A block diagram illustrating the configuration of the display device according to the embodiment. [Figure 26] A diagram illustrating the configuration of the drive circuit and shift register according to the embodiment. [Figure 27] A timing chart illustrating the operation of a shift register. [Figure 28] A timing chart illustrating the operation of a shift register. [Modes for carrying out the invention]

[0036] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, its form and details may be modified in various ways. It will be easily understood by those skilled in the art to obtain this. Therefore, the present invention is as shown in the embodiments below. The description is not to be interpreted as being limited to the stated content. The same reference numeral is used in common across different drawings for parts that are identical or have similar functions. I will omit the explanation of that repetition.

[0037] (Embodiment 1) In this embodiment, a thin-film transistor and pixel electrode using a highly purified oxide semiconductor are used. Examples of constituent pixels are explained below using Figures 1 and 4.

[0038] First, a top view of the pixels is shown in Figure 1(A). The structure of the TFT shown in Figure 1(A) is as follows: As an example, a bottom gate type structure is shown, and the channel is viewed from the gate wiring. On the opposite side of the oxide semiconductor layer, which forms the drain region, are the wirings that will serve as the source and drain electrodes of the TFT. This shows a so-called inverse staggered configuration with layers. Pixel 10 shown in Figure 1(A) 0 represents the first wiring 101 which functions as a scan line, and the second wiring 102 which functions as a signal line. A has an oxide semiconductor layer 103, capacitance lines 104, and pixel electrodes 105. It has a third wiring 102B for electrically connecting the body layer 103 and the pixel electrode 105, and is thin A film transistor 106 is formed.

[0039] The first wiring 101 also functions as the gate of the thin-film transistor 106. The wiring 102A is configured as either the source electrode or the drain electrode and one of the electrodes of the holding capacitance. It is also a wiring that functions. The third wiring 102B is the other of the source electrode or the drain electrode. It is also a wiring that functions as such. The capacitance wire 104 functions as the other electrode of the retaining capacitance. It is a line. The first wiring 101 and the capacity line 104 are provided on the same layer, and the second wiring 10 2A and the third wiring 102B are provided on the same layer. Also, the third wiring 102B and capacity line 1 04 is provided in a partially overlapping manner and forms the holding capacitance of the light-emitting element. The oxide semiconductor layer 103 of the film transistor 106 is branched from the first wiring 101. It is provided on the wiring via a gate insulating film (not shown).

[0040] Figure 1(B) also shows the cross-sectional structure between the dashed line A1-A2 in Figure 1(A). The cross-sectional structure shown in Figure 1(B) is such that a gate is formed on the substrate 111 via the underlayer 112. A first wiring 101 and a capacity line 104 are provided. A gate insulating film 113 is provided so as to cover the line 104. A second wiring is provided on the oxide semiconductor layer 103. 102A and a third wiring 102B are provided. Also, an oxide semiconductor layer 103 and a second On wiring 102A and the third wiring 102B, an acid that functions as a passivation film is applied. An oxide insulating layer 114 is provided. Openings are formed in the oxide insulating layer 114. At the aperture, the pixel electrode 105 and the third wiring 102B are connected. Wiring 102B and capacitance line 104 form a capacitance element using the gate insulating film 113 as the dielectric. It is.

[0041] Furthermore, Figure 1(C) shows a cross-sectional view of the dashed line B1-B2 in Figure 1(A), This diagram shows a configuration in which an insulating layer 121 is provided between the main wire 104 and the second wiring 102A. .

[0042] When the second wiring 102A is provided on the first wiring 101 and capacitance line 104, the gate insulating film is provided. Depending on the film thickness of 113, the first wiring 101 and the second wiring 102A, and the capacitance wire 104 and Parasitic capacitance will occur between the second wiring 102A. Therefore, as shown in Figure 1(C) By providing the insulating layer 121, parasitic capacitance is reduced, thereby reducing malfunctions and other defects. It is possible.

[0043] Note that the pixels shown in Figures 1(A) to (C) are multiple pixels on the substrate 200, as shown in Figure 2. The elements 201 are arranged in a matrix. In Figure 2, the pixel area is on the substrate 200. A configuration having 202, a scan line drive circuit 203, and a signal line drive circuit 204 is shown. The pixel 201 is supplied by the first wiring 101 connected to the scan line drive circuit 203. The scanning signal determines whether each row is selected or not. The pixel 201 selected by the number is connected to the second wiring of the signal line drive circuit 204. 102A provides video voltage (video signal, image signal, video signal) from the second wiring 102A. A video (also called a video file) is supplied.

[0044] In Figure 2, the scan line drive circuit 203 and the signal line drive circuit 204 are provided on the substrate 200. Although the configuration has been shown, either the scan line drive circuit 203 or the signal line drive circuit 204 The configuration may be such that the elements are provided on the substrate 200. Alternatively, only the pixel section 202 may be provided on the substrate 200. It can also be used as a configuration.

[0045] In Figure 2, the pixel section 202 has multiple pixels 201 arranged on a matrix (stripe arrangement). An example is shown. Note that pixel 201 is not necessarily located on the matrix. It is not necessary; for example, pixel 201 may be arranged in a delta configuration or a Bayer configuration. The display method in section 202 shall be either progressive or interlaced. This is possible. Furthermore, the color elements controlled by pixels when displaying color are RGB(R It is not limited to three colors (Red, Green, Blue), but can be more than that, for example, RGBW(W (White), or RGB with one or more additional colors such as yellow, cyan, and magenta. Yes, it is possible. Furthermore, the size of the display area for each dot of the color element may differ.

[0046] In Figure 2, the first wiring 101 and the second wiring 102A represent the number of pixels in the row and column directions. This is shown accordingly. Also, the first wiring 101 and the second wiring 102A are shared between pixels. It is also possible to configure it to drive pixel 201.

[0047] Note that in Figure 1(A), the shape of the second wiring 102A of the TFT is shown as rectangular. However, the shape surrounding the third wiring 102B (specifically, U-shaped or C-shaped) The carrier increases the area of ​​the region it moves through, and the current that flows when the thin-film transistor conducts (on Alternatively, the configuration may be designed to increase the amount of current (also called electric current).

[0048] In this specification, the on-current refers to the state in which a thin-film transistor is turned on (also known as the conducting state). This refers to the current that flows between the source and drain when ) is true. n-channel thin-film transistor In this case, if the voltage applied between the gate and source is greater than the threshold voltage (Vth) This refers to the electric current that flows between the source and the drain.

[0049] The aperture ratio is a term that expresses the ratio of the area through which light passes to a unit area. As the area occupied by the light-impermeable material increases, the aperture ratio decreases, and the area that transmits light decreases. As the area occupied by the material increases, the aperture ratio improves. In display devices, the pixel electrodes are heavy By reducing the area occupied by the wiring, capacitance lines, and the size of the thin-film transistors, This will lead to an improvement in the percentage of votes.

[0050] In particular, with self-illuminating display devices, the observer observes from a position facing the display device. The ratio of the light-emitting area of ​​a light-emitting element to the pixel area is called the aperture ratio.

[0051] Furthermore, a thin-film transistor has at least three terminals, including the gate, drain, and source. It is an element having a drain region and a channel region between the drain region and the source region, Current can be passed through the rain region, channel region, and source region. Here, The terms "sow" and "drain" vary depending on the transistor's structure and operating conditions, so which one is the drain? It is difficult to determine whether it is a source or a drain. Therefore, source and drain The area that functions as a source or drain is sometimes not called a source or drain. In that case, for example... In some cases, these are referred to as the first terminal and the second terminal, respectively. Alternatively, they can be referred to as They are sometimes referred to as the first electrode and the second electrode. Alternatively, they may be referred to as the first region and the second region. There is a match.

[0052] Next, the oxide semiconductor layer 103 will be described.

[0053] The oxide semiconductor used in this embodiment has hydrogen or OH bonds removed, and the oxide semiconductor The amount of hydrogen in the body is 5 x 10 19 / cm 3 The following is preferably 5 × 10 18 / cm 3 below, Comfortable 5x10 17 / cm 3 The following applies. And the carrier concentration is 1 × 10 14 / cm 3 Less than 1 × 10 12 / cm 3 The oxide semiconductor film described below is channel-shaped It is applied to a region to construct a thin-film transistor. Furthermore, the hydrogen concentration in the oxide semiconductor layer is measured. Secondary ion mass spectrometry (SIMS) You can do this using ectroscopy.

[0054] The energy gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, more preferably Alternatively, set the value to 3 eV or higher, and minimize impurities such as hydrogen that form the donor, thereby reducing the carrier concentration. to 1 × 10 14 / cm 3 Less than 1 × 10 12 / cm 3 The following should be achieved. In other words, the carrier concentration in the oxide semiconductor layer is reduced to as close to zero as possible.

[0055] By thoroughly removing the hydrogen contained in the oxide semiconductor layer in this way, high purity is achieved. By using an oxide semiconductor layer in the channel formation region of a thin-film transistor, the off-current value is reduced. We can provide extremely small thin-film transistors.

[0056] For example, a thin-film transistor using a highly purified oxide semiconductor layer has a channel length of 3 μm. Even if the channel width is 10 mm, when the drain voltage is 1V and 10V And, when the gate voltage is in the range of -5V to -20V (off state), the drain current is 1 × 10 -13 It acts in such a way that the result is less than or equal to A.

[0057] The characteristics of a thin-film transistor using a highly purified oxide semiconductor layer are shown in Figures 21 to 21. Let's explain using Figure 24. Figure 21 shows an inverse staggered thin-film transistor using an oxide semiconductor. A longitudinal cross-sectional view is shown. An oxide semiconductor is connected to the gate electrode (GE1) via a gate insulating film (GI). A body layer (OS) is provided, and a source electrode (S) and a drain electrode (D) are provided on top of it. It is.

[0058] Figure 22 shows the energy band diagram (schematic diagram) in the A-A' section shown in Figure 21. Figure 22(A) shows the case where the voltage between the source and drain is at the same potential (VD=0V), as shown in the diagram. Figure 22(B) shows the case where a positive potential (VD>0V) is applied to the drain relative to the source.

[0059] Figure 23 is a schematic diagram of the energy bands in the cross-section B-B' in Figure 21. Figure 23(A) shows the state where a positive potential (+VG) is applied to the gate (G1), and the source This shows the ON state where carriers (electrons) flow between the drain and the capacitor. Also, see Figure 23(B). This is a state where a negative potential (-VG) is applied to the gate (G1), and is an off state (minority capacity). This indicates the case where the rear does not flow.

[0060] Figure 24 shows the relationship between the vacuum level, the work function (φM) of the metal, and the electron affinity (χ) of the oxide semiconductor. This indicates.

[0061] Conventional oxide semiconductors are generally n-type, and in that case, the Fermi level (Ef) is bandg It is located away from the intrinsic Fermi level (Ei) located in the center of the cap, and closer to the conduction band. Furthermore, in oxide semiconductors, some hydrogen acts as a donor, which is one of the factors that leads to n-type semiconductor formation. It is known that it can be done.

[0062] In contrast, the oxide semiconductor according to the present invention removes hydrogen, which is an n-type impurity, from the oxide semiconductor. Furthermore, by purifying the material to the point where it contains as few impurities as possible other than the main components of the oxide semiconductor, It is intended to be true (type i), or to be intended to be true. In other words, it contains impurities such as hydrogen and water. By removing as many impurities as possible, it is possible to obtain a highly purified type i (intrinsic semiconductor) or something close to it. It is characterized by the following. By doing so, the Fermi level (Ef) is the true Fermi level ( It can be brought up to the same level as Ei).

[0063] If the band gap (Eg) of an oxide semiconductor is 3.15 eV, then the electron affinity (χ) is It is said to be 4.3 eV. The titanium (Ti) that makes up the source electrode and drain electrode. The function is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, metal-oxide semiconductor At the body interface, no Schottky-type barrier is formed for electrons.

[0064] That is, when the work function of the metal (φM) and the electron affinity (χ) of the oxide semiconductor are approximately equal. When the two come into contact, an energy band diagram (schematic diagram) like the one shown in Figure 22(A) is displayed. .

[0065] In Figure 22(B), the black circles (●) represent electrons, and when a positive potential is applied to the drain, The particles are injected into the oxide semiconductor, passing through the barrier (h), and flow towards the drain. In total, the height of the barrier (h) changes depending on the gate voltage and drain voltage, but the positive drain When an input voltage is applied, the height of the barrier in Figure 22(A) without voltage application, i.e., the barrier height, is lower. The barrier height (h) will be less than half of the gap (Eg).

[0066] At this time, the electrons are in the gate insulating film and the highly purified oxide semiconductor, as shown in Figure 23(A). At the interface with the oxide semiconductor, it moves to the lowest energetically stable point on the oxide semiconductor side.

[0067] Furthermore, in Figure 23(B), when a negative potential is applied to the gate electrode (G1), a minority can Since the rear section (Hole) is practically zero, the current will be extremely close to zero.

[0068] For example, if the channel width W of a thin-film transistor is 1 × 10⁻⁶ 4 A device with a channel length of 3 μm in μm. Even if the off-current is 10 -13 It is less than or equal to A, and the subthreshold swing value (S value) A voltage of 0.1 V / dec. (gate insulating film thickness 100 nm) is obtained.

[0069] In this way, the purity is increased so that impurities other than the main components of the oxide semiconductor are included as little as possible. This allows for improved operation of the thin-film transistor.

[0070] Thus, a thin-film transistor with an extremely small current value in the off state (off-current value) is used. When used to fabricate memory circuits (memory elements), the off-current value is small and there is almost no leakage. Because it lacks this feature, the time for which electrical signals such as video signals are held can be extended.

[0071] Specifically, the thin-film transistor having the oxide semiconductor layer described above has a channel width of 1 μm. The off-current for each is 1 × 10 -16 It should be less than A / μm, and furthermore, 1aA / μm (1× 10 -18 It is possible to reduce the A / μm to less than or equal to 1 / 2.

[0072] A transistor with an extremely low current value in the off state (off current value) is used as a switch in the pixel area. It is used as a switching transistor (for example, the switching transistor 6401 in Figure 15). By doing so, the holding time of electrical signals such as video signals can be extended. Therefore, for example, the writing interval can be 10 seconds or more, preferably 30 seconds or more. More preferably, it can be 1 minute or more but less than 10 minutes. This can significantly reduce power consumption.

[0073] Furthermore, the resistance to the flow of off-current in a transistor can be expressed as off-resistivity. Resistivity is the resistivity of the channel formation region when the transistor is off, and off-resistivity is It can be calculated from the off-current.

[0074] Specifically, if the values ​​of the off-current and drain voltage are known, then the transistor can be calculated using Ohm's law. The resistance value when the device is off (off-resistance R) can be calculated. And the channel formation region... The cross-sectional area A and the length L of the channel-forming region (corresponding to the distance between the source and drain electrodes) are divided Then, the off-resistivity ρ can be calculated from the formula ρ = RA / L (where R is the off-resistivity).

[0075] Here, the cross-sectional area A is defined as follows, where d is the thickness of the channel-forming region and W is the channel width. It can be calculated from =dW. Also, the length L of the channel formation region is equal to the channel length L. As described above, the off-resistivity can be calculated from the off-current.

[0076] The off-resistivity of the transistor comprising the oxide semiconductor layer of this embodiment is 1 × 10⁻⁶. 9 Ω·m The above is preferable, and furthermore, 1 × 10 10 A value of Ω·m or greater is preferable.

[0077] Note that the pixel configuration shown in Figure 15 is one aspect of this embodiment, and for example, the retaining capacity is used as a drive transistor. It can also be installed between the gate of the inverter 6402 and the power line 6407. The holding capacity is The structure can be constructed by sandwiching an insulating layer as a dielectric between a pair of electrodes. The size of the retaining capacitance is... Considering the off-current of the switching transistor 6401, etc., it is possible to hold the charge for a predetermined period of time. Set it up to do so.

[0078] For example, in a thin-film transistor equipped with low-temperature polysilicon, the off-current is 1 × 10⁻⁶ -12 A It is estimated to be equivalent, and the design will be carried out accordingly. Therefore, it has an oxide semiconductor. In thin-film transistors, compared to thin-film transistors that use low-temperature polysilicon, the retention capacity is When the quantity is equivalent (approximately 0.1pF), the voltage retention period is set to 10 5 To stretch it to about twice its original size. This is possible. Also, in the case of a transistor containing amorphous silicon, the channel width is 1μ. The off-current per m is 1 × 10⁻⁶ -13 It is A / μm or higher. Therefore, the retention capacity is the same When the capacitance is similar (around 0.1pF), a transistor using a high-purity oxide semiconductor is more efficient. Compared to transistors using Rufus silicon, the voltage retention period is 10 4 More than double It can be stretched.

[0079] As an example, pixels that typically have transistors using low-temperature polysilicon display 60 It is done at frames / second (16 msec per frame). This is even for still images. Similarly, lowering the rate (extending the writing interval) lowers the voltage of the pixels and affects the display. This is because it would cause problems. On the other hand, using a transistor equipped with the aforementioned oxide semiconductor layer In this case, because the off-current is small, the retention period for one signal write is 10 5 Double 160 It can be set to approximately 0 seconds.

[0080] As described above, the display device of this embodiment displays still images with a small number of image signal write cycles. It is possible. Because the retention period can be extended, especially when displaying still images, the signal can be written The frequency of writing can be reduced. Therefore, power consumption can be reduced. For example, the number of times a pixel is written to during the display period of a single still image can be either 1 or n times. This is possible. Note that n is 2 or greater than or equal to 10. 3 The number of times should be kept to less than or equal to the number of times. This will reduce the power consumption of the display device. It is possible to measure this.

[0081] Furthermore, in this embodiment, when displaying a still image, the signal lines and scan lines are supplied By operating the drive circuit section to stop the signal output, not only the pixel section but also the drive The power consumption of the circuit section can also be reduced.

[0082] Figure 3 shows the relationship between the write period and the retention period (also called the 1-frame period). In Figure 3, periods 251 and 252 correspond to the retention period, and periods 261 and 262 are written. This corresponds to the packing period. Thin-film transistors equipped with the aforementioned high-purity oxide semiconductor layer. This allows for longer retention periods (periods 251 and 252), making it particularly useful for displaying still images. When displaying, the frequency of writing signals can be significantly reduced. Therefore, the display For displays such as still images with infrequent switching, reduce the number of times signals are written to pixels. This allows for lower power consumption.

[0083] Furthermore, the voltage applied to the gate of the drive transistor connected to the EL element is used for still images. Because it decays while displaying, the voltage applied to the gate of the drive transistor is maintained. Considering the proportion that is being held, a refresh operation may be performed as needed. For example, drive transition A predetermined level relative to the voltage value (initial value) immediately after writing a signal to the gate of the sta. The refresh operation should be performed when the voltage drops to a predetermined level. The pressure should preferably be set to a level where no flickering is noticeable relative to the initial value. Specifically, If the display target is video, the value should be 1.0% lower than the initial value, preferably 0.3% lower. Each time this happens, it is preferable to perform a refresh operation (rewrite). If it is a character, every time it becomes 10% lower than the initial value, preferably 3% lower, then It is preferable to perform a refresh operation (rewrite).

[0084] Figure 4(A) shows the configuration of the top view and cross-sectional view of a pixel when no retention capacity is formed. ), (B) are shown. The configuration shown in Figures 4(A) and (B) is the same as the configuration in Figures 1(A) and (B). This corresponds to a diagram with the quantity curve omitted. This can also be seen from the top view shown in Figure 4(A) and the cross-sectional view shown in Figure 4(B). As can be seen, by using a thin-film transistor having an oxide semiconductor layer, the pixel electrode 10 The area occupied by 5, i.e., the aperture ratio, can be improved. Also, the cross-sectional view shown in Figure 4(B) As can be seen from this, by using a thin-film transistor having an oxide semiconductor layer, capacitance lines This reduces the aperture and expands the area occupied by the pixel electrode 105, i.e., the aperture. The rate can be improved.

[0085] As in this embodiment, a highly purified oxide semiconductor layer is used, resulting in an extremely low off-current value. By applying thin-film transistors to the pixel area, it is possible to create pixels without providing a holding capacitor in the pixel area. A display device capable of displaying images (especially videos) can be provided. Also, when a storage capacity is provided... However, the holding capacity allows for a longer period of time during which the voltage can be maintained, when displaying still images, etc. A display device with reduced power consumption can be provided. Furthermore, by improving the aperture ratio... This enables the provision of a display device having a high-resolution display unit.

[0086] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0087] (Embodiment 2) This embodiment illustrates an example of a thin-film transistor applicable to the display device disclosed herein. The thin-film transistor 410 shown in this embodiment is the same as the thin-film transistor 10 in Embodiment 1. It can be used as 6.

[0088] One embodiment of the thin-film transistor and the method for fabricating the thin-film transistor according to this embodiment is shown in Figure 5 and This will be explained using Figure 6.

[0089] Figures 5(A) and 5(B) show examples of the top surface and cross-sectional structure of a thin-film transistor. The thin-film transistor 410 shown in () is one of the thin-film transistors with a top gate structure. .

[0090] Figure 5(A) is a top view of the thin-film transistor 410 with a top gate structure, and Figure 5(B) is This is a cross-sectional view along the line C1-C2 in Figure 5(A).

[0091] The thin-film transistor 410 has an insulating layer 407 and an oxide semiconductor layer on a substrate 400 having an insulating surface. Conductor layer 412, source electrode layer or drain electrode layer 415a, and source electrode layer or drain It includes an electrode layer 415b, a gate insulating layer 402, and a gate electrode layer 411, and the source electrode layer or Wiring layer 4 is provided on the drain electrode layer 415a, the source electrode layer, or the drain electrode layer 415b, respectively. 14a and wiring layer 414b are located in contact with each other and are electrically connected.

[0092] Furthermore, the thin-film transistor 410 will be explained using a single-gate thin-film transistor. However, if necessary, a thin film transistor with a multi-gate structure having multiple channel formation regions It can also form a "ta".

[0093] The thin-film transistor 410 is fabricated on the substrate 400 using Figures 6(A) to (E) below. Let me explain the process.

[0094] There are no major restrictions on the substrates that can be used for the substrate 400 having an insulating surface, however In both cases, it is necessary that it has sufficient heat resistance to withstand subsequent heat treatment. Glass substrates such as borosilicate glass and aluminoborsilicate glass can be used.

[0095] Furthermore, for glass substrates, if the subsequent heat treatment temperature is high, the strain point will be 730°C or higher. It is best to use the following. Also, for the glass substrate, for example, aluminosilicate glass, Glass materials such as luminoborosilicate glass and bariumborosilicate glass are used. Furthermore, by including more barium oxide (BaO) compared to boron oxide, it becomes more practical. A heat-resistant glass can be obtained. For this reason, a glass substrate containing more BaO than B2O3 is used. It is preferable to do so.

[0096] In addition, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used instead of the glass substrates mentioned above. A substrate made of edge material may also be used. Other materials such as crystallized glass can also be used. Plastic substrates and the like can also be used as appropriate.

[0097] First, an insulating layer 407, which will serve as the base film, is formed on a substrate 400 having an insulating surface. The insulating layer 407 in contact with the conductive layer consists of a silicon oxide layer, a silicon oxide nitride layer, and an aluminum oxide layer. It is preferable to use an oxide insulating layer such as a 4mm layer or an aluminum oxide nitride layer. Insulating layer 4 For the formation of 07, plasma CVD or sputtering methods can be used. However, in order to prevent a large amount of hydrogen from being contained in the insulating layer 407, the sputtering method is used. It is preferable to form an insulating layer 407 using this method.

[0098] In this embodiment, a silicon oxide layer is formed as the insulating layer 407 by sputtering. The substrate 400 is transported to the processing room and spat with high-purity oxygen from which hydrogen and moisture have been removed. Tagas is introduced and a silicon semiconductor target is used to create an insulating layer 407 on the substrate 400. A silicon oxide layer is formed. The substrate 400 may be at room temperature or heated. .

[0099] For example, using quartz (preferably synthetic quartz), with a substrate temperature of 108°C, between the substrate and the target... Distance between terminals (TS distance) 60mm, pressure 0.4Pa, high-frequency power supply 1.5kW, oxygen and Under an argon atmosphere (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1:1), R A silicon oxide film will be deposited using the F sputtering method. The film thickness will be 100 nm. As a target for forming a silicon oxide film, instead of quartz (preferably synthetic quartz) A silicon target can be used. Furthermore, oxygen or oxygen can be used as the sputtering gas. The procedure is carried out using a mixed gas of argon and argon.

[0100] In this case, it is preferable to form the insulating layer 407 while removing residual moisture in the processing chamber. This is to ensure that the insulating layer 407 does not contain hydrogen, hydroxyl groups, or moisture.

[0101] To remove residual moisture from the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable. Furthermore, as an exhaust method, a turbo pump with a cold trap is used. It is also acceptable. The treatment chamber, which has been evacuated using a cryopump, contains, for example, hydrogen atoms and water (H2 Since compounds containing hydrogen atoms, such as O), are exhausted, film formation and isolation are performed in the processing chamber. The concentration of impurities in the marginal layer 407 can be reduced.

[0102] The sputtering gas used when forming the insulating layer 407 is hydrogen, water, hydroxyl groups, or hydrides. A high-purity gas is used in which impurities have been removed to a concentration of approximately ppm, preferably approximately ppb. It is desirable to have them.

[0103] Sputtering methods include RF sputtering, which uses a high-frequency power supply for sputtering, and DC sputtering method using a current power supply, and pulsed DC sputtering method where a pulsed bias is applied. There is a puttering method. RF sputtering is mainly used when depositing insulating films. DC sputtering is primarily used for depositing metal films.

[0104] There are also multi-point sputtering systems that can set up multiple targets made of different materials. The apparatus can deposit multiple layers of different material films in the same chamber, or multiple types of materials in the same chamber. It is also possible to deposit films by simultaneously discharging electrical currents from similar materials.

[0105] Furthermore, sputtering using a magnetron sputtering method that incorporates a magnetic mechanism inside the chamber... ECRs use devices that generate plasma using microwaves instead of glow discharges. There are sputtering machines that use the puttering method.

[0106] Furthermore, as a film deposition method using the sputtering method, the target material and sputtering gas are used during film deposition. Reactive sputtering is a method that uses chemical reactions to form thin films of compounds. Alternatively, there is a bias sputtering method that applies voltage to the substrate during film deposition.

[0107] Furthermore, the insulating layer 407 may also have a laminated structure, for example, a silicon nitride layer from the substrate 400 side, and a silicon nitride layer. Nitride insulation such as a silicon oxide layer, an aluminum nitride layer, or an aluminum nitride oxide layer. A laminated structure of the layer and the oxide insulating layer may also be used.

[0108] For example, a spam containing high-purity nitrogen from which hydrogen and moisture have been removed between the silicon oxide layer and the substrate. A silicon nitride layer is deposited using a silicon target after introducing a tatta gas. Even if there is residual moisture in the processing chamber, similar to the silicon oxide layer, the silicon nitride layer is formed while removing residual moisture in the processing chamber. It is preferable to form a film.

[0109] When forming a silicon nitride layer, the substrate may be heated during film formation.

[0110] When a silicon nitride layer and a silicon oxide layer are laminated as the insulating layer 407, the silicon nitride layer The silicon oxide layer and the silicon oxide layer are deposited in the same processing chamber using a common silicon target. This can be done by first introducing a gas containing nitrogen, and then placing a silicon target installed in the processing chamber. A silicon nitride layer is formed using this method, and then the gas is switched to an oxygen-containing gas to form the same silicon target. A silicon oxide layer is formed using a tweezers. The silicon nitride layer and the silicon oxide layer are exposed to the atmosphere. Because it can be formed continuously without exposure, hydrogen and moisture can be present on the silicon nitride layer surface. This prevents the adsorption of pure substances.

[0111] Next, an oxide semiconductor film with a thickness of 2 nm to 200 nm is formed on the insulating layer 407. .

[0112] Furthermore, in order to minimize the presence of hydrogen, hydroxyl groups, and water in the oxide semiconductor film, As a pretreatment for film deposition, an insulating layer 407 is formed on the substrate in the preheating chamber of the sputtering apparatus. The 400 is preheated to remove impurities such as hydrogen and moisture adsorbed on the substrate 400 and then exhausted. This is preferable. Furthermore, a cryopump is preferred as the exhaust means provided in the preheating chamber. This preheating process can be omitted. Also, this preheating is necessary for the gate formation that occurs later. This may be done on the substrate 400 before the deposition of the insulating layer 402, or on the source electrode layer or other parts that are formed later. Substrate 4 having a rain electrode layer 415a and a source electrode layer or drain electrode layer 415b formed on it. The same procedure can be applied to 00.

[0113] Furthermore, before depositing the oxide semiconductor film by sputtering, argon gas is introduced. Reverse sputtering, which generates plasma, is performed to remove dust adhering to the surface of the insulating layer 407. It is preferable to do so. Reverse sputtering is a method in which voltage is not applied to the target side, and an argon atmosphere is used. Under atmospheric pressure, a voltage is applied to the substrate side using a high-frequency power supply to form plasma near the substrate and the surface This is a method of modification. Note that nitrogen, helium, oxygen, etc., can be used instead of an argon atmosphere. That's good too.

[0114] Oxide semiconductor films are deposited by sputtering. Oxide semiconductor films are In-Ga-Z nO-based non-single crystal films, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga- Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, I n-Sn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn-O series, Zn -O-based oxide semiconductor films are used. In this embodiment, the oxide semiconductor film is In-Ga-Z The film is deposited by sputtering using an nO-based oxide semiconductor film deposition target. Oxide semiconductor films are fabricated under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas Formed by sputtering in a sputtering (typically argon) and oxygen atmosphere. This can be done. Also, when using the sputtering method, SiO2 should be 2% by weight or more and 10% by weight. Film deposition may be performed using targets including the following:

[0115] The sputtering gas used when depositing oxide semiconductor films is hydrogen, water, hydroxyl groups, or hydrides. Which impurities should be removed to a concentration of approximately ppm or ppb in a high-purity gas? It is preferable.

[0116] Zinc oxide is the main material used as a target for fabricating oxide semiconductor films by sputtering. A metal oxide target can be used. Other examples include oxide semiconductor film deposition targets containing In, Ga, and Zn (composition ratio) As such, In2O3:Ga2O3:ZnO = 1:1:1 [mol ratio], In:Ga:Zn =1:1:0.5 [atomic ratio] can be used. Also, as a target for forming an oxide semiconductor film containing In, Ga, and Zn, a target having a composition ratio of In:Ga:Zn = 1:1:1 [at omic ratio], or In:Ga:Zn = 1:1:2 [atomic ratio] can also be used. The filling rate of the target for forming an oxide semiconductor film is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using a target for forming an oxide semiconductor film with a high filling rate, the formed oxide semiconductor film becomes a dense film. The oxide semiconductor film holds a substrate in a processing chamber maintained in a reduced-pressure state, removes residual moisture in the processing chamber, introduces a sputtering gas from which hydrogen and moisture have been removed while removing the residual moisture, and forms an oxide semiconductor film on the substrate 400 using a metal oxide as the target.

[0117] For removing the residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, as an exhaust means, a turbo pump with a cold trap added may be used. The processing chamber evacuated using a cryopump is evacuated of, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well), so that the concentration of impurities contained in the oxide semiconductor film formed in the processing chamber can be reduced. Also, the substrate may be heated during the formation of the oxide semiconductor film. As an example of the film formation conditions, the substrate temperature is room temperature, the distance between the substrate and the target is 110 mm, the pressure is 0.4 Pa, the DC power supply is 0.5 kW, oxygen and argon (oxygen flow rate 15 scc ), and argon flow rate 85 scc) are used. The processing chamber evacuated using a cryopump is evacuated of, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well), so that the concentration of impurities contained in the oxide semiconductor film formed in the processing chamber can be reduced. Also, the substrate may be heated during the formation of the oxide semiconductor film. It may be heated.

[0118] As an example of the film formation conditions, the substrate temperature is room temperature, the distance between the substrate and the target is 110 mm, the pressure is 0.4 Pa, the DC power supply is 0.5 kW, oxygen and argon (oxygen flow rate 15 scc The conditions applied are under an atmosphere with an argon flow rate of 30 sccm. Using a power supply reduces the amount of powdery material (also called particles or dust) generated during film formation. This is preferable because it also results in a uniform film thickness distribution. The oxide semiconductor film is preferably 5 nm or more and 30 nm thick. The thickness should be less than or equal to nm. Note that the appropriate thickness varies depending on the oxide semiconductor material used. You can then choose the appropriate thickness.

[0119] Next, the oxide semiconductor film is transformed into island-shaped oxide semiconductor layers 4 by the first photolithography process. Process to 12 (see Figure 6(A)). Also, to form island-shaped oxide semiconductor layers 412 The resist mask may be formed by an inkjet method. Since the photomask method does not require a photomask, manufacturing costs can be reduced.

[0120] Note that etching of oxide semiconductor films here can be done by dry etching or wet etching. You can use either "gu" or "gu," and both are acceptable.

[0121] Etching gases used in dry etching include chlorine-containing gases (chlorine-based gases, for example) Chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC) l4) etc.) are preferable.

[0122] Also, fluorine-containing gases (fluorinated gases, such as carbon tetrafluoride (CF4) and sulfur hexafluoride (S)) F6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (H Br), oxygen (O2), and these gases can be mixed with noble gases such as helium (He) and argon (Ar). Gases with added sulfites, etc., can be used.

[0123] As for dry etching methods, parallel plate type RIE (Reactive Ion Etching) Methods such as the ing method and ICP (Inductively Coupled Plasma: induction) A coupled plasma etching method can be used. The desired processing shape can be etched. To that end, etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the electrode on the substrate side) Adjust the amount of power used, the electrode temperature on the substrate, etc., as appropriate.

[0124] The etching solution used for wet etching is a solution of phosphoric acid, acetic acid, and nitric acid, Ammonia Hydrogenated Water (31% hydrogen peroxide by weight: 28% ammonia by weight: water = 5:2:2) These can be used. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0125] Furthermore, the etching solution after wet etching is washed away along with the etched material. The material is removed. The waste etching solution containing the removed material is purified, and the material contained in it is removed. It may be reused. Indium and other elements contained in the oxide semiconductor layer can be extracted from the waste liquid after etching. By recovering and reusing materials, resources can be used effectively and costs can be reduced. .

[0126] Etching conditions (etching) can be adjusted according to the material so that the desired processing shape can be etched. Adjust the solution, etching time, temperature, etc. as appropriate.

[0127] In this embodiment, a wet etching solution is used, which is a mixture of phosphoric acid, acetic acid, and nitric acid. The oxide semiconductor film is processed into island-shaped oxide semiconductor layers 412 by etching.

[0128] In this embodiment, the oxide semiconductor layer 412 is subjected to a first heat treatment. The temperature is set to be 400°C or higher and 750°C or lower, preferably 400°C or higher and lower than the distortion point of the substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and heat treatment is performed on the oxide semiconductor layer for 1 hour at 450°C in a nitrogen atmosphere. Then, without exposing the oxide semiconductor layer to air, re-mixing of water or hydrogen into the oxide semiconductor layer is prevented to obtain the oxide semiconductor layer. By this first heat treatment, dehydration or dehydrogenation of the oxide semiconductor layer 412 can be performed. Note that the heat treatment apparatus is not limited to an electric furnace, and it may be equipped with an apparatus that heats the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats the object to be treated by radiation of light (electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the gas, an inert gas such as a noble gas like argon or a gas that does not react with the object to be treated by heat treatment, such as nitrogen, is used. For example, as the first heat treatment, the substrate may be moved and placed in an inert gas heated to a high temperature of 650°C to 700°C, heated for several minutes, and then a GRTA may be performed by moving the substrate out of the inert gas heated to a high temperature. When using GRTA, high-temperature heat treatment in a short time becomes possible. By this first heat treatment, dehydration or dehydrogenation of the oxide semiconductor layer 412 can be performed.

[0129] Note that the heat treatment apparatus is not limited to an electric furnace, and it may be equipped with an apparatus that heats the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats the object to be treated by radiation of light (electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the gas, an inert gas such as a noble gas like argon or a gas that does not react with the object to be treated by heat treatment, such as nitrogen, is used. Note that the heat treatment apparatus is not limited to an electric furnace, and it may be equipped with an apparatus that heats the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats the object to be treated by radiation of light (electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the gas, an inert gas such as a noble gas like argon or a gas that does not react with the object to be treated by heat treatment, such as nitrogen, is used.

[0130] For example, as the first heat treatment, the substrate may be moved and placed in an inert gas heated to a high temperature of 650°C to 700°C, heated for several minutes, and then a GRTA may be performed by moving the substrate out of the inert gas heated to a high temperature. When using GRTA, high-temperature heat treatment in a short time becomes possible. Note that the heat treatment apparatus is not limited to an electric furnace, and it may be equipped with an apparatus that heats the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used.

[0131] In the first heat treatment, nitrogen or a noble gas such as helium, neon, or argon is used. It is preferable that it does not contain water, hydrogen, etc. Alternatively, nitrogen introduced into the heat treatment device, Alternatively, the purity of noble gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably 7N (99.99999%) or higher (i.e., impurity concentration of 1 ppm or less, preferably It is preferable to keep the concentration at 0.1 ppm or less.

[0132] Furthermore, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor film In some cases, crystallization may occur, forming a microcrystalline or polycrystalline film. For example, if the crystallization rate is 90% or higher. Alternatively, it may become an oxide semiconductor film with more than 80% microcrystalline properties. Also, the first heat treatment Depending on the conditions or the material of the oxide semiconductor layer, amorphous oxide semiconductors that do not contain crystalline components may be used. It can also form a conductive film. Furthermore, it can contain microcrystalline regions (particle size 1 nm or larger) within an amorphous oxide semiconductor. In the case of oxide semiconductor films where elements smaller than 20 nm (typically between 2 nm and 4 nm) are mixed together There are also combinations.

[0133] Furthermore, the first heat treatment of the oxide semiconductor layer is performed on the oxide before it is processed into an island-shaped oxide semiconductor layer. This can also be done on semiconductor films. In that case, after the first heat treatment, the substrate is removed from the heating device. The material is removed and the photolithography process is performed.

[0134] Heat treatments that have the effect of dehydrating and dehydrogenating oxide semiconductor layers are used in oxide semiconductor layer formation. After the film is formed, the source electrode and drain electrode are stacked on the oxide semiconductor layer, and then the source electrode and This can be done either after forming a gate insulating layer on the drain electrode, or afterwards.

[0135] Next, a conductive film is formed on the insulating layer 407 and the oxide semiconductor layer 412. It can be formed by the tarting method or vacuum deposition method. Suitable materials for the conductive film include Al, Cr, and Cu. , elements selected from Ta, Ti, Mo, W, or alloys containing the above elements, Examples include alloy films combining the elements described above. Also, manganese, magnesium, zirconium, and zirconium are examples. Even if one or more materials selected from conium, beryllium, and thorium are used That's good. Also, the conductive film may be a single layer or a laminated structure of two or more layers. For example, silica A single-layer structure of an aluminum film containing condensate, and a two-layer structure in which a titanium film is laminated on top of an aluminum film. A Ti film is formed, and an aluminum film is layered on top of the Ti film, and then another Ti film is formed on top of that. Examples include a three-layer film structure. Also, aluminum can be combined with titanium (Ti), tantalum (Ta), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Neodymium (Nd), Sulfur A film, alloy film, or nitrogen film made from a combination of one or more elements selected from the elements of zinc (Sc). A film coating may also be used.

[0136] A second photolithography step forms a resist mask on the conductive film, and selectively extracts the residue. Performing a chapping process, the source electrode layer or drain electrode layer 415a, source electrode layer or drain electrode After forming the polar layer 415b, the resist mask is removed (see Figure 6(B)). The ends of the formed source electrode layer and drain electrode layer are tapered, and the stacked layers on top of them This is preferable because it improves the coverage of the insulating layer.

[0137] In this embodiment, the source electrode layer or drain electrode layer 415a, the source electrode layer or drain A titanium film with a thickness of 150 nm is formed as electrode layer 415b by sputtering.

[0138] Furthermore, during etching of the conductive film, the oxide semiconductor layer 412 is removed. The materials and etching conditions are adjusted so that the insulating layer 407 below is not exposed. Adjust as needed.

[0139] In this embodiment, a Ti film is used as the conductive film, and the oxide semiconductor layer 412 is made of In-Ga -Zn-O based oxide semiconductors are used, with ammonia peroxide (31% by weight) as the etchant. Use hydrogen oxide solution (28% by weight), ammonia solution (5:2:2), and water.

[0140] In the second photolithography process, only a portion of the oxide semiconductor layer 412 is etched. This can result in an oxide semiconductor layer having grooves (recesses). Furthermore, the source electrode layer may also be formed. This is for forming the drain electrode layer 415a, the source electrode layer, or the drain electrode layer 415b The resist mask may be formed by an inkjet method. Since this method eliminates the need for photomasks, manufacturing costs can be reduced.

[0141] For exposure during the resist mask formation in the second photolithography process, ultraviolet light and KrF light are used. A laser beam or ArF laser beam is used. Underneath the adjacent source electrode layer on the oxide semiconductor layer 412. The gap width between the end and the lower end of the drain electrode layer determines the subsequent formation of the thin-film transistor. The channel length L is determined. Note that when performing exposure with a channel length L = less than 25 nm, the number Extreme ultraviolet light (Ultraviolet) has extremely short wavelengths, ranging from nanometers to several tens of nanometers. Using t), exposure is performed during the resist mask formation in the second photolithography step. Exposure with ultraviolet light offers high resolution and a large depth of field. Therefore, the thin film traces that are later formed... The channel length L of the inverter can also be set to 10 nm or more and 1000 nm or less, and the circuit This allows for faster operation speeds and, because the off-current value is extremely small, it also contributes to lower power consumption. It is possible.

[0142] SO, insulating layer 407, oxide semiconductor layer 412, source electrode layer or drain electrode layer 415 a. A gate insulating layer 402 is formed on the source electrode layer or drain electrode layer 415b (Figure 6) See (C). ).

[0143] Here, by removing impurities, the oxide semiconductor is converted to type i or substantially converted to type i (high Purified oxide semiconductors are extremely sensitive to interface states and interface charges, therefore, The interface with the insulating film is important. Therefore, the gate insulating film that comes into contact with the highly purified oxide semiconductor is crucial. The GI (grain edge) requires high quality.

[0144] For example, high-density plasma CVD using μ-wave (2.45 GHz) produces dense materials with high dielectric strength. It is preferable because it can form a high-quality insulating film. High-purity oxide semiconductor and high-quality gas By ensuring close contact with the insulating film, the interface state density is reduced, resulting in improved interface properties. Because it is possible.

[0145] Furthermore, insulating films obtained by high-density plasma CVD can form films of a consistent thickness. Therefore, it has excellent step coverage. In addition, the insulating film obtained by a high-density plasma CVD apparatus This allows for precise control of the thickness of thin films.

[0146] Of course, if it can form a good insulating film as a gate insulating film, sputtering Other film deposition methods such as plasma CVD can be applied. Furthermore, post-deposition heat treatment can be performed. Even if the film quality of the gate insulating film and the interface characteristics with the oxide semiconductor are modified by this process, Good. In any case, it is essential that the film quality as a gate insulating film is good, as well as oxidation Any material that can reduce the interface state density with the semiconductor and form a good interface would be acceptable.

[0147] Furthermore, 85℃, 2×10 6 V / cm, 12-hour gate bias thermal stress test (B In the T test, if impurities are added to the oxide semiconductor, the impurities and the oxide semiconductor... The bonds with the main component are broken by a strong electric field (B: bias) and high temperature (T: temperature), and The resulting uncoupled hands induce a drift in the threshold voltage (Vth). Therefore, the present invention removes impurities from oxide semiconductors, especially hydrogen and water, as much as possible, and as described above. By improving the interfacial properties with the insulating film, a stable thin film transit is achieved even under BT testing. This makes it possible to obtain Zista.

[0148] Furthermore, the gate insulating layer consists of a silicon oxide layer, a silicon nitride layer, a silicon oxide nitride layer, and an acid nitride layer. A silicon oxide layer or an aluminum oxide layer can be formed as a single layer or in a laminated manner.

[0149] The gate insulating layer is formed using a high-density plasma CVD apparatus. Here, high-density plasma The CVD apparatus is 1 × 10 11 / cm 3 This refers to a device capable of achieving the above plasma density. For example, by applying microwave power of 3kW to 6kW to generate plasma, an insulating film is formed. The film is formed.

[0150] Monosilane gas (SiH4), nitrous oxide (N2O), and dilute gas are placed in the chamber as material gases. By introducing a system that generates high-density plasma under a pressure of 10 Pa to 30 Pa, it can insulate glass and other materials. An insulating film is formed on a substrate with a surface. Then, the supply of monosilane gas is stopped, and the atmosphere is exposed. Plasma treatment is performed on the insulating film surface by introducing nitrous oxide (N2O) and a noble gas without exposure to the elements. It is permissible to do so. At a minimum, it should be done by introducing nitrous oxide (N2O) and a noble gas onto the insulating film surface. The plasma treatment is performed after the deposition of the insulating film. The insulating film that has undergone the above process sequence is a film This insulating film is thin, and can ensure reliability even at thicknesses of less than 100 nm. .

[0151] The flow rate ratio of monosilane gas (SiH4) to nitrous oxide (N2O) introduced into the chamber is The ratio should be in the range of 1:10 to 1:200. Furthermore, the noble gas to be introduced into the chamber is: Helium, argon, krypton, xenon, etc. can be used, but among them the cheapest is It is preferable to use a certain type of argon.

[0152] The insulating film obtained through the above process sequence is different from the insulating film obtained with a conventional parallel-plate type PCVD apparatus. The results differ significantly, and when comparing etching rates using the same etchant, Therefore, the insulating film obtained with a parallel-plate type PCVD apparatus is 10% or more slower or 20% or more slower, and high The insulating film obtained using a density plasma CVD system can be described as a dense film.

[0153] In this embodiment, the gate insulating layer 402 is a silicon oxide nitride (SiO2) film with a thickness of 100 nm. Also called xNy, where x>y>0). The gate insulating layer 402 is high-density plasma Monosilane (SiH4), nitrous oxide (N2O), and A are used as film-forming gases in the CVD apparatus. Using argone (Ar), the respective flow rates are SiH4 / N2O / Ar = 250 / 2500 / With a pressure of 2500 (sccm), deposition pressure of 30 Pa, and deposition temperature of 325°C, a 5kW microphone was used. Plasma is generated by applying radio wave power, and then the film is deposited.

[0154] Alternatively, the gate insulating layer 402 may be formed by sputtering. When forming a silicon oxide film, a silicon target or a quartz target can be used as the target. Using a blob, the sputtering gas is either oxygen or a mixture of oxygen and argon. When using the sputtering method, a large amount of hydrogen is not included in the gate insulating layer 402. can.

[0155] Furthermore, the gate insulating layer 402 is the source electrode layer or drain electrode layer 415a, source electrode layer Alternatively, a structure can be formed in which a silicon oxide layer and a silicon nitride layer are stacked from the drain electrode layer 415b side. It is also possible to use an acid coating with a film thickness of 5 nm to 300 nm as the first gate insulating layer. Silicon ionized layer (SiO x (x>0)) is formed, and a second gate insulating layer is placed on the first gate insulating layer. As the border layer, a silicon nitride layer with a thickness of 50 nm to 200 nm is formed by sputtering. SiN y (y>0)) can be stacked. For example, a pressure of 0.4 Pa and a high-frequency power supply of 1.5 kΩ may be used. W, oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1:1) atmosphere A silicon oxide layer with a thickness of 100 nm can be formed by RF sputtering under ambient air conditions.

[0156] Next, a resist mask is formed by a third photolithography process, and then selectively etched. By performing a process to remove a portion of the gate insulating layer 402, the source electrode layer or drain electrode layer 4 15a, forming openings 421a, 421b that reach the source electrode layer or drain electrode layer 415b. To accomplish (see Figure 6(D)).

[0157] Next, after forming a conductive film on the gate insulating layer 402 and the openings 421a and 421b, the fourth The gate electrode layer 411 and wiring layers 414a and 414b are formed by the photolithography process. The resist mask may also be formed by an inkjet method. Since the inkjet method does not require the use of a photomask, manufacturing costs can be reduced.

[0158] Furthermore, the materials for the gate electrode layer 411 and the wiring layers 414a and 414b are molybdenum, titanium, Metals such as chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium It can be formed in a single layer or in layers using materials or alloy materials that mainly consist of these materials. Cut.

[0159] For example, a two-layer stacked structure consisting of a gate electrode layer 411 and wiring layers 414a and 414b is: A two-layer laminated structure in which a molybdenum layer is laminated on top of a luminium layer, or a molybdenum layer on top of a copper layer. A two-layer structure with stacked layers, or a copper layer with a titanium nitride layer or tantalum nitride layer stacked on top of it. A two-layer structure, preferably a two-layer structure consisting of a titanium nitride layer and a molybdenum layer, is preferred. 3 The layered structure consists of a tungsten layer or tungsten nitride, and aluminum and silicon. A laminate of a condensing alloy or an alloy of aluminum and titanium, and a titanium nitride or titanium layer. It is preferable to form a laminate. Furthermore, a conductive film with light-transmitting properties is used to form the gate electrode layer. It is also possible to do so. Examples of conductive films with light-transmitting properties include translucent conductive oxides. It is possible to do so.

[0160] In this embodiment, the gate electrode layer 411 and the wiring layers 414a and 414b are sputtered. A titanium film with a thickness of 150 nm is formed by this method.

[0161] Next, a second heat treatment (preferably 2) is performed under an inert gas atmosphere or an oxygen gas atmosphere. The process is carried out at a temperature between 00°C and 400°C, for example, between 250°C and 350°C. A second heat treatment is performed at 250°C for 1 hour under a nitrogen atmosphere. This may also be done after forming a protective insulating layer or a planar insulating layer on the thin-film transistor 410.

[0162] Furthermore, a heat treatment is performed in air at a temperature between 100°C and 200°C for between 1 hour and 30 hours. This may also be done by heating while maintaining a constant heating temperature, or by heating from room temperature to 10 The process involves repeatedly raising the temperature from 0°C to 200°C and then lowering it back down to room temperature. This may be done. Alternatively, this heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. Good. Heating under reduced pressure can shorten the heating time.

[0163] In the above process, the concentrations of hydrogen, water, hydride, and hydroxide are reduced in the oxide semiconductor layer 41. A thin-film transistor 410 having 2 can be formed (see Figure 6(E)). Transistor 410 is applied as thin-film transistor 106 in Embodiment 1. It is possible.

[0164] Furthermore, a protective insulating layer and a planarizing insulating layer for planarization are provided on the thin-film transistor 410. Alternatively, a silicon oxide layer, a silicon nitride layer, or silicon oxide-nitride can be used as a protective insulating layer. A layer, a silicon nitride oxide layer, or an aluminum oxide layer can be formed as a single layer or in a laminated manner. can.

[0165] Furthermore, the planar insulating layer can be made of polyimide, acrylic, benzocyclobutene, or polyamide. In addition, heat-resistant organic materials such as epoxy can be used. In addition, low-dielectric constant materials (low-k materials), siloxane resins, PSG (phosphorus glass), BP SG (Limboron glass), etc., can be used. A planar insulating layer may be formed by laminating multiple edge films.

[0166] Siloxane-based resins are formed using siloxane-based materials as the starting material for Si-OS. This corresponds to a resin containing i-bonds. Siloxane resins use organic groups (e.g., alkyl groups) as substituents. You may also use aryl groups or fluoro groups. Furthermore, organic groups may have fluoro groups. You can.

[0167] The method for forming the planar insulating layer is not particularly limited and can be done by sputtering, SOG, etc., depending on the material. Spin coating, dipping, spray coating, droplet ejection (inkjet method, screen printing) Printing (offset printing, etc.), doctor knife, roll coater, curtain coater, knife Coaters and the like can be used.

[0168] As described above, when forming an oxide semiconductor film, residual moisture in the reaction atmosphere is removed. This makes it possible to reduce the concentration of hydrogen and hydrides in the oxide semiconductor film. This can help stabilize oxide semiconductor films.

[0169] As described above, by applying a highly purified oxide semiconductor layer to a thin-film transistor, This makes it possible to provide a thin-film transistor with reduced off-current. By applying the thin-film transistor with reduced off-current, as explained above, to the pixels of a display device, Therefore, the retention capacitance provided in the pixel can extend the period during which the voltage can be retained. This allows us to provide a display device that consumes less power when displaying data.

[0170] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0171] (Embodiment 3) This embodiment illustrates an example of a thin-film transistor applicable to the display device disclosed herein. Furthermore, parts and processes that are the same as or have similar functions as those in Embodiment 2 are considered to be in Embodiment 2. The same procedure as in section 2 can be used, and the explanation of the repetition will be omitted. Detailed explanations of the same sections will also be omitted. Omitted. The thin-film transistor 460 shown in this embodiment is the thin-film transistor of Embodiment 1. It can be used as Ta106.

[0172] One embodiment of the thin-film transistor and the method for fabricating the thin-film transistor according to this embodiment is shown in Figure 7 and This will be explained using Figure 8.

[0173] Figures 7(A) and 7(B) show examples of the top surface and cross-sectional structure of a thin-film transistor. The thin-film transistor 460 shown in () is one of the thin-film transistors with a top-gate structure. .

[0174] Figure 7(A) is a top view of the thin-film transistor 460 with a top gate structure, and Figure 7(B) is This is a cross-sectional view along the line D1-D2 in Figure 7(A).

[0175] The thin-film transistor 460 has an insulating layer 457 on a substrate 450 having an insulating surface, and a source power Polar layer or drain electrode layer 465a (465a1, 465a2), oxide semiconductor layer 462, Source electrode layer or drain electrode layer 465b, wiring layer 468, gate insulating layer 452, gate Includes electrode layer 461 (461a, 461b), source electrode layer or drain electrode layer 465a (465a1, 465a2) are electrically connected to wiring layer 464 via wiring layer 468. Furthermore, although not shown in the diagram, the source electrode layer or drain electrode layer 465b is also a gate insulating layer. The opening provided in 452 is electrically connected to the wiring layer.

[0176] The thin-film transistor 460 is fabricated on the substrate 450 using Figures 8(A) to (E) below. Let me explain the process.

[0177] First, an insulating layer 457, which will serve as the base film, is formed on a substrate 450 having an insulating surface.

[0178] In this embodiment, a silicon oxide layer is formed as the insulating layer 457 by sputtering. The substrate 450 is transported to the processing room and spat with high-purity oxygen from which hydrogen and moisture have been removed. Tagus is introduced and a silicon target or quartz (preferably synthetic quartz) is used on the substrate 45 A silicon oxide layer is formed as an insulating layer 457 on 0. Oxygen or This is done using a mixed gas of oxygen and argon.

[0179] For example, using quartz (preferably synthetic quartz) with a purity of 6N, and with a substrate temperature of 108°C, Distance between the plate and target (TS distance) 60 mm, pressure 0.4 Pa, high-frequency power supply 1.5kW, oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1 1) A silicon oxide film is deposited by RF sputtering under atmospheric conditions. The film thickness is 100 The value should be nm. Furthermore, quartz (preferably) is used as the target for forming the silicon oxide film. A silicon target can be used instead of synthetic quartz.

[0180] In this case, it is preferable to form the insulating layer 457 while removing residual moisture in the processing chamber. This is to ensure that the insulating layer 457 does not contain hydrogen, hydroxyl groups, or moisture. The treatment chamber, which is evacuated using an optopod, contains, for example, hydrogen atoms and water (H2O) containing hydrogen atoms. Because compounds containing the included compounds are exhausted, the film is formed in the processing chamber and is contained in the insulating layer 457. The concentration of impurities can be reduced.

[0181] The sputtering gas used when forming the insulating layer 457 is hydrogen, water, hydroxyl groups, or hydrides. By using high-purity gas from which impurities have been removed to concentrations of approximately ppm or ppb, preferable.

[0182] Furthermore, the insulating layer 457 may also have a laminated structure, for example, a silicon nitride layer from the substrate 450 side, and a silicon nitride layer. Nitride insulating layers such as silicon oxide layer, aluminum nitride layer, and aluminum nitride oxide layer Alternatively, a laminated structure with the above-mentioned oxide insulating layer may be used.

[0183] For example, a spam containing high-purity nitrogen from which hydrogen and moisture have been removed between the silicon oxide layer and the substrate. A silicon nitride layer is deposited using a silicon target after introducing a tatta gas. Even if there is residual moisture in the processing chamber, similar to the silicon oxide layer, the silicon nitride layer is formed while removing residual moisture in the processing chamber. It is preferable to form a film.

[0184] Next, a conductive film is formed on the insulating layer 457, and the conductive film is made conductive by the first photolithography process. A resist mask is formed on the film, and selective etching is performed on the source electrode layer or drain. After forming electrode layers 465a1 and 465a2, remove the resist mask (see Figure 8(A)). (Illuminate.) The source electrode layer or drain electrode layer 465a1, 465a2 is divided in the cross-sectional view. As shown, it is a continuous film. Note that the formed source electrode layer and drain electrode layer A tapered end is preferable because it improves the coverage of the gate insulating layer laminated on top. stomach.

[0185] The material for the source electrode layer or drain electrode layer 465a1, 465a2 is Al, Cr, An element selected from Cu, Ta, Ti, Mo, and W, or an alloy containing the above elements. Examples include alloy films combining the elements mentioned above. Also, manganese, magnesium, Using a material selected from one or more of zirconium, beryllium, and thorium This is also acceptable. Furthermore, the conductive film may be a single-layer structure or a multi-layer structure of two or more layers. For example, A single-layer structure of an aluminum film containing silicon, and a two-layer structure with a titanium film laminated on top of the aluminum film. Structure: Ti film, an aluminum film layered on top of the Ti film, and then another Ti film on top of that. Examples include a three-layer structure for forming a thin film. Also, titanium (Ti) and tantalum (Ta) can be added to Al. ), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), s A film, alloy film, or a combination of one or more elements selected from candium (Sc) A nitride film may also be used.

[0186] In this embodiment, the source electrode layer or drain electrode layer 465a1, 465a2 is spade A titanium film with a thickness of 150 nm is formed using the taring method.

[0187] Next, an oxide semiconductor layer 462 with a thickness of 2 nm to 200 nm is formed.

[0188] The formed oxide semiconductor film is transformed into island-shaped oxide semiconductor layers 4 by a second photolithography process. Process to 62 (see Figure 8(B)). In this embodiment, In- The film is deposited by sputtering using a Ga-Zn-O oxide semiconductor film deposition target. ru.

[0189] The oxide semiconductor film is processed by holding the substrate in a processing chamber that is kept under reduced pressure, and the residual moisture in the processing chamber is also processed. Sputtered gas, from which hydrogen and moisture have been removed while removing other elements, is introduced, and the metal oxide is targeted. An oxide semiconductor film is formed on the substrate 450. To remove residual moisture in the processing chamber... It is preferable to use an adsorption-type vacuum pump. For example, a cryopump or an ion pump. It is preferable to use a titanium sublimation pump. Furthermore, as an exhaust means, A turbopump with a cold trap added may also be used. The exhausted treatment chamber contains, for example, hydrogen atoms, water (H2O), and other compounds containing hydrogen atoms (preferably Because substances such as carbon atoms (and other compounds) are exhausted, oxide semiconductors formed in the processing chamber are affected. The concentration of impurities in the conductive film can be reduced. Furthermore, heating the substrate during oxide semiconductor film deposition is also possible. You may do so.

[0190] The sputtering gas used when depositing oxide semiconductor films is hydrogen, water, hydroxyl groups, or hydrides. Which impurities should be removed to a concentration of approximately ppm or ppb in a high-purity gas? It is preferable.

[0191] An example of film deposition conditions is a substrate temperature of room temperature and a distance of 110 mm between the substrate and the target. Pressure 0.4 Pa, DC power supply 0.5 kW, oxygen and argon (oxygen flow rate 15 scc) The conditions applied are under an atmosphere with an argon flow rate of 30 sccm. Using a power supply reduces the amount of powdery material (also called particles or dust) generated during film formation. This is preferable because it also results in a uniform film thickness distribution. The oxide semiconductor film is preferably 5 nm or more and 30 nm thick. The thickness should be less than or equal to nm. Note that the appropriate thickness varies depending on the oxide semiconductor material used. You can then choose the appropriate thickness.

[0192] In this embodiment, a wet etching solution is used, which is a mixture of phosphoric acid, acetic acid, and nitric acid. The oxide semiconductor film is processed into island-shaped oxide semiconductor layers 462 by an etching method.

[0193] In this embodiment, the oxide semiconductor layer 462 is subjected to a first heat treatment. The temperature should be between 400°C and 750°C, preferably between 400°C and below the strain point of the substrate. Here, a substrate is introduced into an electric furnace, which is one of the heat treatment devices, and nitrogen is applied to the oxide semiconductor layer. After heating at 450°C for 1 hour in an ambient atmosphere, oxidation was performed without exposure to air. This prevents the re-importation of water and hydrogen into the semiconductor layer and obtains an oxide semiconductor layer. Therefore, the oxide semiconductor layer 462 can be dehydrated or dehydrogenated.

[0194] Furthermore, the heat treatment device is not limited to electric furnaces, but also includes heat conduction or heat from heat-generating elements such as resistance heating elements. The device may include an apparatus that heats the object to be processed by radiation. For example, GRTA(Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Angle) for Thermal Annealing devices, etc. A neal apparatus can be used. For example, as the first heat treatment, 650°C to 70°C The substrate is moved into an inert gas heated to a high temperature of 0°C and heated for several minutes, after which the substrate is... GRTA may be performed by moving the material and releasing it from an inert gas heated to a high temperature. Having it allows for high-temperature heating treatment in a short amount of time.

[0195] In the first heat treatment, nitrogen or a noble gas such as helium, neon, or argon is used. It is preferable that it does not contain water, hydrogen, etc. Alternatively, nitrogen introduced into the heat treatment device, Alternatively, the purity of noble gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably 7N (99.99999%) or higher (i.e., impurity concentration of 1 ppm or less, preferably It is preferable to keep the concentration at 0.1 ppm or less.

[0196] Furthermore, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor film In some cases, crystallization may occur, forming a microcrystalline or polycrystalline film.

[0197] Furthermore, the first heat treatment of the oxide semiconductor layer is performed on the oxide before it is processed into an island-shaped oxide semiconductor layer. This can also be done on semiconductor films. In that case, after the first heat treatment, the substrate is removed from the heating device. The material is removed and the photolithography process is performed.

[0198] Heat treatments that have the effect of dehydrating and dehydrogenating oxide semiconductor layers are used in oxide semiconductor layer formation. After the film is formed, source electrodes and drain electrodes are further stacked on the oxide semiconductor layer, and then the source electrode This may be done either after forming a gate insulating layer on the electrode and drain electrode.

[0199] Next, a conductive film is formed on the insulating layer 457 and the oxide semiconductor layer 462, and the third photolithography is performed. A resist mask is formed on the conductive film by a sography process, and selective etching is performed. After forming the source electrode layer or drain electrode layer 465b and the wiring layer 468, a resist mask is formed. Remove (see Figure 8(C)). Source electrode layer or drain electrode layer 465b, wiring layer 4 68 is made of the same material and process as the source electrode layer or drain electrode layer 465a1, 465a2 Just form it.

[0200] In this embodiment, the source electrode layer or drain electrode layer 465b and the wiring layer 468 are spade A titanium film with a thickness of 150 nm is formed by the taring method. In this embodiment, the source electrode Layer or drain electrode layer 465a1, 465a2 and source electrode layer or drain electrode layer 465 This is an example where the same titanium film is used in b, so source electrode layer or drain electrode layer 465a1, 46 5a2 and the source electrode layer or drain electrode layer 465b have a selectivity ratio in etching. No. Therefore, the source electrode layer or drain electrode layer 465a1, 465a2 is the source electrode. To prevent etching during etching of the layer or drain electrode layer 465b, A wiring layer 468 is placed on the source electrode layer or drain electrode layer 465a2 that is not covered by the body layer 462. It is provided. Source electrode layer or drain electrode layer 465a1, 465a2 and source electrode layer or The drain electrode layer 465b and a different material having a high selectivity ratio in the etching process are used. When used, protect the source electrode layer or drain electrode layer 465a2 during etching. The wiring layer 468 does not necessarily have to be provided.

[0201] Furthermore, during the etching of the conductive film, the oxide semiconductor layer 462 is not removed. The materials and etching conditions are adjusted as appropriate.

[0202] In this embodiment, a Ti film is used as the conductive film, and the oxide semiconductor layer 462 is made of In-Ga -Zn-O based oxide semiconductors are used, with ammonia peroxide (31% by weight) as the etchant. Use hydrogen oxide solution (28% by weight), ammonia solution (5:2:2), and water.

[0203] In the third photolithography process, only a portion of the oxide semiconductor layer 462 is etched. This can result in an oxide semiconductor layer having grooves (recesses). Furthermore, the source electrode layer may also be formed. The resist mask is inkjet for forming the drain electrode layer 465b and the wiring layer 468. It may also be formed by the inkjet method. If the resist mask is formed by the inkjet method, it becomes a photomask. Because it does not use [a specific ingredient / method], manufacturing costs can be reduced.

[0204] The following are an insulating layer 457, an oxide semiconductor layer 462, and a source electrode layer or drain electrode layer 465. a1, 465a2, a gate insulating layer 452 on the source electrode layer or drain electrode layer 465b To form.

[0205] The gate insulating layer 452 is formed using plasma CVD or sputtering, etc. A layer, silicon nitride layer, silicon oxide nitride layer, silicon nitride oxide layer, or aluminum oxide layer The layer can be formed as a single layer or in multiple layers. Note that hydrogen is present in the gate insulating layer 452. To prevent excessive contamination, the gate insulating layer 452 is deposited using the sputtering method. It is preferable to do so. When forming a silicon oxide film by sputtering, the target A silicon target or a quartz target is used as the sputtering gas, and oxygen or This is done using a mixed gas of oxygen and argon.

[0206] The gate insulating layer 452 is the source electrode layer or drain electrode layer 465a1, 465a2, A silicon oxide layer and a silicon nitride layer are laminated from the side of the drain electrode layer or drain electrode layer 465b. It can also be structured as follows. In this embodiment, the pressure is 0.4 Pa, the high-frequency power supply is 1.5 kW, Oxygen and argon atmosphere (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1:1) Below, a silicon oxide layer with a thickness of 100 nm is formed by RF sputtering.

[0207] Next, a resist mask is formed by a fourth photolithography step, and then selectively etched. By performing a process to remove a portion of the gate insulation layer 452, an opening 423 is created that reaches the wiring layer 468. Form (see Figure 8(D)). Although not shown, when forming the opening 423, the source electrode layer or An opening reaching the rain electrode layer 465b may be formed. In this embodiment, the source electrode layer Alternatively, the opening to the drain electrode layer 465b is formed after further lamination of the interlayer insulating layer, and electrical This example shows how to form a wiring layer to connect to an opening.

[0208] Next, after forming a conductive film on the gate insulating layer 452 and the opening 423, a fifth photolithography is performed. The gate electrode layer 461 (461a, 461b) and the wiring layer 464 are formed by the graphing process. The resist mask may also be formed by an inkjet method. Since the cgetting method does not require the use of a photomask, manufacturing costs can be reduced.

[0209] Furthermore, the materials for the gate electrode layer 461 (461a, 461b) and the wiring layer 464 are molybdenum. Titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium Formed using metallic materials such as lum or alloy materials mainly composed of these, either in a single layer or in layers. It is possible.

[0210] In this embodiment, the gate electrode layer 461 (461a, 461b) and the wiring layer 464 are made of spa A titanium film with a thickness of 150 nm is formed using the tarring method.

[0211] Next, a second heat treatment (preferably 2) is performed under an inert gas atmosphere or an oxygen gas atmosphere. The process is carried out at a temperature between 00°C and 400°C, for example, between 250°C and 350°C. A second heat treatment is performed at 250°C for 1 hour under a nitrogen atmosphere. This may also be done after forming a protective insulating layer or a planar insulating layer on the thin-film transistor 460.

[0212] Furthermore, a heat treatment is performed in air at a temperature between 100°C and 200°C for between 1 hour and 30 hours. This may also be done by heating while maintaining a constant heating temperature, or by heating from room temperature to 10 The process involves repeatedly raising the temperature from 0°C to 200°C and then lowering it back down to room temperature. This may be done. Alternatively, this heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. Good. Heating under reduced pressure can shorten the heating time.

[0213] In the above process, the concentrations of hydrogen, water, hydride, and hydroxide are reduced in the oxide semiconductor layer 46. A thin-film transistor 460 having 2 can be formed (see Figure 8(E)). Transistor 460 is a thin-film transistor used in each pixel of the pixel section 202 in Embodiment 1. It can be used for this purpose.

[0214] Furthermore, a protective insulating layer and a planarizing insulating layer for planarization are provided on the thin-film transistor 460. This is also acceptable. Note that although not shown in the diagram, the gate insulating layer 452, protective insulating layer and planar insulating layer may also be used. An opening is formed that reaches the electrode layer or the drain electrode layer 465b, and the source electrode layer or This forms a wiring layer that is electrically connected to the drain electrode layer 465b.

[0215] As described above, when forming an oxide semiconductor film, residual moisture in the reaction atmosphere is removed. This makes it possible to reduce the concentration of hydrogen and hydrides in the oxide semiconductor film. This can help stabilize oxide semiconductor films.

[0216] As described above, by applying a highly purified oxide semiconductor layer to a thin-film transistor, This makes it possible to provide a thin-film transistor with reduced off-current. By applying the thin-film transistor with reduced off-current, as explained above, to the pixels of a display device, Therefore, the retention capacitance provided in the pixel can extend the period during which the voltage can be retained. This allows us to provide a display device that consumes less power when displaying data.

[0217] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0218] (Embodiment 4) This embodiment provides another example of a thin-film transistor applicable to the display device disclosed herein. This is shown. Note that parts and processes that are the same as or have similar functions as those in Embodiment 2 are shown in the implementation. The same procedure as in Form 2 is sufficient, and the explanation of the repetition is omitted. Also, a detailed explanation of the same section is omitted. The details are also omitted. The thin-film transistors 425 and 426 shown in this embodiment are the same as those in Embodiment 1. It can be used as a film transistor 106.

[0219] The thin-film transistor of this embodiment will be described with reference to Figure 9.

[0220] Figures 9(A) and 9(B) show an example of the cross-sectional structure of a thin-film transistor. Thin-film transistors 425 and 426 have an oxide semiconductor layer sandwiched between a conductive layer and a gate electrode layer. It is a type of thin-film transistor.

[0221] Furthermore, in Figures 9(A) and 9(B), a silicon substrate is used, and the silicon substrate 42 Thin-film transistors 425 and 426 are provided on an insulating layer 422 provided on 0, respectively. It is.

[0222] In Figure 9(A), the insulating layer 422 and the insulating layer 407 provided on the silicon substrate 420 A conductive layer 427 is provided in between, overlapping at least the entire oxide semiconductor layer 412. .

[0223] Figure 9(B) shows that the conductive layer between insulating layer 422 and insulating layer 407 is similar to conductive layer 424. Processed by etching, including at least the channel region of the oxide semiconductor layer 412 This is an example that overlaps with some others.

[0224] The conductive layers 427 and 424 can be made of any metal material that can withstand the heat treatment temperature in the subsequent process. Titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), Elements selected from chromium (Cr), neodymium (Nd), and scandium (Sc), or the above An alloy containing the aforementioned elements, or an alloy film made up of the aforementioned elements, or the aforementioned elements Nitrides containing the above components can be used. Furthermore, both single-layer and multi-layer structures are acceptable. For example, a single layer of tungsten, or a laminated structure of tungsten nitride and tungsten layers. You can use it.

[0225] Furthermore, the conductive layers 427 and 424 have a potential equal to the gate electrode layer of thin-film transistors 425 and 426. It can be the same as 411, or it can be different, and it will function as a second gate electrode layer. It is also possible that the potentials of conductive layers 427 and 424 are fixed potentials of GND and 0V. That's good too.

[0226] The conductive layers 427 and 424 control the electrical characteristics of the thin-film transistors 425 and 426. It is possible.

[0227] As described above, by applying a highly purified oxide semiconductor layer to a thin-film transistor, This makes it possible to provide a thin-film transistor with reduced off-current. By applying the thin-film transistor with reduced off-current, as explained above, to the pixels of a display device, Therefore, the retention capacitance provided in the pixel can extend the period during which the voltage can be retained. This allows us to provide a display device that consumes less power when displaying data.

[0228] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0229] (Embodiment 5) This embodiment provides another example of a thin-film transistor applicable to the display device disclosed herein. As shown, the thin-film transistor 390 shown in this embodiment is the same as the thin-film transistor of Embodiment 1. It can be used as 106.

[0230] An example of the cross-sectional structure of the thin-film transistor of this embodiment is shown in Figures 10(A) to (E). The thin-film transistor 390 shown in 10(A) to (E) is one of the bottom-gate structures. Also known as an inverse staggered thin-film transistor.

[0231] Furthermore, the thin-film transistor 390 will be explained using a single-gate thin-film transistor. However, if necessary, a thin film transistor with a multi-gate structure having multiple channel formation regions It can also form a "ta".

[0232] The following describes how thin-film transistors 390 are fabricated on substrate 394 using Figures 10(A) to (E). Let's explain the process.

[0233] First, a conductive film is formed on a substrate 394 having an insulating surface, and then the first photolithography is performed. The gate electrode layer 391 is formed by the process. The ends of the formed gate electrode layer are tapered. This is preferable because it improves the coverage of the gate insulating layer laminated on top. The mask may be formed by an inkjet method. This eliminates the need for photomasks, thus reducing manufacturing costs.

[0234] There are no major restrictions on the substrates that can be used for the substrate 394 having an insulating surface, however In both cases, it is necessary that it has sufficient heat resistance to withstand subsequent heat treatment. Glass substrates such as borosilicate glass and aluminoborsilicate glass can be used.

[0235] Furthermore, for glass substrates, if the subsequent heat treatment temperature is high, the strain point will be 730°C or higher. It is best to use the following. Also, for the glass substrate, for example, aluminosilicate glass, Glass materials such as luminoborosilicate glass and bariumborosilicate glass are used. Furthermore, by including more barium oxide (BaO) compared to boron oxide, it becomes more practical. A heat-resistant glass can be obtained. For this reason, a glass substrate containing more BaO than B2O3 is used. It is preferable to do so.

[0236] In addition, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used instead of the glass substrates mentioned above. A substrate made of edge material may also be used. Other materials such as crystallized glass can also be used. Plastic substrates and the like can also be used as appropriate.

[0237] An insulating film that serves as the base film may be provided between the substrate 394 and the gate electrode layer 391. It has the function of preventing the diffusion of impurity elements from the substrate 394, silicon nitride film, silicon oxide One or more films selected from a silicon nitride film, silicon nitride film, or silicon oxide film. It can be formed by a laminated structure.

[0238] Furthermore, the material of the gate electrode layer 391 is molybdenum, titanium, chromium, tantalum, tungsten Metal materials such as tungsten, aluminum, copper, neodymium, scandium, or materials with these as their main components. It can be formed using alloy materials, either as a single layer or in layers.

[0239] For example, as a two-layer stacked structure of the gate electrode layer 391, molybdenum on an aluminum layer A two-layer laminated structure with layers stacked on top of each other, a two-layer structure with a molybdenum layer stacked on top of a copper layer, and a nitrogen layer on top of a copper layer. A two-layer structure consisting of a titanium nitride layer or a tantalum nitride layer, and a titanium nitride layer and a molybdenum layer. A two-layer structure in which a tungsten nitride layer and a tungsten layer are stacked, or a two-layer structure in which a tungsten nitride layer and a tungsten layer are stacked. It is preferable to do so. The three-layer laminated structure may be a tungsten layer or tungsten nitride. Layers, aluminum-silicon alloy or aluminum-titanium alloy, and titanium nitride. It is preferable to have a laminated structure consisting of a layer or a titanium layer. The gate electrode layer can also be formed using [a specific material]. As a transparent conductive film, [a specific material] Conductive oxides are one example of this.

[0240] Next, a gate insulating layer 397 is formed on the gate electrode layer 391.

[0241] The gate insulating layer 397 is formed using plasma CVD or sputtering, etc. A layer, silicon nitride layer, silicon oxide nitride layer, silicon nitride oxide layer, or aluminum oxide layer The layer can be formed as a single layer or in stacks. Note that hydrogen is present in the gate insulating layer 397. To prevent excessive contamination, the gate insulating layer 397 is deposited using the sputtering method. It is preferable to do so. When forming a silicon oxide film by sputtering, the target A silicon target or a quartz target is used as the sputtering gas, and oxygen or This is done using a mixed gas of oxygen and argon.

[0242] The gate insulating layer 397 is constructed by stacking a silicon nitride layer and a silicon oxide layer from the gate electrode layer 391 side. A layered structure can also be used. For example, as the first gate insulating layer, the sputtering method can be used. A silicon nitride layer (SiN) with a thickness of 50 nm to 200 nm. y (y>0) , an acid coating with a film thickness of 5 nm to 300 nm is applied as a second gate insulating layer on the first gate insulating layer. Silicon ionized layer (SiO x Layers (x>0) are stacked to form a gate insulating layer with a thickness of 100 nm. .

[0243] Furthermore, the gate insulating layer 397 and the oxide semiconductor film 393 contain as much hydrogen, hydroxyl groups, and moisture as possible. To prevent this from happening, as a pre-treatment for film deposition, the sputtering apparatus is heated in a preheating chamber. A substrate 394 on which the gate electrode layer 391 is formed, or a substrate on which the gate insulating layer 397 is formed The plate 394 is preheated to remove impurities such as hydrogen and moisture adsorbed on the substrate 394, and then exhausted. Preferably, the preheating temperature should be between 100°C and 400°C. The temperature is between 150°C and 300°C. The exhaust means installed in the preheating chamber is a cryopump. This is preferable. However, this preheating process can be omitted. Also, this preheating is Before forming the oxide insulating layer 396, up to the source electrode layer 395a and drain electrode layer 395b The same procedure may be performed on the formed substrate 394.

[0244] Next, an oxide semiconductor film 39 with a thickness of 2 nm to 200 nm is placed on the gate insulating layer 397. Form 3 (see Figure 10(A)).

[0245] Furthermore, before depositing the oxide semiconductor film 393 by sputtering, an argon gas was introduced. Reverse sputtering is performed to generate plasma by introducing the material, and it adheres to the surface of the gate insulating layer 397. It is preferable to remove any debris. Reverse sputtering is a method where no voltage is applied to the target side. Under an argon atmosphere, a voltage is applied to the substrate side using an RF power supply to form plasma near the substrate. This is a method of modifying the surface. Note that nitrogen, helium, oxygen, etc., can be used instead of an argon atmosphere. You may use any of these.

[0246] The oxide semiconductor film 393 is deposited by sputtering. The oxide semiconductor film 393 is I n-Ga-Zn-O non-single crystal films, In-Sn-Zn-O systems, In-Al-Zn-O systems, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-S nO series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn -O-based and Zn-O-based oxide semiconductor films are used. In this embodiment, oxide semiconductor film 39 3 is subjected to sputtering using an In-Ga-Zn-O oxide semiconductor film deposition target. Further film formation is performed. In addition, the oxide semiconductor film 393 is formed under a rare gas (typically argon) atmosphere. Sputtering under an oxygen atmosphere, or under a noble gas (typically argon) and oxygen atmosphere. It can be formed by the ring method. Also, when using the sputtering method, SiO2 Film deposition may be performed using a target containing 2% to 10% by weight of [the substance].

[0247] Zinc oxide is used as a target for fabricating oxide semiconductor film 393 by sputtering. A metal oxide target with as its main component can be used. Other examples of targets include oxide semiconductor film deposition targets containing In, Ga, and Zn. The composition ratio is In2O3:Ga2O3:ZnO = 1:1:1 [mol ratio], In:Ga Zn = 1:1:0.5 [atomic ratio] can be used. Also, In, Ga As a target for deposition of oxide semiconductor films containing Zn, In:Ga:Zn=1:1:1 [atomic ratio], or a composition ratio of In:Ga:Zn=1:1:2[atomic ratio] It is also possible to use a target that has been used. The packing density of the target for oxide semiconductor film deposition is 90 The percentage is between % and 100%, preferably between 95% and 99.9%. High-filling oxides. By using a semiconductor film deposition target, the deposited oxide semiconductor film becomes a dense film. .

[0248] The substrate is held in a processing chamber under reduced pressure, and the substrate is subjected to a temperature of room temperature or below 400°C. Heat it. Then, remove the residual moisture in the processing chamber and remove the hydrogen and moisture from the sputtered material. A smear is introduced, and an oxide semiconductor film 393 is deposited on a substrate 394 using a metal oxide as the target. To remove residual moisture from the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, using cryopumps, ion pumps, and titanium sublimation pumps. This is preferable. Furthermore, as an exhaust means, a turbo pump with a cold trap added is preferable. It may also be done. The treatment chamber, which has been evacuated using a cryopump, may contain, for example, hydrogen atoms, water ( Compounds containing hydrogen atoms (more preferably compounds containing carbon atoms) such as H2O are exhausted. Therefore, the concentration of impurities in the oxide semiconductor film deposited in the processing chamber can be reduced. Furthermore, sputter deposition is performed while removing residual moisture in the processing chamber using a cryopump. Therefore, the substrate temperature when depositing the oxide semiconductor film 393 is set to room temperature or less than 400°C. It is possible.

[0249] An example of film deposition conditions is a distance of 100 mm between the substrate and the target, and a pressure of 0.6 Pa. The conditions applied are a DC power supply of 0.5kW and an oxygen atmosphere (oxygen flow rate ratio of 100%). It can be used. Furthermore, when using a pulsed DC power supply, powdery material (particulate matter) generated during film formation can be produced. This is preferable because it reduces debris (also called 'crumbs' or 'dust') and results in a more uniform film thickness distribution. The film thickness is preferably 5 nm to 30 nm. Note that the oxide semiconductor material used may vary depending on the material. The appropriate thickness varies, and you should select the appropriate thickness depending on the material.

[0250] Sputtering methods include RF sputtering, which uses a high-frequency power supply for sputtering, and DC sputtering. DC sputtering method using a power supply, and pulsed DC sputtering method where a pulsed bias is applied. There is a sputtering method. RF sputtering is mainly used when depositing insulating films, D C sputtering is primarily used for depositing metal films.

[0251] There are also multi-point sputtering systems that can set up multiple targets made of different materials. The apparatus can deposit multiple layers of different material films in the same chamber, or multiple types of materials in the same chamber. It is also possible to deposit films by simultaneously discharging electrical currents from similar materials.

[0252] Furthermore, sputtering using a magnetron sputtering method that incorporates a magnetic mechanism inside the chamber... ECRs use devices that generate plasma using microwaves instead of glow discharges. There are sputtering machines that use the puttering method.

[0253] Furthermore, as a film deposition method using the sputtering method, the target material and sputtering gas are used during film deposition. Reactive sputtering is a method that uses chemical reactions to form thin films of compounds. Alternatively, there is a bias sputtering method that applies voltage to the substrate during film deposition.

[0254] Next, the oxide semiconductor film is transformed into island-shaped oxide semiconductor layers 3 by a second photolithography process. Process to form 99 (see Figure 10(B)). Also, form island-shaped oxide semiconductor layers 399. A resist mask may be formed by an inkjet method. Since the wet process does not require the use of a photomask, manufacturing costs can be reduced.

[0255] Furthermore, when forming contact holes in the gate insulating layer 397, the process is carried out in an oxide semiconductor. This can be done when forming layer 399.

[0256] Note that the etching of the oxide semiconductor film 393 here can be done by dry etching or wet etching. You can use either "checking" or both.

[0257] Etching gases used in dry etching include chlorine-containing gases (chlorine-based gases, for example) Chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC) l4) etc.) are preferable.

[0258] Also, fluorine-containing gases (fluorinated gases, such as carbon tetrafluoride (CF4) and sulfur hexafluoride (S)) F6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (H Br), oxygen (O2), and these gases can be mixed with noble gases such as helium (He) and argon (Ar). Gases with added sulfites, etc., can be used.

[0259] As for dry etching methods, parallel plate type RIE (Reactive Ion Etching) Methods such as the ing method and ICP (Inductively Coupled Plasma: induction) A coupled plasma etching method can be used. The desired processing shape can be etched. To that end, etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the electrode on the substrate side) Adjust the amount of power used, the electrode temperature on the substrate, etc., as appropriate.

[0260] The etching solution used for wet etching is a solution of phosphoric acid, acetic acid, and nitric acid, Ammonia Hydrogenated Water (31% hydrogen peroxide by weight: 28% ammonia by weight: water = 5:2:2) These can be used. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0261] Furthermore, the etching solution after wet etching is washed away along with the etched material. The material is removed. The waste etching solution containing the removed material is purified, and the material contained in it is removed. It may be reused. Indium and other elements contained in the oxide semiconductor layer can be extracted from the waste liquid after etching. By recovering and reusing materials, resources can be used effectively and costs can be reduced. .

[0262] Etching conditions (etching) can be adjusted according to the material so that the desired processing shape can be etched. Adjust the solution, etching time, temperature, etc. as appropriate.

[0263] Furthermore, before forming the conductive film in the next step, reverse sputtering is performed to form the oxide semiconductor layer 399 and the gate It is preferable to remove any resist residue or other material adhering to the surface of the insulating layer 397.

[0264] Next, a conductive film is formed on the gate insulating layer 397 and the oxide semiconductor layer 399. The film can be formed by sputtering or vacuum deposition. Suitable materials for the conductive film include Al and C. Elements selected from r, Cu, Ta, Ti, Mo, and W, or compounds containing the above elements. Examples include gold or alloy films combining the elements mentioned above. Also, manganese and magnesium A material selected from one or more of the following: thorium, zirconium, beryllium, and thorium. It may be used. Furthermore, the conductive film may be a single-layer structure or a multi-layer structure of two or more layers. For example... For example, a single-layer structure of an aluminum film containing silicon, or a titanium film laminated on top of an aluminum film. It has a two-layer structure: a Ti film, and an aluminum film is layered on top of the Ti film, and then another Ti film is layered on top of that. Examples include a three-layer structure for forming an i-film. Also, Al can be combined with titanium (Ti), tantalum ( Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd) , a film, alloy film, or a combination of one or more elements selected from scandium (Sc). Alternatively, a nitride film may be used.

[0265] A third photolithography step forms a resist mask on the conductive film, and selectively extracts the residue. After performing ching to form the source electrode layer 395a and drain electrode layer 395b, the resist Remove the mask (see Figure 10(C)).

[0266] For exposure during resist mask formation in the third photolithography process, ultraviolet light and KrF light are used. A laser or ArF laser light is used. Below the adjacent source electrode layer on the oxide semiconductor layer 399. The gap width between the end and the lower end of the drain electrode layer determines the subsequent formation of the thin-film transistor. The channel length L is determined. Note that when performing exposure with a channel length L = less than 25 nm, the number Extreme ultraviolet light (Ultraviolet) has extremely short wavelengths, ranging from nanometers to several tens of nanometers. Using t), exposure is performed during the resist mask formation in the third photolithography step. Exposure with ultraviolet light offers high resolution and a large depth of field. Therefore, the thin film traces that are later formed... The channel length L of the inverter can also be set to 10 nm or more and 1000 nm or less, and the circuit This allows for faster operation speeds and, because the off-current value is extremely small, it also contributes to lower power consumption. It is possible.

[0267] Furthermore, during the etching of the conductive film, the oxide semiconductor layer 399 is not removed. The materials and etching conditions are adjusted as appropriate.

[0268] In this embodiment, a Ti film is used as the conductive film, and the oxide semiconductor layer 399 is made of In-Ga -Zn-O based oxide semiconductors are used, with ammonia peroxide (31% by weight) as the etchant. Use hydrogen oxide solution (28% by weight), ammonia solution (5:2:2), and water.

[0269] In the third photolithography process, only a portion of the oxide semiconductor layer 399 is etched. This can result in an oxide semiconductor layer having grooves (recesses). Also, the source electrode layer 3 A resist mask for forming the drain electrode layer 395b is created by inkjet printing. It may be formed. If the resist mask is formed by the inkjet method, a photomask is used. Therefore, manufacturing costs can be reduced.

[0270] Furthermore, in order to reduce the number of photomasks and processes used in the photolithography process, The resist mask formed by a multi-tone mask, which is an exposure mask where the light has multiple intensities, is formed by the light. The etching process may be performed using a mask. A resist mask formed using a multi-gradation mask. The ske will have a shape with multiple film thicknesses, and its shape can be further deformed by etching. Because it can do this, it can be used in multiple etching processes that process different patterns. Therefore, a single multi-tone mask can accommodate at least two different patterns. This allows for the formation of a resist mask. Therefore, the number of exposure masks can be reduced. Furthermore, the corresponding photolithography process can also be reduced, thus simplifying the overall process.

[0271] Oxides exposed by plasma treatment using gases such as N2O, N2, or Ar. Adsorbed water and other substances adhering to the surface of the semiconductor layer may be removed. Alternatively, a mixture of oxygen and argon may be used. Plasma treatment may be performed using a special device.

[0272] When plasma treatment is performed, a protective layer comes into contact with a portion of the oxide semiconductor layer without being exposed to the atmosphere. An oxide insulating layer 396 is formed as an oxide insulating layer that will serve as an insulating film (see Figure 10(D)). In this embodiment, the oxide semiconductor layer 399 is the source electrode layer 395a, and the drain electrode layer 3 In the region that does not overlap with 95b, the oxide semiconductor layer 399 and the oxide insulating layer 396 are in contact. To form in that manner.

[0273] In this embodiment, the oxide insulating layer 396 is an island-shaped oxide semiconductor layer 399, and the source power The substrate 394, on which the electrode layer 395a and drain electrode layer 395b have been formed, is left at room temperature or at 100°C. The device is heated to a high temperature, and sputtered gas containing high-purity oxygen from which hydrogen and moisture have been removed is introduced. A silicon oxide layer containing defects is deposited using a reconstituted semiconductor target.

[0274] For example, a silicon target with a purity of 6N and doped with boron (resistance value 0.01 Using Ωcm, the distance between the substrate and the target (TS distance) was set to 89 mm, and the pressure to 0. Pulsed DC under 4 Pa, 6 kW DC power supply, and an oxygen (100% oxygen flow rate) atmosphere. A silicon oxide film is deposited by sputtering. The film thickness is 300 nm. As a target for depositing silicon films, quartz can be used instead of a silicon target. (Or synthetic quartz) can be used. Furthermore, oxygen or oxygen and This is done using a mixed gas of argon and bisulfite.

[0275] In this case, the oxide insulating layer 396 is formed while removing residual moisture in the processing chamber. Preferably, the oxide semiconductor layer 399 and the oxide insulating layer 396 contain hydrogen, hydroxyl groups, or water. This is to prevent them from getting sick.

[0276] To remove residual moisture from the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable. Furthermore, as an exhaust method, a turbo pump with a cold trap is used. It is also acceptable. The treatment chamber, which has been evacuated using a cryopump, contains, for example, hydrogen atoms and water (H2 Since compounds containing hydrogen atoms, such as O), are exhausted, the film formed in the processing chamber is affected. The concentration of impurities in the oxide insulating layer 396 can be reduced.

[0277] Furthermore, as the oxide insulating layer 396, instead of the silicon oxide layer, a silicon oxide nitride layer, or an oxide An aluminum layer or an aluminum oxide-nitride layer can also be used.

[0278] Furthermore, with the oxide insulating layer 396 and the oxide semiconductor layer 399 in contact, the temperature is 100°C to 40°C. Heat treatment may be performed at 0°C. The oxide insulating layer 396 in this embodiment has many defects. Therefore, this heat treatment removes hydrogen, water, and hydroxyl groups contained in the oxide semiconductor layer 399. Alternatively, impurities such as hydrides are diffused into the oxide insulating layer 396, and into the oxide semiconductor layer 399 The amount of impurities contained can be further reduced.

[0279] In the above process, the oxide semiconductor layer 39 has a reduced concentration of hydrogen, water, hydroxyl groups, or hydrides. A thin-film transistor 390 having 2 can be formed (see Figure 10(E)).

[0280] As described above, when forming an oxide semiconductor film, residual moisture in the reaction atmosphere is removed. This makes it possible to reduce the concentration of hydrogen and hydrides in the oxide semiconductor film. This can help stabilize oxide semiconductor films.

[0281] A protective insulating layer may be provided on the oxide insulating layer. In this embodiment, the protective insulating layer 398 is acid It is formed on the oxide insulating layer 396. The protective insulating layer 398 is a silicon nitride film, an oxide nitride film. A silicon film, aluminum nitride film, or aluminum nitride oxide film is used.

[0282] As a protective insulating layer 398, the substrate 394, which has an oxide insulating layer 396 formed on it, is heated at 100°C to 4°C. Sputtered gas containing high-purity nitrogen, from which hydrogen and moisture have been removed, is introduced after heating to a temperature of 0°C. A silicon nitride film is deposited using a silicon semiconductor target. Similar to the oxide insulating layer 396, the protective insulating layer 398 is formed while removing residual moisture in the processing chamber. It is preferable to form a film.

[0283] When forming the protective insulating layer 398, the temperature during film formation of the protective insulating layer 398 is based on 100°C to 400°C. By heating plate 394, hydrogen or moisture contained in the oxide semiconductor layer is removed from the oxide insulation. It can be diffused into the layer. In this case, heat treatment is performed after the formation of the oxide insulating layer 396. You don't have to.

[0284] A silicon oxide layer is formed as the oxide insulating layer 396, and a silicon nitride layer is formed as the protective insulating layer 398. When stacking silicon layers, the silicon oxide layer and the silicon nitride layer are processed in the same processing chamber using a common process. The film can be deposited using a recontactic. First, an oxygen-containing gas is introduced, and then the process is carried out. A silicon oxide layer is formed using a silicon target installed indoors, followed by the formation of nitrogen-containing Switch to gas and deposit a silicon nitride layer using the same silicon target. Since the silicon nitride layer and the silicon nitride layer can be formed continuously without exposure to the atmosphere, oxidation This prevents impurities such as hydrogen and moisture from adsorbing onto the surface of the silicon layer. In this case, a silicon oxide layer is formed as the oxide insulating layer 396, and a nitride is formed as the protective insulating layer 398. After stacking silicon layers, hydrogen or moisture contained in the oxide semiconductor layer is removed from the oxide insulating layer. It is recommended to perform a heat treatment (temperature 100°C to 400°C) to facilitate diffusion.

[0285] After forming the protective insulating layer, further immerse in air at a temperature between 100°C and 200°C for 1 to 30 hours. The following heat treatment may be performed. This heat treatment may be carried out while maintaining a constant heating temperature. Furthermore, the process involves raising the temperature from room temperature to a heating temperature of 100°C or more and 200°C, and then returning the temperature from the heating temperature back to room temperature. The cooling process may be repeated multiple times. Alternatively, this heat treatment may be performed before the formation of the oxide insulating layer. This can also be done under reduced pressure. Heating under reduced pressure can shorten the heating time. This heat treatment allows for the creation of normally-off thin-film transistors. Therefore, the reliability of the display device can be improved.

[0286] Furthermore, when forming an oxide semiconductor layer on the gate insulating layer to serve as a channel formation region, the reaction By removing residual moisture from the atmosphere, the concentrations of hydrogen and hydrides in the oxide semiconductor layer are reduced. It can be reduced.

[0287] The above process is carried out at a temperature of 400°C or less, so the thickness is 1 mm or less and the length of one side is 1 m. It can also be applied to manufacturing processes using glass substrates exceeding 400°C. Because all processes can be carried out at controlled temperatures, a large amount of energy is required to manufacture the display panel. This eliminates the need to consume ghee.

[0288] As described above, by applying a highly purified oxide semiconductor layer to a thin-film transistor, This makes it possible to provide a thin-film transistor with reduced off-current. By applying the thin-film transistor with reduced off-current, as explained above, to the pixels of a display device, Therefore, the retention capacitance provided in the pixel can extend the period during which the voltage can be retained. This allows us to provide a display device that consumes less power when displaying data.

[0289] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0290] (Embodiment 6) This embodiment provides another example of a thin-film transistor applicable to the display device disclosed herein. As shown, the thin-film transistor 310 shown in this embodiment is the same as the thin-film transistor of Embodiment 1. It can be used as 106.

[0291] An example of the cross-sectional structure of the thin-film transistor of this embodiment is shown in Figures 11(A) to (E). The thin-film transistor 310 shown in 11(A) to (E) is one of the bottom-gate structures. Also known as an inverse staggered thin-film transistor.

[0292] Furthermore, the thin-film transistor 310 will be explained using a single-gate thin-film transistor. However, if necessary, a thin film transistor with a multi-gate structure having multiple channel formation regions It can also form a "ta".

[0293] The following describes how thin-film transistors 310 are fabricated on substrate 300 using Figures 11(A) to (E). The process will be explained. Note that in Figure 11(E), a protective insulating layer is applied to the thin-film transistor 310. The formed structure is shown below.

[0294] First, a conductive film is formed on a substrate 300 having an insulating surface, and then a first photolithography is performed. The gate electrode layer 311 is formed by the process. The resist mask is made by the inkjet method. It may be formed. If the resist mask is formed by the inkjet method, a photomask is used. Therefore, manufacturing costs can be reduced.

[0295] There are no major restrictions on the substrates that can be used for the substrate 300 having an insulating surface, however In both cases, it is necessary that it has sufficient heat resistance to withstand subsequent heat treatment. Glass substrates such as borosilicate glass and aluminoborsilicate glass can be used.

[0296] Furthermore, for glass substrates, if the subsequent heat treatment temperature is high, the strain point will be 730°C or higher. It is best to use the following. Also, for the glass substrate, for example, aluminosilicate glass, Glass materials such as luminoborosilicate glass and bariumborosilicate glass are used. Furthermore, by including more barium oxide (BaO) compared to boron oxide, it becomes more practical. A heat-resistant glass can be obtained. For this reason, a glass substrate containing more BaO than B2O3 is used. It is preferable to do so.

[0297] In addition, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used instead of the glass substrates mentioned above. A substrate made of edge material may also be used. Other materials, such as crystallized glass, can also be used.

[0298] An insulating film that serves as the underlayer may be provided between the substrate 300 and the gate electrode layer 311. It has the function of preventing the diffusion of impurity elements from the substrate 300, and the silicon nitride film, silicon oxide film, A laminated structure consisting of one or more films selected from silicon nitride or silicon oxidnitride films. It can be formed.

[0299] Furthermore, the material of the gate electrode layer 311 is molybdenum, titanium, chromium, tantalum, tungsten Metal materials such as tungsten, aluminum, copper, neodymium, scandium, or materials with these as their main components. It can be formed using alloy materials, either as a single layer or in layers.

[0300] For example, as a two-layer stacked structure of the gate electrode layer 311, molybdenum on an aluminum layer A two-layer laminated structure with layers stacked on top of each other, a two-layer laminated structure with a molybdenum layer stacked on top of a copper layer, copper layer A two-layer laminated structure with a titanium nitride layer or tantalum nitride layer laminated on top, and a titanium nitride layer and molybdenum A two-layer laminated structure consisting of a butene layer, or a tungsten nitride layer and a tungsten layer. A laminated structure of layers is preferred. A three-layer laminated structure may include a tungsten layer or a nitrogen layer. A tungsten oxide layer, an aluminum-silicon alloy or an aluminum-titanium alloy, It is preferable to have a laminated structure consisting of a titanium nitride layer or a titanium layer.

[0301] Next, a gate insulating layer 302 is formed on the gate electrode layer 311.

[0302] The gate insulating layer 302 is formed by a silicon oxide layer using plasma CVD or sputtering. , a silicon nitride layer, a silicon oxide nitride layer, a silicon oxide nitride layer, or an aluminum oxide layer as a single layer or It can be formed by stacking. For example, SiH4, oxygen, and nitrogen can be used as the film-forming gas. Then, a silicon oxide nitride layer can be formed by plasma CVD. The thickness shall be between 100 nm and 500 nm, and in the case of lamination, for example, the film thickness shall be 50 nm or more. A first gate insulating layer with a thickness of 00 nm or less, and a layer with a film thickness of 5 nm or more and 300 nm on the first gate insulating layer. The second gate insulating layer is laminated with a length of m or less.

[0303] In this embodiment, the gate insulating layer 302 is made by plasma CVD with a film thickness of 100 nm or less. This forms the silicon oxide nitride layer below.

[0304] Next, an oxide semiconductor film 33 with a thickness of 2 nm to 200 nm is placed on the gate insulating layer 302. Forms 0.

[0305] Furthermore, before depositing the oxide semiconductor film 330 by sputtering, argon gas was introduced. Reverse sputtering is performed to generate plasma, and dust adhering to the surface of the gate insulating layer 302 is removed. It is preferable to remove the argon atmosphere. You may use it.

[0306] The oxide semiconductor film 330 is an In-Ga-Zn-O non-single crystal film, an In-Sn-Zn-O system In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn- Al-Zn-O system, In-Sn-O system, In-Zn-O system, Sn-Zn-O system, Al-Z The present implementation uses oxide semiconductor films based on nO, In-O, Sn-O, and Zn-O. In this state, the oxide semiconductor film 330 is a target for In-Ga-Zn-O based oxide semiconductor film deposition. The film is deposited using a sputtering method with a tweezers. The cross-sectional view at this stage corresponds to Figure 11(A). Furthermore, the oxide semiconductor film 330 was subjected to a rare gas (typically argon) atmosphere and an oxygen atmosphere. Formed by sputtering under a low-gas (typically argon) and oxygen atmosphere. It is possible to do so. Also, when using the sputtering method, SiO2 must be 2% by weight or more. Film deposition may be performed using a target containing less than or equal to a certain percentage by weight.

[0307] Zinc oxide is used as a target for fabricating oxide semiconductor film 330 by sputtering. A metal oxide target with as its main component can be used. Other examples of targets include oxide semiconductor film deposition targets containing In, Ga, and Zn. The composition ratio is In2O3:Ga2O3:ZnO = 1:1:1 [mol ratio], In:Ga Zn = 1:1:0.5 [atomic ratio] can be used. Also, In, Ga As a target for deposition of oxide semiconductor films containing Zn, In:Ga:Zn=1:1:1 [atomic ratio], or a composition ratio of In:Ga:Zn=1:1:2[atomic ratio] It is also possible to use a target that has been used. The packing density of the target for oxide semiconductor film deposition is 90 The percentage is between % and 100%, preferably between 95% and 99.9%. High-filling oxides. By using a semiconductor film deposition target, the deposited oxide semiconductor film becomes a dense film. .

[0308] The sputtering gas used when depositing the oxide semiconductor film 330 is hydrogen, water, hydroxyl group or hydrogen Using high-purity gas from which impurities such as phosphates have been removed to concentrations of approximately ppm or ppb. It is preferable to do so.

[0309] The substrate is held in a processing chamber maintained under reduced pressure, and the substrate temperature is kept between 100°C and 600°C. The temperature should be between 200°C and 400°C. By depositing the film while heating the substrate, The concentration of impurities in the deposited oxide semiconductor film can be reduced. Damage caused by rinsing is reduced. And, while removing residual moisture in the processing chamber, hydrogen and moisture are removed. The removed sputtering gas is introduced and the metal oxide is targeted onto the gate insulating layer 302. An oxide semiconductor film 330 is formed on it. To remove residual moisture in the processing chamber, an adsorption type It is preferable to use a vacuum pump. For example, a cryopump, ion pump, or titanium pump. It is preferable to use a breech pump. Furthermore, a turbopump is preferred as the exhaust means. A cold trap may be added to this. Treatment is performed by exhausting using a cryopump. The chamber contains, for example, hydrogen atoms, water (H2O) and other compounds containing hydrogen atoms (more preferably carbon Because compounds containing atoms are also exhausted, the oxide semiconductor film deposited in the processing chamber contains... The concentration of impurities can be reduced.

[0310] An example of film deposition conditions is a distance of 100 mm between the substrate and the target, and a pressure of 0.6 Pa. The conditions applied are a DC power supply of 0.5kW and an oxygen atmosphere (oxygen flow rate ratio of 100%). It can be used. Furthermore, when using a pulsed DC power supply, powdery material (particulate matter) generated during film formation can be produced. This is preferable because it reduces debris (also called 'crumbs' or 'dust') and results in a more uniform film thickness distribution. The film thickness is preferably 5 nm to 30 nm. Note that the oxide semiconductor material used may vary depending on the material. The appropriate thickness varies, and you should select the appropriate thickness depending on the material.

[0311] Next, the oxide semiconductor film 330 is transformed into island-shaped oxide semiconductors by a second photolithography process. The material is processed into layers. Additionally, a resist mask is used to form island-shaped oxide semiconductor layers. It may also be formed by the jet method. If the resist mask is formed by the inkjet method, photomask Because no screws are used, manufacturing costs can be reduced.

[0312] Next, the oxide semiconductor layer is subjected to a first heat treatment. This first heat treatment causes the oxide semiconductor layer The conductive layer can be dehydrated or dehydrogenated. The temperature of the first heat treatment is 400°C. The temperature shall be 750°C or less, preferably 400°C or more, and below the strain point of the substrate. The substrate is introduced into an electric furnace, one of the scientific devices, and the oxide semiconductor layer is subjected to a nitrogen atmosphere at 450°C. After heating at °C for 1 hour, water is added to the oxide semiconductor layer without exposure to air. This prevents the re-imposition of hydrogen and obtains the oxide semiconductor layer 331 (see Figure 11(B)).

[0313] Furthermore, the heat treatment device is not limited to electric furnaces, but also includes heat conduction or heat from heat-generating elements such as resistance heating elements. The device may include an apparatus that heats the object to be processed by radiation. For example, GRTA(Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Angle) for Thermal Annealing devices, etc. A neal device can be used. The LRTA device uses halogen lamps and metal halide lamps. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high pressure A device that heats an object to be processed by radiation of light (electromagnetic waves) emitted from lamps such as mercury lamps. The GRTA device is a device that performs heat treatment using high-temperature gas. The gas contains A Inert gases such as argon or nitrogen, which do not react with the material being treated by heat treatment. A gaseous substance is used.

[0314] For example, as a first heat treatment, the base is placed in an inert gas heated to a high temperature of 650°C to 700°C. The board is moved and placed inside, heated for several minutes, then the substrate is moved and placed in a hot inert gas chamber. GRTA can be performed using this method. Using GRTA allows for high-temperature heat treatment in a short time. Yes.

[0315] In the first heat treatment, nitrogen or a noble gas such as helium, neon, or argon is used. It is preferable that it does not contain water, hydrogen, etc. Alternatively, nitrogen introduced into the heat treatment device, Alternatively, the purity of noble gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably 7N (99.99999%) or higher (i.e., impurity concentration of 1 ppm or less, preferably It is preferable to keep the concentration at 0.1 ppm or less.

[0316] Furthermore, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor film In some cases, crystallization may occur, forming a microcrystalline or polycrystalline film. For example, if the crystallization rate is 90% or higher. Alternatively, it may become an oxide semiconductor film with more than 80% microcrystalline properties. Also, the first heat treatment Depending on the conditions or the material of the oxide semiconductor layer, amorphous oxide semiconductors that do not contain crystalline components may be used. It can also form a conductive film. Furthermore, it can contain microcrystalline regions (particle size 1 nm or larger) within an amorphous oxide semiconductor. In the case of oxide semiconductor films where elements smaller than 20 nm (typically between 2 nm and 4 nm) are mixed together There are also combinations.

[0317] Furthermore, the first heat treatment of the oxide semiconductor layer is performed on the oxide before it is processed into an island-shaped oxide semiconductor layer. This can also be done on the semiconductor film 330. In that case, after the first heat treatment, the heating device is used The substrate is removed, and the photolithography process is performed.

[0318] Heat treatments that have the effect of dehydrating and dehydrogenating oxide semiconductor layers are used in oxide semiconductor layer formation. After the film is formed, the source electrode and drain electrode are stacked on the oxide semiconductor layer, and then the source electrode and This can be done either after forming a protective insulating film on the drain electrode, or afterwards.

[0319] Furthermore, when forming contact holes in the gate insulating layer 302, the process is carried out in an oxide semiconductor. This can be done before or after dehydration or dehydrogenation treatment of the membrane 330.

[0320] Note that the etching of oxide semiconductor films here is not limited to wet etching, but also includes dry etching. Etching may be used.

[0321] Etching conditions (etching) can be adjusted according to the material so that the desired processing shape can be etched. Adjust the solution, etching time, temperature, etc. as appropriate.

[0322] Next, a conductive film is formed on the gate insulating layer 302 and the oxide semiconductor layer 331. The film can be formed by sputtering or vacuum deposition. Suitable materials for the conductive film include Al, Cr, and C. An element selected from u, Ta, Ti, Mo, W, or an alloy containing the above elements, Examples include alloy films combining the elements mentioned above. Also, manganese, magnesium, and di Using a material selected from one or more of the following: thorium, beryllium, or thorium This is also acceptable. Furthermore, the conductive film may be a single-layer structure or a laminated structure of two or more layers. For example, A single-layer structure of an aluminum film containing ricon, and a two-layer structure in which a titanium film is laminated on top of an aluminum film. A Ti film is constructed, and an aluminum film is layered on top of the Ti film, and then another Ti film is layered on top of that. Examples include a three-layer structure for film formation. Also, aluminum can be combined with titanium (Ti) and tantalum (Ta). Tungsten (W), Molybdenum (Mo), Chromium (Cr), Nd (Neodymium), Sc A film, alloy film, or a combination of one or more elements selected from (scandium). A nitride film may also be used.

[0323] If a heat treatment is performed after the conductive film is applied, the conductive film must have sufficient heat resistance to withstand this heat treatment. This is preferable.

[0324] A third photolithography step forms a resist mask on the conductive film, and selectively extracts the residue. After performing ching to form the source electrode layer 315a and drain electrode layer 315b, a resist is applied. Remove the mask (see Figure 11(C)).

[0325] For exposure during resist mask formation in the third photolithography process, ultraviolet light and KrF light are used. A laser or ArF laser light is used. Below the adjacent source electrode layer on the oxide semiconductor layer 331. The gap width between the end and the lower end of the drain electrode layer determines the subsequent formation of the thin-film transistor. The channel length L is determined. Note that when performing exposure with a channel length L = less than 25 nm, the number Extreme ultraviolet light (Ultraviolet) has extremely short wavelengths, ranging from nanometers to several tens of nanometers. Using t), exposure is performed during the resist mask formation in the third photolithography step. Exposure with ultraviolet light offers high resolution and a large depth of field. Therefore, the thin film traces that are later formed... The channel length L of the inverter can also be set to 10 nm or more and 1000 nm or less, and the circuit This allows for faster operation speeds and, because the off-current value is extremely small, it also contributes to lower power consumption. It is possible.

[0326] Furthermore, during the etching of the conductive film, the oxide semiconductor layer 331 is not removed. The materials and etching conditions are adjusted as appropriate.

[0327] In this embodiment, a Ti film is used as the conductive film, and the oxide semiconductor layer 331 is made of In-Ga -Zn-O based oxide semiconductors are used, with ammonia peroxide (31% by weight) as the etchant. Use hydrogen oxide solution (28% by weight), ammonia solution (5:2:2), and water.

[0328] In the third photolithography process, only a portion of the oxide semiconductor layer 331 is etched. This can result in an oxide semiconductor layer having grooves (recesses). Also, the source electrode layer 3 15a, A resist mask for forming the drain electrode layer 315b is made by inkjet method It may be formed. If the resist mask is formed by the inkjet method, a photomask is used. Therefore, manufacturing costs can be reduced.

[0329] Furthermore, an oxide conductive layer is formed between the oxide semiconductor layer and the source electrode layer and drain electrode layer. The metal layers for forming the oxide conductive layer, the source electrode layer, and the drain electrode layer may be: Continuous film deposition is possible. The oxide conductive layer can function as both a source region and a drain region.

[0330] The source region and drain region consist of an oxide conductive layer, an oxide semiconductor layer and a source electrode layer and By placing it between the drain electrode layer, the resistance of the source region and the drain region can be reduced. This enables high-speed operation of transistors.

[0331] Furthermore, in order to reduce the number of photomasks and processes used in the photolithography process, The resist mask formed by a multi-tone mask, which is an exposure mask where the light has multiple intensities, is formed by the light. The etching process may be performed using a mask. A resist mask formed using a multi-gradation mask. The ske will have a shape with multiple film thicknesses, and its shape can be further deformed by etching. Because it can do this, it can be used in multiple etching processes that process different patterns. Therefore, a single multi-tone mask can accommodate at least two different patterns. This allows for the formation of a resist mask. Therefore, the number of exposure masks can be reduced. Furthermore, the corresponding photolithography process can also be reduced, thus simplifying the overall process.

[0332] Next, plasma treatment is performed using a gas such as N2O, N2, or Ar. The process removes adsorbed water and other substances adhering to the surface of the exposed oxide semiconductor layer. Alternatively, plasma treatment may be performed using a mixed gas of oxygen and argon.

[0333] After plasma treatment, a protective insulation is applied to a portion of the oxide semiconductor layer without contact with the atmosphere. An oxide insulating layer 316, which forms the edge film, is created.

[0334] The oxide insulating layer 316 has a thickness of at least 1 nm, and is made of oxide insulating material by sputtering or other methods. The layer 316 can be formed using a method that prevents the introduction of impurities such as water and hydrogen. If hydrogen is present in the oxide insulating layer 316, the hydrogen may penetrate into the oxide semiconductor layer, or the hydrogen may penetrate into the oxide semiconductor layer. The region where oxygen is extracted from the oxide semiconductor layer and channels are formed in the oxide semiconductor layer is The opposite side (the so-called back channel side) becomes less resistant (N-type), and the parasitic channel There is a risk of hydrogen formation. Therefore, the oxide insulating layer 316 should be a film that contains as little hydrogen as possible. To achieve this, it is important not to use hydrogen in the film deposition method.

[0335] In this embodiment, a sputtering method is used to form an oxide insulating layer 316 with a thickness of 200 nm. A silicon film is deposited. The substrate temperature during film deposition should be between room temperature and 300°C. The temperature is set to 100°C. For silicon oxide film deposition by sputtering, a noble gas (typically, a) is used. Under an argon atmosphere, under an oxygen atmosphere, or under a noble gas (typically argon) and oxygen atmosphere This can be done below. Also, silicon oxide target or silicon tag can be used as the target. A target can be used. For example, a silicon target can be used in an oxygen and nitrogen atmosphere. Silicon oxide can be formed by sputtering under gas pressure. This creates a low-resistance oxide semiconductor layer. The oxide insulating layer 316 formed in contact with the surface is resistant to moisture, hydrogen ions, and OH - Impurities such as It does not contain these substances, and an inorganic insulating film is used to block their intrusion from the outside, typically acid Silicon oxide film, silicon oxide nitride film, aluminum oxide film, or aluminum oxide nitride film A membrane or similar structure is used.

[0336] In this case, the oxide insulating layer 316 is formed while removing residual moisture in the processing chamber. Preferably, the oxide semiconductor layer 331 and the oxide insulating layer 316 contain hydrogen, hydroxyl groups, or water. This is to prevent them from getting sick.

[0337] To remove residual moisture from the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable. Furthermore, as an exhaust method, a turbo pump with a cold trap is used. It is also acceptable. The treatment chamber, which has been evacuated using a cryopump, contains, for example, hydrogen atoms and water (H2 Since compounds containing hydrogen atoms, such as O), are exhausted, the film formed in the processing chamber is affected. The concentration of impurities in the oxide insulating layer 316 can be reduced.

[0338] The sputtering gas used when forming the oxide insulating layer 316 is hydrogen, water, hydroxyl group or hydrogenated High-purity gas is used, from which impurities such as substances have been removed to concentrations of approximately ppm or ppb. It is preferable.

[0339] Next, a second heat treatment (preferably 2) is performed under an inert gas atmosphere or an oxygen gas atmosphere. Perform the procedure at temperatures between 0°C and 400°C (for example, between 250°C and 350°C). For example, under a nitrogen atmosphere. A second heat treatment is performed at 250°C for 1 hour under gas pressure. After the second heat treatment, the oxide semiconductor A portion of the body layer (channel-forming region) is heated while in contact with the oxide insulating layer 316.

[0340] Through the above process, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After performing a heat treatment to reduce resistance, a portion of the oxide semiconductor film is selectively treated to remove excess oxygen. This is the state. As a result, the channel formation region 313 overlapping with the gate electrode layer 311 becomes i-type. Furthermore, the high-resistance source region 314a overlaps the source electrode layer 315a, and the drain electrode layer 315 A high-resistance drain region 314b overlapping b is formed self-aligned. Transistor 310 is formed (see Figure 11(D)).

[0341] Furthermore, a heat treatment is performed in air at a temperature between 100°C and 200°C for between 1 hour and 30 hours. This may also be done. In this embodiment, the heat treatment is performed at 150°C for 10 hours. This heat treatment is constant You may heat while maintaining the heating temperature, or you may heat from room temperature to a heating temperature of 100°C or higher and 200°C or higher. The heating and cooling process from the heating temperature back to room temperature may be repeated multiple times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. This allows for a reduction in heating time. This heat treatment results in a thin film that is normally off. A transistor can be obtained, thus improving the reliability of the display device.

[0342] Furthermore, the oxide semiconductor layer superimposed on the drain electrode layer 315b (and source electrode layer 315a) To form a high-resistance drain region 314b (or high-resistance source region 314a) in this region. This can improve the reliability of thin-film transistors. Specifically, high resistance drain By forming the in region 314b, the drain electrode layer 315b is separated into a high-resistance drain region 3 14b, extending to the channel formation region 313, a structure is provided that allows for a stepwise change in conductivity. This is possible. Therefore, a high power supply potential Vdd is supplied to the drain electrode layer 315b. When connected to a wire and operated, high Even when voltage is applied, the high-resistance drain region acts as a buffer, making localized electric field concentration less likely. This allows for a configuration that improves the voltage rating of the transistor.

[0343] Furthermore, the high-resistance source region or high-resistance drain region in the oxide semiconductor layer is When the body layer is thin, with a thickness of 15 nm or less, it is formed throughout the entire thickness direction, but oxide semi-semi If the thickness of the conductive layer is thicker than 30 nm to 50 nm, a portion of the oxide semiconductor layer, - The region in contact with the electrode layer or drain electrode layer and its vicinity becomes low resistance, resulting in a high resistance source region. Alternatively, a high-resistance drain region is formed, and in the oxide semiconductor layer, the region close to the gate insulating film is It can also be represented as type i.

[0344] A protective insulating layer may be formed on the oxide insulating layer 316. For example, by RF sputtering. A silicon nitride film is formed using this method. RF sputtering is suitable for mass production and is used for forming protective insulating layers. This method is preferable. The protective insulating layer protects against moisture, hydrogen ions, and OH - It contains impurities such as Furthermore, an inorganic insulating film is used to block these from entering from the outside, and a silicon nitride film is used. Aluminum nitride film, silicon nitride film, aluminum nitride film, etc. are used. In this configuration, a protective insulating layer 303 is formed using a silicon nitride film as a protective insulating layer. (See Figure 11(E).)

[0345] In this embodiment, the protective insulating layer 303 is formed on a substrate 3 up to the oxide insulating layer 316. 00 is heated to a temperature of 100°C to 400°C, and contains high-purity nitrogen from which hydrogen and water have been removed. A silicon nitride film is deposited using a silicon semiconductor target after introducing a sputtering gas. In this case as well, similar to the oxide insulating layer 316, residual moisture in the processing chamber is removed while maintaining It is preferable to form a protective insulating layer 303.

[0346] A planarizing insulating layer may be provided on the protective insulating layer 303 for planarization.

[0347] As described above, by applying a highly purified oxide semiconductor layer to a thin-film transistor, This makes it possible to provide a thin-film transistor with reduced off-current. By applying the thin-film transistor with reduced off-current, as explained above, to the pixels of a display device, Therefore, the retention capacitance provided in the pixel can extend the period during which the voltage can be retained. This allows us to provide a display device that consumes less power when displaying data.

[0348] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0349] (Embodiment 7) This embodiment provides another example of a thin-film transistor applicable to the display device disclosed herein. As shown, the thin-film transistor 360 shown in this embodiment is the same as the thin-film transistor of Embodiment 1. It can be used as 106.

[0350] An example of the cross-sectional structure of the thin-film transistor of this embodiment is shown in Figures 12(A) to (D). The thin-film transistors 360 shown in 12(A) to (D) are channel-protected (channel-straight) It is a type of bottom-gate structure called an inverse staggered thin-film transistor (also known as a bottom-gate type). It is also said that.

[0351] Furthermore, thin-film transistor 360 will be explained using a single-gate thin-film transistor. However, if necessary, a thin film transistor with a multi-gate structure having multiple channel formation regions It can also form a "ta".

[0352] The following describes how to fabricate a thin-film transistor 360 on a substrate 320 using Figures 12(A) to (D). Let's explain the process.

[0353] First, a conductive film is formed on a substrate 320 having an insulating surface, and then a first photolithography is performed. The gate electrode layer 361 is formed by the process. The resist mask is made by the inkjet method. It may be formed. If the resist mask is formed by the inkjet method, a photomask is used. Therefore, manufacturing costs can be reduced.

[0354] Furthermore, the material of the gate electrode layer 361 is molybdenum, titanium, chromium, tantalum, tungsten Metal materials such as tungsten, aluminum, copper, neodymium, scandium, or materials with these as their main components. It can be formed using alloy materials, either as a single layer or in layers.

[0355] Next, a gate insulating layer 322 is formed on the gate electrode layer 361.

[0356] In this embodiment, the gate insulating layer 322 is made by plasma CVD with a film thickness of 100 nm or less. This forms the silicon oxide nitride layer below.

[0357] Next, an oxide semiconductor film with a thickness of 2 nm to 200 nm is formed on the gate insulating layer 322. This is achieved, and then processed into island-shaped oxide semiconductor layers by a second photolithography process. In terms of form, it is an oxide semiconductor film, specifically a target for depositing In-Ga-Zn-O-based oxide semiconductor films. The film is deposited by sputtering using [a specific method].

[0358] In this case, it is preferable to deposit the oxide semiconductor film while removing residual moisture in the processing chamber. This is to prevent hydrogen, hydroxyl groups, or water from being present in the oxide semiconductor film.

[0359] To remove residual moisture from the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable. Furthermore, as an exhaust method, a turbo pump with a cold trap is used. It is also acceptable. The treatment chamber, which has been evacuated using a cryopump, contains, for example, hydrogen atoms and water (H2 Since compounds containing hydrogen atoms, such as O), are exhausted, the film formed in the processing chamber is affected. The concentration of impurities in oxide semiconductor films can be reduced.

[0360] The sputtering gas used when depositing oxide semiconductor films is hydrogen, water, hydroxyl groups, or hydrides. Which impurities should be removed to a concentration of approximately ppm or ppb in a high-purity gas? It is preferable.

[0361] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400°C to 750°C, preferably 400°C or higher, to reduce substrate strain. The value is set to less than 1. Here, a substrate is introduced into an electric furnace, which is one of the heat treatment devices, and an oxide semiconductor The body layer is subjected to a heat treatment at 450°C for 1 hour under a nitrogen atmosphere, and then exposed to air. Without doing so, the re-importation of water and hydrogen into the oxide semiconductor layer is prevented, and the oxide semiconductor layer 332 is obtained. See Figure 12(A).

[0362] Next, plasma treatment is performed using a gas such as N2O, N2, or Ar. The process removes adsorbed water and other substances adhering to the surface of the exposed oxide semiconductor layer. Alternatively, plasma treatment may be performed using a mixed gas of oxygen and argon.

[0363] Next, an oxide insulating layer was formed on the gate insulating layer 322 and the oxide semiconductor layer 332. Next, a resist mask is formed by a third photolithography process, followed by selective etching. After performing the procedure to form the oxide insulating layer 366, the resist mask is removed.

[0364] In this embodiment, the oxide insulating layer 366 is made of oxide with a thickness of 200 nm using the sputtering method. A silicon film is deposited. The substrate temperature during film deposition should be between room temperature and 300°C. The temperature is set to 100°C. For silicon oxide film deposition by sputtering, a noble gas (typically, a) is used. Under an argon atmosphere, under an oxygen atmosphere, or under a noble gas (typically argon) and oxygen atmosphere This can be done below. Also, silicon oxide target or silicon tag can be used as the target. A target can be used. For example, a silicon target can be used in an oxygen and nitrogen atmosphere. Silicon oxide can be formed by sputtering under gas pressure. This creates a low-resistance oxide semiconductor layer. The oxide insulating layer 366 formed in contact with the surface is resistant to moisture, hydrogen ions, and OH - Impurities such as It does not contain these substances, and an inorganic insulating film is used to block their intrusion from the outside, typically acid Silicon oxide film, silicon oxide nitride film, aluminum oxide film, or aluminum oxide nitride film A membrane or similar structure is used.

[0365] In this case, the oxide insulating layer 366 is formed while removing residual moisture in the processing chamber. Preferably, the oxide semiconductor layer 332 and the oxide insulating layer 366 contain hydrogen, hydroxyl groups, or water. This is to prevent them from getting sick.

[0366] To remove residual moisture from the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable. Furthermore, as an exhaust method, a turbo pump with a cold trap is used. It is also acceptable. The treatment chamber, which has been evacuated using a cryopump, contains, for example, hydrogen atoms and water (H2 Since compounds containing hydrogen atoms, such as O), are exhausted, the film formed in the processing chamber is affected. The concentration of impurities in the oxide insulating layer 366 can be reduced.

[0367] The sputtering gas used when forming the oxide insulating layer 366 is hydrogen, water, hydroxyl group or hydrogenated High-purity gas is used, from which impurities such as substances have been removed to concentrations of approximately ppm or ppb. It is preferable.

[0368] Next, a second heat treatment (preferably 2) is performed under an inert gas atmosphere or an oxygen gas atmosphere. The temperature may be between 0°C and 400°C, for example between 250°C and 350°C. For example, A second heat treatment is performed at 250°C for 1 hour under a nitrogen atmosphere. During the second heat treatment, the acid A portion of the oxide semiconductor layer (channel formation region) is heated while in contact with the oxide insulating layer 366. ru.

[0369] This embodiment further provides an oxide insulating layer 366, and a portion of the oxide semiconductor is exposed. Layer 332 is heat-treated under nitrogen, an inert gas atmosphere, or under reduced pressure. Oxide insulating layer 3 The region of the exposed oxide semiconductor layer 332 that is not covered by 66 is nitrogen, inert gas Heat treatment under a nitrogen atmosphere or reduced pressure can reduce resistance. For example, nitrogen Heat treatment is performed at 250°C for 1 hour under controlled conditions.

[0370] Heat treatment of an oxide semiconductor layer 332 provided with an oxide insulating layer 366 under a nitrogen atmosphere As a result, the exposed region of the oxide semiconductor layer 332 has low resistance, and the regions with different resistances (Figure 12) In B), the oxide semiconductor layer 362 has the shaded region and the white region.

[0371] Next, on the gate insulating layer 322, the oxide semiconductor layer 362, and the oxide insulating layer 366, After forming the film, a resist mask is formed by a fourth photolithography step, and then selected After etching is performed to form the source electrode layer 365a and the drain electrode layer 365b, Remove the resist mask (see Figure 12(C)).

[0372] The materials for the source electrode layer 365a and the drain electrode layer 365b are Al, Cr, Cu, and T. an element selected from a, Ti, Mo, and W, or an alloy containing the above elements, as described above. Examples include alloy films made by combining these elements. Furthermore, conductive films can have a single-layer structure or two or more layers. A laminated structure may also be used.

[0373] Through the above process, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After performing a heat treatment to reduce resistance, a portion of the oxide semiconductor film is selectively treated to remove excess oxygen. This is the state. As a result, the channel formation region 363 that overlaps with the oxide insulating layer 366 is i-type and This results in a high-resistance source region 364a overlapping the source electrode layer 365a, and a drain electrode layer 36 The high-resistance drain region 364b that overlaps with 5b is formed in a self-aligned manner. A film transistor 360 is formed.

[0374] Furthermore, a heat treatment is performed in air at a temperature between 100°C and 200°C for between 1 hour and 30 hours. This may also be done. In this embodiment, the heat treatment is performed at 150°C for 10 hours. This heat treatment is constant You may heat while maintaining the heating temperature, or you may heat from room temperature to a heating temperature of 100°C or higher and 200°C or higher. The heating and cooling process from the heating temperature back to room temperature may be repeated multiple times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. This allows for a reduction in heating time. This heat treatment results in a thin film that is normally off. A transistor can be obtained, thus improving the reliability of the display device.

[0375] Furthermore, the oxide semiconductor layer overlapping the drain electrode layer 365b (and source electrode layer 365a) In this configuration, a high-resistance drain region 364b (or a high-resistance source region 364a) is formed. This can further improve the reliability of thin-film transistors. Specifically, high-resistance dray By forming the drain region 364b, the drain electrode layer is separated from the drain electrode layer into the high-resistance drain region 364b. In the channel formation region 363, the structure is designed to allow for a stepwise change in conductivity. Yes, it is possible. Therefore, connect it to the wiring that supplies a high power supply potential Vdd to the drain electrode layer 365b. When operating, a high voltage is applied between the gate electrode layer 361 and the drain electrode layer 365b. Even if this occurs, the high-resistance drain region 364b acts as a buffer, making it less likely for localized electric field concentration to occur. This allows for a configuration that improves the voltage rating of the transistor.

[0376] Next, protective insulating layer 365a, drain electrode layer 365b, and oxide insulating layer 366 are placed on the source electrode layer 365a, drain electrode layer 365b, and oxide insulating layer 366. An edge layer 323 is formed. In this embodiment, the protective insulating layer 323 is formed using a silicon nitride film. To accomplish (see Figure 12(D)).

[0377] Furthermore, on top of the source electrode layer 365a, drain electrode layer 365b, and oxide insulating layer 366, An oxide insulating layer may be formed, and a protective insulating layer 323 may be laminated on the oxide insulating layer.

[0378] As described above, by applying a highly purified oxide semiconductor layer to a thin-film transistor, This makes it possible to provide a thin-film transistor with reduced off-current. By applying the thin-film transistor with reduced off-current, as explained above, to the pixels of a display device, Therefore, the retention capacitance provided in the pixel can extend the period during which the voltage can be retained. This allows us to provide a display device that consumes less power when displaying data.

[0379] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0380] (Embodiment 8) This embodiment provides another example of a thin-film transistor applicable to the display device disclosed herein. As shown, the thin-film transistor 350 shown in this embodiment is the same as the thin-film transistor of Embodiment 1. It can be used as 106.

[0381] An example of the cross-sectional structure of the thin-film transistor of this embodiment is shown in Figures 13(A) to (D).

[0382] Furthermore, the thin-film transistor 350 will be explained using a single-gate thin-film transistor. However, if necessary, a thin film transistor with a multi-gate structure having multiple channel formation regions It can also form a "ta".

[0383] The following describes how thin-film transistors 350 are fabricated on substrate 340 using Figures 13(A) to (D). Let's explain the process.

[0384] First, a conductive film is formed on a substrate 340 having an insulating surface, and then a first photolithography is performed. A gate electrode layer 351 is formed by the process. In this embodiment, the gate electrode layer 351 is Then, a tungsten film with a thickness of 150 nm is formed using the sputtering method.

[0385] Next, a gate insulating layer 342 is formed on the gate electrode layer 351. In this embodiment, As the insulating layer 342, a silicon oxide nitride layer with a thickness of 100 nm or less is formed by plasma CVD. To form.

[0386] Next, a conductive film is formed on the gate insulating layer 342, and then a second photolithography process is performed. A resist mask is formed on the conductive film, and selective etching is performed to create the source electrode layer 355a. After forming the drain electrode layer 355b, the resist mask is removed (see Figure 13(A)). . ) .

[0387] Next, an oxide semiconductor film 345 is formed (see Figure 13(B)). In this embodiment, oxidation Using an In-Ga-Zn-O-based oxide semiconductor film deposition target as the material semiconductor film 345 The film is deposited by sputtering. The oxide semiconductor film 345 is deposited by a third photolithography process. It is processed into an island-shaped oxide semiconductor layer.

[0388] In this case, the oxide semiconductor film 345 is formed while removing residual moisture in the processing chamber. This is preferable. To ensure that the oxide semiconductor film 345 does not contain hydrogen, hydroxyl groups, or water. It is.

[0389] To remove residual moisture from the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable. Furthermore, as an exhaust method, a turbo pump with a cold trap is used. It is also acceptable. The treatment chamber, which has been evacuated using a cryopump, contains, for example, hydrogen atoms and water (H2 Since compounds containing hydrogen atoms, such as O), are exhausted, the film formed in the processing chamber is affected. The concentration of impurities in the oxide semiconductor film 345 can be reduced.

[0390] The sputtering gas used when depositing the oxide semiconductor film 345 is hydrogen, water, hydroxyl group or hydrogen Using high-purity gas from which impurities such as phosphates have been removed to concentrations of approximately ppm or ppb. It is preferable to do so.

[0391] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400°C to 750°C, preferably 400°C or higher, to reduce substrate strain. The value is set to less than 1. Here, a substrate is introduced into an electric furnace, which is one of the heat treatment devices, and an oxide semiconductor The body layer is subjected to a heat treatment at 450°C for 1 hour under a nitrogen atmosphere, and then exposed to air. Without doing so, the re-importation of water and hydrogen into the oxide semiconductor layer is prevented, and the oxide semiconductor layer 346 is obtained. See Figure 13(C).

[0392] Furthermore, as a first heat treatment, the substrate is placed in an inert gas heated to a high temperature of 650°C to 700°C. Move it in and heat for several minutes, then move the substrate and heat it in an inert gas that has been heated to a high temperature. GRTA can be performed. Using GRTA allows for high-temperature heat treatment in a short time. ru.

[0393] Next, an oxide insulating layer 356 is formed, which will serve as a protective insulating film in contact with the oxide semiconductor layer 346.

[0394] The oxide insulating layer 356 has a thickness of at least 1 nm, and is made using a sputtering method or similar process. Layer 356 can be formed using an appropriate method that prevents the introduction of impurities such as water and hydrogen. If hydrogen is present in the oxide insulating layer 356, the hydrogen may penetrate into the oxide semiconductor layer, or the hydrogen may penetrate into the oxide semiconductor layer. The region where oxygen is extracted from the oxide semiconductor layer and channels are formed in the oxide semiconductor layer is The opposite side (the so-called back channel side) becomes less resistant (N-type), and the parasitic channel There is a risk of hydrogen formation. Therefore, the oxide insulating layer 356 should be a film that contains as little hydrogen as possible. To achieve this, it is important not to use hydrogen in the film deposition method.

[0395] In this embodiment, the oxide insulating layer 356 is made of oxide with a thickness of 200 nm using the sputtering method. A silicon film is deposited. The substrate temperature during film deposition should be between room temperature and 300°C. The temperature is set to 100°C. For silicon oxide film deposition by sputtering, a noble gas (typically, a) is used. Under an argon atmosphere, under an oxygen atmosphere, or under a noble gas (typically argon) and oxygen atmosphere This can be done below. Also, silicon oxide target or silicon tag can be used as the target. A target can be used. For example, a silicon target can be used in an oxygen and nitrogen atmosphere. Silicon oxide can be formed by sputtering under gas pressure. This creates a low-resistance oxide semiconductor layer. The oxide insulating layer 356 formed in contact with the surface is resistant to moisture, hydrogen ions, and OH - Impurities such as It does not contain these substances, and an inorganic insulating film is used to block their intrusion from the outside, typically acid Silicon oxide film, silicon oxide nitride film, aluminum oxide film, or aluminum oxide nitride film A membrane or similar structure is used.

[0396] In this case, the oxide insulating layer 356 is formed while removing residual moisture in the processing chamber. Preferably, the oxide semiconductor layer 346 and the oxide insulating layer 356 contain hydrogen, hydroxyl groups, or water. This is to prevent them from getting sick.

[0397] To remove residual moisture from the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable. Furthermore, as an exhaust method, a turbo pump with a cold trap is used. It is also acceptable. The treatment chamber, which has been evacuated using a cryopump, contains, for example, hydrogen atoms and water (H2 Since compounds containing hydrogen atoms, such as O), are exhausted, the film formed in the processing chamber is affected. The concentration of impurities in the oxide insulating layer 356 can be reduced.

[0398] The sputtering gas used when forming the oxide insulating layer 356 is hydrogen, water, hydroxyl group or hydrogenated High-purity gas is used, from which impurities such as substances have been removed to concentrations of approximately ppm or ppb. It is preferable.

[0399] Next, a second heat treatment (preferably 2) is performed under an inert gas atmosphere or an oxygen gas atmosphere. Perform the procedure at temperatures between 0°C and 400°C (for example, between 250°C and 350°C). For example, under a nitrogen atmosphere. A second heat treatment is performed at 250°C for 1 hour under gas pressure. After the second heat treatment, the oxide semiconductor The body layer is heated while in contact with the oxide insulating layer 356.

[0400] Through the above process, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After performing a heat treatment to reduce its resistance, the oxide semiconductor film is subjected to an oxygen-rich state. As a result, an i-type oxide semiconductor layer 352 is formed. The thin-film transistor 35 is formed through the above process. A value of 0 is formed.

[0401] Furthermore, a heat treatment is performed in air at a temperature between 100°C and 200°C for between 1 hour and 30 hours. This may also be done. In this embodiment, the heat treatment is performed at 150°C for 10 hours. This heat treatment is constant You may heat while maintaining the heating temperature, or you may heat from room temperature to a heating temperature of 100°C or higher and 200°C or higher. The heating and cooling process from the heating temperature back to room temperature may be repeated multiple times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. This allows for a reduction in heating time. This heat treatment results in a thin film that is normally off. A transistor can be obtained, thus improving the reliability of the display device.

[0402] Furthermore, a protective insulating layer may be formed on the oxide insulating layer 356. For example, RF Spa A silicon nitride film is formed using the T method. In this embodiment, a protective insulating layer 3 is used as the protective insulating layer. 43 is formed using a silicon nitride film (see Figure 13(D)).

[0403] Alternatively, a planarizing insulating layer may be provided on the protective insulating layer 343 for planarization.

[0404] As described above, by applying a highly purified oxide semiconductor layer to a thin-film transistor, This makes it possible to provide a thin-film transistor with reduced off-current. By applying the thin-film transistor with reduced off-current, as explained above, to the pixels of a display device, Therefore, the retention capacitance provided in the pixel can extend the period during which the voltage can be retained. This allows us to provide a display device that consumes less power when displaying data.

[0405] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0406] (Embodiment 9) This embodiment provides another example of a thin-film transistor applicable to the display device disclosed herein. As shown, the thin-film transistor 380 shown in this embodiment is the same as the thin-film transistor of Embodiment 1. It can be used as 106.

[0407] In this embodiment, Figure 1 shows an example where part of the thin-film transistor fabrication process differs from that of Embodiment 6. As shown in 4. Figure 14 is the same as Figure 11 except that the process is slightly different, so the same parts are shown. The same symbols are used, and detailed explanations of the same sections are omitted.

[0408] According to Embodiment 6, a gate electrode layer 381 is formed on the substrate 370, and the first gate insulation Layer 372a and a second gate insulating layer 372b are laminated. In this embodiment, the gate insulating layer The gate insulating layer has a two-layer structure, with a nitride insulating layer on the first gate insulating layer 372a and a second gate insulating layer 3 An oxide insulating layer is used for 72b.

[0409] The oxide insulating layer can be a silicon oxide layer, a silicon oxide nitride layer, or an aluminum oxide layer. Alternatively, an aluminum oxide nitride layer can be used. Furthermore, as the nitride insulating layer, Silicon nitride layer, silicon nitride oxide layer, aluminum nitride layer, or aluminum nitride oxide layer Layers and other elements can be used.

[0410] In this embodiment, the silicon nitride layer and the silicon oxide layer are laminated from the gate electrode layer 381 side. The structure is as follows. The first gate insulating layer 372a is made with a film thickness of 50n by sputtering. A silicon nitride layer (SiN) with a thickness of m or more and 200 nm or less (50 nm in this embodiment). y (y> 0)) is formed, and a film is formed on the first gate insulating layer 372a as the second gate insulating layer 372b. A silicon oxide layer (SiO) with a thickness of 5 nm to 300 nm (100 nm in this embodiment) x Layers (x>0) are stacked to form a gate insulating layer with a thickness of 150 nm.

[0411] Next, an oxide semiconductor film is formed, and the oxide semiconductor film is processed using a photolithography process to create island-like structures. The oxide semiconductor layer is processed. In this embodiment, the oxide semiconductor film is In-Ga-Z The film is deposited by sputtering using an nO-based oxide semiconductor film deposition target.

[0412] In this case, it is preferable to deposit the oxide semiconductor film while removing residual moisture in the processing chamber. This is to prevent hydrogen, hydroxyl groups, or water from being present in the oxide semiconductor film.

[0413] To remove residual moisture from the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable. Furthermore, as an exhaust method, a turbo pump with a cold trap is used. It is also acceptable. The treatment chamber, which has been evacuated using a cryopump, contains, for example, hydrogen atoms and water (H2 Since compounds containing hydrogen atoms, such as O), are exhausted, the film formed in the processing chamber is affected. The concentration of impurities in oxide semiconductor films can be reduced.

[0414] The sputtering gas used when depositing oxide semiconductor films is hydrogen, water, hydroxyl groups, or hydrides. Which impurities should be removed to a concentration of approximately ppm or ppb in a high-purity gas? It is preferable.

[0415] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature for the heat treatment in step 1 shall be 400°C or higher and 750°C or lower for the substrate, preferably 425°C or higher. Furthermore, if the temperature is 425°C or higher, the heat treatment time can be 1 hour or less, but if it is below 425°C... If so, the heat treatment time shall be longer than 1 hour. Here, one of the heat treatment apparatuses The substrate is introduced into an electric furnace, and the oxide semiconductor layer is heat-treated under a nitrogen atmosphere. After this process, without exposure to the atmosphere, the re-incorporation of water and hydrogen into the oxide semiconductor layer is prevented, and oxidation occurs. A material semiconductor layer is obtained. Then, high-purity oxygen gas, high-purity N2O gas, or ultra-dry gas is introduced into the same furnace. Cooling is performed by introducing dry air (dew point of -40°C or lower, preferably -60°C or lower). It is preferable that the gas or N2O gas does not contain water, hydrogen, etc. Alternatively, heat treatment equipment The purity of the oxygen gas or N2O gas introduced into the device should preferably be 6N (99.9999%) or higher. Or 7N (99.99999%) or higher (i.e., the concentration of impurities in oxygen gas or N2O gas) It is preferable to set the concentration to 1 ppm or less, preferably 0.1 ppm or less.

[0416] Furthermore, the heating apparatus is not limited to electric furnaces; for example, GRTA (Gas Rapid Th) thermal annealing) equipment, LRTA (Lamp Rapid Thermal) Using RTA (Rapid Thermal Anneal) devices such as Anneal devices It is possible to use a LRTA device with halogen lamps, metal halide lamps, and xenon lamps. Arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps, etc. This device heats the object being processed by radiating light (electromagnetic waves) from a lamp. Heat conduction or thermal radiation from heat-generating elements such as TA devices, lamps, and resistive heating elements. It may also be equipped with a device for heating the object to be processed. GRTA refers to heating using high-temperature gas. This is a method of processing. The gas can be a noble gas such as argon, or a gas such as nitrogen, which is heated. An inert gas that does not react with the material being processed is used. The RTA method is used at 600°C. You may also heat-treat it at ~750°C for several minutes.

[0417] Furthermore, after the first heat treatment in which dehydration or dehydrogenation is performed, the temperature is preferably between 200°C and 400°C. Alternatively, heating treatment at a temperature between 200°C and 300°C under an oxygen or N2O gas atmosphere. It is permissible to act rationally.

[0418] Furthermore, the first heat treatment of the oxide semiconductor layer is performed on the oxide before it is processed into an island-shaped oxide semiconductor layer. This can also be done on semiconductor films. In that case, after the first heat treatment, the substrate is removed from the heating device. The material is removed and the photolithography process is performed.

[0419] By going through the above process, the entire oxide semiconductor film is made into an oxygen-rich state, The material is converted to type i, thus obtaining an oxide semiconductor layer 382 that is entirely of type i.

[0420] Next, a conductive film is formed on the gate insulating layer 372b and the oxide semiconductor layer 382. Furthermore, a resist mask is formed on the conductive film by a photolithography process, and selectively esters the film. Ching is performed to form the source electrode layer 385a and the drain electrode layer 385b, and then by sputtering An oxide insulating layer 386 is formed.

[0421] In this case, the oxide insulating layer 386 is formed while removing residual moisture in the processing chamber. Preferably, the oxide semiconductor layer 382 and the oxide insulating layer 386 contain hydrogen, hydroxyl groups, or water. This is to prevent them from getting sick.

[0422] To remove residual moisture from the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable. Furthermore, as an exhaust method, a turbo pump with a cold trap is used. It is also acceptable. The treatment chamber, which has been evacuated using a cryopump, contains, for example, hydrogen atoms and water (H2 Since compounds containing hydrogen atoms, such as O), are exhausted, the film formed in the processing chamber is affected. The concentration of impurities in the oxide insulating layer 386 can be reduced.

[0423] The sputtering gas used when forming the oxide insulating layer 386 is hydrogen, water, hydroxyl group or hydrogenated High-purity gas is used, from which impurities such as substances have been removed to concentrations of approximately ppm or ppb. It is preferable.

[0424] The thin-film transistor 380 can be formed through the above process.

[0425] Next, in order to reduce variations in the electrical characteristics of thin-film transistors, under an inert gas atmosphere or perform heat treatment under a nitrogen gas atmosphere (preferably 150°C or higher and less than 350°C). Alternatively, a heat treatment may be performed at 250°C for 1 hour under a nitrogen atmosphere.

[0426] Furthermore, heat treatment is performed in air at temperatures between 100°C and 200°C for between 1 hour and 30 hours. This may also be done. In this embodiment, the heat treatment is performed at 150°C for 10 hours. This heat treatment is constant You may heat while maintaining the heating temperature, or you may heat from room temperature to a heating temperature of 100°C or higher and 200°C or higher. The heating and cooling process from the heating temperature back to room temperature may be repeated multiple times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. This allows for a reduction in heating time. This heat treatment results in a thin film that is normally off. A transistor can be obtained, thus improving the reliability of the display device.

[0427] Next, a protective insulating layer 373 is formed on the oxide insulating layer 386. In this embodiment, protective insulating A silicon nitride film with a thickness of 100 nm is formed as the edge layer 373 using the sputtering method.

[0428] The protective insulating layer 373 and the first gate insulating layer 372a, which are made of a nitride insulating layer, are resistant to moisture and water. It does not contain impurities such as elements, hydrides, and hydroxides, and blocks their entry from the outside. It has a locking effect.

[0429] Therefore, in the manufacturing process after the formation of the protective insulating layer 373, impurities such as moisture from the outside It can prevent intrusion. Furthermore, even after the device is completed as a display device, it can provide long-term protection. This prevents the intrusion of impurities such as moisture from the outside, improving the long-term reliability of the device. It is possible.

[0430] Furthermore, between the protective insulating layer 373, which is made of a nitride insulating layer, and the first gate insulating layer 372a The insulating layer is removed, and the protective insulating layer 373 and the first gate insulating layer 372a are in contact. It may also be a structure that does not require a specific structure.

[0431] Therefore, the ultimate goal is to remove impurities such as water, hydrogen, hydrides, and hydroxides from the oxide semiconductor layer. This reduces the impurity to a certain level and prevents its re-introduction, thereby maintaining a low impurity concentration in the oxide semiconductor layer. It is possible.

[0432] Furthermore, a planarizing insulating layer may be provided on the protective insulating layer 373 for the purpose of planarization.

[0433] As described above, by applying a highly purified oxide semiconductor layer to a thin-film transistor, This makes it possible to provide a thin-film transistor with reduced off-current. By applying the thin-film transistor with reduced off-current, as explained above, to the pixels of a display device, Therefore, the retention capacitance provided in the pixel can extend the period during which the voltage can be retained. This allows us to provide a display device that consumes less power when displaying data.

[0434] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0435] (Embodiment 10) This embodiment provides another example of a thin-film transistor applicable to the display device disclosed herein. The thin-film transistors shown in this embodiment are the thin-film transistors of Embodiments 2 to 8. It can be applied to this.

[0436] In this embodiment, the gate electrode layer, source electrode layer, and drain electrode layer have light-transmitting conductive elements. An example using electrical materials is shown. Therefore, the rest can be carried out in the same manner as in the above embodiment, and the above practical Descriptions of the form of application, parts that are identical or have a similar function, and repetition of processes are omitted. Further detailed explanations of the same section will be omitted.

[0437] For example, the materials used for the gate electrode layer, source electrode layer, and drain electrode layer are transparent to visible light. Photoconductive materials, such as In-Sn-O systems, In-Sn-Zn-O systems, and In-Al -Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn- O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn-O Metal oxides based on the Zn-O system can be applied, and the film thickness can be between 50 nm and 300 nm. Select appropriately within the range. Metal acids used for the gate electrode layer, source electrode layer, and drain electrode layer. Methods for depositing nitriles include sputtering, vacuum deposition (such as electron beam deposition), and arc deposition. Discharge ion plating and spray methods are used. Sputtering is also used. In this case, film deposition is performed using a target containing 2% to 10% by weight of SiO2, and light transmission is performed. SiO2, which inhibits crystallization in conductive films that possess certain properties. x (X>0) is included, and heating is performed in a later step. It is preferable to suppress crystallization during processing.

[0438] The composition ratio of the light-transmitting conductive film is expressed in atomic percent, and the electron beam microanalyzer... (EPMA:Electron Probe X-ray MicroAnalyzer The evaluation shall be conducted by analysis using ).

[0439] Furthermore, pixels on which thin-film transistors are placed have a pixel electrode layer or other electrode layer ( The electrode layer (such as the capacitance layer) and other wiring layers (such as the capacitance wiring layer) are transparent to visible light. Using a conductive film makes it possible to realize a display device with a high aperture ratio. Of course, the pixels The gate insulating layer, oxide insulating layer, protective insulating layer, and planar insulating layer are also transparent to visible light. It is preferable to use a membrane having [a specific characteristic].

[0440] In this specification, a film that is transparent to visible light is defined as a film with a visible light transmittance of 75 to 100. This refers to a film with a thickness of %; if the film is conductive, it is also called a transparent conductive film. Also, gate electrode layer, source electrode layer, drain electrode layer, pixel electrode layer, or other electrodes As a metal oxide applied to the layer and other wiring layers, a conductive film that is semi-transparent to visible light is used. It is acceptable. Semi-transparent to visible light means that the transmittance of visible light is between 50% and 75%. .

[0441] As described above, by making thin-film transistors transmissive, the aperture ratio can be improved. In particular, for small display panels of 10 inches or less, the number of gate wires can be increased. To achieve high resolution in displayed images, even when pixel dimensions are reduced, a high aperture ratio is achieved. This can be achieved. Furthermore, by using a light-transmitting film as a component of the thin-film transistor, high density can be achieved. Even with a large arrangement of thin-film transistors, a large aperture ratio can be achieved, increasing the display area. It can be sufficiently secured. Furthermore, the same material can be used in the same process as the components of thin-film transistors. By forming a retention capacity, the retention capacity can also be made light-transmitting, thus further increasing the aperture ratio. It can be improved.

[0442] Furthermore, by applying a highly purified oxide semiconductor layer to a thin-film transistor, A thin-film transistor with reduced current can be provided. Furthermore, as described in this embodiment... By applying thin-film transistors with reduced off-current to the pixels of a display device, The built-in holding capacity allows the voltage to be maintained for a longer period. Therefore, when displaying still images, etc. This allows us to provide a display device that consumes less power when operating.

[0443] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0444] (Embodiment 11) This embodiment shows examples of light-emitting elements applicable to the display devices disclosed herein, as shown in Figures 15 to 15. The following explanation will be given using Figure 17.

[0445] In this embodiment, electroluminescence is used as the display element in the pixels of the display device. Examples of light-emitting elements used are given. Light-emitting elements that utilize electroluminescence are light-emitting materials They are distinguished by whether the substance is an organic compound or an inorganic compound; generally, the former is organic EL elements, and the latter are called inorganic EL elements.

[0446] An organic EL element has an anode, a cathode, and a layer containing an organic compound between them. The potential of the anode is set to the cathode. The potential is raised above a certain level, and holes are injected from the anode and electrons from the cathode into the layer containing the organic compound. When electrons and holes (carriers) recombine in a layer containing organic compounds, energy is generated. The resulting energy excites the luminescent organic compound, and the excited organic compound then... It emits light when it returns to its bottom state. Due to this mechanism, organic EL elements are current-excited type emitters. This is an example of an optical element.

[0447] Inorganic electroluminescent (EL) elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements based on their element configuration. They are classified as such. Dispersive inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The luminescence mechanism utilizes donor and acceptor levels, and the donor-acceptor level is the key to this process. This is a receptor recombination type light emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. Furthermore, it has a structure where it is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. This is a localized light emission. Here, we will explain using an organic EL element as the light-emitting element. ru.

[0448] Figure 15 is an equivalent circuit diagram showing an example of a pixel configuration.

[0449] The structure and operation of pixels will be explained. Here, the oxide semiconductor layer is used to form the channel region. This example shows how to use two n-channel transistors in a single pixel.

[0450] Pixel 6400 consists of a switching transistor 6401, a driving transistor 6402, and has a light-emitting element 6404. The switching transistor 6401 has a gate that runs It is connected to signal line 6406, and the first electrode (either the source electrode or the drain electrode) is connected to signal line 64 It is connected to 05, and the second electrode (the other of the source electrode and drain electrode) is the drive transistor. It is connected to the gate of 6402. The drive transistor 6402 has a switch at its gate. The second electrode (the other of the source electrode and drain electrode) of the 6401 transistor for rakes is connected. The first electrode is connected to the power line 6407, and the second electrode is connected to the first electrode (image) of the light-emitting element 6404. It is connected to the primary electrode. The second electrode of the light-emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate.

[0451] Furthermore, a low power supply potential is set for the second electrode (common electrode 6408) of the light-emitting element 6404. The low power supply potential is defined as the low power supply potential set on power line 6407 relative to the high power supply potential. The potential is the potential that satisfies the high power supply potential, and low power supply potentials include, for example, GND and 0V. It may be fixed. The potential difference between this high power supply potential and the low power supply potential is applied to the light-emitting element 6404. Then, in order to pass current through the light-emitting element 6404 and make the light-emitting element 6404 emit light, a high power supply potential is used. The potential difference between the low power supply potential and the light-emitting element 6404 is set to be greater than or equal to the forward threshold voltage of the light-emitting element 6404. Set the potential for each.

[0452] Furthermore, DC power is supplied to power line 6407. In particular, pulsed DC power is supplied to power line 640 By supplying power to 7, the light-emitting element 6404 can be made to emit light in a pulsed manner. By displaying a video feed, it's possible to sequentially switch between and display multiple still images. Such displays can be used, for example, in the display of seconds on a clock. It is acceptable to supply DC power that is not present.

[0453] In this embodiment, a thin film having a highly purified oxide semiconductor layer and suppressed off-current is used. Because the transistor is applied to the pixel area, the switching transistor 6401 is turned off. During this state, the potential written to the gate of the drive transistor 6402 is maintained. Even if a capacitive element is placed between the gate of the drive transistor 6402 and the power line 6407, good.

[0454] As an example of a method for driving the light-emitting element 6404, a method for performing analog grayscale driving will be described. The forward voltage of the light-emitting element 6404 + the drive transistor is connected to the gate of the dynamic transistor 6402. Apply a voltage greater than or equal to Vth of the light-emitting element 6404. The forward voltage of the light-emitting element 6404 is the desired brightness. This refers to the voltage when set to degrees, and includes at least the forward threshold voltage. Note that for driving When inputting a video signal (image signal) that causes the transistor 6402 to operate in the saturation region... This allows current to flow through the light-emitting element 6404. The driving transistor 6402 is then saturated. To operate in the region, the potential of the power line 6407 is the gate of the drive transistor 6402. The potential is raised higher. By making the video signal analog, the video signal is sent to the light-emitting element 6404. By applying a current corresponding to the number, analog grayscale driving can be performed.

[0455] Furthermore, oxide semiconductor layers that are not laser crystallized exhibit less variation in properties within the substrate surface. Therefore, the characteristics of thin-film transistors arranged in multiple locations in the display area using the oxide semiconductor layer It is also homogeneous. The driving transistor 6402 has little variation in characteristics, and the light-emitting element 640 The current flowing through 4 can be precisely controlled according to the programmed gate voltage. As a result, this power One embodiment of a display device enables high-quality display with minimal display unevenness.

[0456] Furthermore, the voltage input voltage drive method allows for area gradation display using multiple pixels, and different emission colors. Color representation using a combination of multiple pixels (e.g., R, G, B), (e.g., R+G, G +B, R+B, R+G+B, etc. are possible. In the case of a voltage input voltage drive method, the drive is The gate of transistor 6402 is either sufficiently turned on by the driver transistor 6402, A signal is input that results in one of two states: either off or off. In other words, the drive transistor 64 02 operates in the linear region. The drive transistor 6402 operates in the linear region. A voltage higher than the voltage of the power line 6407 is applied to the gate of the drive transistor 6402. Note that the signal line 6405 has (power line voltage + Vth of the drive transistor 6402) Apply the above voltage.

[0457] Furthermore, whether the light-emitting element 6404 is driven by analog gradation or by voltage input voltage, The off-current per 1 μm channel width of the switching transistor 6401 is, for example, 1 × 10 -16 Because it is suppressed to A / μm or less, the gate current of the drive transistor 6402 The position retention period is long. Therefore, even with a small number of image signal writes, the static display on the display unit is maintained. It can display images. Because the frequency of writing signals can be reduced, This allows for lower power consumption. Furthermore, the pixel configuration shown in Figure 15 is not limited to this. For example, a switch, resistor, capacitive element, transistor or You may add logic circuits or other components.

[0458] Next, the cross-sectional structure of the pixels will be explained using Figure 16. Note that Figures 16(A), (B), The driving TFTs 7011, 7021, and 7001 exemplified in (C) contain highly purified acid A thin-film transistor having a semiconductor layer can be used, for example, in Embodiments 2 to 2. A thin-film transistor as described in form 10 can be used.

[0459] The light-emitting element illustrated in this embodiment has a configuration in which an EL layer is sandwiched between the first electrode and the second electrode. To possess.

[0460] For the first and second electrodes of the light-emitting element, the cathode electrode is made of a material with a small work function. For example, specifically alkali metals such as Li and Cs, and alkali metals such as Mg, Ca, and Sr. Potassium earth metals and alloys containing them (such as Mg:Ag, Al:Li, etc.), as well as Yb and E Rare earth metals such as r are preferred. Furthermore, the electrode that becomes the anode should be made of a material with a large work function, for example... For example, titanium nitride, ZrN, Ti, W, Ni, Pt, Cr, etc., or ITO, IZO (in oxide). Transparent conductive materials such as zinc oxide (zium oxide) and ZnO are preferred. Note that the electron injection layer is placed at the cathode. When forming in contact with the anode, or when forming a hole injection layer in contact with the anode, the work function of the electrode material The influence can be reduced. Examples of electron injection layers and hole injection layers include organic compounds and metals. Oxide composite materials, metal oxides, organic compounds and alkali metals, alkaline earth metals, or These compounds can be used to form composite materials, or they can be combined in appropriate ways.

[0461] Furthermore, the EL layer formed on the first electrode may consist of a single layer or multiple layers stacked together. Either way is fine. If the EL layer is composed of multiple layers, the anode, hole injection layer, A hole transport layer, an emissive layer, an electron transport layer, an electron injection layer, and a cathode are stacked in this order in contact with each other. A configuration like this can be given as an example. Note that it is not necessary to include all of these layers. Furthermore, multiple EL layers separated by an intermediate layer that functions as a charge generation layer are used as the first electrode and the second electrode. It may also be configured to be placed between the electrodes.

[0462] Furthermore, in order to extract light from the light-emitting element, at least one of the first electrode or the second electrode It is formed from a light-transmitting conductive film. The light emitted by the light-emitting element formed on the substrate is extracted. When classifying light-emitting elements by direction, the top surface is removed from the side of the substrate where the light-emitting elements are formed. Injection molding, bottom injection molding where the material is removed from the substrate side, and removal from both the substrate side and the side opposite the substrate. There are three representative structures of double-sided emission light-emitting elements, and the pixel configuration depends on the emission structure of the light-emitting element. It can also be applied to this.

[0463] Furthermore, when an EL layer is laminated on the first electrode, the periphery of the first electrode is covered with a partition wall. The partition wall is For example, organic resin films such as polyimide, acrylic, polyamide, and epoxy, inorganic insulating films, and It is formed using organic polysiloxane. In addition, a photosensitive resin material is used to form the partition. It is preferable to leave a partition wall around the periphery of the first electrode while covering the first electrode. When an opening is formed in a photosensitive resin material, the side wall from the partition to the opening has a continuous curvature. This is because it creates a sloped surface and eliminates the need to form a resist mask.

[0464] Furthermore, a color filter can also be formed between the substrate and the light-emitting element. Etching is performed using droplet ejection methods such as inkjet printing, printing methods, and photolithography techniques. It can be formed using methods such as shaping.

[0465] Furthermore, if an overcoat layer is formed on the color filter, and then a protective insulating layer is formed, By applying an overcoat layer, the irregularities caused by the color filter can be made flat. Protection Forming an insulating film prevents impurities from diffusing from the color filter to the light-emitting element. .

[0466] Furthermore, a light-emitting element is placed on the protective insulating layer, overcoat layer, and insulating layer of the thin-film transistor. When formed, the protective insulating layer, the overcoat layer, and the insulating layer penetrate the thin-film transistor. A contact hole is formed that reaches the source electrode layer or the drain electrode layer. In particular, the If contact holes are laid out and formed in a position that overlaps with the aforementioned partition wall, the opening ratio will be reduced. It is preferable because it can be suppressed.

[0467] The configuration of a pixel having a light-emitting element with a bottom-extrusion structure will be described. A driving TF provided in the pixel... Figure 16(A) shows a cross-sectional view of the cross-section including T7011 and the light-emitting element 7012.

[0468] The driver TFT7011 has an insulating layer, an oxide semiconductor layer, a source electrode layer and a drive layer on the substrate. It has a source electrode layer, a gate insulating layer, and a gate electrode layer, and the source electrode layer and drain electrode layer are Each wiring layer is electrically connected and installed.

[0469] Furthermore, an insulating layer 7031 is formed covering the drive TFT 7011, and openings are formed on the insulating layer 7031. A color filter 7033 having an opening is provided. A light-transmitting conductive film 7017 The color filter 7033 is covered by an overcoat layer 7034 and an insulating layer 7 It is formed on 035. Note that the drain electrode of the driving TFT 7011 and the conductive film 701 7 is an opening formed in the overcoat layer 7034, the insulating layer 7035, and the insulating layer 7031. They are electrically connected via the opening. Furthermore, the first light-emitting element 7012 is located on the conductive film 7017. The electrode 7013 is provided in contact with it.

[0470] The light-emitting element 7012 has an EL layer 7014 between the first electrode 7013 and the second electrode 7015. To hold by pinching.

[0471] The light-transmitting conductive film 7017 includes indium oxide containing tungsten oxide, acid Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, oxide Titanium-containing indium tin oxide, indium tin oxide (hereinafter referred to as ITO), Translucent conductive materials such as zinc oxide and indium tin oxide with added silicon oxide. A conductive film can be used.

[0472] This section describes the case where the first electrode 7013 of the light-emitting element 7012 is used as the cathode. When the first electrode 7013 is used as the cathode, a metal with a small work function is preferable. In Figure 16(A), the film thickness of the first electrode 7013 is such that it transmits light (preferably 5 (Approximately nm to 30 nm) For example, an aluminum film or M with a thickness of 20 nm. A g-Ag alloy film is used for the first electrode 7013.

[0473] Furthermore, after laminating a transparent conductive film and an aluminum film, selective etching is performed. A transparent conductive film 7017 and a first electrode 7013 may be formed, in which case the same Etching can be performed using a mask, which is preferable.

[0474] Furthermore, the second electrode 7015 formed on the EL layer 7014 is made of a material with a large work function. It is preferable that a shielding film 7016, for example, a light-blocking metal, be placed on the second electrode 7015. A metal that reflects light is used. In this embodiment, an ITO film is used as the second electrode 7015. A Ti film is used as the shielding film 7016.

[0475] Furthermore, the color filter 7033 is covered with an overcoat layer 7034, and a protective insulating layer 7 Cover with 035. Note that in Figure 16(A), the overcoat layer 7034 is shown as having a thin film thickness. However, the overcoat layer 7034 flattens the irregularities caused by the color filter 7033. Yes, they are.

[0476] Furthermore, the overcoat layer 7034 and the protective insulating layer 7035 are formed, and the drain electricity The contact hole reaching the polar layer 7030 is positioned to overlap with the septum 7019. .

[0477] In the case of the pixel structure shown in Figure 16(A), the light emitted by the light-emitting element 7012 is as indicated by the arrow. It is emitted towards the first electrode 7013, passes through the color filter 7033, and exits the display device. ru.

[0478] Note that in Figure 16(A), the gate electrode layer, source electrode layer, and drain electrode layer are translucent. This shows an example of constructing a driving TFT7011 using a conductive film having the following properties. Therefore, light emission A portion of the light emitted from element 7012 is directed to the color filter 7033 and the driver TFT 701 It is launched after passing through point 1.

[0479] Next, the configuration of a pixel having a double-sided extrusion light-emitting element will be described. Figure 16(B) shows a cross-sectional view of the TFT 7021 and the light-emitting element 7022.

[0480] The driver TFT7021 has an insulating layer, an oxide semiconductor layer, a source electrode layer and a drive layer on the substrate. It has a source electrode layer, a gate insulating layer, and a gate electrode layer, and the source electrode layer and drain electrode layer are Each wiring layer is electrically connected and installed.

[0481] Furthermore, an insulating layer 7041 is formed covering the drive TFT 7021, and openings are formed on the insulating layer 7041. A color filter 7043 having an opening is provided. A light-transmitting conductive film 7027 The color filter 7043 is covered by an overcoat layer 7044 and an insulating layer 7 It is formed on 045. Note that the drain electrode of the driving TFT 7021 and the conductive film 702 7 is an opening formed in the overcoat layer 7044, the insulating layer 7045, and the insulating layer 7041. They are electrically connected via the opening. Furthermore, the first light-emitting element 7022 is located on the conductive film 7027. The electrode 7023 is provided in contact with it.

[0482] The light-emitting element 7022 has an EL layer 7024 between the first electrode 7023 and the second electrode 7025. To hold by pinching.

[0483] This section describes the case where the first electrode 7023 of the light-emitting element 7022 is used as the cathode. The conductive film 7027, which has light-transmitting properties, is the same as the conductive film 7017 shown in Figure 16(A). It is sufficient to form it as shown in Figure 16(A), and the first electrode 7023 is the first electrode 7013 It can be formed in the same manner as shown above, and the EL layer 7024 is the same as the EL layer 7014 shown in Figure 16(A) Since the same process can be followed, a detailed explanation will be omitted here.

[0484] The second electrode 7025 formed on the EL layer 7024 functions as an anode here, Materials with a large work function, such as transparent conductive materials like ITO, IZO, and ZnO, are preferred. In this embodiment, ITO is formed as the second electrode 7025.

[0485] Furthermore, the color filter 7043, the overcoat layer 7044, and the protective insulating layer 7045 are The color filter 7033 and overcoat layer 703 of the pixel illustrated in Figure 16(A) Layer 4 and the protective insulating layer 7035 may be formed in the same manner.

[0486] In the pixel structure shown in Figure 16(B), the light emitted from the light-emitting element 7022 is indicated by the arrow. The first electrode 7023 side and the second electrode 7025 side are injected in this manner, and the first electrode 70 The light from side 23 passes through color filter 7043 and exits the display device.

[0487] In Figure 16(B), the gate electrode layer, source electrode layer, and drain electrode layer are made of light-transmitting material. This shows an example of constructing a driving TFT7021 using a conductive film having the following properties. Therefore, light emission A portion of the light emitted from element 7022 is directed to the color filter 7043 and the driver TFT 702. It is launched after passing through point 1.

[0488] Furthermore, the overcoat layer 7044 and the insulating layer 7045 are formed, and the drain electrode layer The contact hole reaching 7040 is positioned to overlap with partition wall 7029. The layout involves overlapping the contact hole that reaches the rain electrode layer with the partition wall 7029. By doing so, the aperture ratio on the second electrode 7025 side and the aperture ratio on the first electrode 7023 side are made to be approximately the same. It is possible.

[0489] However, if both display surfaces of a double-sided injection-type light-emitting element are to be full-color displays, the second Light from electrode 7025 does not pass through color filter 7043, therefore a separate color filter is required. It is preferable to provide a sealing substrate equipped with a t-type element above the second electrode 7025.

[0490] Next, the configuration of a pixel having a light-emitting element with an upper surface emission structure will be described. Figure 16(C) shows a cross-sectional view of the TFT 7001 and the light-emitting element 7002.

[0491] The driver TFT7001 has an insulating layer, an oxide semiconductor layer, a source electrode layer and a drive layer on the substrate. It has a source electrode layer, a gate insulating layer, and a gate electrode layer, and the source electrode layer and drain electrode layer are Each wiring layer is electrically connected and installed.

[0492] Furthermore, an insulating layer 7051 is formed covering the drive TFT 7001, and openings are formed on the insulating layer 7051. An insulating layer 7053 having a mouth is provided. The first electrode 7003 is provided with the insulating layer 7053 It is formed on an insulating layer 7055 that covers the driving TFT 7001. The drain electrode and the first electrode 7003 are formed in the insulating layer 7055 and the insulating layer 7051. It is electrically connected through the opening.

[0493] The insulating layer 7053 is made of polyimide, acrylic, benzocyclobutene, polyamide, and Resin materials such as oxy can be used. In addition to the above resin materials, low dielectric constant materials (l (ow-k material), siloxane resin, PSG (phosphorus glass), BPSG (phosphorus boron glass) Materials such as (S) can be used. Furthermore, multiple insulating films formed from these materials can be stacked. The insulating layer 7053 may be formed by this method. The method for forming the insulating layer 7053 is not particularly limited. Depending on the material, sputtering, SOG, spin coating, dipping, and spray coating methods are used. Droplet ejection method (inkjet method, screen printing, offset printing, etc.), Doctor Knife Roll coaters, curtain coaters, knife coaters, etc. can be used. By forming 7053, it is possible to flatten irregularities caused by, for example, the drive TFT.

[0494] The light-emitting element 7002 has an EL layer 7004 between the first electrode 7003 and the second electrode 7005. They are held in between. In the light-emitting element 7002 illustrated in Figure 16(C), the first electrode 700 Let's explain the case where 3 is used as the cathode.

[0495] The first electrode 7003 can be made by applying the same material as the first electrode 7013 shown in Figure 16(A). However, in the light-emitting element with an upper surface injection structure shown in Figure 16(C), the first electrode 7003 is It is preferable that the electrode does not transmit light and instead has high reflectivity. By using electrodes that do this, the efficiency of light extraction can be increased.

[0496] The first electrode 7003 may be, for example, an aluminum film or a material mainly composed of aluminum. A composite alloy film or an aluminum film laminated with a titanium film is preferred. (Figure 16(C)) The first electrode 7003 uses a laminated film in which a Ti film, an aluminum film, and another Ti film are stacked in that order. ru.

[0497] Furthermore, the EL layer 7004 can be formed in the same manner as the EL layer 7014 shown in Figure 16(A), Furthermore, the second electrode 7005 can be formed in the same manner as the second electrode 7025 shown in Figure 16(B). Therefore, a detailed explanation will be omitted here.

[0498] In the pixel structure shown in Figure 16(C), the light emitted from the light-emitting element 7002 is indicated by the arrow. The injection is directed toward the second electrode 7005.

[0499] When using the structure in Figure 16(C) to perform full-color display, for example, the light-emitting element 7002 is set to green. The light-emitting elements are configured such that one adjacent light-emitting element is red, and the other is blue. This will be used as a light-emitting element. In addition to the three types of light-emitting elements, there will also be four types of light-emitting elements, including a white light element. A light-emitting display device capable of full-color display may be manufactured.

[0500] Furthermore, if all of the multiple light-emitting elements arranged in the structure of Figure 16(C) are white light-emitting elements, A sealing substrate having a color filter or the like is placed above each light-emitting element, including the sub-element 7002. A light-emitting display device capable of full-color display may be created by arranging the device in such a configuration. By forming elements that emit colored light and combining them with color filters and color conversion layers, full Color display is possible.

[0501] Of course, single-color illumination may also be used. For example, a lighting device can be formed using white light. Alternatively, a monochromatic light emission may be used to form an area-color type light-emitting device.

[0502] Furthermore, if necessary, optical films such as polarizing films, including circular polarizers, may be provided.

[0503] Here, we have discussed organic EL elements as light-emitting elements, but inorganic EL elements can also be used as light-emitting elements. It is also possible to incorporate an L element.

[0504] Furthermore, the thin-film transistor (driving TFT) that controls the driving of the light-emitting element and the light-emitting element are electrically connected. An example of connection was shown, but a current control TFT is connected between the driving TFT and the light-emitting element. It may be a continuation of the same configuration.

[0505] Next, the appearance and cross-section of a light-emitting display panel (also called a light-emitting panel), which corresponds to one form of display device. The surface will be explained using Figure 17. Figure 17(A) shows a thin film formed on the first substrate. The transistor and light-emitting element are sealed between the second substrate and the panel with a sealing material. This is a top view, and Figure 17(B) corresponds to the cross-sectional view of HI in Figure 17(A).

[0506] Pixel section 4502, signal line driving circuit 4503a, 450 provided on the first substrate 4501 3b, and the scan line drive circuits 4504a and 4504b are surrounded by a sealing material 4505 A pixel unit 4502, signal line driving circuits 4503a, 4503b, and A second substrate 4506 is provided on top of the scan line driving circuits 4504a and 4504b. The pixel section 4502, signal line driving circuits 4503a, 4503b, and scan line driving circuit 45 04a and 4504b consist of a first substrate 4501, a sealing material 4505, and a second substrate 4506. It is sealed together with the filler 4507. Highly dense protective film with minimal degassing (laminated film, UV-curing resin film) It is preferable to package (seal) the product with a cover material such as a linoleum.

[0507] Also provided on the first substrate 4501 are the pixel section 4502, the signal line driving circuit 4503a, 4 503b, and the scan line driving circuits 4504a and 4504b have multiple thin-film transistors. In Figure 17(B), the thin-film transistor 4510 included in the pixel section 4502 and the signal The thin-film transistor 4509 included in the line drive circuit 4503a is shown as an example. An insulating layer 4542 is provided on the transistors 4509 and 4510. Also, an insulating layer 4 The source electrode of the thin-film transistor 4510 is connected via a contact hole provided at 542. The layer or drain electrode layer and the first electrode layer 4517 of the light-emitting element 4511 are electrically connected. It is.

[0508] Thin-film transistors 4509 and 4510 are provided with the high-performance transistors described in Embodiments 1 to 10. A thin-film transistor having a purified oxide semiconductor layer is used.

[0509] On the insulating layer 4542, the oxide semiconductor layer of the thin-film transistor 4509 for the drive circuit A conductive layer 4540 is provided in a position that overlaps with the channel formation region. The conductive layer 4540 is acid By placing it in a position that overlaps with the channel formation region of the synthetic semiconductor layer, BT stress test (Bias and temperature stress test) Threshold voltage of thin-film transistor 4509 before and after the test. The amount of change can be reduced. Note that in this specification, BT stress test (biased) A temperature stress test involves applying a high gate voltage to a thin-film transistor under a high-temperature atmosphere. This refers to the test. Also, the conductive layer 4540 has a potential that is the gate of the thin-film transistor 4509. It can be the same as the electrode layer or different, and it can function as a second gate electrode layer. It is also possible to have the conductive layer 4540 at GND, 0V, or floating. It's okay to have it.

[0510] The light-emitting element 4511 consists of a first electrode layer 4517, an electroluminescent layer 4512, and a second electrode layer The 4513 is a stacked structure, but is not limited to the configuration shown. The configuration of the light-emitting element 4511 can be changed as appropriate to match the direction of light and other factors.

[0511] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, using a photosensitive material, an opening is formed on the first electrode layer 4517, and the side wall of the opening It is preferable to form it so that it becomes an inclined surface with a continuous curvature.

[0512] Even if the electroluminescent layer 4512 consists of a single layer, it is configured to be stacked with multiple layers. It's fine either way.

[0513] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting element 4511, the second electrode layer A protective film may be formed on 4513 and the partition wall 4520. The protective film may be a silicon nitride film. It can form silicon nitride oxide films, DLC films, and the like.

[0514] Also, signal line drive circuits 4503a, 4503b and scan line drive circuits 4504a, 4504b The various signals and potentials applied to the pixel section 4502 are FPC4518a, 4518 It is supplied by b.

[0515] The connection terminal electrode 4515 has the same conductive film as the first electrode layer 4517 of the light-emitting element 4511. It is formed from. Also, the terminal electrode 4516 is formed from thin-film transistors 4509 and 4510. It is formed from the same conductive film as the source electrode layer and drain electrode layer of the device.

[0516] The connecting terminal electrode 4515 is connected to the terminal of FPC4518a via the anisotropic conductive film 4519. They are electrically connected.

[0517] The substrate located in the direction of light extraction from the light-emitting element 4511 must be translucent. In that case, glass plate, plastic plate, polyester film or acrylic film A translucent material like M is used.

[0518] Furthermore, in addition to inert gases such as nitrogen and argon, UV-curable resin can also be used as the filler 4507. Oils or thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's all you need to do.

[0519] Furthermore, if necessary, a polarizing plate or circular polarizing plate (including elliptical polarizing plate) may be placed on the emission surface of the light-emitting element. You may also appropriately incorporate optical films such as phase difference plates (λ / 4 plate, λ / 2 plate) and color filters. Furthermore, an anti-reflective coating may be provided on the polarizing plate or circular polarizing plate. For example, by the surface irregularities An anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0520] The signal line drive circuits 4503a and 4503b, and the scan line drive circuits 4504a and 4504b are Drive turns formed by a single-crystal semiconductor film or polycrystalline semiconductor film on a separately prepared substrate It may be implemented in the circuit. Also, only the signal line drive circuit, or part of it, or the scan line drive circuit The road may be formed separately or partially, and the configuration is not limited to that shown in Figure 17.

[0521] With the above configuration, a thin-film transistor with a highly purified oxide semiconductor layer and reduced off-current is achieved. A display device using a transistor can be provided. A thin-film transistor with reduced off-current can be used. Because it is applied directly, the holding capacitance provided in the pixel can hold the voltage for a longer period. As a result, a display device can be provided that offers stable operation when displaying still images, etc., and consumes less power. .

[0522] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0523] (Embodiment 12) In this embodiment, one aspect of a display device in which a phosphorescent layer is provided in the pixel portion is described using Figure 18. explain.

[0524] Figure 18 is a cross-sectional view of the pixel section of the bottom-face injection structure, showing the driving TFT7211 provided in the pixel, This is a cross-sectional view of the cut surface including the light-emitting element 7212.

[0525] The driver TFT7211 has an insulating layer, an oxide semiconductor layer, a source electrode layer and a drive layer on the substrate. It has a source electrode layer, a gate insulating layer, and a gate electrode layer, and the source electrode layer and drain electrode layer are Each wiring layer is electrically connected and installed.

[0526] Furthermore, an insulating layer 7231 is formed covering the drive TFT 7211, and openings are formed on the insulating layer 7231. A phosphorescent layer 7233 having an opening is provided. The light-transmitting conductive film 7217 is phosphorescent. Formed on the overcoat layer 7234 and insulating layer 7235 that cover layer 7233 It is made that the drain electrode 7230 and conductive film 7217 of the driving TFT 7211 are made of Through the openings formed in the overcoat layer 7234, the insulating layer 7235, and the insulating layer 7231 They are electrically connected. Furthermore, the first electrode 7 of the light-emitting element 7212 is placed on the conductive film 7217. 213 is located adjacent to it.

[0527] The driving TFT 7211 and the light-emitting element 7212 were manufactured using the method described in Embodiment 11. Since it is possible to do so, a detailed explanation will be omitted here.

[0528] The phosphorescent layer 7233 contains a phosphorescent material and stores the light emitted by adjacent light-emitting elements. Even after the light is interrupted, the phosphorescent material contained in the phosphorescent layer 7233 continues to emit light. Therefore, copper-plated activated zinc sulfide (ZnS:Cu) is used as the phosphorescent material. Also, strontium sulfide Phosphors made by adding activators to sulfides such as sulfides (SrS) as a base, and phosphors made by activating rare earth elements. Potassium aluminates include CaAl2O4:Eu, CaAl2O4:Nd, and Sr4Al 14 O 25 :Eu,Sr4Al 14 O 25:Dy, SrAl2O4:Eu, and SrAl You may also use 2O4:Dy, etc.

[0529] The duration for which the phosphorescent layer 7233 continues to emit light can be varied depending on the type of phosphorescent material used. It is possible. The duration of luminescence, or afterglow time, varies depending on the type of phosphorescent material, so depending on the application... Select materials accordingly. For example, a table used for applications where the displayed content does not need to be frequently rewritten. For the display device, a phosphorescent material with a long afterglow time should be selected and used. Also, the display should be relatively frequent. When rewriting, you should select and use a phosphorescent material with a short afterglow time. If the particles are inorganic particles, the particle size is 1 nm to 10 μm, preferably 10 nm to 5 μm. The following applies: If the particle size is 1 nm or less, the phosphorescence is lost, and if the particle size is 10 μm If the above conditions are present, the flatness of the phosphorescent layer will be compromised, making it difficult to fabricate the light-emitting element. That is the case.

[0530] Furthermore, in this embodiment, the phosphorescent layer 7233 contains a binder polymer and disperses phosphorescent material. The dispersion is then processed using droplet ejection methods such as inkjet, printing, spin coating, and photolithography. The material is formed by selecting an appropriate etching method, such as one using sography technology.

[0531] Furthermore, the phosphorescent layer 7233 is covered with an overcoat layer 7234, and the overcoat layer 7234 It is covered with an insulating layer 7235. Note that in Figure 18, the overcoat layer 7234 is shown as having a thin film thickness. However, the overcoat layer 7234 has the function of flattening the unevenness of the phosphorescent layer 7233. ru.

[0532] Furthermore, the location where the phosphorescent layer is provided is not limited to between the user of the display device and the light-emitting element. For example, A light-emitting element with a double-sided injection structure, in which an EL layer is sandwiched between a pair of translucent electrodes, is translucent. Therefore, when the light-emitting element is translucent, the phosphorescent layer will not be visible to the user of the display device. It can be placed on the back side of the light layer. In other words, between the phosphorescent layer and the user of the display device. A light-emitting element can be placed. If the light-emitting element is placed between the user of the display device and the phosphorescent layer... Furthermore, since the phosphorescent layer does not necessarily need to be translucent, the range of phosphorescent materials that can be selected is broadened. In terms of quantity, this will enable the use of phosphorescent materials with a particle size of 100 μm or less.

[0533] With the above configuration, the pixel portion has a phosphorescent layer and a thin film transistor having a highly purified oxide semiconductor layer. A display device to which a converter is applied can be provided. This display device has a thin film with reduced off-current. Because transistors are applied to the pixels, the retention capacitance provided in the pixels can hold the voltage for a certain period of time. This allows for longer battery life. As a result, the operation when displaying still images, etc., becomes more stable, and power consumption is reduced. We can provide the equipment.

[0534] Furthermore, one embodiment of the present invention is a self-luminous device that can display images with excellent visibility even in environments with weak ambient light. A display device of this type can be provided. Furthermore, because the pixel portion has a phosphorescent layer to which phosphorescent material is applied, This technology enables the provision of a display device that exhibits minimal flicker even with long intervals between light emission from optical elements. Furthermore, it drives the light-emitting element and provides energy to the phosphorescent material even in environments with weak ambient light. Therefore, it is possible to provide a display device that can be used continuously for a long period of time.

[0535] This embodiment can be appropriately combined with other embodiments shown herein. .

[0536] (Embodiment 13) In this embodiment, an example of an electronic device equipped with a display device as described in the above embodiment is I will explain about that.

[0537] Figure 19(A) shows a portable gaming machine, consisting of a casing 9630, a display unit 9631, and a speaker 9633. It may have, for example, an operation key 9635, a connection terminal 9636, a recording medium reading unit 9672, etc. The portable gaming machine shown in Figure 19(A) has a program or data recorded on the recording medium. Features include the ability to read data and display it on the display unit, and the ability to share information wirelessly with other portable gaming machines. It can have the following functions, etc. Note that the portable gaming machine shown in Figure 19(A) has the following functions. The functions are not limited to these, and it can have a variety of functions.

[0538] Figure 19(B) shows a digital camera, consisting of a housing 9630, a display unit 9631, and a speaker 963 3. Operation key 9635, connection terminal 9636, shutter button 9676, image receiving unit 9677 It can have, etc. The digital camera with television receiving function shown in Figure 19(B) is Features for taking still images, recording videos, and automatically or manually correcting captured images. Functions, functions to acquire various information from the antenna, captured images, or information acquired from the antenna It has a function to save the information it has collected, and it displays the captured image or information acquired from the antenna on the display unit. It can have functions such as the ability to receive television signals. The functions of a camera are not limited to these; it can have a variety of functions.

[0539] Figure 19(C) shows a television receiver, consisting of a housing 9630, a display unit 9631, and a speaker 9633. It may have an operation key 9635, a connection terminal 9636, etc., as shown in Figure 19(C). A television receiver has the function of processing television signals and converting them into image signals, and processing the image signals. It has functions such as converting signals to those suitable for display, and converting the frame frequency of image signals. It is possible to do so. However, the functions of the television receiver shown in Figure 19(C) are not limited to this. Furthermore, it can have a variety of functions.

[0540] Figure 20(A) shows a computer, consisting of a casing 9630, a display unit 9631, and a speaker 9633. Operation key 9635, connection terminal 9636, pointing device 9681, external connection port It can have a 9680, etc. The computer shown in Figure 20(A) can provide various information Functions to display (still images, videos, text images, etc.) on the display unit, various software (P Functions that control processing by program, communication functions such as wireless or wired communication, communication devices Functions that connect to various computer networks using their capabilities, and functions that connect to various data It can have functions for transmitting or receiving data, etc. Note that the code shown in Figure 20(A) The functions of a computer are not limited to these; it can have a variety of functions.

[0541] Next, Figure 20(B) shows a mobile phone, consisting of a casing 9630, a display unit 9631, and a speaker 963 3. It may have operation keys 9635, a microphone 9638, etc. Figure 20(B) The mobile phone shown has the function of displaying various information (still images, videos, text images, etc.). Functions to display a calendar, date, or time on the display unit, and to operate the information displayed on the display unit. This includes editing functions, functions to control processing by various software (programs), etc. It may have these functions. However, the functions of the mobile phone shown in Figure 20(B) are not limited to these. It can have various functions.

[0542] Next, Figure 20(C) shows an electronic paper (also called an e-book), with a casing 9630 and a front It may have an indicator 9631, an operation key 9635, etc. The electronic page shown in Figure 20(C) The page has functions to display various information (still images, videos, text images, etc.), and a calendar. A function to display the date or time on the display unit, and a function to operate or edit the information displayed on the display unit. It has functions, such as the ability to control processing through various software (programs). This is possible. However, the functions of the electronic paper shown in Figure 20(C) are not limited to this. It can have a variety of functions.

[0543] The electronic device described in this embodiment has multiple pixels constituting the display unit that are turned off. This can reduce the current. Therefore, the period during which the voltage can be held by the holding capacitance can be extended. An electric power supply equipped with a display device that can perform the following actions and can reduce power consumption when displaying still images, etc. It can be used as a sub-device. Furthermore, by improving the aperture ratio, it can have a high-resolution display. It can be used as a display device.

[0544] Furthermore, one embodiment of the present invention is a self-luminous device that can display images with excellent visibility even in environments with weak ambient light. A display device of this type can be provided. Furthermore, when a phosphorescent layer with phosphorescent material is applied to the pixel portion, We can provide a display device in which flicker is not noticeable even when the light-emitting interval of the light-emitting element is long. Furthermore, even in environments with weak ambient light, the light-emitting element is driven to provide energy to the phosphorescent material. Because this is possible, we can provide a display device that can be used continuously for a long period of time.

[0545] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0546] (Embodiment 14) In this embodiment, a block diagram of the display device and the procedure for stopping and opening the operation of the drive circuit are provided. The starting procedure is shown below. First, Figure 25 explains the block diagram of the display device.

[0547] The display device 1000 shown in this embodiment includes a display panel 1001, a signal generation circuit 1002, It has a memory circuit 1003, a comparison circuit 1004, a selection circuit 1005, and a display control circuit 1006. ru.

[0548] The display panel 1001, for example, includes a drive circuit section 1007 and a pixel section 1008. It has a gate line drive circuit 1009A and a signal line drive circuit 1009B. Gate line drive circuit 1 009A, the signal line driving circuit 1009B drives the pixel section 1008 which has multiple pixels. This is a drive circuit for that purpose. Also, gate line drive circuit 1009A and signal line drive circuit 1009B The pixel section 1008 and the other pixel section are configured with circuits made of thin-film transistors formed on the same substrate. It can be anything.

[0549] Furthermore, the gate line drive circuit 1009A, the signal line drive circuit 1009B, and the pixel section 1008 are constructed as follows: Some or all of the thin-film transistors that make up the structure have an n-channel semiconductor layer made of oxide semiconductor. A thin-film transistor of type L is used. Note that the gate line drive circuit 10 is located in the drive circuit section 1007. 09A or the signal line drive circuit 1009B may be formed on the same board. Alternatively, the configuration may involve mounting it on a separate substrate.

[0550] Furthermore, the signal generation circuit 1002 includes the gate line drive circuit 1009A and the signal line drive circuit 10 From 09B, a pulse signal is generated to output a signal for displaying at the pixel unit 1008. This is the circuit. The signal generation circuit 1002 also outputs to the drive circuit section 1007 via wiring. A circuit for doing so, and an image signal (also called video voltage, video signal, or video data), This is a circuit for outputting to the memory circuit 1003 via wiring. In other words, the drive circuit section 1 To generate and output control signals for driving 007 and image signals to be supplied to the pixel section. This is the circuit.

[0551] Specifically, the signal generation circuit 1002 uses the gate line drive circuit 1009A as a control signal. And the signal line drive circuit 1009B is supplied with a high power supply potential Vdd and a low power supply potential Vss, which are the power supply voltages. It supplies the gate line drive circuit 1009A with a start pulse for the gate line drive circuit. SP generates and outputs a clock signal CK, which is then sent to the signal line drive circuit 1009B. Generates and outputs a start pulse SP and a clock signal CK for the circuit. Also, signal generation circuit 1 002 outputs image signal data for displaying a moving image or still image to the storage circuit 1003. To exert force.

[0552] Furthermore, moving images are created by rapidly switching between multiple time-divided images over multiple frame periods. This refers to an image that is recognized as a moving image by the eye at an interval. Specifically, it refers to an image that is displayed 60 times per second (60 By switching between multiple images (frames), the flicker is reduced, and the image is perceived as moving by the human eye. A still image is a series of images. Unlike a moving image, a still image consists of multiple frames. Although it operates by rapidly switching between multiple time-divided images over a period of time, the continuous frame period For example, an image signal that does not change between the nth frame and the (n+1)th frame. It means that.

[0553] The signal generation circuit 1002 is also a circuit that generates other signals such as image signals and latch signals. It is also acceptable to do so. Furthermore, the signal generation circuit 1002 is connected to the gate line drive circuit 1009A and / or signal The line drive circuit 1009B has a reset signal to stop the output of the pulse signal of each drive circuit. The configuration may also output a signal Res. Note that each signal is a first clock signal, a second clock signal It may also be a signal composed of multiple signals, such as a "K" signal.

[0554] High power supply potential Vdd refers to a potential higher than the reference potential, while low power supply potential refers to a potential higher than the reference potential. This refers to a potential below a certain level. Note that both high and low power supply potentials are critical for transistor operation. It is desirable that the potential be at a level that allows for this.

[0555] Voltage is defined as the potential difference between a certain potential and a reference potential (for example, ground potential). It is often used to indicate these things. Therefore, voltage, potential, and potential difference are often rephrased as potential, voltage, and voltage difference, respectively. It is possible to do so.

[0556] Furthermore, the output of the image signal from the signal generation circuit 1002 to the memory circuit 1003 is an analog signal. In that case, the signal is converted to a digital signal via an A / D converter, etc., and stored in the memory circuit 1003. You should configure it to output.

[0557] The memory circuit 1003 stores multiple frames of image signals for multiple frame periods. It has frame memory 1010. The number of frame memories in the memory circuit 1003 is not particularly limited. It is not something that is stored, but rather any element that can store image signals for multiple frame periods. Note that frame memory is, for example, DRAM (Dynamic Random Accelerator). ss Memory), SRAM (Static Random Access Mem It can be constructed using memory elements such as (ory).

[0558] The frame memory 1010 can be configured to store image signals for each frame period. The number of frame memories is not particularly limited. Also, frame memory 101 The image signal of 0 is selectively read out by the comparison circuit 1004 and the selection circuit 1005. That is the case.

[0559] The comparison circuit 1004 compares the image signals of consecutive frame periods stored in the memory circuit 1003. This is a circuit for selectively reading out images, comparing them, and detecting the difference. When a difference is detected by comparing the image signals in the comparison circuit 1004, the difference is detected. In a continuous frame period, it is determined to be a moving image. On the other hand, the image in the comparison circuit 1004 When no difference is detected by comparing the signals, the consecutive frames that did not detect that difference are... During this period, it is determined to be a still image. That is, by detecting the difference in the comparison circuit 1004... Whether the image signal for a continuous frame period is an image signal for displaying a moving image, This determines whether the signal is an image signal for displaying a still image. The difference obtained through comparison is considered detected when it exceeds a certain level. You can set it up that way.

[0560] The selection circuit 1005 selects a number of switches, such as switches formed by thin-film transistors. When the image signal for displaying a moving image is determined by the detection of the difference in the comparison circuit, The system selects an image signal from the frame memory 1010 in which the image signal is stored and controls the display. This is a circuit for outputting to path 1006. Note that the frame comparison was performed by the comparison circuit 1004. If no difference in image signals is detected, the image displayed between those frames is a still image. In this configuration, the image signal for the frame period is not output to the display control circuit 1006. That's all you need to do.

[0561] The display control circuit 1006 receives the image signal, high power supply potential Vdd, low power supply potential Vss, and start power Regarding the control signals for Res SP, clock signal CK, and reset signal Res, the drive circuit section This is a circuit for switching the supply or cessation of power to 1007. Specifically, the comparison circuit 100 When it is determined to be a moving image according to 4, that is, when the difference in image signals over a continuous frame period is extracted The image signal is supplied from the selection circuit 1005 and driven via the display control circuit 1006 to the drive circuit. The control signal is supplied to unit 1007 and transmitted to the drive circuit unit 1007 via the display control circuit 1006. It will be supplied to the. On the other hand, the comparison circuit 1004 determines that it is a still image, i.e., a continuous frame If the difference in the image signal during the frame period is not extracted, the image signal is supplied by the selection circuit 1005. Since no signal is supplied, the display control circuit 1006 does not supply an image signal to the drive circuit 1007. The supply of the control signal to the drive circuit 1007 will cause the display control circuit 1006 to stop.

[0562] Furthermore, if the image is determined to be a still image, and the period during which it is determined to be a still image is short, control The system may be configured not to stop the signals at the high power supply potential Vdd and the low power supply potential Vss. Power consumption due to frequent stopping and restarting of high power supply potential Vdd and low power supply potential Vss This is preferable because it can reduce the increase.

[0563] The stopping of the image signal and control signal occurs when each pixel of the pixel unit 1008 can hold the image signal. It is desirable to do this over time, supplying the image signal again after the retention period at each pixel. The display control circuit 1005 will then resupply the image signal and control signal that it previously supplied. This configuration would be appropriate.

[0564] The supply of a signal refers to supplying a predetermined potential to the wiring. The deactivation of a signal refers to the supply of a predetermined potential to the wiring. The supply of a predetermined potential is stopped, and a wiring to which a predetermined fixed potential is supplied, for example, a low power supply potential Vs s refers to connecting to the wiring to which the signal is supplied. Also, stopping the signal means that a predetermined potential is supplied. This refers to disconnecting the electrical connection to the wiring, thereby creating a floating state.

[0565] As described above, a thin-film transistor having an oxide semiconductor layer has a channel length of 10 μm. In this case, the off-current per 1 μm of channel width is 1 aA (1 × 10⁻¹⁰). -18 A) Below (this Since this can be expressed as 1 aA / μm, the retention period can be extended. Therefore, when displaying still images in this embodiment, the phase is in which power consumption is reduced. A multiplicative effect can be expected.

[0566] As described above, the video signals are compared to determine whether it is a moving image or a still image, and the clock signal and starter signal are also used. By selectively restarting or stopping the supply of control signals such as RUSS to the drive circuit, low power consumption is achieved. It can be electrified.

[0567] Next, the gate line drive circuit 1009A and signal line drive circuit 1009B of the drive circuit section 1007 Figure 26 shows an example of the configuration of the shift registers that make up the system.

[0568] The shift register shown in Figure 26(A) is a first pulse output circuit 10_1 to the Nth pulse It has an output circuit 10_N (a natural number N≧3). The shift register shown in Figure 26(A) The first pulse output circuit 10_1 to the Nth pulse output circuit 10_N have a first wiring 1 First clock signal CK1 from wire 1, second clock signal CK2 from wire 12, third The third clock signal CK3 is obtained from wiring 13, and the fourth clock signal CK is obtained from the fourth wiring 14. 4 is supplied. Also, in the first pulse output circuit 10_1, a star from the fifth wiring 15 is supplied. The first start pulse (SP1) is input. Also, the nth pulse from the second stage onward is input. In the output circuit 10_n (where n is a natural number between 2 and N), the pulse output circuit of the preceding stage... A signal (called the preceding signal OUT(n-1)) (a natural number n≧2) is input. Also, the first In the pulse output circuit 10_1, the signal from the third pulse output circuit 10_3, which is two stages later, is received. It is powered. Similarly, in the nth pulse output circuit 10_n from the second stage onward, the (n)th of the second stage onward The signal from the pulse output circuit 10_(n+2) (the subsequent signal OUT(n+2)) ) is input. Therefore, the pulse output circuit of each stage outputs the pulse of the subsequent stage and / or the stage two stages prior. The first output signal (OUT(1)(SR)~OUT(N)) for input to the output circuit SR)) and a second output signal (OUT(1)~OUT(N)) which is input to another circuit etc. It is powered. Furthermore, as shown in Figure 26(A), the last two stages of the shift register are: Since the subsequent signal OUT(n+2) is not input, for example, from the sixth wiring 17 separately... The second start pulse SP2 and the third start pulse SP3 are respectively transmitted from the seventh wiring 18. It may also be configured to input this signal. Alternatively, it may be a signal generated internally within a separate shift register. This is also acceptable. For example, the (N+1)th pulse output circuit 10 that does not contribute to the pulse output to the pixel area. A (N+1) and (N+2) pulse output circuit 10_(N+2) is provided (also known as a dummy stage). (u) From the dummy stage, the second start pulse (SP2) and the third start pulse (S A configuration that generates a signal equivalent to P3) may also be used.

[0569] The first clock signal (CK1) through the fourth clock signal (CK4) are transmitted at regular intervals. This is a signal that alternates between an H signal and an L signal. Also, the first clock signal (CK1) to the fourth The clock signals (CK4) are sequentially delayed by 1 / 4 period. In this embodiment, the first Using the clock signal (CK1) to the fourth clock signal (CK4), the pulse output cycle It controls the drive of the road, etc. The clock signal CK is used according to the input drive circuit, G While it is sometimes referred to as CK or SCK, we will use CK in this explanation.

[0570] Furthermore, if it is explicitly stated that A and B are connected, it means that A and B are electrically connected. When A and B are functionally connected, and when A and B are directly connected This includes cases where... Here, A and B are the objects (e.g., devices, elements, circuits). (Wiring, electrodes, terminals, conductive film, layer, etc.) Therefore, a predetermined connection relationship, For example, not limited to the connection relationships shown in the diagram or text, This includes those who are not in charge of the department.

[0571] Each of the first pulse output circuit 10_1 to the Nth pulse output circuits 10_N is the first input Input terminal 21, second input terminal 22, third input terminal 23, fourth input terminal 24, fifth input It has a power terminal 25, a first output terminal 26, and a second output terminal 27 (see Figure 26(B)). ).

[0572] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11. It is electrically connected to any of the wirings 14 through to the fourth. For example, see Figures 26(A), (B) In this configuration, the first pulse output circuit 10_1 has a first input terminal 21 that is connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input Terminal 23 is electrically connected to the third wiring 13. Also, the second pulse output circuit 10 _2 is such that the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 The third wire 13 is electrically connected, and the third input terminal 23 is electrically connected to the fourth wire 14. It is connected.

[0573] Also, in Figures 26(A) and (B), the first pulse output circuit 10_1 is connected to the fourth input terminal A start pulse is input to terminal 24, and the subsequent signal OUT(3) is input to the fifth input terminal 25. Then, the first output signal OUT(1)(SR) is output from the first output terminal 26, and the second output This means that the second output signal OUT(1) is being output from power terminal 27.

[0574] Next, an example of a specific circuit configuration for a pulse output circuit will be explained in Figure 26(C).

[0575] In Figure 26(C), the first transistor 31 has its first terminal electrically connected to the power line 51. The second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode is It is electrically connected to the fourth input terminal 24. The second transistor 32 has the first terminal It is electrically connected to the power line 52, and the second terminal is electrically connected to the first terminal of the ninth transistor 39. It is connected, and the gate electrode is electrically connected to the gate electrode of the fourth transistor 34. The third transistor 33 has its first terminal electrically connected to the first input terminal 21, and Two terminals are electrically connected to the first output terminal 26. The fourth transistor 34 is One terminal is electrically connected to the power line 52, and the second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has its first terminal electrically connected to the power line 52, and The two terminals are the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. It is electrically connected to the fourth input terminal 24, and the gate electrode is electrically connected to the fourth input terminal 24. The transistor 36 has its first terminal electrically connected to the power line 51, and its second terminal connected to the second terminal The gate electrode of transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected. The gate electrode is electrically connected to the fifth input terminal 25. The seventh transistor 3 7 has its first terminal electrically connected to the power line 51, and its second terminal connected to the 8th transistor 38. The second terminal is electrically connected, and the gate electrode is electrically connected to the third input terminal 23. The eighth transistor 38 has its first terminal connected to the gate electrode of the second transistor 32 and The gate electrode of transistor 34 is electrically connected, and the gate electrode is connected to the second input terminal 2. It is electrically connected to 2. The ninth transistor 39 has its first terminal connected to the first transistor Electrically connected to the second terminal of the 31 and the second terminal of the second transistor 32, the second terminal The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are electrically charged. The gate electrode is electrically connected to the power line 51. The tenth transient The sta 40 has its first terminal electrically connected to the first input terminal 21, and its second terminal is connected to the second output terminal. It is electrically connected to terminal 27, and the gate electrode is electrically connected to the second terminal of the ninth transistor 39. The 11th transistor 41 has its first terminal electrically connected to the power line 52. The second terminal is electrically connected to the second output terminal 27, and the gate electrode is connected to the second transient The gate electrode of transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected. ru.

[0576] In Figure 26(C), the gate electrode of the third transistor 33 and the tenth transistor 4 The connection point between the gate electrode of transistor 0 and the second terminal of transistor 9 39 is defined as node NA. Also, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, The second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, and the eighth transistor The connection point between the first terminal of transistor 38 and the gate electrode of transistor 41 (number 11) is a node. Let's call it NB.

[0577] In Figure 26(C), if the pulse output circuit is the first pulse output circuit 10_1, the first input The first clock signal CK1 is input to input terminal 21, and the second clock signal CK1 is input to the second input terminal 22. A lock signal CK2 is input, and a third clock signal CK3 is input to the third input terminal 23. Then, a start pulse SP is input to the fourth input terminal 24, and the fifth input terminal 25 The subsequent signal OUT(3) is input, and the first output signal OUT(1) is output from the first output terminal 26. )(SR) is output, and the second output signal OUT(1) is output from the second output terminal 27. This will result in...

[0578] Here, the timing of a shift register equipped with multiple pulse output circuits as shown in Figure 26(C) The chart is shown in Figure 27. Note that if the shift register is a gate line drive circuit, In Figure 27, period 61 corresponds to the vertical retrace period, and period 62 corresponds to the gate selection period.

[0579] As shown in Figures 26 and 27, an example was fabricated using multiple n-channel transistors. In the drive circuit, the operation of switching from still image display to moving image display, or provided in the pixel section The operation of rewriting the TFT used to drive the EL element (hereinafter also referred to as the refresh operation). For the procedure of supplying or stopping the potential of each wire to the drive circuit section during this process, refer to Figure 28. Let me explain. Figure 28 shows the wiring that supplies a high power supply potential (Vdd) to the shift register, and a low power supply. Wiring that supplies power potential (Vss), wiring that supplies start pulse (SP), and 1 Wiring that supplies the clock signal (CK1) or the fourth clock signal (CK4) This diagram shows the change in potential of the wiring before and after a period (T1).

[0580] In the display device of this embodiment, the display of moving images and still images, or the refresh operation, Therefore, it is possible to display still images without constantly operating the drive circuit. As shown in Figure 28, the shift register is subjected to a high power supply potential (Vdd) and the first clock signal. The clock signals (CK1) through the fourth clock signal (CK4), and control signals such as the start pulse are supplied. There are periods during which the signal is supplied and periods during which the control signal is not supplied. Note that period T is shown in Figure 28. 1 is the period during which the control signal is supplied, i.e., the period during which the moving image is displayed and the refresh operation. This corresponds to the period during which the following is performed. Also, the period T2 shown in Figure 28 is the period during which no control signal is supplied. This corresponds to the period during which still images are displayed.

[0581] In Figure 28, the period during which the high power supply potential (Vdd) is supplied is not limited to period T1, but also includes period T1 And it is set up over a period T2. Also in Figure 28, the first clock During the period when signal (CK1) to the fourth clock signal (CK4) is supplied, the high power supply potential (V) It is provided from the time after dd is supplied until before the high power potential (Vdd) is stopped. Yes, they are.

[0582] Also, as shown in Figure 28, the first clock signal (CK1) to the fourth clock signal (CK 4) Before the start of period T1, the signal is initially a high-potential signal before being converted to a clock signal of a fixed period. Oscillation begins, and after period T1 ends, it is converted to a low-voltage signal before the clock signal starts oscillating. The configuration should be set to terminate automatically.

[0583] As described above, in the display device of this embodiment, during period T2, the shift register receives high power supply Vdd, the first clock signal (CK1) to the fourth clock signal (CK4), and The supply of control signals such as the start pulse will be stopped. And the period during which the supply of control signals is stopped. In this system, the conduction or non-conductivity of each transistor is controlled to operate and output from the shift register. The pulse signal being transmitted also stops. Therefore, the power consumed in the shift register and The power consumed in the pixel section driven by the shift register is reduced. It will become possible.

[0584] Please note that the above refresh operation may cause a degradation in the image quality of the displayed still images. Therefore, it needs to be done regularly. The display device of this embodiment has an EL element provided in each pixel. As a switching element that controls the voltage applied to the driving TFT, the above-mentioned oxide semiconductor It employs a transistor with a physical body. This drastically reduces the off-current. This allows for low fluctuations in the voltage applied to the TFT used to drive the EL elements in each pixel. It is possible to reduce it. In other words, displaying a still image stops the operation of the shift register. Even over long periods, image quality degradation can be reduced. For example, during that period Even if it's only 3 minutes, it's possible to maintain the quality of the displayed still image. For example, A display device that rewrites data 60 times per second and performs a refresh operation once every 3 minutes. Compared to a display device, power consumption can be reduced to approximately 1 / 10000.

[0585] The above-mentioned shutdown of the high power supply potential (Vdd) refers to the shutdown of the low power supply potential (Vs) as shown in Figure 28. s) is to be at the same potential as, and the stopping of the high power supply potential (Vdd) is when the high power supply potential is supplied The potential of the supplied wiring may be set to a floating state.

[0586] Furthermore, increasing the potential of the wiring to which the high power supply potential (Vdd) is supplied, i.e., during period T1 When increasing the power supply potential from a low power supply potential (Vss) to a high power supply potential (Vdd), the electrical current of the wiring in question It is preferable to control the change in potential so that it is gradual. The gradient of the potential change in the wiring is If the voltage is too steep, the change in potential becomes noise, causing an incorrect pulse to be output from the shift register. There is a possibility that the shift register in question is the same as the shift register in the gate line drive circuit. In some cases, an illegal pulse becomes a signal that turns on a transistor. The voltage applied to the TFT driving the EL element changes due to the rust, causing the image of the still image to change. This is because there is a possibility that this will happen. Considering the above, in Figure 28, the high power supply potential (Vdd) This diagram illustrates an example where the rising edge of a signal is gentler than its falling edge. In this embodiment of the display device, when a still image is displayed in the pixel section, the shift A configuration in which the supply of high power potential (Vdd) to the resistor is stopped and restarted as appropriate. Yes. In other words, changes in the potential of the wiring supplying the high power potential (Vdd) appear as noise in the pixels. If the noise affects the area, it directly leads to degradation of the displayed image. Therefore, in this embodiment In a display device, changes in the potential of the wiring (especially an increase in potential) can be perceived as noise in the pixel area. It is important to control the system to prevent intrusion. [Explanation of Symbols]

[0587] 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 17 Wiring 18 Wiring 51 Power line 52 Power line 61 period 62 period 100 pixels 101 Wiring 102 Wiring 102A Wiring 102B Wiring 103 Oxide semiconductor layer 104 Capacity Line 105 Pixel electrodes 106 Thin-film transistors 108 Substrate temperature 111 circuit board 112 Undercoat 113 Gate insulating film 114 Oxide insulating layer 121 Insulating layer 200 circuit boards 201 pixels 202 pixel section 203 Scan line drive circuit 204 Signal Line Drive Circuit 251 period 252 period 261 period 300 circuit boards 302 Gate Insulation Layer 303 Protective insulating layer 310 Thin-Film Transistors 311 Grid gate layer 313 Channel formation region 314a High-resistance source region 314b High-resistance drain region 315a Source electrode layer 315b Drain electrode layer 316 Oxide insulating layer 320 circuit boards 322 Gate Insulation Layer 323 Protective insulating layer 330 Oxide semiconductor film 331 Oxide semiconductor layer 332 Oxide semiconductor layer 340 circuit boards 342 Gate Insulation Layer 343 Protective insulating layer 345 Oxide semiconductor film 346 Oxide semiconductor layer 350 Thin-Film Transistors 351 Grid gate layer 352 Oxide semiconductor layer 355a Source electrode layer 355b Drain electrode layer 356 Oxide Insulating Layer 360 Thin-Film Transistors 361 Grid control layer 362 Oxide semiconductor layer 363 Channel formation region 364a High-resistance source region 364b High-resistance drain region 365a Source electrode layer 365b Drain electrode layer 366 Oxide insulating layer 370 circuit boards 372a Gate Insulation Layer 372b Gate insulating layer 373 Protective insulating layer 380 Thin-Film Transistors 381 Grid Unit Layer 382 Oxide semiconductor layer 385a Source electrode layer 385b Drain electrode layer 386 Oxide insulating layer 390 Thin-Film Transistors 391 Grid gate layer 392 Oxide semiconductor layer 393 Oxide semiconductor film 394 circuit boards 395a Source electrode layer 395b Drain electrode layer 396 Oxide insulating layer 397 Gate Insulation Layer 398 Protective insulating layer 399 Oxide semiconductor layer 400 circuit boards 402 Gate Insulation Layer 407 Insulating layer 410 Thin-film transistors 411 Guard Layer 412 Oxide semiconductor layer 414a wiring layer 414b wiring layer 415a Drain electrode layer 415b Drain electrode...

Claims

1. A first conductive layer having the function of a transistor gate electrode, A first insulating layer having a region located on the first conductive layer, An oxide semiconductor layer having a region located on the first insulating layer and having a channel formation region for the transistor, A second conductive layer having a region in contact with the upper surface of the oxide semiconductor layer, a region in contact with the side surface of the oxide semiconductor layer, and a region in contact with the upper surface of the first insulating layer, and functioning as one of the source electrode and drain electrode of the transistor, A third conductive layer having a region in contact with the upper surface of the oxide semiconductor layer, a region in contact with the side surface of the oxide semiconductor layer, and a region in contact with the upper surface of the first insulating layer, and having the function of the other of the source electrode and drain electrode of the transistor, A second insulating layer having a region in contact with the upper surface of the second conductive layer and a region in contact with the upper surface of the third conductive layer, A fourth conductive layer having a region located on the second insulating layer and functioning as wiring, A fifth conductive layer having a region located on the second insulating layer and functioning as wiring, The fourth conductive layer is electrically connected to the second conductive layer through the first opening of the second insulating layer. The fifth conductive layer is electrically connected to the third conductive layer through the second opening of the second insulating layer. The first opening of the second insulating layer does not overlap with the oxide semiconductor layer. The second opening of the second insulating layer does not overlap with the oxide semiconductor layer. The first conductive layer has at least a region that overlaps with the entire oxide semiconductor layer, The first conductive layer has an overlap with the first opening of the second insulating layer. The first conductive layer described above has a laminated structure, The second conductive layer and the third conductive layer each have a single-layer structure containing titanium. The fourth conductive layer and the fifth conductive layer each have a laminated structure. The first insulating layer has a laminated structure comprising a first film having nitrogen and silicon, and a second film having a region located on the first film and having oxygen and silicon. A display device having a laminated structure in which the second insulating layer comprises a third film having oxygen and silicon, and a fourth film having a region located on the third film and having nitrogen and silicon.

2. A first conductive layer having the function of a transistor gate electrode, A first insulating layer having a region located on the first conductive layer, An oxide semiconductor layer having a region located on the first insulating layer and having a channel formation region for the transistor, A second conductive layer having a region in contact with the upper surface of the oxide semiconductor layer, a region in contact with the side surface of the oxide semiconductor layer, and a region in contact with the upper surface of the first insulating layer, and functioning as one of the source electrode and drain electrode of the transistor, A third conductive layer having a region in contact with the upper surface of the oxide semiconductor layer, a region in contact with the side surface of the oxide semiconductor layer, and a region in contact with the upper surface of the first insulating layer, and having the function of the other of the source electrode and drain electrode of the transistor, A second insulating layer having a region in contact with the upper surface of the second conductive layer and a region in contact with the upper surface of the third conductive layer, A fourth conductive layer having a region located on the second insulating layer and functioning as wiring, A fifth conductive layer having a region located on the second insulating layer and functioning as wiring, The fourth conductive layer is electrically connected to the second conductive layer through the first opening of the second insulating layer. The fifth conductive layer is electrically connected to the third conductive layer through the second opening of the second insulating layer. The first opening of the second insulating layer does not overlap with the oxide semiconductor layer. The second opening of the second insulating layer does not overlap with the oxide semiconductor layer. The first conductive layer has at least a region that overlaps with the entire oxide semiconductor layer, The first conductive layer has an overlap with the first opening of the second insulating layer. The fourth conductive layer has a region that extends in a direction parallel to the channel length direction of the transistor, The fifth conductive layer has a region that extends in a direction parallel to the channel length direction of the transistor, The first conductive layer described above has a laminated structure, The second conductive layer and the third conductive layer each have a single-layer structure containing titanium. The fourth conductive layer and the fifth conductive layer each have a laminated structure. The first insulating layer has a laminated structure comprising a first film having nitrogen and silicon, and a second film having a region located on the first film and having oxygen and silicon. A display device having a laminated structure in which the second insulating layer comprises a third film having oxygen and silicon, and a fourth film having a region located on the third film and having nitrogen and silicon.

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