Circuit devices and oscillators

Abstract

To provide a circuit device, etc., that can reduce wasteful power consumption and implement low power consumption.SOLUTION: A circuit device 20 includes a first phase comparison circuit 30 having a sampling circuit 32 for sampling a feedback signal FBSG based on a reference clock signal RFCK, a first charge pump circuit 40 for outputting the current corresponding to a sampling voltage, a second phase comparison circuit 50 which includes a dead zone detection circuit 52 for detecting whether a phase difference between the reference clock signal RFCK and the feedback clock signal FBCK falls into a dead zone, and outputs a phase difference signal when the phase difference does not fall into the dead zone, a second charge pump circuit 60, and a clock signal generation circuit 70 for generating a clock signal CK having a frequency to be controlled based on the output of the first charge pump circuit 40 or the second charge pump circuit 60. The second charge pump circuit 60 is set to a disable or low power consumption mode during a dead zone period.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a circuit device, an oscillator, and the like.

Background Art

[0002] Conventionally, voltage sampling type PLLs such as sampling PLLs and sub-sampling PLLs have been known. For example, in Non-Patent Document 1, it is disclosed that in a sampling PLL, by tilting the edge of the clock to be sampled by an LSG (Linear Slope Generator), a high-precision fractional PLL can be realized without using a DTC (Digital-to-Time converter).

Prior Art Documents

Non-Patent Documents

[0003]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Such a voltage sampling type PLL has two feedback loops, and thus has a problem of high power consumption.

Means for Solving the Problems

[0005] One aspect of the present disclosure includes a sampling circuit that samples a feedback signal of a clock signal based on a reference clock signal, a first phase comparison circuit that outputs a sampling voltage of the sampling circuit, a first charge pump circuit that outputs a current corresponding to the sampling voltage, a dead zone detection circuit that detects whether the phase difference between the reference clock signal and the feedback clock signal of the clock signal has entered a dead zone, a second phase comparison circuit that outputs a phase difference signal based on a phase comparison between the reference clock signal and the feedback clock signal if the phase difference has not entered the dead zone, a second charge pump circuit that performs charge pump operation according to the phase difference signal, and a clock signal generation circuit that generates the clock signal at a frequency controlled based on the output of the first charge pump circuit or the output of the second charge pump circuit, wherein the second charge pump circuit is set to disabled or low power consumption mode during the dead zone period when the phase difference has entered the dead zone.

[0006] Another aspect of this disclosure relates to an oscillator including the circuit device described above and a resonator for generating the reference clock signal. [Brief explanation of the drawing]

[0007] [Figure 1] An example of the configuration of the circuit device of this embodiment. [Figure 2] A detailed configuration example of the circuit device of this embodiment. [Figure 3] Detailed other configuration examples of the circuit device of this embodiment. [Figure 4] A signal waveform diagram illustrating the operation of the circuit device of this embodiment. [Figure 5] Example configuration of a slope signal generation circuit and a first phase comparison circuit. [Figure 6] Signal waveform diagram illustrating the operation of the slope signal generation circuit and the first phase comparison circuit. [Figure 7] An example configuration of a dead zone detection circuit. [Figure 8]Configuration example of an enable signal generation circuit. [Figure 9] Example of signal waveforms for explaining the operations of a dead zone detection circuit and an enable signal generation circuit. [Figure 10] Configuration example of a pulsar circuit. [Figure 11] Signal waveform diagram for explaining the operation of a pulsar circuit. [Figure 12] Configuration example of a second charge pump circuit. [Figure 13] Explanation diagram of a method for setting two dead zone widths. [Figure 14] Configuration example of the delay circuit of a dead zone detection circuit. [Figure 15] Explanation diagram regarding the return operation of a second charge pump circuit. [Figure 16] Explanation diagram of a method for setting a dead zone using two enable signals. [Figure 17] Explanation diagram of a method for setting a dead zone using two enable signals. [Figure 18] Another configuration example of a dead zone detection circuit. [Figure 19] Another configuration example of an enable signal generation circuit. [Figure 20] Configuration example of a phase interpolation type frequency divider circuit. [Figure 21] Signal waveform diagram for explaining the operation of a phase interpolation type frequency divider circuit. [Figure 22] First configuration example of the oscillator of this embodiment. [Figure 23] Second configuration example of the oscillator of this embodiment.

Mode for Carrying Out the Invention

[0008] Hereinafter, this embodiment will be described. Note that the embodiment described below does not unduly limit the content described in the claims. Also, not all of the configurations described in this embodiment are essential constituent elements.

[0009] 1. Circuit device Fig. 1 shows a configuration example of the circuit device 20 of this embodiment. The circuit device 20 includes a first phase comparison circuit 30, a first charge pump circuit 40, a second phase comparison circuit 50, a second charge pump circuit 60, and a clock signal generation circuit 70. The circuit device 20 can also include a frequency division circuit 80. A PLL (Phase Locked Loop) circuit is realized by the circuit device 20 with this configuration. The circuit device 20 is an integrated circuit device called an IC (Integrated Circuit) for example. For example, the circuit device 20 is an IC manufactured by a semiconductor process and is a semiconductor chip on which circuit elements are formed on a semiconductor substrate.

[0010] The first phase comparison circuit 30 has a sampling circuit 32 that samples the feedback signal FBSG of the clock signal CK based on the reference clock signal RFCK, and outputs the sampling voltage VSA of the sampling circuit 32. For example, the sampling circuit 32 samples the feedback signal FBSG by the reference clock signal RFCK or a signal based on the reference clock signal RFCK. The feedback signal FBSG of the clock signal CK is a feedback signal in the feedback loop of a voltage sampling type PLL. The feedback signal FBSG is, for example, the slope signal SLP in Fig. 2 or the oscillation signal VCOS of the VCO in Fig. 3 described later. Then, the first phase comparison circuit 30 outputs the voltage obtained by sampling the feedback signal FBSG by the sampling circuit 32 as the sampling voltage VSA. The reference clock signal RFCK is a clock signal generated, for example, by oscillating an oscillator as described later.

[0011] The first charge pump circuit 40 outputs a current corresponding to the sampling voltage VSA in the sampling circuit 32. For example, the first charge pump circuit 40 outputs a current that increases as the sampling voltage VSA increases as a charge pump current to the clock signal generation circuit 70. As a result, the clock signal generation circuit 70 outputs a clock signal CK having a frequency corresponding to this charge pump current.

[0012] The second phase comparison circuit 50 outputs a phase difference signal PDS based on a phase comparison between the reference clock signal RFCK and the feedback clock signal FBCK. Specifically, the second phase comparison circuit 50 includes a dead zone detection circuit 52 that detects whether the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK has entered a dead zone. The phase difference can also be called a phase error. The dead zone is a dead zone, for example, the range in which the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK is below a threshold. The dead zone detection circuit 52 performs a dead zone generation process and determines whether the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK has entered a dead zone. The dead zone is generated based on the delay time of a delay circuit provided in the dead zone detection circuit 52. Then, if the phase difference has not entered a dead zone, the second phase comparison circuit 50 outputs a phase difference signal PDS based on a phase comparison between the reference clock signal RFCK and the feedback clock signal FBCK. For example, the second phase comparison circuit 50 outputs an up signal or a down signal as a phase difference signal PDS based on a phase comparison between the reference clock signal RFCK and the feedback clock signal FBCK. For example, the second phase comparison circuit 50 outputs an up signal if the feedback clock signal FBCK is behind the reference clock signal RFCK in phase, and outputs a down signal if the feedback clock signal FBCK is ahead of the reference clock signal RFCK in phase.

[0013] The second charge pump circuit 60 performs charge pump operation in accordance with the phase difference signal PDS from the second phase comparison circuit 50. For example, when an up signal is input as the phase difference signal PDS to the second charge pump circuit 60, it generates an up current as the charge pump current, which flows from the high-potential side power supply to the output node of the second charge pump circuit 60 during the active period of the up signal. Also, when a down signal is input as the phase difference signal PDS to the second charge pump circuit 60, it generates a down current as the charge pump current, which flows from the output node of the second charge pump circuit 60 to the low-potential side power supply during the active period of the down signal.

[0014] The clock signal generation circuit 70 generates a clock signal CK with a frequency controlled based on the output of the first charge pump circuit 40 or the output of the second charge pump circuit 60. For example, the clock signal generation circuit 70 generates a clock signal CK with a frequency controlled based on the charge pump current of the first charge pump circuit 40 or the charge pump current of the second charge pump circuit 60. For example, the circuit device 20 performs a first synchronous operation in a first feedback loop including the first phase comparison circuit 30, the first charge pump circuit 40, and the clock signal generation circuit 70, and a second synchronous operation in a second feedback loop including the second phase comparison circuit 50, the second charge pump circuit 60, and the clock signal generation circuit 70. The first synchronous operation is, for example, an SPLL (Sampling Phase Locked Loop) operation, and the second synchronous operation is, for example, an FLL (Frequency Locked Loop) operation. The SPLL operation may be the sampling PLL operation shown in Figure 2, which will be described later, or the subsampling PLL operation shown in Figure 3. In this embodiment, the operation of voltage sampling type PLLs, such as sampling PLLs and subsampling PLLs, is referred to as SPLL operation. The clock signal generation circuit 70 generates a clock signal CK with a frequency controlled based on the charge pump current of the first charge pump circuit 40 during first synchronous operation, and generates a clock signal CK with a frequency controlled based on the charge pump current of the second charge pump circuit 60 during second synchronous operation.

[0015] The frequency divider circuit 80 divides the clock signal CK and outputs a divided clock signal DVCK. For example, the clock signal generation circuit 70 generates a clock signal CK with a frequency obtained by multiplying the frequency of the reference clock signal RFCK. In this case, the multiplication factor is set by the division ratio of the frequency divider circuit 80. The frequency divider circuit 80 is a decimal-point frequency divider that can perform decimal division, for example, a phase-interpolation type frequency divider can be used as the frequency divider circuit 80. This makes it possible to realize a fractional-N type PLL circuit. The frequency divider circuit 80 may also be an integer frequency divider with an integer division ratio.

[0016] In this embodiment, the second charge pump circuit 60 is set to disabled or low-power mode during the dead zone period when the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK falls into the dead zone. When the second charge pump circuit 60 is set to disabled, its operation stops. For example, the operation of the second charge pump circuit 60 stops so that it does not output charge pump current. When the second charge pump circuit 60 is set to disabled, control may be performed to prevent current from flowing through the current path of the second charge pump circuit 60. For example, current from the current source of the analog circuit constituting the second charge pump circuit 60 may be prevented from flowing through the current path. When the second charge pump circuit 60 is set to low-power mode, the power consumption of the second charge pump circuit 60 is set to a lower power consumption than during normal operation. For example, the low-power mode is set by reducing the current flowing through the current path of the second charge pump circuit 60. For example, control is performed to reduce the current from the current source of the analog circuit constituting the second charge pump circuit 60. By setting the second charge pump circuit 60 to disabled or low-power mode in this way, it is possible to prevent unnecessary power consumption in the second charge pump circuit 60 when the first synchronous operation is being performed in the first feedback loop including the first phase comparison circuit 30, the first charge pump circuit 40, and the clock signal generation circuit 70, thereby achieving low power consumption of the circuit device 20.

[0017] For example, in Figure 1, the second phase comparison circuit 50 outputs an enable signal ENCP for the charge pump to the second charge pump circuit 60. For example, the second phase comparison circuit 50 generates an enable signal ENCP based on the dead zone detection result of the dead zone detection circuit 52 and outputs it to the second charge pump circuit 60. The enable signal ENCP is active during the non-dead zone period when the phase difference is not in the dead zone, and is inactive during the dead zone period when the phase difference is in the dead zone. When the enable signal ENCP is active, the operation of the second charge pump circuit 60 is enabled, and the second charge pump circuit 60 outputs a charge pump current corresponding to the phase difference signal PDS to the clock signal generation circuit 70. On the other hand, when the enable signal ENCP is inactive, the operation of the second charge pump circuit 60 is set to disabled or set to low power consumption mode. This prevents the second charge pump circuit 60 from wasting power during the dead zone period when the enable signal ENCP is inactive.

[0018] Figures 2 and 3 show detailed configuration examples of the circuit device 20 of this embodiment. Note that the circuit device 20 is not limited to the configurations shown in Figures 2 and 3, and various modifications can be made, such as omitting some of these components, adding other components, or replacing some components with other components.

[0019] Figure 2 shows an example configuration of the circuit device 20 when the PLL realized according to this embodiment is a sampling PLL. In Figure 2, the circuit device 20 includes a slope signal generation circuit 22 and a pulser circuit 24 in addition to the configuration in Figure 1. The circuit device 20 may also include a pulse width extension circuit 90 and an output circuit 78.

[0020] The slope signal generation circuit 22 generates a slope signal SLP based on the feedback clock signal FBCK of the clock signal CK. The slope signal generation circuit 22 is a circuit called, for example, an LSG (Linear Slope Generator). The feedback clock signal FBCK is a clock signal obtained by feeding back the clock signal CK. For example, in Figure 2, the clock signal CK generated by the clock signal generation circuit 70 is fed back to the input side via a frequency divider circuit 80, etc., and this becomes the feedback clock signal FBCK. The feedback clock signal FBCK is a square wave clock signal, and the slope signal generation circuit 22 generates a slope signal SLP with a linear slope from this square wave feedback clock signal FBCK. The slope of the slope signal SLP only needs to be approximately linear. For example, the slope signal generation circuit 22 generates a slope signal SLP by tilting the edges of the square wave feedback clock signal FBCK.

[0021] The pulser circuit 24 outputs a pulse signal PLS based on a reference clock signal RFCK. For example, the pulser circuit 24 outputs a pulse signal PLS of a predetermined pulse width that becomes active each time the reference clock signal RFCK becomes active. For example, the pulser circuit 24 has a first delay circuit and a second delay circuit. The pulser circuit 24 outputs a pulse signal PLS that becomes active at a time delayed by a first delay time of the first delay circuit from the time the reference clock signal RFCK becomes active, and remains active for the second delay time of the second delay circuit. The active level is either a high level or a low level, and the inactive level is either a high level or a low level.

[0022] The sampling circuit 32 of the first phase comparison circuit 30 includes a sampling switch circuit SS and a sampling capacitor CS. The sampling switch circuit SS is provided between the output node of the slope signal generation circuit 22 and the sampling node of the sampling voltage VSA, and is turned on when the reference clock signal RFCK is active. One end of the sampling capacitor CS is connected to the sampling node of the sampling voltage VSA. By providing such a sampling switch circuit SS and capacitor CS, the voltage of the slope signal SLP at the timing when the reference clock signal RFCK changes from active to inactive can be sampled as the sampling voltage VSA.

[0023] The first charge pump circuit 40 includes an amplifier circuit AP and a switch circuit SP for the charge pump. The amplifier circuit AP, also called a transconductor, is a circuit that performs voltage-to-current conversion according to, for example, transconductance Gm. For example, the amplifier circuit AP converts the sampling voltage VSA into a current and outputs it. For example, the amplifier circuit AP outputs a current that increases as the sampling voltage VSA increases. The switch circuit SP for the charge pump is turned on during the active period when the pulse signal PLS with pulse width TP from the pulser circuit 24 is active. As a result, the first charge pump circuit 40 outputs a current corresponding to the sampling voltage VSA to the clock signal generation circuit 70 during the active period of the pulse signal PLS.

[0024] The second phase comparison circuit 50 includes a dead zone detection circuit 52 and an enable signal generation circuit 54. The configuration and operation of the dead zone detection circuit 52 are as described above.

[0025] The enable signal generation circuit 54 generates the enable signal ENSP for the pulser circuit 24 and the enable signal ENCP for the second charge pump circuit 60. The enable signal ENSP is the first enable signal, and is used, for example, to enable or disable the operation of the pulser circuit 24. The enable signal ENCP is the second enable signal, and is used, for example, to enable or disable the operation of the second charge pump circuit 60. The enable signal generation circuit 54 generates the enable signal ENSP and the enable signal ENCP based on the dead zone detection result. The enable signal generation circuit 54 may generate the inverted signal of the enable signal ENSP as the enable signal ENCP, or it may generate the enable signal ENSP and the enable signal ENCP separately.

[0026] The clock signal generation circuit 70 includes a loop filter circuit 72, a voltage-controlled oscillator circuit 74, and a buffer circuit 76. The loop filter circuit 72 generates a control voltage that controls the oscillation frequency of the voltage-controlled oscillator circuit 74. For example, the loop filter circuit 72 generates the control voltage by integrating and smoothing the charge pump current from the first charge pump circuit 40 or the charge pump current from the second charge pump circuit 60. The loop filter circuit 72 can be implemented, for example, by an RC low-pass filter composed of a capacitor and a resistor. The voltage-controlled oscillator circuit 74, which is a VCO, generates an oscillation signal whose oscillation frequency is controlled by the control voltage from the loop filter circuit 72. The voltage-controlled oscillator circuit 74 may be implemented by an LC type oscillator circuit using an inductor and a capacitor, or by a loop type oscillator circuit in which multiple inverter circuits are connected in a loop. The buffer circuit 76 buffers the oscillation signal generated by the voltage-controlled oscillator circuit 74 to generate the clock signal CK. For example, when the voltage-controlled oscillator circuit 74 generates a differential oscillation signal, the buffer circuit 76 generates and outputs a square wave clock signal CK based on this differential sinusoidal oscillation signal. The output circuit 78 then buffers the clock signal CK and outputs an output clock signal CKQ to the outside. For example, the output circuit 78 outputs the output clock signal CKQ in a single-ended CMOS signal format. Alternatively, the output circuit 78 may output the output clock signal CKQ in a signal format such as LVDS (Low Voltage Differential Signaling) or PECL (Positive Emitter Coupled Logic).

[0027] In this embodiment, the clock signal generation circuit 70 includes a loop filter circuit 72 that outputs a control voltage for the oscillation frequency based on the output of the first charge pump circuit 40 or the output of the second charge pump circuit 60, and a voltage-controlled oscillator circuit 74 that generates a clock signal CK with an oscillation frequency corresponding to the control voltage. In this configuration, during the first synchronous operation in the first feedback loop including the first phase comparison circuit 30, the first charge pump circuit 40, and the clock signal generation circuit 70, the loop filter circuit 72 outputs a control voltage based on the output of the first charge pump circuit 40, and the voltage-controlled oscillator circuit 74 generates a clock signal CK with an oscillation frequency corresponding to the control voltage. Furthermore, during the second synchronous operation in the second feedback loop including the second phase comparison circuit 50, the second charge pump circuit 60, and the clock signal generation circuit 70, the loop filter circuit 72 outputs a control voltage based on the output of the second charge pump circuit 60, and the voltage-controlled oscillator circuit 74 generates a clock signal CK with an oscillation frequency corresponding to the control voltage. This enables the generation of a clock signal CK through a first synchronous operation in the first feedback loop and the generation of a clock signal CK through a second synchronous operation in the second feedback loop.

[0028] The pulse width expansion circuit 90 expands the pulse width of the divided clock signal DVCK and outputs it as a feedback clock signal FBCK. For example, the pulse width expansion circuit 90 expands the pulse width of the feedback clock signal FBCK so that it changes from active to inactive after the pulse signal PLS changes from active to inactive. In this way, the voltage level of the feedback clock signal FBCK does not change during the active period of the pulse signal PLS, thereby suppressing fluctuations in the sampling voltage VSA caused by changes in the voltage level of the feedback clock signal FBCK. Alternatively, the pulse width expansion circuit 90 may be omitted from the circuit device 20, and the divided clock signal DVCK of the divided circuit 80 may be input as the feedback clock signal FBCK to the slope signal generation circuit 22, etc.

[0029] Figure 3 shows an example of the configuration of the circuit device 20 when the PLL realized in this embodiment is a subsampling PLL. The difference between the configuration in Figure 3 and that in Figure 2 is that in Figure 3, the oscillation signal VCOS from the voltage-controlled oscillation circuit 74 of the clock signal generation circuit 70 is fed back to the first phase comparison circuit 30 as the feedback signal FBSG in Figure 1. Also, in Figure 3, the slope signal generation circuit 22 and pulse width extension circuit 90 in Figure 2 are not provided. In Figure 3, the oscillation signal VCOS of the VCO is input to the first phase comparison circuit 30 via a buffer circuit BUF, but a configuration without the buffer circuit BUF is also possible.

[0030] In the subsampling PLL shown in Figure 3, the sinusoidal oscillation signal VCOS from the voltage-controlled oscillator circuit 74 (VCO) is input to the first phase comparison circuit 30 as a feedback signal FBSG. The sampling circuit 32 of the first phase comparison circuit 30 samples the oscillation signal VCOS based on the reference clock signal RFCK. The slope of the sinusoidal oscillation signal VCOS at, for example, the zero-crossing point performs a function similar to the slope of the slope signal SLP in Figure 2. In this case, the subsampling PLL in Figure 3 samples every M segments of the sinusoidal waveform of the oscillation signal VCOS. For example, by setting the sampling timing of the oscillation signal VCOS using a time-to-digital converter (DCT) with a delta-sigma modulator, a fractional-N type subsampling PLL can be realized.

[0031] A subsampling PLL has the advantage of reducing noise caused by frequency dividers because it does not have a frequency divider in its first feedback loop. On the other hand, the first phase comparison circuit 30 has the disadvantage of being difficult to operate and design using CMOS circuits because it is necessary to perform sampling on an oscillation signal VCOS with a high frequency, such as several GHz. The method of this embodiment can be applied not only to the sampling PLL in Figure 2 but also to the subsampling PLL in Figure 3, but in the following explanation, for the sake of simplicity, we will mainly use the case where the method of this embodiment is applied to a sampling PLL as an example.

[0032] Figure 4 is a signal waveform diagram illustrating the operation of the circuit device 20 in this embodiment. For example, after power-on, the circuit device 20 performs FLL operation, which is a second synchronous operation in the second feedback loop. For example, the second charge pump circuit 60 performs charge pump operation based on the up signal UP and down signal DN output by the second phase comparison circuit 50 based on the phase comparison between the reference clock signal RFCK and the feedback clock signal FBCK. The charge pump current from this charge pump operation is input to the loop filter circuit 72, which generates a control voltage, and the clock signal CK is generated by the oscillation operation of the voltage-controlled oscillator circuit 74 based on this control voltage. This clock signal CK is fed back to the second phase comparison circuit 50 as a feedback clock signal FBCK via the frequency divider circuit 80, etc. As a result, as shown in A1 of Figure 4, FLL operation is performed to bring the frequency of the feedback clock signal FBCK closer to the frequency of the reference clock signal RFCK. The frequency divider circuit 80 is set with a frequency division ratio setting code to set the clock signal CK to a target frequency. For example, if the frequency of the clock signal CK is fck, the frequency of the reference clock signal RFCK is ffr, and the frequency division ratio is DV, then the relationship fck = DV × ffr holds true.

[0033] Specifically, the dead zone detection circuit 52 detects whether the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK has entered the dead zone. During the non-dead zone period when the phase difference has not entered the dead zone, the second charge pump circuit 60 performs charge pump operation, enabling FLL operation in the second feedback loop. Note that in Figures 4A2 and A3, the SPLL operation enable signal ENSP is transiently active because even if the reference clock signal RFCK and the feedback clock signal FBCK have different frequencies, they are judged to be the same frequency if their phases are rotated 360 degrees.

[0034] As a result of this FLL operation, as shown in A4, the frequency of the feedback clock signal FBCK approaches the frequency of the reference clock signal RFCK, and it is detected that the phase difference has entered the dead zone. During this dead zone period when the phase difference is in the dead zone, the enable signal ENSP becomes active. This causes the pulser circuit 24 to output a pulse signal PLS, and the first charge pump circuit 40 outputs a charge pump current corresponding to the sampling voltage VSA of the sampling circuit 32 of the first phase comparison circuit 30 during the active period of the pulse signal PLS. This charge pump current is then input to the loop filter circuit 72, which generates a control voltage, and the oscillation operation of the voltage-controlled oscillator circuit 74 based on this control voltage generates a clock signal CK. As a result, as shown in A5 of Figure 4, phase synchronization by SPLL is performed, which further brings the phases of the reference clock signal RFCK and the feedback clock signal FBCK closer together.

[0035] As shown in Figure 4, the FLL operation by the second feedback loop is performed until the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK enters the dead zone. When it is detected that the phase difference has entered the dead zone, the system switches from the FLL operation by the second feedback loop to the SPLL operation by the first feedback loop. This SPLL operation by the first feedback loop allows for a higher PLL gain compared to the FLL operation by the second feedback loop, thereby reducing the in-band noise of the PLL. In other words, the gain in SPLL operation is set by the slope of the slope signal SLP, the transconductance Gm of the amplifier circuit AP, and the length of the active period of the pulse signal PLS. For example, the gain can be set higher by increasing the slope of the slope signal SLP, increasing the transconductance Gm, or lengthening the active period of the pulse signal PLS. As a result, even if the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK increases, the high PLL gain allows the phase difference to be brought closer in a short time, making it possible to reduce in-band noise compared to FLL operation. Furthermore, by reducing in-band noise, the phase noise of the clock signal CK can be reduced, making it possible to generate a clock signal CK with good noise characteristics.

[0036] As described above, according to this embodiment, a PLL can be realized that performs a first synchronous operation in a first feedback loop including a first phase comparison circuit 30, a first charge pump circuit 40, and a clock signal generation circuit 70, and a second synchronous operation in a second feedback loop including a second phase comparison circuit 50, a second charge pump circuit 60, and a clock signal generation circuit 70.

[0037] In this embodiment, the second charge pump circuit 60 is set to disabled or low-power mode during the dead zone period when the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK falls into the dead zone. That is, in Figure 4, the second charge pump circuit 60 for FLL operation is set to disabled or low-power mode during the dead zone period when SPLL operation is performed. This prevents the second charge pump circuit 60 from wasting power during the dead zone period when charge pump operation by the second charge pump circuit 60 is unnecessary, thereby preventing the circuit device 20 from consuming excessive power. Consequently, while realizing a PLL that enables the first synchronous operation in the first feedback loop and the second synchronous operation in the second feedback loop, it is possible to suppress the consumption of unnecessary power during the first synchronous operation in the first feedback loop and achieve low power consumption of the circuit device 20.

[0038] Furthermore, the circuit device 20 of this embodiment includes a pulser circuit 24 that outputs a pulse signal PLS based on a reference clock signal RFCK, and the first charge pump circuit 40 outputs a current corresponding to the sampling voltage VSA during the active period of the pulse signal PLS. The pulser circuit 24 is set to disabled or low-power mode during the non-dead zone period when the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK is not in the dead zone. That is, in Figure 4, during the non-dead zone period in which FLL operation is performed, the pulser circuit 24 for SPLL operation is set to disabled or low-power mode. For example, when the pulser circuit 24 is set to disabled, the operation of the pulser circuit 24 stops. For example, the operation of the pulser circuit 24 stops so that it does not output a pulse signal PLS. Also, when the pulser circuit 24 is set to disabled, control may be performed to prevent current from flowing through the current path of the pulser circuit 24. For example, current from the current source of the analog circuit constituting the pulser circuit 24 may be prevented from flowing through the current path. Furthermore, when the pulser circuit 24 is set to low power consumption mode, the power consumption of the pulser circuit 24 is set to a lower level than during normal operation. This is achieved by reducing the current flowing through the current path in the pulser circuit 24. For example, control is performed to reduce the current of the current sources of the analog circuits that make up the pulser circuit 24.

[0039] In this way, by setting the pulser circuit 24 to disabled or low-power mode during the non-dead zone period, it is possible to prevent unnecessary power consumption in the pulser circuit 24 when the second synchronous operation is being performed in the second feedback loop, which includes the second phase comparison circuit 50, the second charge pump circuit 60, and the clock signal generation circuit 70, thereby achieving low power consumption of the circuit device 20.

[0040] Specifically, as shown in Figures 2 and 3, the second phase comparison circuit 50 includes an enable signal generation circuit 54 that generates an enable signal ENSP which becomes active during the dead zone period and outputs the enable signal ENSP to the pulser circuit 24. The pulser circuit 24 is set to disabled or low power consumption mode when the enable signal ENSP is inactive. On the other hand, the second charge pump circuit 60 is set to disabled or low power consumption mode when the enable signal ENSP is active. In this way, during the non-dead zone period in Figure 4, the enable signal ENSP becomes inactive, setting the pulser circuit 24 to disabled or low power consumption mode, thus preventing unnecessary power consumption in the pulser circuit 24, which does not need to operate in the second synchronous operation of the second feedback loop. On the other hand, during the dead zone period shown in Figure 4, the enable signal ENSP becomes active, setting the second charge pump circuit 60 to disabled or low power consumption mode. This prevents unnecessary power consumption in the second charge pump circuit 60, which does not need to operate during the first synchronous operation of the first feedback loop.

[0041] In Figures 2 and 3, the enable signal ENCP for the charge pump input to the second charge pump circuit 60 is the inverted signal of the enable signal ENSP input to the pulser circuit 24. Therefore, when the enable signal ENSP is active, the enable signal ENCP input to the second charge pump circuit 60 becomes inactive, thereby setting the second charge pump circuit 60 to disabled or low power consumption mode.

[0042] 2. Slope signal generation circuit, first phase comparison circuit Figure 5 shows an example configuration of the slope signal generation circuit 22 and the first phase comparison circuit 30. As shown in Figure 5, the slope signal generation circuit 22 includes a P-type transistor TA1, a variable resistor RA, and an N-type transistor TA2, which are connected in series between the high-potential-side power supply node and the low-potential-side power supply node. The high-potential-side power supply node is, for example, the VDD node, and the low-potential-side power supply node is the GND node. For example, the source of the P-type transistor TA1 is connected to the VDD node, and the drain is connected to one end of the variable resistor RA. The other end of the variable resistor RA is connected to the output node NQ of the slope signal generation circuit 22 and the drain of the N-type transistor TA2. The source of the N-type transistor is connected to the GND node. Here, the voltage of GND is the ground voltage, and GND can also be called VSS. Furthermore, the voltage of VDD, which is the high-potential-side power supply, can be a different voltage depending on each circuit that makes up the circuit device 20. For example, a regulator in the power supply circuit provided in the circuit device 20 regulates the power supply voltage of VCC from an external source, and this voltage is supplied to each circuit as VDD.

[0043] The gates of the P-type transistor TA1 and the N-type transistor TA2 are controlled based on the feedback clock signal FBCK. For example, in Figure 5, a negative logic feedback clock signal XFBCK, which is the inverted version of the feedback clock signal FBCK, is input to the gates of transistors TA1 and TA2. The sampling circuit 32 also includes a sampling switch circuit SS and a capacitor CS. The sampling switch circuit SS is provided between the output node NQ of the slope signal generation circuit 22 and the sampling node NS of the sampling voltage VSA, and is turned on or off based on the reference clock signal RFCK. For example, in Figure 5, the sampling switch circuit SS is made up of an N-type transistor TA3, and a negative logic reference clock signal XRFCK, which is the inverted version of the reference clock signal RFCK, is input to the gate of this N-type transistor TA3. Therefore, when the reference clock signal RFCK is at a low level (inactive level), the switch circuit SS is turned on, and when the reference clock signal RFCK is at a high level (active level), the switch circuit SS is turned off. The sampling capacitor CS has one end connected to the sampling node NS. The other end of the sampling capacitor CS is connected to a node at a predetermined potential, such as a GND node.

[0044] Figure 6 is a signal waveform diagram illustrating the operation of the slope signal generation circuit 22 and the first phase comparison circuit 30. At timing t1 in Figure 6, when the feedback clock signal FBCK changes from a low level to a high level, the P-type transistor TA1 of the slope signal generation circuit 22 turns on, and current flows from the VDD node through transistor TA1 and variable resistor RA to the output node NQ of the slope signal generation circuit 22. At this time, since the reference clock signal RFCK is at a low level, the switch circuit SS, which is composed of the N-type transistor TA3, turns on, and the current from the output node NQ flows to the sampling capacitor CS, charging it, causing the output voltage VQ of the output node NQ to rise with a predetermined slope. This generates a slope signal SLP whose voltage changes with a predetermined slope. At this time, the slope of the slope signal SLP, which is the slope of the output voltage VQ with respect to the passage of time, can be set by the resistance value of the variable resistor RA and the capacitance of the capacitor CS. For example, if the resistance value of the variable resistor RA is reduced or the capacitance of the capacitor CS is reduced, the slope will increase, and if the resistance value is increased or the capacitance is increased, the slope will decrease. By increasing the slope of the SLP slope signal, the gain of the PLL loop increases, which reduces in-band noise.

[0045] At timing t2 in Figure 6, when the reference clock signal RFCK changes from a low level to a high level, the switch circuit SS, composed of N-type transistor TA3, turns off. The output voltage VQ at timing t2, when the switch circuit SS turns off, is then sampled as the sampling voltage VSA by the sampling node NS. In this case, the greater the delay between timing t1, when the feedback clock signal FBCK becomes high, and timing t2, when the reference clock signal RFCK becomes high, the larger the sampling voltage VSA becomes. Therefore, the sampling voltage VSA is a voltage corresponding to the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK, and the larger the phase difference, the larger the sampling voltage VSA. Note that when the switch circuit SS turns off, the sampling capacitor CS is disconnected from the output node NQ, so the slope of the output voltage VQ becomes larger. During the period when the pulse signal PLS is high, the sampling switch circuit SP in Figure 2 turns on. As a result, the charge pump current generated by the amplifier circuit AP converting the sampling voltage VSA into a voltage-to-current is input to the loop filter circuit 72, generating a control voltage, and the frequency of the clock signal CK is controlled by the voltage-controlled oscillator circuit 74. When the feedback clock signal FBCK goes low at timing t3, the P-type transistor TA1 of the slope signal generation circuit 22 turns off and the N-type transistor TA2 turns on, causing the output voltage VQ to decrease. Also, when the reference clock signal RFCK goes low at timing t4, the switch circuit SS turns on, and the sampling voltage VSA becomes approximately the same potential as the output voltage VQ.

[0046] As described above, the circuit device 20 of this embodiment includes a slope signal generation circuit 22 that generates a slope signal SLP based on a reference clock signal RFCK. The sampling circuit 32 then samples the slope signal SLP based on the reference clock signal RFCK. In this way, the slope signal generation circuit 22 generates a slope signal SLP having a predetermined slope, and by sampling this slope signal SLP based on the reference clock signal RFCK, it becomes possible to output a sampling voltage VSA. This sampling voltage VSA is a voltage corresponding to the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK. Therefore, the first charge pump circuit 40 outputs a current corresponding to the sampling voltage VSA during the active period of the pulse signal PLS, thereby enabling the clock signal generation circuit 70 to output a current corresponding to the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK. This makes it possible to realize a sampling PLL circuit that can reduce in-band noise and generate a clock signal CK with reduced phase noise.

[0047] 3. Dead zone detection circuit Figure 7 shows an example configuration of the dead zone detection circuit 52 shown in Figures 2 and 3, and Figure 8 shows an example configuration of the enable signal generation circuit 54. Figure 9 shows signal waveform diagrams to explain the operation of these circuits.

[0048] As explained in Figure 2, the dead zone detection circuit 52 detects whether the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK falls within the dead zone. The second phase comparison circuit 50 outputs a phase difference signal PDS based on the phase comparison between the reference clock signal RFCK and the feedback clock signal FBCK if the dead zone detection circuit 52 detects that the phase difference is not within the dead zone. In this way, if the phase difference is not within the dead zone, the second synchronization operation in the second feedback loop makes it possible to bring the phase and frequency of the reference clock signal RFCK and the feedback clock signal FBCK closer together. If the phase difference falls within the dead zone, the first synchronization operation in the first feedback loop makes it possible to bring the phases of the reference clock signal RFCK and the feedback clock signal FBCK even closer together. As a result, SPLL operation is performed in the first feedback loop, which has a high gain, making it possible to generate a clock signal CK with reduced phase noise.

[0049] Specifically, the dead zone detection circuit 52 in Figure 7 includes flip-flop circuits FFE1, FFE2, FFE3, and FFE4, AND circuits ANE1, ANE2, and ANE3, and delay circuits 56 and 57, etc. Flip-flop circuit FFE1 receives VDD as input to its D terminal, a reference clock signal RFCK as input to its CK terminal, and outputs signal UPI from its Q terminal. Flip-flop circuit FFE2 receives VDD as input to its D terminal, a feedback clock signal FBCK as input to its CK terminal, and outputs signal DNI from its Q terminal. AND circuit ANE1 outputs the logical AND signal of signals UPI and DNI as a reset signal RES to the reset terminals of flip-flop circuits FFE1 and FFE2.

[0050] Delay circuit 56 outputs the signal RFCKDL, which is a delayed version of the reference clock signal RFCK, and delay circuit 57 outputs the signal FBCKDL, which is a delayed version of the feedback clock signal FBCK. Flip-flop circuit FFE3 receives the signal UPI at terminal D, the signal RFCKDL at terminal CK, and outputs the signal FFUP from terminal Q. Flip-flop circuit FFE4 receives the signal DNI at terminal D, the signal FBCKDL at terminal CK, and outputs the signal FFDN from terminal Q. AND circuit ANE2 outputs the signal obtained by the logical AND of the delayed signal UPI and the signal FFUP as the up signal UP. AND circuit ANE3 outputs the signal obtained by the logical AND of the delayed signal DNI and the signal FFDN as the down signal DN.

[0051] As shown in Figure 8, the enable signal generation circuit 54 includes a flip-flop circuit FFE7, a NOR circuit NOE1, and inverter circuits IVE1 and IVE2. Signals FFUP and FFDN are input to the NOR circuit NOE1. The output signal of the NOR circuit NOE1 is input to the D terminal of the flip-flop circuit FFE7, and the signal obtained by inverting the reference clock signal RFCK by the inverter circuit IVE1 is input to the CK terminal. The enable signal ENSP is output from the Q terminal of the flip-flop circuit FFE7. The signal obtained by inverting the enable signal ENSP by the inverter circuit IVE2 is output as the enable signal ENCP.

[0052] Next, we will explain the operation of the up side using Figure 9. The operation of the down side is the same as the up side, so we will omit a detailed explanation.

[0053] When the reference clock signal RFCK changes from a low level to a high level, VDD is input to the D terminal, and the signal UPI at the Q terminal of the flip-flop circuit FFE1, which has the reference clock signal RFCK input to the CK terminal, becomes high level. The delay circuit 56 outputs a signal RFCKDL, which is the reference clock signal RFCK delayed by a delay time TD. At the moment when the signal RFCKDL changes from a low level to a high level, a high-level signal UPI is input to the D terminal, and the signal FFUP at the Q terminal of the flip-flop circuit FFE3, which has the signal RFCKDL input to the CK terminal, changes from a low level to a high level.

[0054] Subsequently, when the feedback clock signal FBCK changes from a low level to a high level, VDD is input to the D terminal, and the signal DNI at the Q terminal of the flip-flop circuit FFE2, which receives the feedback clock signal FBCK at its CK terminal, becomes high level. As a result, the reset signal RES output by the AND circuit ANE2, which receives the high-level signal UPI and the high-level signal DNI, becomes high level, and the flip-flop circuit FFE1 is reset, causing the signal UPI to change from a high level to a low level. In this way, a signal UPI with a pulse width of PD1 is generated. The length of this pulse width PD1 corresponds to the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK. Then, the logical AND signal of the delayed signal UPI and the signal FFUP is output as an up signal UP with a pulse width of PD1.

[0055] Then, due to the second synchronization operation in the second feedback loop, as the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK decreases, the pulse width PD2 of the signal UPI also decreases, as shown in Figure 9. For example, in Figure 9, the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK is smaller than the delay time TD in the delay circuit 56. That is, the pulse width PD2 of the signal UPI corresponding to the phase difference is smaller than the delay time TD. In this case, the signal of the logical AND of the delayed signal UPI and the signal FFUP in the AND circuit ANE2 becomes low level, and the pulse of the up signal UP is not output, as shown in C1 in Figure 9. That is, it is detected that the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK has entered the dead zone, and the pulse of the up signal UP is not output.

[0056] Furthermore, at C1 in Figure 9, since both signals FFUP and FFDN are at a low level, when the reference clock signal RFCK changes from a high level to a low level, the enable signal ENSP output from the Q terminal of the flip-flop circuit FFE7 in Figure 8 changes from a low level to a high level, as shown at C2. This enables the SPLL operation, which is the first synchronous operation in the first feedback loop including the first phase comparison circuit 30, the first charge pump circuit 40, and the clock signal generation circuit 70. Also, as shown at C3, the enable signal ENCP changes from a high level to a low level. This sets the operation of the second charge pump circuit 60 to disabled or low power mode.

[0057] As shown in Figure 7, in the dead zone detection circuit 52, if the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK is greater than the delay time TD in the delay circuits 56 and 57, it is detected that the circuit is not in the dead zone, and pulses of the up signal UP and down signal DN are output. This enables the FLL operation, which is the second synchronous operation in the second feedback loop including the second phase comparison circuit 50, the second charge pump circuit 60, and the clock signal generation circuit 70.

[0058] Then, due to this FLL operation, the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK becomes smaller than the delay time TD in the delay circuits 56 and 57. When it is detected that the phase difference has entered the dead zone, the pulse of the up signal UP is not output, as shown in C1 of Figure 9. As a result, the FLL operation in the second feedback loop is stopped. Also, as shown in C2, the enable signal ENSP becomes high level, and the SPLL operation in the first feedback loop begins. As a result, the SPLL operation, which has a high loop gain, performs phase synchronization, bringing the phases of the reference clock signal RFCK and the feedback clock signal FBCK even closer together, and a clock signal CK with reduced phase noise is generated.

[0059] 4. Pulsar Circuit Figure 10 shows an example configuration of the pulser circuit 24, and Figure 11 shows a signal waveform diagram illustrating the operation of the pulser circuit 24.

[0060] The pulser circuit 24 in Figure 10 includes delay circuits 25 and 26, inverter circuits IVB1 and IVB2, and AND circuits ANB1 and ANB2. The signal obtained by inverting the reference clock signal RFCK by inverter circuit IVB1 is input to delay circuit 25. The signal delayed by delay circuit 25 by a delay time td1 is then input to delay circuit 26 and inverter circuit IVB2. The signal delayed by delay circuit 26 by a delay time td2, along with the output signal of inverter circuit IVB2, is input to AND circuit ANB1. The output signal of AND circuit ANB1 and the enable signal ENSP are then input to AND circuit ANB2, which outputs the pulse signal PLS.

[0061] In this way, as shown in Figure 11, after the reference clock signal RFCK goes from a low level to a high level, a pulse signal PLS is generated that goes from a low level to a high level after a delay time td1 has elapsed, and then goes from a high level to a low level after a delay time td2 has elapsed. The signal delay times td1 and td2 in the delay circuits 25 and 26 are adjustable. By adjusting the delay times td1 and td2 in this way, it becomes possible to adjust the timing at which the pulse signal PLS goes high after the reference clock signal RFCK goes high, and the pulse width of the pulse signal PLS.

[0062] In Figure 10, the output signal of AND circuit ANB1 is input to one input terminal of AND circuit ANB2, and the enable signal ENSP is input to the other terminal of AND circuit ANB2. As a result, when the enable signal ENSP is at an active level (high level), a pulse signal PLS is output. Therefore, during the dead zone period in Figure 4, when the enable signal ENSP is at a high level, the pulse signal PLS is output from the pulser circuit 24. This enables SPLL operation in the first feedback loop, which includes the first phase comparison circuit 30, the first charge pump circuit 40, and the clock signal generation circuit 70. On the other hand, when the enable signal ENSP is at an inactive level (low level), the pulse signal PLS output by AND circuit ANB2 is fixed at a low level. Therefore, during the non-dead zone period in Figure 4, when the enable signal ENSP is at a low level, the pulse signal PLS from the pulser circuit 24 is not output, and SPLL operation in the first feedback loop is not performed.

[0063] In Figure 10, for example, the enable signal ENSP is also input to delay circuits 25 and 26. When the enable signal ENSP is at a high level, delay circuits 25 and 26 perform their normal signal delay operation. This enables the operation of the pulser circuit 24. On the other hand, when the enable signal ENSP is at a low level, the operation of delay circuits 25 and 26 is disabled, and the operation of the pulser circuit 24 is also disabled.

[0064] For example, delay circuits 25 and 26 have a current source and a capacitor with a variable capacity that is charged by the bias current from the current source. The delay amount, the delay times td1 and td2 shown in Figure 11, is set by this bias current and the capacitance of the capacitor. For example, the delay times td1 and td2 can be controlled by controlling the capacitance of the capacitor. For example, when the enable signal ENSP is at a low level, the bias current from this current source is prevented from flowing into the current path. This disables the operation of delay circuits 25 and 26, and also disables the operation of pulser circuit 24. Furthermore, by preventing the bias current from flowing into the current path, a low-power mode for delay circuits 25 and 26 can be realized, and pulser circuit 24 can be set to a low-power mode during the non-dead zone period. In this case, instead of completely blocking the bias current from flowing, the low-power mode may be achieved by reducing the bias current flowing to the current source.

[0065] 5. Second charge pump circuit Figure 12 shows an example configuration of the second charge pump circuit 60. As shown in Figure 12, the second charge pump circuit 60 includes a reference current generation circuit 62 and a current output circuit 64. The reference current generation circuit 62 generates a reference current IRF based on a reference voltage VBGR. The reference voltage VBGR is, for example, a bandgap reference voltage. The current output circuit 64 outputs a charge pump current ICP based on the mirror current of the reference current IRF, based on an up signal UP or a down signal DN from the second phase comparison circuit 50. For example, a charge pump current ICP based on the current obtained by mirroring the reference current IRF with a current mirror circuit is output from the current output circuit 64. In this way, the reference current generation circuit 62 generates a reference current IRF based on the reference voltage VBGR, which enables the generation of a reference current IRF that is maintained constant with respect to changes in power supply voltage, temperature, etc. Then, by outputting the charge pump current ICP based on the mirror current of such a reference current IRF based on an up signal UP or a down signal DN, a charge pump current ICP that is maintained constant with respect to changes in power supply voltage, temperature, etc. can be output to the clock signal generation circuit 70. This enables proper frequency control of the clock signal CK based on the charge pump current ICP.

[0066] In this embodiment, the reference current IRF and its mirror current are turned off during the dead zone period. For example, in Figure 4, when the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK enters the dead zone and the system switches from FLL operation to SPLL operation, the reference current IRF and its mirror current in the second charge pump circuit 60 are turned off. This prevents the reference current IRF and its mirror current from flowing unnecessarily and consuming power in the second charge pump circuit 60, which does not need to operate during the dead zone period. This makes it possible to reduce the power consumption of the circuit device 20.

[0067] Specifically, in Figure 12, the reference current generation circuit 62 includes an operational amplifier OPB2, a P-type transistor TB7 and a resistor RB connected in series between the VDD node and the GND node, and a P-type transistor TB5 and an N-type transistor TB6 connected in series between the VDD node and the GND node. The operational amplifier OPB2 receives the reference voltage VBGR as input to its non-inverting input terminal, and its inverting input terminal is connected to the connection node of transistor TB7 and resistor RB. The output signal of the operational amplifier OPB2 is then input to the gates of transistors TB7, TB5, and TB1. The drain of transistor TB5 is connected to the drain and gate of transistor TB6. With this configuration, the reference current generation circuit 62 can generate a reference current IRF based on the reference voltage VBGR.

[0068] The current output circuit 64 includes a P-type transistor TB1, a first switch SC1, a second switch SC2, and an N-type transistor TB2.

[0069] The P-type transistor TB1 is located between the VDD node, which is the high-potential power supply node, and the first node NC1, and an up current IUP flows through it as the charge pump current ICP. For example, the up current IUP that flows through transistor TB1 is generated by mirroring the reference current IRF using the current mirror circuit of transistors TB5 and TB1. The first switch SC1 is located between the first node NC1 and the output node NCQ of the current output circuit 64, and turns on when the up signal UP is active. The up signal UP is input to the second charge pump circuit 60 as a phase difference signal PDS from the preceding second phase comparison circuit 50.

[0070] The N-type transistor TB2 is located between the second node NC2 and the GND node, which is the low-potential power supply node, and a down current IDN flows through it as the charge pump current ICP. For example, the down current IDN that flows through transistor TB2 is generated by mirroring the reference current IRF through the current mirror circuit of transistors TB6 and TB2. The second switch SC2 is located between the output node NCQ and the second node NC2 and turns on when the down signal DN is active. The down signal DN is input to the second charge pump circuit 60 as a phase difference signal PDS from the preceding second phase comparison circuit 50.

[0071] In this way, when the up signal UP from the second phase comparison circuit 50 becomes active, the first switch SC1 turns on, allowing the up current IUP to flow as the charge pump current ICP based on the Miller current of the reference current IRF. Also, when the down signal DN from the second phase comparison circuit 50 becomes active, the second switch SC2 turns on, allowing the down current IDN to flow as the charge pump current ICP based on the Miller current of the reference current IRF. As a result, the charge pump current ICP corresponding to the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK is output to the clock signal generation circuit 70, enabling frequency control of the clock signal CK according to the phase difference.

[0072] As shown in Figure 12, the current output circuit 64 further includes a third switch SC3, a fourth switch SC4, and an operational amplifier OPB1.

[0073] The third switch SC3 is located between the first node NC1 and the mirror node NCM of the output node NCQ, and turns on when the up signal UP is inactive. In other words, the third switch SC3 turns on when the signal XUP, which is the negative logic signal of the up signal UP, is active. The fourth switch SC4 is located between the mirror node NCM and the second node NC2, and turns on when the down signal DN is inactive. In other words, the fourth switch SC4 turns on when the signal XDN, which is the negative logic signal of the down signal DN, is active. The operational amplifier OPB1 is a voltage follower operational amplifier with the output node NCQ connected to its input terminal and the mirror node NCM connected to its output terminal. For example, the operational amplifier OPB1 has a voltage follower connection with the inverting input terminal and output terminal connected, and the output node NCQ is connected to its non-inverting input terminal.

[0074] In this way, a third switch SC3 and a fourth switch SC4, which act as mirror circuits of the first switch SC1 and the second switch SC2, are provided between the first node NC1 and the second node NC2. Then, the operational amplifier OPB1, connected as a voltage follower, can set the voltage of the mirror node NCM between the third switch SC3 and the fourth switch SC4 to the same voltage as the output node NCQ between the first switch SC1 and the second switch SC2, enabling bootstrap operation. Consequently, when the up signal UP becomes active, changing from an on-off state where the first switch SC1 is on and the second switch SC2 is off, to an off-off state where both the first switch SC1 and the second switch SC2 are off, the third switch SC3 and the fourth switch SC4 turn on, thereby maintaining the voltage of the mirror node NCM at the voltage of the output node NCQ. This prevents a situation where, during the above-mentioned off-off state, the voltage at the first node NC1 becomes VDD and the voltage at the second node NC2 becomes GND, and allows the appropriate up current IUP or down current IDN to flow when the first switch SC1 or the second switch SC2 is turned on.

[0075] Similarly, when the down signal DN becomes active, changing from an off-on state where the first switch SC1 is off and the second switch SC2 is on, to an off-off state where both the first switch SC1 and the second switch SC2 are off, the third switch SC3 and the fourth switch SC4 turn on, thereby maintaining the voltage of the mirror node NCM at the voltage of the output node NCQ. This prevents a situation where, in the above off-off state, the voltage of the first node NC1 becomes VDD and the voltage of the second node NC2 becomes GND, and allows the appropriate up current IUP or down current IDN to flow when the first switch SC1 or the second switch SC2 is turned on next.

[0076] Figure 12 also shows that a P-type transistor TB3 is provided, with the drain connected to the gates of transistors TB1 and TB5, its source connected to the VDD node, and the enable signal ENCP input to its gate. Furthermore, an N-type transistor TB4 is provided, with the drain connected to the gates of transistors TB2 and TB6, its source connected to the GND node, and the negative logic enable signal XENCP input to its gate. The enable signal ENCP is also input to operational amplifiers OPB1 and OPB2. Here, the enable signal ENSP is, for example, a signal obtained by inverting the enable signal ENSP using an inverter.

[0077] In this way, for example, when the enable signal ENSP becomes high and the enable signal ENCP becomes low during the dead zone period, the P-type transistor TB3, which has the enable signal ENCP input to its gate, and the N-type transistor TB4, which has the negative logic enable signal XENCP input to its gate, turn on. As a result, the gates of the P-type transistors TB1 and TB5 are set to VDD, and the gates of the N-type transistors TB2 and TB6 are set to GND, turning off the reference current IRF and its mirror current, and stopping their flow. The up current IUP and down current IDN, which are based on the mirror current, also turn off and stop flowing. Furthermore, when the enable signal ENSP becomes high and the enable signal ENCP becomes low, the operation of the operational amplifiers OPB1 and OPB2 is disabled. In this way, when the reference current IRF and its mirror current are turned off and the operation of the operational amplifiers OPB1 and OPB2 is disabled, the operation of the second charge pump circuit 60 is disabled. Furthermore, by eliminating the flow of the reference current IRF and Miller current, and disabling the operation of operational amplifiers OPB1 and OPB2, unnecessary current is eliminated, enabling a low-power mode. Note that instead of completely turning off the reference current IRF and Miller current, the low-power mode can also be achieved by reducing the current.

[0078] As shown in Figure 12, when the phase difference is detected to have entered the dead zone and the system transitions from FLL operation to SPLL operation, the reference current IRF and its Miller current in the second charge pump circuit 60 are turned off, allowing the second charge pump circuit 60 to be set to disabled or low-power mode. Therefore, during SPLL operation in the dead zone period, current does not flow to the unnecessary second charge pump circuit 60, preventing unnecessary power consumption and enabling low power consumption of the circuit device 20.

[0079] 6. Hysteresis of dead zone width In this embodiment, hysteresis may be introduced into the dead zone width. For example, as shown in Figure 13, when it is detected that the phase difference has entered the dead zone and the enable signal ENSP becomes high level, the dead zone width is changed from the first dead zone width DW1 to the second dead zone width DW2, which is wider than DW1. Specifically, the dead zone detection circuit 52 sets the dead zone to the second dead zone width DW2, which is wider than the first dead zone width DW1, after detecting that the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK has entered the dead zone of the first dead zone width DW1. In this way, when it is detected that the phase difference has entered the dead zone of the first dead zone width DW1, the dead zone width is changed to the second dead zone width DW2, which is wider than DW1. Therefore, even if the phase difference increases due to noise or the like after entering the dead zone, it is possible to prevent it from being mistakenly judged as not being in the dead zone. In other words, the phase difference enters the dead zone, causing a switch from FLL operation to SPLL operation, and then the phase difference increases, preventing it from entering the dead zone again and switching back from SPLL operation to FLL operation. This prevents frequent switching between FLL and SPLL operation.

[0080] For example, the dead zone width is set by the delay time TD of the delay circuits 56 and 57, as explained in Figures 7 and 9. When the delay time TD is small, the dead zone width becomes narrow, and when the delay time TD is large, the dead zone width becomes wide. Therefore, the dead zone detection circuit 52 sets the delay time TD of the delay circuits 56 and 57 to, for example, the delay time TD1 corresponding to the first dead zone width DW1, and detects whether or not the phase difference has entered the dead zone. After the dead zone detection circuit 52 detects that the phase difference has entered the dead zone of the first dead zone width DW1 corresponding to the delay time TD1, it sets the delay time TD of the delay circuits 56 and 57 to a delay time TD2 that is larger than the delay time TD1. As a result, the dead zone is set to a second dead zone width DW2, which is wider than the first dead zone width DW1. Therefore, even if the phase difference increases due to noise, etc., after it has been detected that the dead zone has entered, it is possible to prevent it from being mistakenly judged as not being in the dead zone because the dead zone is set to the wider second dead zone width DW2. Therefore, it is possible to prevent situations where FLL operation and SPLL operation switch frequently.

[0081] For example, Figure 14 shows an example configuration of delay circuits 56 and 57. In Figure 14, one end of capacitors CC1 and CC2 is connected to node NC, which connects the first-stage inverter circuit, composed of a current source ISC and transistors TC1 and TC2, to the second-stage inverter circuit, composed of transistors TC3 and TC4. The other end of capacitor CC1 is connected to the GND node, the other end of capacitor CC2 is connected to switch SC, and the other end of switch SC is connected to the GND node.

[0082] Then, when setting the delay time TD to TD1 and the dead zone to the first dead zone width DW1, switch SC is turned off. This sets the delay time TD of the delay circuits 56 and 57 to the delay time TD1 determined by the current of the current source ISC and the capacitance of capacitor CC1.

[0083] On the other hand, when setting the dead zone to the second dead zone width DW2, switch SC is turned on. This sets the delay time TD of delay circuits 56 and 57 to the delay time TD2, which is determined by the current of the current source ISC and the capacitances of capacitors CC1 and CC2. As a result, the capacitance at the connected node NC increases, making the delay time TD2 larger than the delay time TD1. Therefore, it becomes possible to set the second dead zone width DW2, which is larger than the first dead zone width DW1, and to introduce hysteresis into the dead zone width.

[0084] 7. Recovery time of the second charge pump circuit In Figure 15, the enable signal ENCP becomes high, enabling the second charge pump circuit 60, which then outputs a charge pump current ICP due to the up signal UP, thus performing FLL operation. Subsequently, the enable signal ENSP becomes high and the enable signal ENCP becomes low, disabling the operation of the second charge pump circuit 60. Disabling the operation of the second charge pump circuit 60 in this way also turns off the bias current IBS flowing through it. Then, the enable signal ENSP becomes low and the enable signal ENCP becomes high, enabling the operation of the second charge pump circuit 60 from disabled. In this case, since the second charge pump circuit 60 is an analog circuit, the recovery time TRC until the bias current IBS rises and it returns to the proper operating state that outputs a stable charge pump current ICP is long. A long recovery time TRC for the second charge pump circuit 60 leads to the problem that the time until proper FLL operation starts becomes long.

[0085] To prevent such problems from occurring, instead of providing only one dead zone DZ as shown in Figure 16, a method is adopted to provide two dead zones DZ1 and DZ2 as shown in Figure 17. In other words, a method of having two dead zones is adopted. Specifically, as shown in Figure 8, the enable signal ENCP of the second charge pump circuit 60 is not simply an inverted signal of the enable signal ENSP, but rather the enable signal ENCP and the enable signal ENSP are made to be signals that change at different timings.

[0086] Specifically, the circuit device 20 includes a pulser circuit 24 that outputs a pulse signal PLS based on a reference clock signal RFCK, and the second phase comparison circuit 50 includes an enable signal generation circuit 54. The enable signal generation circuit 54 generates an enable signal ENSP that becomes active during the dead zone period and outputs it to the pulser circuit 24. In this case, the enable signal ENSP becomes the first enable signal. The enable signal generation circuit 54 also generates an enable signal ENCP that becomes active during the non-dead zone period when the phase difference is not in the dead zone and outputs it to the second charge pump circuit 60. In this case, the enable signal ENCP becomes the second enable signal.

[0087] As shown in Figure 17, when switching from the non-dead zone period to the dead zone period, the first enable signal, enable signal ENSP, changes from inactive to active, and then the second enable signal, enable signal ENCP, changes from active to inactive. In other words, the enable signal generation circuit 54 generates enable signals ENSP and ENCP such that after the enable signal ENSP changes from a low level to a high level, the enable signal ENCP changes from a high level to a low level.

[0088] On the other hand, when switching from a dead zone period to a non-dead zone period, the second enable signal, enable signal ENCP, changes from inactive to active, and then the first enable signal, enable signal ENSP, changes from active to inactive. That is, the enable signal generation circuit 54 generates enable signals ENSP and ENCP such that after the enable signal ENCP changes from a low level to a high level, the enable signal ENSP changes from a high level to a low level. For example, as shown in Figure 17, when the enable signal ENCP changes from a low level to a high level with a delay time td2, the enable signal ENSP changes from a high level to a low level with a delay time td1, which is later than the delay time td2. This sets the dead zone DZ1 by the enable signal ENSP and the dead zone DZ2 by the enable signal ENCP.

[0089] In this way, as shown in Figure 15, when the operation of the second charge pump circuit 60 is disabled and then re-enabled, as shown in Figure 17, the enable signal ENCP changes from a low level to a high level before the enable signal ENSP changes from a high level to a low level. As a result, the enable signal ENCP changes to the active level (high level) at an earlier timing, making it possible to re-enable and re-enable the operation of the second charge pump circuit 60 at an earlier timing. Therefore, even if the recovery time TRC until the second charge pump circuit 60 outputs the appropriate charge pump current is long, the operation of the second charge pump circuit 60 can be re-enabled at an earlier timing, and the FLL operation can be started.

[0090] Figures 18 and 19 show examples of the configurations of the dead zone detection circuit 52 and the enable signal generation circuit 54 when the method shown in Figure 17 is adopted. In the dead zone detection circuit 52 of Figure 18, in addition to the configuration of Figure 7, delay circuits 58 and 59 and flip-flop circuits FFE5 and FFE6 are provided.

[0091] Delay circuit 56 outputs the signal RFCKDL, which is the reference clock signal RFCK delayed by a delay time td1. Delay circuit 58 outputs the signal RFCKDL2, which is the reference clock signal RFCK delayed by a delay time td2. Delay circuit 57 outputs the signal FBCKDL, which is the feedback clock signal FBCK delayed by a delay time td1. Delay circuit 59 outputs the signal RFCKDL2, which is the feedback clock signal FBCK delayed by a delay time td2. As shown in Figure 17, the relationship td1 > td2 holds for delay times td1 and td2.

[0092] Furthermore, the flip-flop circuit FFE5 receives the signal UPI at terminal D, the signal RFCKDL2 from delay circuit 58 at terminal CK, and outputs the signal FFUP2 at terminal Q. The flip-flop circuit FFE6 receives the signal DNI at terminal D, the signal FBCKDL2 from delay circuit 59 at terminal CK, and outputs the signal FFDN2 at terminal Q.

[0093] As shown in Figure 19, the enable signal generation circuit 54 includes, in addition to the flip-flop circuit FFE7, NOR circuit NOE1, and inverter circuit IVE1 shown in Figure 8, a flip-flop circuit FFE8, a NOR circuit NOE2, and inverter circuits IVE3 and IVE4. The signals FFUP2 and FFDN2 from the flip-flop circuits FFE5 and FFE6 shown in Figure 18 are input to the NOR circuit NOE2. The output signal of the NOR circuit NOE2 is input to the D terminal of the flip-flop circuit FFE8, and the signal obtained by inverting the reference clock signal RFCK by the inverter circuit IVE3 is input to the CK terminal. The signal obtained by inverting the signal from the Q terminal of the flip-flop circuit FFE8 by the inverter circuit IVE4 is output as the enable signal ENCP.

[0094] In this way, the enable signal ENCP of the second charge pump circuit 60 can be generated not as a simple inverted signal of the enable signal ENSP, but as a signal that changes at a timing separate from the enable signal ENSP. That is, as shown in Figure 17, when switching from a non-dead zone period to a dead zone period, the enable signal ENSP goes from a low level to a high level, and then the enable signal ENCP goes from a high level to a low level. On the other hand, when switching from a dead zone period to a non-dead zone period, the enable signal ENCP goes from a low level to a high level, and then the enable signal ENSP goes from a high level to a low level. As a result, the second charge pump circuit 60, which has a long recovery time, can be enabled at an earlier timing and transition to proper FLL operation.

[0095] 8. Frequency divider circuit Figure 20 shows an example configuration of the frequency divider circuit 80, and Figure 21 shows a signal waveform diagram illustrating the operation of the frequency divider circuit 80. Figure 20 is an example configuration of a phase interpolation type frequency divider circuit 80. The frequency divider circuit 80 includes a multiphase clock signal generation circuit 82, a multiplexer 86, and a phase interpolation circuit 88. The multiphase clock signal generation circuit 82 includes frequency dividers 83 and 84 and five flip-flop circuits FF.

[0096] The frequency divider 83 is a frequency divider circuit that divides the frequency by two. Specifically, the frequency divider 83 receives a clock signal CK and a clock signal XCK which is the inverted clock signal CK, and outputs signals I, Q, IB, and QB which are obtained by dividing these signals by two. If the period of the clock signal CK is TVCO, then as shown in Figure 21, the period of the divided signals I, Q, IB, and QB is 2 × TVCO. That is, the frequencies of signals I, Q, IB, and QB are half the frequency of the clock signal CK. Also, with respect to signal I, signals Q, IB, and QB are delayed by 90 degrees, 180 degrees, and 270 degrees in phase, respectively. Thus, signals I, Q, IB, and QB are signals that are shifted in phase by 90 degrees each.

[0097] The frequency divider 84 is a frequency divider circuit called a feedback divider (FDIV). Specifically, the frequency divider 84 divides the signal QB by a set integer division ratio N and outputs the signal FDIVCLK. Then, by inputting the signal FDIVCLK to the CK terminal of the flip-flop circuit FF, to which signals I, Q, IB, and QB are input at terminal D, and sampling, the divided clock signals P0, P90, P180, and P270 are output from the Q terminal of the flip-flop circuit FF, as shown in Figure 21. Also, by inputting the signal FDIVCLK to the CK terminal of the flip-flop circuit FF, to which the divided clock signal P0 is input at terminal D, and sampling, the divided clock signal P360 is output from the Q terminal of the flip-flop circuit FF.

[0098] As shown in Figure 21, the divided clock signals P0, P90, P180, P270, and P360 are obtained by dividing signals I, Q, IB, QB, and I by an integer division ratio N using the frequency divider 84. For example, if the period of signals I, Q, IB, QB, and I is 2 × TVCO, then the period of the divided clock signals P0, P90, P180, P270, and P360 will be N × 2 × TVCO. Furthermore, the divided clock signals P0, P90, P180, P270, and P360 are signals whose signal levels change at edges corresponding to the edges of signals I, Q, IB, QB, and I. The phase difference between P0 and P90 corresponds to the phase difference between I and Q, and the phase difference between P90 and P180 corresponds to the phase difference between Q and IB. The phase difference between P180 and P270 corresponds to the phase difference between IB and QB, and the phase difference between P270 and P360 corresponds to the phase difference between QB and I.

[0099] In this way, the multiphase clock signal generation circuit 82 outputs multiple divided clock signals P0, P90, P180, P270, and P360, which are obtained by dividing the clock signals CK and XCK by an integer division ratio of N × 2 and have different phases.

[0100] For example, the circuit device 20 of this embodiment includes a control circuit (not shown), which includes a delta-sigma modulator that performs delta-sigma modulation based on a frequency division ratio setting code, and an integrator that integrates the output of the delta-sigma modulator. The delta-sigma modulator performs delta-sigma modulation based on the fractional part of the frequency division ratio in the frequency division ratio setting code, and the integrator performs integration processing of the output value of the delta-sigma modulator. The control circuit then outputs an integer frequency division control code that sets an integer frequency division ratio N to the frequency divider 84. The control circuit also outputs an interpolation control code based on the integrated value of the integrator to the phase interpolation circuit 88 and the multiplexer 86. This control circuit corresponds, for example, to the control circuits 160 and 260 in Figures 22 and 23 described later, and the delta-sigma modulator and integrator correspond to the delta-sigma modulators 162 and 262 and the integrators 164 and 264 in Figures 22 and 23.

[0101] The multiplexer 86 selects the i-th division-divide clock signal PCK1 and the i+1th division-divide clock signal PCK2 from among the division-divide clock signals P0, P90, P180, P270, and P360, based on the higher bits of the interpolation control code M[4:0] from the control circuit, for example, M[4:3]. For example, if it is determined that the region is in the first quadrant (0-90 degrees) based on the higher bits of the interpolation control code M[4:3], the division-divide clock signals P0 and P90 are selected as PCK1 and PCK2, respectively. If it is determined that the region is in the second quadrant (90-180 degrees), P90 and P180 are selected as PCK1 and PCK2. Furthermore, based on the upper bits of the interpolation control code, M[4:3], if it is determined to be in the third quadrant (180-270 degrees), P180 and P270 are selected as PCK1 and PCK2, respectively. If it is determined to be in the fourth quadrant (270-360 degrees), P270 and P360 are selected as PCK1 and PCK2, respectively.

[0102] Then, the phase interpolation circuit 88 outputs, as the divided clock signal DVCK, an interpolation clock signal selected based on, for example, M[2:0] which is the lower bits of the interpolation control code M[4:0] from among a plurality of interpolation clock signals generated by phase interpolation based on the i-th divided clock signal PCK1 and the (i + 1)-th divided clock signal PCK2. Here, i is an integer greater than or equal to 1. Also, PCK1 and PCK2 are included in the interpolation clock signals to be selected. For example, it is determined to be in the first quadrant based on M[4:3] which is the upper bits of the correction control code, and it is assumed that the divided clock signals P0 and P90 are selected as PCK1 and PCK2. In this case, the phase interpolation circuit 88 outputs, as the divided clock signal DVCK, an interpolation clock signal selected based on M[2:0] which is the lower bits of the interpolation control code from among a plurality of interpolation clock signals generated by 8-fold phase interpolation based on the i-th divided clock signal PCK1 = P0 and the (i + 1)-th divided clock signal PCK2 = P90. For example, the k-th interpolation clock signal between the m-th interpolation clock signal and the n-th interpolation clock signal can be generated by short-circuiting the output terminals of the buffers buffering the m-th interpolation clock signal and the output terminals of the buffers buffering the n-th interpolation clock signal to cause signal collision. Here, m, k, and n are integers greater than or equal to 1 satisfying the relationship m < k < n. For example, by connecting the output terminal of the buffer buffering PCK1 and the output terminal of the buffer buffering PCK2 to cause signal collision, the fourth interpolation clock signal of phase division can be generated. By connecting the output terminal of the buffer buffering PCK1 and the output terminal of the buffer buffering the fourth interpolation clock signal of phase division to cause signal collision, the second interpolation clock signal of phase division can be generated. The interpolation clock signal generated in this way often becomes a narrow pulse signal.

[0103] In this way, the phase interpolation circuit 88 selects a divided clock signal DVCK, which is a clock signal for phase comparison with the reference clock signal RFCK, from among multiple interpolated clock signals generated by phase interpolation based on the i-th divided clock signal PCK1 and the i+1th divided clock signal PCK2 of multiple divided clock signals P0, P90, P180, P270, and P360, based on the interpolation control code. In this way, a phase interpolation type frequency divider circuit 80 can be realized. With the phase interpolation type frequency divider circuit 80, the interpolated clock signal with high resolution phase division can be used, which reduces the amplitude of frequency fluctuations due to delta-sigma modulation and enables the generation of a clock signal CK with reduced phase noise.

[0104] For example, in Figure 20, the phase is divided into four by the multiphase clock signal generation circuit 82, and then further divided into eight by the phase interpolation circuit 88, resulting in 32 phase divisions. Then, an interpolation control code based on the integrated value of an integrator that integrates the output of the delta-sigma modulator selects one of these 32 phase clock signals and outputs it as a divided clock signal DVCK. In this case, the phase is integrated by the integrator that integrates the output of the delta-sigma modulator, and at the timing when the phase transitions from 31 to 0 among the 32 phase divisions, i.e., when the phase completes one cycle, a carry signal is output from the control circuit to the frequency divider 84, as shown in H1 in Figure 21. As a result, the integer division ratio of the frequency divider 84 is carried up from N to N+1, as shown in H2. Note that at the timing when the phase transitions from 0 to 31 among the 32 phase divisions, a carry-down signal is output from the control circuit to the frequency divider 84, and the integer division ratio of the frequency divider 84 is carried down.

[0105] 9. Oscillator Figure 22 shows a first configuration example of the oscillator 4 of this embodiment. The oscillator 4 of this embodiment includes the circuit device 20 of this embodiment and a resonator 10 for generating a reference clock signal RFCK. For example, in Figure 22, the resonator 10 is electrically connected to the circuit device 20. The resonator 10 and the circuit device 20 are electrically connected, for example, using internal wiring, bonding wires, or metal bumps in the package that houses the resonator 10 and the circuit device 20.

[0106] The oscillator 10 is an element that generates mechanical vibrations in response to an electrical signal. The oscillator 10 can be realized by a vibrating element such as a quartz crystal. For example, the oscillator 10 can be realized by a quartz crystal that vibrates with a thickness shear, such as an AT cut or SC cut, a tuning fork type quartz crystal, or a double tuning fork type quartz crystal. For example, the oscillator 10 may be an oscillator built into the oscillator of an SPXO (Simple Packaged Crystal Oscillator), an oscillator built into a temperature-compensated crystal oscillator (TCXO) without a constant temperature chamber, or an oscillator built into a constant temperature chamber type quartz oscillator (OCXO) with a constant temperature chamber. The oscillator 10 of this embodiment can also be realized by various vibrating elements such as vibrating elements other than thickness shear type, tuning fork type or double tuning fork type, or piezoelectric vibrating elements made of materials other than quartz. For example, the oscillator 10 can be a SAW (Surface Acoustic Wave) resonator or a MEMS (Micro Electro Mechanical Systems) oscillator, which is a silicon oscillator formed using a silicon substrate.

[0107] The circuit device 20 in Figure 22 includes an oscillator circuit 130, a PLL circuit 150, a control circuit 160, and an output circuit 180.

[0108] The oscillation circuit 130 is a circuit that causes the resonator 10 to oscillate. For example, the oscillation circuit 130 generates an oscillation signal by causing the resonator 10 to oscillate. For example, the oscillation circuit 130 can be realized by an oscillation drive circuit electrically connected to one end and the other end of the resonator 10, and passive elements such as capacitors and resistors. The drive circuit can be realized by, for example, a CMOS inverter circuit or a bipolar transistor. The drive circuit is the core circuit of the oscillation circuit 130, and the drive circuit causes the resonator 10 to oscillate by voltage driving or current driving the resonator 10. Various types of oscillation circuits such as inverter type, Pierce type, Colpitts type, or Hartley type can be used as the oscillation circuit 130. Note that the connection in this embodiment is an electrical connection. An electrical connection is a connection that allows electrical signals to be transmitted, and is a connection that enables the transmission of information by electrical signals. The electrical connection may be a connection via passive elements, etc.

[0109] The PLL circuit 150 is a PLL circuit realized by the circuits of this embodiment described in Figure 1, etc. The PLL circuit 150 receives a clock signal based on the oscillation signal generated by the oscillator circuit 130 that causes the resonator 10 to oscillate, as a reference clock signal RFCK. The PLL circuit 150 then performs a phase comparison between the reference clock signal RFCK based on the oscillation signal of the resonator 10 and the feedback clock signal FBCK, and generates a clock signal CK by charge pump operation, etc. If the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK is not in the dead zone, the PLL circuit 150 performs a synchronization operation by the FLL operation of the second feedback loop, and if the phase difference is in the dead zone, it performs a synchronization operation by the SPLL operation of the first feedback loop.

[0110] The control circuit 160 is a logic circuit that performs various control and calculation processes. For example, the control circuit 160 controls the entire circuit device 20 and controls the operation sequence of the circuit device 20. The control circuit 160 also performs various processes for controlling the oscillator circuit 130. The control circuit 160 can be implemented, for example, by an ASIC (Application Specific Integrated Circuit) circuit using automatic placement and routing such as a gate array.

[0111] The control circuit 160 includes a delta-sigma modulator 162 and an arithmetic circuit 163, and the arithmetic circuit 163 includes an integrator 164. For example, if the frequency divider circuit 80 in this embodiment is a phase interpolation type frequency divider, the delta-sigma modulator 162 performs delta-sigma modulation based on the fractional part of the division ratio in the division ratio setting code, and the integrator 164 of the arithmetic circuit 163 performs integration of the output values ​​of the delta-sigma modulator. Then, based on the interpolation control code based on the integration result of the integrator 164, processes such as selecting the frequency divider clock signal DVCK from a plurality of interpolation clock signals are performed. In addition, integer division is performed by the integer frequency divider of the frequency divider circuit 80 based on the integer part of the division ratio in the division ratio setting code.

[0112] The output circuit 180 buffers the clock signal CK from the PLL circuit 150 and outputs an output clock signal CKQ. This output clock signal CKQ becomes the external output clock signal for oscillator 4. This output circuit 180 corresponds to the output circuit 78 in Figure 2. The output circuit 180 also outputs the output clock signal CKQ when an external output enable signal OE is input and the output enable signal OE is active. This causes the output clock signal CKQ to be output to the outside of oscillator 4. On the other hand, when the output enable signal OE is inactive, the output terminal of the output clock signal CKQ is set to a fixed voltage, such as a low level.

[0113] Note that in Figure 22, a temperature compensation circuit is not provided, in which case oscillator 4 becomes an SPXO oscillator. Specifically, oscillator 4 becomes a programmable SPXO that can output an output clock signal CKQ of any frequency by setting a frequency division ratio code set in the PLL circuit 150. However, in the configuration of Figure 22, a temperature compensation circuit that performs temperature compensation processing based on the temperature detection result of the temperature sensor may be provided to configure oscillator 4 as a TCXO. In this case, a variable capacitance circuit whose capacitance is controlled by the temperature compensation voltage from the temperature compensation circuit should be provided in the oscillator circuit 130.

[0114] Figure 23 shows a second configuration example of the oscillator 4. The oscillator 4 in Figure 23 includes a resonator 10, a circuit device 21 which is a first circuit device, and a circuit device 20 of this embodiment which is a second circuit device.

[0115] The circuit device 21 includes an oscillation circuit 130, a temperature compensation circuit 140, a temperature sensor 148, a control circuit 160, and an output circuit 180. Since the configuration of the control circuit 160 and the output circuit 180 is the same as in Figure 22, a detailed explanation is omitted.

[0116] The oscillation circuit 130 includes a variable capacitance circuit 132. The variable capacitance circuit 132 is provided at least one of the two ends of the oscillator 10 and is a circuit for adjusting the load capacitance of the oscillator 10. By adjusting the capacitance of the variable capacitance circuit 132, the oscillation frequency of the oscillation circuit 130 is adjusted. The variable capacitance circuit 132 can be realized by a variable capacitance element such as a varactor. For example, the variable capacitance circuit 132 can be realized by a variable capacitance element whose capacitance is controlled based on a temperature compensation voltage. Alternatively, the variable capacitance circuit 132 may be realized by a capacitor array and a switch array connected to the capacitor array. In this case, the capacitance of the variable capacitance circuit 132 is controlled by turning on or off a plurality of switches included in the switch array, for example, by a digital control signal.

[0117] The temperature compensation circuit 140 is a circuit that performs temperature compensation for the oscillation frequency of the oscillation circuit 130. For example, the temperature compensation circuit 140 outputs a temperature compensation signal that temperature-compensates the oscillation frequency of the oscillation circuit 130 based on the temperature detection result of the temperature sensor 148. Temperature compensation is a process that suppresses and compensates for fluctuations in the oscillation frequency due to temperature fluctuations, for example. That is, the temperature compensation circuit 140 performs temperature compensation for the oscillation frequency of the oscillation circuit 130 so that the oscillation frequency remains constant even when there are temperature fluctuations. Specifically, the temperature compensation circuit 140 generates a temperature compensation voltage as a temperature compensation signal. Then, the capacitance of the variable capacitance circuit 132 is controlled using this temperature compensation voltage as a capacitance control voltage, thereby realizing temperature compensation processing of the oscillation frequency. As the temperature compensation circuit 140, for example, a temperature compensation circuit that performs analog temperature compensation using polynomial approximation can be used. For example, when the temperature compensation voltage that compensates for the frequency-temperature characteristics of the oscillator 10 is approximated by a polynomial, the temperature compensation circuit 140 performs analog temperature compensation based on the coefficient information of the polynomial. Analog temperature compensation is achieved, for example, by adding analog signals such as current signals or voltage signals.

[0118] The temperature sensor 148 is a sensor that detects temperature. Specifically, the temperature sensor 148 outputs a temperature-dependent voltage that changes according to the ambient temperature as a temperature detection signal, which is the temperature detection voltage. For example, the temperature sensor 148 generates the temperature detection voltage, which is the temperature detection signal, by utilizing a circuit element that has temperature dependence. Specifically, the temperature sensor 148 outputs a temperature detection voltage whose voltage changes depending on the temperature, for example, by using the temperature dependence of the forward voltage of a PN junction.

[0119] In Figure 23, the temperature compensation circuit 140 performs a first temperature compensation process based on the temperature detection result from the temperature sensor 148. As a result, the first temperature compensation process is performed on the clock signal CK1 generated by the oscillation circuit 130 causing the oscillator 10 to oscillate, and the clock signal CK1 after the first temperature compensation process is output from the circuit device 21. The clock signal CK1 after the first temperature compensation process is then input to the circuit device 20.

[0120] The circuit device 20 includes a PLL circuit 250, a control circuit 260, a temperature sensor 248, and an output circuit 280.

[0121] The PLL circuit 250 is a PLL circuit realized by the circuits of this embodiment described in Figure 1, etc. The PLL circuit 250 receives a clock signal CK1 based on the oscillation signal of the oscillator 10 as a reference clock signal RFCK from the circuit device 21. The PLL circuit 250 then performs a phase comparison between the reference clock signal RFCK based on the oscillation signal of the oscillator 10 and the feedback clock signal FBCK, and generates a clock signal CK by charge pump operation, etc. If the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK is not in the dead zone, the PLL circuit 250 performs a synchronization operation by the FLL operation of the second feedback loop, and if the phase difference is in the dead zone, it performs a synchronization operation by the SPLL operation of the first feedback loop.

[0122] The output circuit 280 then buffers the clock signal CK from the PLL circuit 250 and outputs an output clock signal CKQ. This output clock signal CKQ becomes the external output clock signal for the oscillator 4.

[0123] The control circuit 260 includes a delta-sigma modulator 262 and an arithmetic circuit 263, the arithmetic circuit 263 including an integrator 264. The configuration and operation of the delta-sigma modulator 262 and integrator 264 are the same as those of the delta-sigma modulator 162 and integrator 164 in Figure 22, so a detailed explanation is omitted.

[0124] The circuit device 20 also performs a second temperature compensation process. This second temperature compensation process is performed, for example, by the arithmetic circuit 263 of the control circuit 260. That is, the circuit device 20 performs the second temperature compensation process on the clock signal CK1 after the first compensation process performed by the circuit device 21. For example, the circuit device 20 performs the second temperature compensation process based on the temperature detection result of the temperature sensor 248, etc. Specifically, the arithmetic circuit 263 of the circuit device 20 performs the second temperature compensation process using neural network calculations, etc., based on the temperature detection result from the temperature sensor 248 or temperature sensor 148 and the information of the trained model. For example, a memory circuit (not shown) stores information of a trained model that has been trained to obtain a corresponding temperature compensation value for the temperature measurement result. The arithmetic circuit 263 performs the second temperature compensation process to determine the temperature compensation value corresponding to each temperature based on the temperature detection result and the information of the trained model in the memory circuit.

[0125] As shown in Figure 23, circuit device 21 performs the first temperature compensation process and outputs the clock signal CK1 to circuit device 20, and circuit device 20 performs the second temperature compensation process and outputs the output clock signal CKQ. As a result, the output clock signal CKQ, which has undergone the first temperature compensation process by circuit device 21 and the second temperature compensation process by circuit device 20, is output from oscillator 4. In this way, it is possible to output an output clock signal CKQ from oscillator 4 with reduced phase noise, etc., while achieving more accurate temperature compensation processing. Alternatively, circuit device 20 may be equipped with a heater control circuit to control the temperature of the constant temperature bath, thereby realizing the oscillator 4 of the OCXO.

[0126] As described above, the circuit device of this embodiment includes a sampling circuit that samples the feedback signal of the clock signal based on a reference clock signal, a first phase comparison circuit that outputs the sampling voltage of the sampling circuit, and a first charge pump circuit that outputs a current corresponding to the sampling voltage. The circuit device also includes a dead zone detection circuit that detects whether the phase difference between the reference clock signal and the feedback clock signal of the clock signal has entered a dead zone, and a second phase comparison circuit that outputs a phase difference signal based on a phase comparison between the reference clock signal and the feedback clock signal if the phase difference has not entered a dead zone. The circuit device also includes a second charge pump circuit that performs charge pump operation according to the phase difference signal, and a clock signal generation circuit that generates a clock signal with a frequency controlled based on the output of the first charge pump circuit or the output of the second charge pump circuit. The second charge pump circuit is set to disabled or low power consumption mode during the dead zone period when the phase difference has entered a dead zone.

[0127] According to this embodiment, the second charge pump circuit is set to disabled or low-power mode during the dead zone period when the phase difference between the reference clock signal and the feedback clock signal falls into the dead zone. This prevents the second charge pump circuit from wasting power during the dead zone period when charge pump operation by the second charge pump circuit is not required, thus preventing the circuit device from consuming excessive power. Therefore, while realizing a PLL circuit that enables the first synchronous operation in the first feedback loop and the second synchronous operation in the second feedback loop, it is possible to suppress the consumption of wasted power during the first synchronous operation in the first feedback loop and achieve low power consumption of the circuit device 20.

[0128] Furthermore, this embodiment may include a pulser circuit that outputs a pulse signal based on a reference clock signal. The first charge pump circuit outputs a current corresponding to the sampling voltage during the active period of the pulse signal, and the pulser circuit may be set to disabled or low-power mode during the non-dead zone period when the phase difference is not in the dead zone.

[0129] This prevents unnecessary power consumption in the pulser circuit when the second synchronous operation is being performed in the second feedback loop, which includes the second phase comparison circuit, the second charge pump circuit, and the clock signal generation circuit.

[0130] In this embodiment, the second phase comparison circuit may also include an enable signal generation circuit that generates an enable signal that becomes active during the dead zone period and outputs the enable signal to the pulser circuit. The pulser circuit may be set to disabled or low power mode when the enable signal is inactive, and the second charge pump circuit may be set to disabled or low power mode when the enable signal is active.

[0131] In this way, the enable signal becomes inactive during the non-dead zone period, setting the pulser circuit to a disabled or low-power mode, preventing unnecessary power consumption in the pulser circuit, which is not required to operate during the second synchronous operation of the second feedback loop. Conversely, the enable signal becomes active during the dead zone period, setting the second charge pump circuit to a disabled or low-power mode, preventing unnecessary power consumption in the second charge pump circuit, which is not required to operate during the first synchronous operation of the first feedback loop.

[0132] Furthermore, this embodiment includes a slope signal generation circuit that generates a slope signal based on a feedback clock signal, and the sampling circuit may sample the slope signal based on a reference clock signal.

[0133] In this way, the slope signal generation circuit generates a slope signal with a gradient, and by sampling this slope signal based on a reference clock signal, it becomes possible to output a sampling voltage.

[0134] In this embodiment, the dead zone detection circuit may, after detecting that the phase difference has entered a dead zone of the first dead zone width, set the dead zone to a second dead zone width that is wider than the first dead zone width.

[0135] In this way, when it is detected that the phase difference has entered the dead zone of the first dead zone width, the dead zone width is changed to a second dead zone width which is wider than the first dead zone width. This prevents the system from mistakenly determining that the phase difference is not in the dead zone even if it increases due to noise or other factors after entering the dead zone.

[0136] Furthermore, this embodiment may include a pulser circuit that outputs a pulse signal based on a reference clock signal. The second phase comparison circuit may also include an enable signal generation circuit that generates a first enable signal that becomes active during the dead zone period and outputs it to the pulser circuit, and generates a second enable signal that becomes active during the non-dead zone period when the phase difference is not in the dead zone and outputs it to the second charge pump circuit. When switching from the non-dead zone period to the dead zone period, the first enable signal may become active from inactive, and then the second enable signal may become inactive from active. Also, when switching from the dead zone period to the non-dead zone period, the second enable signal may become active from inactive, and then the first enable signal may become inactive from active.

[0137] In this way, when the operation of the second charge pump circuit is disabled or otherwise disabled and then re-enabled, the second enable signal changes to the active level at an earlier timing, making it possible to restore the operation of the second charge pump circuit at an earlier timing.

[0138] In this embodiment, the clock signal generation circuit may also include a loop filter circuit that outputs a control voltage for the oscillation frequency based on the output of the first charge pump circuit or the output of the second charge pump circuit, and a voltage-controlled oscillator circuit that generates a clock signal with an oscillation frequency corresponding to the control voltage.

[0139] In this way, it becomes possible to generate a clock signal through a first synchronous operation in a first feedback loop including a first phase comparison circuit, a first charge pump circuit, and a clock signal generation circuit, and to generate a clock signal through a second synchronous operation in a second feedback loop including a second phase comparison circuit, a second charge pump circuit, and a clock signal generation circuit.

[0140] In this embodiment, the second charge pump circuit may also include a reference current generation circuit that generates a reference current based on a reference voltage, and a current output circuit that outputs a charge pump current based on the Miller current of the reference current based on an up signal or down signal from the second phase comparison circuit.

[0141] In this way, it becomes possible to generate a reference current that is maintained constant regardless of changes in power supply voltage, temperature, etc., and to output a charge pump current that is maintained constant regardless of changes in power supply voltage, temperature, etc., to the clock signal generation circuit.

[0142] In this embodiment, the reference current and Miller current may be turned off during the dead zone period.

[0143] In this way, it is possible to prevent unnecessary power consumption by having the reference current and its Miller current flow in the second charge pump circuit, which does not need to operate during the dead zone period.

[0144] In this embodiment, the current output circuit may also include a P-type transistor provided between the high-potential-side power supply node and the first node, through which an up current flows as a charge pump current, and a first switch provided between the first node and the output node of the current output circuit, which turns on when the up signal is active. The current output circuit may also include an N-type transistor provided between the second node and the low-potential-side power supply node, through which a down current flows as a charge pump current, and a second switch provided between the output node and the second node, which turns on when the down signal is active.

[0145] In this way, a charge pump current corresponding to the phase difference between the reference clock signal and the feedback clock signal is output to the clock signal generation circuit, enabling frequency control of the clock signal according to the phase difference.

[0146] In this embodiment, the current output circuit may also include a third switch provided between the first node and the mirror node of the output node, which turns on when the up signal is inactive, and a fourth switch provided between the mirror node and the second node, which turns on when the down signal is inactive. The current output circuit may also include an operational amplifier in voltage follower configuration, where the output node is connected to the input terminal and the mirror node is connected to the output terminal.

[0147] In this way, a third switch and a fourth switch, which act as mirror circuits of the first and second switches, are placed between the first and second nodes. Then, by operational amplification using a voltage follower connection, the voltage of the mirror node between the third and fourth switches can be set to the same voltage as the output node between the first and second switches.

[0148] Furthermore, the oscillator of this embodiment includes the circuit device described above and a resonator for generating a reference clock signal.

[0149] Although this embodiment has been described in detail above, it will be readily apparent to those skilled in the art that many modifications are possible without substantially departing from the novelty and effects of this disclosure. Therefore, all such modifications are included within the scope of this disclosure. For example, any term that appears at least once in the specification or drawings together with a broader or synonymous term may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of this embodiment and its modifications are also included within the scope of this disclosure. In addition, the configuration and operation of the circuit device, oscillator, etc., are not limited to those described in this embodiment, and various modifications are possible. [Explanation of symbols]

[0150] 4...Oscillator, 10...Resonator, 20, 21...Circuit device, 22...Slope signal generation circuit, 24...Pulsar circuit, 25, 26...Delay circuit, 30...First phase comparison circuit, 32...Sampling circuit, 40...First charge pump circuit, 50...Second phase comparison circuit, 52...Dead zone detection circuit, 54...Enable signal generation circuit, 56, 57, 58, 59...Delay circuit, 60...Second charge pump circuit, 62...Reference current generation circuit, 6 4…Current output circuit, 70…Clock signal generation circuit, 72…Loop filter circuit, 74…Voltage-controlled oscillator circuit, 76…Buffer circuit, 78…Output circuit, 80…Frequency divider circuit, 82…Multiphase clock signal generation circuit, 83, 84…Frequency divider, 86…Multiplexer, 88…Phase interpolation circuit, 90…Pulse width expansion circuit, 130…Oscillator circuit, 132…Variable capacitance circuit, 140…Temperature compensation circuit, 148…Temperature sensor, 150…PLL Circuit, 160…Control circuit, 162…Delta-sigma modulator, 163…Arithmetic circuit, 164…Integrator, 180…Output circuit, 248…Temperature sensor, 250…PLL circuit, 260…Control circuit, 262…Delta-sigma modulator, 263…Arithmetic circuit, 264…Integrator, 280…Output circuit, AP…Amplifier circuit, CK, CK1…Clock signal, CKQ…Output clock signal, CS…Capacitor, DN…Down signal, DVCK…Frequency divider clock signal, DW1…First dead zone width, DW2…Second dead zone width, ENCP, ENSP…Enable signal, FBCK…Feedback clock signal, FBSG…Feedback signal, IRF…Reference current, NS…Sampling node, PDS…Phase difference signal, PLS…Pulse signal, RFCK…Reference clock signal, SLP…Slope signal, SS…Switch circuit, UP…Up signal, VSA…Sampling voltage

Claims

1. A sampling circuit has a sampling circuit that samples the feedback signal of a clock signal based on a reference clock signal, and a first phase comparison circuit that outputs the sampling voltage of the sampling circuit, A pulser circuit that outputs a pulse signal based on the aforementioned reference clock signal, During the active period of the pulse signal, a first charge pump circuit outputs a current corresponding to the sampling voltage, The circuit includes a dead zone detection circuit that detects whether the phase difference between the reference clock signal and the feedback clock signal of the clock signal has entered a dead zone, and a second phase comparison circuit that outputs a phase difference signal based on a phase comparison between the reference clock signal and the feedback clock signal if the phase difference has not entered the dead zone. A second charge pump circuit that performs charge pump operation in accordance with the phase difference signal, A clock signal generation circuit that generates the clock signal having a frequency controlled based on the output of the first charge pump circuit or the output of the second charge pump circuit, Includes, The second charge pump circuit is, During the dead zone period when the phase difference enters the dead zone, the system is set to disabled or low power consumption mode. The aforementioned pulser circuit is A circuit device characterized in that, during a non-dead zone period in which the phase difference does not fall within the dead zone, the device is set to a disabled or low-power consumption mode.

2. In the circuit device according to claim 1, The aforementioned second phase comparison circuit is, Includes an enable signal generation circuit that generates an enable signal that becomes active during the dead zone period and outputs the enable signal to the pulser circuit, The aforementioned pulser circuit is If the enable signal is inactive, the system is set to disabled or low-power mode. The second charge pump circuit is, A circuit device characterized in that, when the enable signal is active, it is set to a disabled or low-power mode.

3. In the circuit device according to claim 1 or 2, Includes a slope signal generation circuit that generates a slope signal based on the aforementioned feedback clock signal, The sampling circuit described above is A circuit device characterized by sampling the slope signal, which is the feedback signal, based on the reference clock signal.

4. In the circuit device according to any one of claims 1 to 3, The dead zone detection circuit is, A circuit device characterized in that, after it is detected that the phase difference has entered the dead zone of the first dead zone width, the dead zone is set to a second dead zone width that is wider than the first dead zone width.

5. A sampling circuit has a sampling circuit that samples the feedback signal of a clock signal based on a reference clock signal, and a first phase comparison circuit that outputs the sampling voltage of the sampling circuit, A pulser circuit that outputs a pulse signal based on the aforementioned reference clock signal, During the active period of the pulse signal, a first charge pump circuit outputs a current corresponding to the sampling voltage, The circuit includes a dead zone detection circuit that detects whether the phase difference between the reference clock signal and the feedback clock signal of the clock signal has entered a dead zone, and a second phase comparison circuit that outputs a phase difference signal based on a phase comparison between the reference clock signal and the feedback clock signal if the phase difference has not entered the dead zone. A second charge pump circuit that performs charge pump operation in accordance with the phase difference signal, A clock signal generation circuit that generates the clock signal having a frequency controlled based on the output of the first charge pump circuit or the output of the second charge pump circuit, Includes, The second charge pump circuit is, During the dead zone period when the phase difference enters the dead zone, the system is set to disabled or low power consumption mode. The aforementioned second phase comparison circuit is, The circuit includes an enable signal generation circuit that generates a first enable signal that becomes active during the dead zone period and outputs it to the pulser circuit, and generates a second enable signal that becomes active during the non-dead zone period when the phase difference is not in the dead zone and outputs it to the second charge pump circuit. The aforementioned pulser circuit is When the first enable signal is inactive, the system is set to disabled or low power mode. The second charge pump circuit is, When the second enable signal is inactive, the system is set to disabled or low-power mode. When switching from the non-dead zone period to the dead zone period, the first enable signal changes from inactive to active, and then the second enable signal changes from active to inactive. A circuit device characterized in that, when switching from the dead zone period to the non-dead zone period, the second enable signal changes from inactive to active, and then the first enable signal changes from active to inactive.

6. In the circuit device according to any one of claims 1 to 5, The aforementioned clock signal generation circuit is A loop filter circuit that outputs a control voltage for the oscillation frequency based on the output of the first charge pump circuit or the output of the second charge pump circuit, A voltage-controlled oscillator circuit that generates the clock signal having the oscillation frequency corresponding to the control voltage, A circuit device characterized by including the following.

7. In the circuit device according to any one of claims 1 to 6, The second charge pump circuit is, A reference current generation circuit that generates a reference current based on a reference voltage, A current output circuit that outputs a charge pump current based on the Miller current of the reference current based on an up signal or down signal from the second phase comparison circuit, A circuit device characterized by including the following.

8. In the circuit device according to claim 7, A circuit device characterized in that the reference current and the Miller current are turned off during the dead zone period.

9. In the circuit device according to claim 7 or 8, The current output circuit is, A P-type transistor is provided between the high-potential power supply node and the first node, through which an up current flows as the charge pump current. A first switch is provided between the first node and the output node of the current output circuit, and turns on when the up signal is active, An N-type transistor is provided between the second node and the low-potential side power supply node, through which a down current flows as the charge pump current, A second switch is provided between the output node and the second node, and turns on when the down signal is active. A circuit device characterized by including the following.

10. In the circuit device according to claim 9, The current output circuit is, A third switch is provided between the first node and the mirror node of the output node, and turns on when the up signal is inactive, A fourth switch is provided between the mirror node and the second node, and turns on when the down signal is inactive. An operational amplifier in a voltage follower configuration, wherein the output node is connected to the input terminal and the mirror node is connected to the output terminal, A circuit device characterized by including the following.

11. A circuit device according to any one of claims 1 to 10, A vibrator for generating the aforementioned reference clock signal, An oscillator characterized by including [a certain component].

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