System and method for low-latency modular multiplication

Abstract

To provide systems and methods for low latency modular multiplication.SOLUTION: An integrated circuit device includes multiplier circuitry configured to determine a plurality of columns of subproducts by multiplying a plurality of values. Each column of the plurality of columns includes one or more subproducts of a plurality of subproducts. The integrated circuit device also includes adder circuitry configured to determine a plurality of sums, each sum being a sum of one column of the plurality of columns. A first portion of the adder circuitry associated with a first column of the plurality of columns is configured to receive a first value and second value that are associated with the first column and a third value associated with a second column of the plurality of columns that differs from the first column. The third value is a carry-out value generated by a second portion of the adder circuitry associated with the second column of the plurality of columns.SELECTED DRAWING: Figure 2

Description

Background Art

[0001] The present disclosure generally relates to integrated circuit (IC) devices such as programmable logic devices (PLDs). More specifically, the present disclosure relates to techniques for performing modular multiplication operations in integrated circuit devices including programmable logic devices such as field programmable gate arrays (FPGAs).

[0002] This section is intended to introduce readers to various aspects of technologies that may be related to various aspects of the present disclosure described and / or claimed below. This discussion is believed to be helpful in providing readers with background information that facilitates a better understanding of various aspects of the present disclosure. Thus, it can be understood that these descriptions should be read from this perspective and should not be read as an admission of prior art.

[0003] Integrated circuit devices can be utilized for various purposes or applications such as digital signal processing, machine learning, and cryptocurrency or other blockchain-related applications. Programmable logic devices, for example, may be utilized to perform these functions using specific circuits (e.g., processing blocks). In some cases, the specific circuits that are effective for performing multiplication operations (e.g., modular multiplication operations) may execute these operations with an undesirably high latency, the specific circuits may occupy an undesirable amount of area on the integrated circuit device, or both.

Brief Description of the Drawings

[0004] Various aspects of the present disclosure can be better understood by reading the following detailed description and referring to the drawings.

[0005] [Figure 1]This is a block diagram of a system that can implement arithmetic operations using a multiplier circuit according to embodiments of the present disclosure. [Figure 2] This is a block diagram of an example of an integrated circuit device shown in Figure 1, according to an embodiment of the present disclosure. [Figure 3] This is a flowchart of the processes that can be executed when the multiplier circuit of the integrated circuit device in Figure 1 performs a multiplication operation, according to embodiments of the present disclosure. [Figure 4] This is a block diagram representing columns of subproducts and rows of the sum of the columns of subproducts, according to embodiments of the present disclosure. [Figure 5] This figure illustrates an example of generating modulus values ​​and summing them up according to an embodiment of the present disclosure. [Figure 6] This figure illustrates another example of generating modulus values ​​and summing them up, according to other embodiments of the present disclosure. [Figure 7] This is a block diagram representing the columns of subproducts and the rows of the sum of the subproducts in Figure 4, along with the reduced sum, according to an embodiment of the present disclosure. [Figure 8] This is a block diagram of an independent adder tree according to an embodiment of the present disclosure. [Figure 9] This is a block diagram of an adder tree in which carry-out values ​​are shared among adder trees according to an embodiment of the present disclosure. [Figure 10] This is a block diagram of an adder tree in which carry-out values ​​are shared among adder trees, according to other embodiments of the present disclosure. [Figure 11] This is a block diagram of an adder circuit that may be included in one or more of the adder trees in Figure 10, according to embodiments of the present disclosure. [Figure 12] Figure 11 is a block diagram of a binary adder circuit according to an embodiment of the present disclosure. [Figure 13] This is a data processing system according to an embodiment of the present disclosure. [Modes for carrying out the invention]

[0006] One or more specific embodiments are described below. Not all features of the actual embodiments are described in this specification in order to give a specific description of these embodiment fluids. Naturally, in the development of any such actual embodiment, as is seen in any engineering or design project, numerous embodiment-specific decisions must be made to achieve the specific goals of the developers, which may vary from embodiment to embodiment, such as compliance with system-related and business-related constraints. Furthermore, naturally, such development efforts may be complex and time-consuming, but nevertheless, they will be routine design, fabrication, and manufacturing efforts for those skilled in the art who have access to this disclosure.

[0007] When describing elements of various embodiments of this disclosure, the articles “a,” “an,” and “the” (as stated above) are intended to mean that there is one or more elements. “Including” and “having” are intended to mean comprehensive and that there may be additional elements other than those listed. Furthermore, it should be understood that references to “some embodiments,” “embodiments,” “one embodiment,” or “an embodiment” in this disclosure are not intended to be interpreted as excluding the existence of additional embodiments that further incorporate the described features. Furthermore, the expression A “based on” B is intended to mean that A is at least partially based on B. Furthermore, the term “or” is intended to be comprehensive (e.g., logical OR) and not exclusive (e.g., logical XOR). That is, the expression A “or” B is intended to mean A, B, or both A and B.

[0008] As various applications such as machine learning, artificial intelligence applications, cryptocurrency-related applications, and digital signal processing (DSP) applications become increasingly prevalent, there is a growing demand for more efficient execution of various operations related to these applications. For example, there may be a demand to change (e.g., reduce) the amount of circuitry used to perform one or more of these operations in order to create space for the circuitry to perform one or more other operations. Similarly, there may be a demand to reduce the amount of time used to perform operations related to these applications. In other words, performing these operations with lower latency may be desirable, for example, to enable operations to be performed faster. With this in mind, the techniques described below relate to reducing the latency associated with modular multiplication operations and reducing the amount of circuitry used to perform modular multiplication operations. For example, when used for machine learning, artificial intelligence applications, and cryptocurrency-related applications, modular multiplication operations can be performed by integrated circuit devices, including programmable logic devices such as FPGAs, Application-Specific Standard Product(s) (ASSPs), and Application-Specific Integrated Circuits (ASICs). As described below, the circuits contained within the integrated circuit device (e.g., DSP circuits, multiplier circuits, adder circuits) perform modular multiplication in such a way that they reduce the amount of area on the integrated circuit device used to perform these operations, while also reducing the latency associated with performing these operations.

[0009] As a more specific example, integrated circuit devices can perform arithmetic operations related to variable delay functions (VDFs) that can be used as proof of work in cryptographic applications such as cryptocurrency or blockchain applications. Generally, proof of work is a proof in which one party (e.g., a party operating or associated with one or more integrated circuit devices used for a cryptocurrency application) proves to other parties (one or more parties in a cryptocurrency transaction) that a certain amount of computational work has been spent. That is, VDFs cannot be accelerated or parallelized beyond their most well-known implementation. Therefore, it is advantageous to determine the best (e.g., most efficient or fastest) implementation for the VDF. In many cases, modular multiplication and other mathematical operations (e.g., addition) are performed by the circuitry included in the integrated circuit device as the part that determines such implementations. Therefore, by performing modular multiplication (and the operations performed as the part that performs modular multiplication) with lower latency, integrated circuit devices can determine a better (e.g., best or fastest) solution to VDF, thereby improving the performance of the integrated circuit device, especially when used for cryptocurrency and blockchain applications.

[0010] With the above in mind, Figure 1 is a block diagram of a system 10 that can implement arithmetic operations such as modular multiplication using a multiplier circuit. A designer may want to implement functions such as the high-precision arithmetic operations of this disclosure in an integrated circuit device 12 (e.g., a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)). In some cases, a designer may specify a high-level program to be implemented, such as an OpenCL program. This may allow the designer to provide programming instructions more efficiently and easily to construct a set of programmable logic cells for the integrated circuit device 12 without having to be particularly familiar with a low-level hardware description language (e.g., Verilog or VHDL). For example, OpenCL is very similar to other high-level programming languages ​​such as C++, and a programmer of programmable logic who is familiar with such a programming language will have a reduced learning burden than a designer who would have to learn an unfamiliar low-level hardware description language in order to implement new functions in the integrated circuit device 12.

[0011] Designers may implement their high-level designs using design software 14, such as a version of Intel Quartus from Intel Corporation. The design software 14 may use a compiler 16 to translate the high-level program into a low-level description. The compiler 16 may supply machine-readable instructions representing the high-level program to the host 18 and the integrated circuit device 12. The host 18 may receive a host program 22, which can be implemented by a kernel program 20. To implement the host program 22, the host 18 may communicate instructions from the host program 22 to the integrated circuit device 12 via a communication link 24. The communication link 24 may be, for example, Direct Memory Access (DMA) communication or Peripheral Component Interconnect express (PCIe) communication. In some embodiments, the kernel program 20 and the host 18 may enable the configuration of a multiplier circuit 26 in the integrated circuit device 12. The multiplier circuit 26 may include circuits used to perform several different operations. For example, the multiplier circuit 26 may include one or more multipliers and adders used to perform multiplication and addition operations, respectively. Thus, the multiplier circuit 26 may include circuits that implement operations for performing multiplication for AI or non-AI data processing (e.g., modular multiplication, matrix-matrix multiplication, matrix-vector multiplication, vector-vector multiplication). Furthermore, in some embodiments, the multiplier circuit 26 may include one or more DSP blocks, and the integrated circuit device 12 may include many (e.g., hundreds or thousands) DSP blocks. The DSP blocks may be coupled communicatively so that data output from one DSP block can be supplied to other DSP blocks. Furthermore, an adder circuit may be included in the multiplier circuit 26, for example, to add subproducts determined when performing a multiplication operation.In fact, as illustrated by the example below, the multiplier circuit 26 can perform multiplication with relatively large values ​​(e.g., multiplier and / or multiplicand) by decomposing one or more values ​​into several smaller values, generating subproducts, and adding the subproducts. When performing modular multiplication, the modulus value of one or more sums related to the subproducts (e.g., the sum of a sequence of subproducts) can also be determined.

[0012] Although the above techniques describe the application of high-level programs, in some embodiments, the designer may use design software 14 to generate and / or specify low-level programs, such as the low-level hardware description language described above. Furthermore, in some embodiments, the system 10 may be implemented without a separate host program 22. Furthermore, in some embodiments, the techniques described herein may be implemented in a circuit as a non-programmable circuit design. For example, the multiplier circuit 26 may be formed at least partially in a non-programmable portion of a programmable logic device (e.g., FPGA or ASIC). Furthermore, in other embodiments, the multiplier circuit 26 may be partially implemented in a portion of the integrated circuit device 12 that is programmable by the end user (e.g., software logic) and in a portion of the integrated circuit device 12 that is not programmable by the end user (e.g., hard logic). For example, the DSP block may be implemented in hard logic, while other circuits included in the multiplier circuit, including circuits reserved for routing data between parts of the multiplier circuit, may be implemented in software logic. Thus, the embodiments described herein are intended to be illustrative and not limiting.

[0013] Referring to a more detailed description of the integrated circuit device 12, Figure 2 shows an example of the integrated circuit device 12 as a programmable logic device such as a field-programmable gate array (FPGA). Furthermore, it should be understood that the integrated circuit device 12 may be any other suitable type of integrated circuit device (e.g., application-specific integrated circuits and / or application-specific standard products). As shown, the integrated circuit device 12 may include input / output circuits 42 that drive signals to the outside of the device and receive signals from other devices via input / output pins 44. Interconnection resources 46 such as global and local vertical and horizontal conductors and buses may be used for routing signals in the integrated circuit device 12. Furthermore, the interconnection resources 46 may include fixed interconnects (conductors) and programmable interconnects (e.g., programmable connections between each fixed interconnect). The programmable logic 48 may include combinational and sequential logic. For example, the programmable logic 48 may include lookup tables, registers, and multiplexers. In various embodiments, the programmable logic 48 may be configured to perform custom logic functions. A programmable interconnect associated with interconnection resources may be considered part of the programmable logic 48.

[0014] The programmable logic devices that the integrated circuit device 12 can represent may include programmable elements 50 within the programmable logic 48. For example, as described above, a designer (e.g., a customer) may program (e.g., configure) the programmable logic 48 to perform one or more desired functions. As an example, some programmable logic devices can be programmed by configuring their programmable elements 50 using a mask programming arrangement performed during semiconductor manufacturing. Other programmable logic devices can be configured after the semiconductor manufacturing operation is complete, for example, by using electronic programming or laser programming to program their programmable elements 50. Generally, the programmable elements 50 may be based on any suitable programmable technology, such as fuses, antifuses, electrically programmable read-only memory technology, random access memory cells, mask-programmed elements, etc.

[0015] Many programmable logic devices are electrically programmed. According to the electrical programming arrangement, the programmable element 50 may be formed from one or more memory cells. For example, during programming, configuration data is loaded into the memory cells using pins 44 and input / output circuits 42. In one embodiment, the memory cells may be implemented as random access memory (RAM) cells. The use of memory cells based on RAM technology described herein is intended to be merely an example. Furthermore, since these RAM cells are loaded with configuration data during programming, they are sometimes referred to as configuration RAM cells (CRAM). These memory cells may each supply corresponding static control output signals that control the state of the relevant logic components in the programmable logic 48. For example, in some embodiments, the output signals may be applied to the gates of metal-oxide-semiconductor (MOS) transistors in the programmable logic 48.

[0016] With the above in mind, the multiplier circuit 26 described herein can be used for a variety of applications and to perform a wide range of application-related operations, such as multiplication and addition. For example, modular multiplication may be suitable for cryptocurrency applications. As described below, the multiplier circuit 26 can reduce the latency associated with modular multiplication due to the multiplier circuit 26 itself and the manner in which the multiplier circuit 26 performs modular multiplication. To help give an overview of the operations that the multiplier circuit 26 can perform, Figure 3 is given. In particular, Figure 3 is a flowchart of the process 70 that the multiplier circuit 26 can perform on the data it receives in order to determine the product of the input data. Furthermore, it should be noted that the operations described with respect to process 70 will be described in more detail in relation to later figures. Process 70 generally includes receiving data (process block 72), determining subproducts from the received data (process block 74), and determining the sum of the subproducts (process block 76). Process block 76 may be performed by determining the sum of each column of the subproduct (subprocess block 78) and adding up the sums of the columns of the subproduct (subprocess block 80). Process 70 may also include reducing the columns of the subproduct (process block 82) and determining and outputting one or more sums (process block 84).

[0017] In process block 72, multiplier circuit 26 receives data. The data may include a value to be multiplied. The data may include a fixed-point data type. In some cases, the value to be multiplied may be more precise than the precision of the individual parts of multiplier circuit 26 used to perform the multiplication operation. For example, multiplier circuit 26 can include a 27-bit wide DSP block for processing values, but one or more of the values to be multiplied may include more bits than 27 bits (e.g., 128 bits, 256 bits, 512 bits, 1024 bits, or more than 1024 bits). In such embodiments, multiplier circuit 26 or integrated circuit device 12 may subdivide one or more of the values to be multiplied into several smaller values. For example, continuing with the example where multiplier circuit 26 includes a DSP block that processes 27-bit values, two 128-bit values to be multiplied can each be divided into five subterms.

[0018] In process block 74, multiplier circuit 26 can determine sub-products. That is, multiplier circuit 26 can multiply a subterm associated with one value (e.g., the multiplicand) by a subterm associated with another value (e.g., a constant), or another value if only one value is divided into subterms. In the above example where two 128-bit values are each divided into five subterms, twenty-five DSP blocks (e.g., a 5×5 arrangement of DPS blocks) can be used to multiply the subterms.

[0019] To help further extend the multiplier circuit 26 that generates subproducts, Figure 4 is given. In particular, Figure 4 is a diagram showing columns 90 of subproducts 92 (e.g., examples 90A to 90G) and rows 94 of the sum 96 of columns 90 (e.g., sum 96A to 96G). More specifically, Figure 4 includes seven columns 90 of subproducts 92. It should be noted that while seven columns 90 of subproducts are provided, the number of columns 90 and subproducts 92 may differ in other embodiments. In fact, the seven columns 90 do not have to correspond to any particular size of multiplier or decomposition (e.g., one or more values ​​to be multiplied). Rather, the number of columns 90 and the depth of the columns 90 (i.e., the number of subproducts 92 per column 90) may depend on the size of the value to be multiplied and how the value is subdivided (e.g., decomposed into smaller values ​​that will be multiplied to generate subproducts 92). For example, in an example where two 128-bit values ​​are decomposed into 27-bit DSP blocks (e.g., a 5x5 arrangement of DSP blocks), there will be 10 columns 90 with a column depth of up to 9 terms (i.e., subproducts 92). That said, regardless of the number of columns 90, the number of subproducts 92 in each column 90 generally increases from right to left to the middle (e.g., column 90D), as shown in Figure 4, and then decreases again from the middle to the left. Thus, Figure 4 includes 7 columns 90 of subproducts 92 with a maximum depth of 7 (7 subproducts 92 in column 90D), but the multiplication operation shown in Figure 4 is just one example. Other embodiments may include fewer or more columns 90 than those in Figure 4, and the maximum depth of the columns 90 may differ from that in Figure 4.

[0020] Returning to the description of FIG. 3 and process 70, with FIG. 4 in mind, at process block 76, multiplier circuit 26 may determine the sum of the sub-products. That is, an adder circuit that may be included in multiplier circuit 26 may add sub-products 92 (for example, as part of determining the product of two initial values to be multiplied). To determine the sum of the sub-products, multiplier circuit 26 determines, at sub-block 78, the sum of each column 90 of sub-products 92 (for example, by adding each sub-product 92 in a particular column 90), and adds the sums of columns 90 at sub-block 80. That is, multiplier circuit 26 may add each of the sub-products of a column 90 for each column 90, and then add the sums of columns 90. For example, in FIG. 4, each of sums 96 is a sum determined by adding sub-products 92 of a particular column 90 (i.e., the column 90 in which a given sum 96 is located). More specifically, each sum 96 may be determined independently. That is, a sum 96 may be determined without considering values related to other columns (for example, sub-products, sums, word growth).

[0021] Generally, word growth may occur depending on the number of columns 90 of sub-products 92 and the depth of columns 90. That is, as represented by any bit represented by a bar within bit 98 (for example, bits 98A - 98E) or sum 96 (for example, sums 96B - 96F), a part of sum 96 may include one or more bits more than the width that can be processed by the DSP block included in multiplier circuit 26. For example, in FIG. 4, sums 96B, 96F include a 2-bit word growth, while sums 96C, 96D, 96E include a 3-bit word growth. As another example, in the case of the above-described 27-bit wide DSP block, the sum 96 of a given column 90 of sub-products 92 may include 1, 2, 3, or 4 bits more than 27 bits (i.e., 1, 2, 3, or 4-bit word growth). Similar to the depth of the column, the amount of word growth generally increases from the right to the middle (for example, column 90D) and decreases from the middle to the left.

[0022] The multiplier circuit 26 may perform further addition operations to sum the sums 96. For example, in process block 82, the multiplier circuit 26 may reduce one or more of the sums 96 in column 90 by determining the modulus for each sum 96 that has a rank greater than the input argument size. That is, each sum 96 that contains more bits than the refined value multiplied by the multiplier circuit (which may be the same number of bits as the width of the DSP block used to determine the subproduct 92) may be replaced by its modulus. Modular reduction may be performed based on the modulus units (identities) given below: ((A+B)modN)=AmodN+BmodN Here, A and B1 are the values ​​to be added (for example, two of the sums of 96), "mod" is the modulo operation, and N is the value. In particular, the value of N may be an integer value determined on a case-by-case basis by the multiplier circuit 26 or integrated circuit device 12 based on the value of the sum of 96. Thus, the modulus value of each of the sums of 96 can be determined.

[0023] Returning to the description of Figure 3 and process 70, in process block 84, the multiplier circuit 26 may determine and output one or more sums. For example, the adder circuit within the multiplier circuit 26 may add the values ​​generated by performing the above modular reduction.

[0024] To help extend this explanation, Figure 5 is provided. In particular, Figure 5 illustrates an example of how the integrated circuit device 12 and the multiplier circuit 26 may perform the operations described above with respect to process blocks 82 and 84 of process 70. For example, a multiplier block 100 (e.g., multiplier blocks 100A to 100I) (indicated as "MUL" in the figure) may be included in the multiplier circuit 26 to determine the subproducts 92 and the sum 96. A lookup table (LUT) 102 (e.g., LUTs 102A to 102E) included in the multiplier circuit 26 (or elsewhere in the integrated circuit device 12) may be communicatively coupled to the corresponding multiplier block 100, receive an output (e.g., the sum 96) from that multiplier block 100, and perform a modulo operation on the value received from the multiplier block 100 to output a modulo value. Thus, LUT 102 may be used to perform modular reduction. Similar to the description of column 90 and its depth above, the amount of multiplier blocks 100 and LUT 102 used may vary depending on the number of bits being multiplied. Therefore, in other embodiments, fewer or more multiplier blocks 100 and LUT 102 than those shown in Figure 5 may be used.

[0025] The output of LUT102 may be supplied to an adder circuit 104. The adder circuit 104 may be included in the multiplier circuit 26 or otherwise included in the integrated circuit device 12. In particular, the first part (e.g., row) 106 of the adder circuit 104 may receive values ​​(e.g., portions of values ​​generated by modulo operation) from two of the LUT102 (e.g., LUT102D and LUT102E), add the values, produce an output (e.g., the sum of the added values), and supply the output to the subsequent part (e.g., second part 108) of the adder circuit 104. In addition to the second part 108, the third part 110 and fourth part 112 of the adder circuit 104 may receive a set of values ​​from the preceding part of the adder circuit 104 and a set of values ​​from one of the LUT102, and add the two sets of values ​​together. The adder circuit 104 is represented as having four rows (e.g., parts 106, 108, 110, 112) each containing four adders, but in other embodiments, the adder circuit 104 may include a different number of rows and a different number of adders per row, based on, for example, the number of LUTs 102, the size of the value to be multiplied (e.g., the number of bits), the width of the DSP block, or a combination thereof.

[0026] Before continuing to explain how the integrated circuit device 12 and the multiplier circuit 26 can execute parts of process 70 faster (i.e., with less latency), it should be noted that process 70 may include additional operations. For example, in other embodiments, process 70 may include determining the product of two initial values ​​and outputting such product. More specifically, the product may be determined based on the sum determined in process block 84 and the sum 96 of the column 90 of subproduct 92, which is not reduced (e.g., in process block 82). Thus, the multiplier circuit 26 and the integrated circuit device 12 may determine the product of two values ​​by performing multiplication and addition (and modulo) operations using the subvalues ​​of the two values. Furthermore, as an alternative to the above explanation, it should be noted that each of the represented multiplier blocks 100 can be thought of as the sum 96, and LUT 102 can be thought of as the modulus value output by the lookup table contained in the integrated circuit device 12.

[0027] With the above in mind, since an adder circuit may be used to add a partial product to a value generated by modular reduction, the circuits used to perform the initial value multiplication (e.g., multiplier circuit 26, LUT 102, and adder circuit 104) may utilize a larger area than desired on the integrated circuit device 12. Furthermore, the division of the initial value to be multiplied may introduce latency when performing the multiplication operation. For example, as described above, if the initial value is converted to several smaller values, a partial product may be determined, and the partial products will be summed to determine the product of the initial values. In other words, since the number of operations increases, the amount of time used to calculate the product of the values ​​will be greater than when the multiplication operation is performed using a circuit configured to perform multiplication on data having the same width (e.g., number of bits) as the initial value. Furthermore, relatively large latency may appear based on the amount of data (e.g., depth of column 90), the order in which column 90 is summed, the sum of column 90 subproducts determined independently of each other, or any combination thereof. Latency can also manifest due to word growth (for example, by performing reduction operations to reduce word growth).

[0028] For example, in Figure 4, the fourth column 90D of the subproducts contains more partial products than any of the other columns 90, so it will take more time for the multiplier circuit 26 to determine the subproduct 92 of column 90D. This means that it may also take longer to determine the sum 96 of the fourth column 90D. Conversely, the other columns (e.g., columns 90A, 90B, 90F, 90G) may contain relatively fewer subproducts 92, meaning that the sums associated with columns 90A, 90B, 90F, 90G (e.g., sums 96A, 96B, 96F, 96G, respectively) may be determined faster than the sum 96 associated with column 90 which has more subproducts 92.

[0029] With this in mind, referring to Figure 5, the multiplier block 100 may show a pattern that is generally similar to the pattern of column 90 and sum 96 in Figure 4. For example, multiplier block 100I may relate to a subproduct 92 of a first number, multiplier block 100H may relate to a more number of subproducts 92 (e.g., a subproduct 92 of a second number), multiplier block 100G may relate to a more number of subproducts 92 (e.g., a subproduct 92 of a third number), multiplier block 100F may relate to a more number of subproducts 92 (e.g., a subproduct 92 of a fourth number), and multiplier block 100E may relate to a more number of subproducts 92 (e.g., a subproduct 92 of a fifth number). The multiplier block 100D may relate to a smaller number of subproducts 92 (e.g., a fourth number of subproducts 92), the multiplier block 100C may relate to a smaller number of subproducts 92 (e.g., a third number of subproducts 92), the multiplier block 100B may relate to a smaller number of subproducts 92 (e.g., a second number of subproducts 92), and the multiplier block 100A may relate to a smaller number of subproducts 92 (e.g., a first number of subproducts 92). As described above, columns 90 with fewer subproducts may be summed before columns 90 with more subproducts 92. Therefore, LUT 102 related to columns 90 with more subproducts 92 will take more time to generate an output that can be supplied to the adder circuit 104 for summing. Therefore, in Figure 5, the outputs from LUT102E and LUT102D take relatively more time to determine and generate than the outputs from LUT102C, 102B, and 102A.

[0030] To reduce latency, additions with reduced values ​​(values ​​generated in relation to process block 82 of process 70) may be performed sequentially based on the amount of delay associated with each column 90, which may correspond to the depth of column 90. That is, the order in which the addition operations are performed may take into account the number of partial products 92 that column 90 has with one or more of the other columns 90. Figure 6 is a block diagram of the same circuit as in Figure 5, arranged to perform additions sequentially based on column depth. More specifically, in Figure 6 (compared to Figure 5), the addition is performed by the first part 106 of the adder circuit 104 using the outputs from LUT102A and LUT102B, which are in columns that have the relatively smallest amount of partial products 92 (compared to LUT102C, 102D, and 102E, for example). The second part 108 of the adder circuit 104 receives the outputs from LUT102C and LUT102D and adds the inputs. The outputs from the first part 106 and the second part 108 of the adder circuit 104 are added by the third part 110 of the adder circuit 104. Furthermore, the fourth part 112 of the adder circuit 104 adds the value received from the third part 110 of the adder circuit 104 and from LUT 102E, which is LUT 102 associated with the longest delay by relating to the column with the most partial products. In this way, each part of the modulus generated by LUT 102 is input to each part of the adder circuit 104, and each column is added independently (i.e., without any carries between columns). Thus, columns 90 may be grouped by the expected delay (e.g., based on the number of partial products 92 in each column 90), and addition operations (e.g., additions with modulus values) related to columns with a larger delay (e.g., latency) are performed further down in the adder tree (e.g., after additions related to columns with smaller expected delays). In fact, a specific sum (for example, the value output by the first part 106 of the adder circuit 104) can be determined before other LUTs (for example, LUTs 102C, 102D) output their modulus values.

[0031] Continuing with the diagrams, Figure 7 is a block diagram generally similar to Figure 4, further including an adder circuit 120 (including adder 122) used to reduce the sum of 96 in row 94 of the sum 96. In particular, adder 122 may be an adder that receives one of the sums 96 and a carry-out value from a preceding column (e.g., column 90 immediately to the right of column 90 in which a given adder 122 is located). That is, each of the adders 122 may add a carry-out bit (a word-growth bit such as bit 98) from the sum 96 to a bit of the next highest sum (in which case the carry-out bit 98 may be the same size as the n least significant bits of the next highest sum, where n is the number of bit values ​​in a given carry-out value). Thus, any additional carries in each column (e.g., bit 98) are reduced by adding each column again individually. Since there is no carry across columns, the carry-out from column reduction is added to the next highest-ranking column. Furthermore, the sums 124 produced by some of the adders 122 (e.g., sums 124A to 124G) may contain extra bits (e.g., bit 126), where the extra bit 126 is a single bit instead of some carry bits appearing in row 128 of sum 124. These extra bits 98 can be removed by performing the addition again. For example, any single bit 126 can be treated as a carry-out value added to the sum from a column one digit higher (e.g., column 90 immediately to the left).

[0032] However, while adders can be used to reduce the number of word-growth and carry-out bits, they can be relatively expensive in terms of the amount of space they occupy on the integrated circuit device 12 and the latency associated with the several steps of addition that must be performed. For example, when a 27-bit DSP block is used to perform multiplication with a 128-bit multiplier, the 128-bit multiplier can be represented by the following 5-term polynomial: a4x 4 +a3x 3 +a2x 2 +a1x+a0 Here, each a coefficient is a 26-bit value. In this case, there may be six columns 90 of partial products 92 to be reduced (e.g., by removing or reducing the amount of word growth), and the maximum depth of a column 90 is 9, meaning that a given example 90 may have up to nine subproducts 92. In this example, up to four 2-input adders will be required to calculate the sum 96 of each column 90. Furthermore, the six columns are reduced (e.g., by utilizing the modulus value of each column generated by LUT 102), and up to three 2-input adders will be required to perform addition on the reduced values. Thus, a total of seven adder circuits will be required in total. Ignoring the cost of the DSP block or modulo LUT, adding the final carry-reduction adder circuit can increase the amount of area used by the adder circuit by approximately 15%.

[0033] Continuing with the drawings, Figure 8 represents an adder circuit 140A that can be used to add subproducts 92 to determine the sum 96 of column 90. Adder circuit 140A may also be used to perform addition with modulus values. In particular, adder circuit 140A includes a first adder tree 142A, a second adder tree 144A, and a third adder tree 146A, which are independent of each other. Each of the adder trees 142A, 144A, and 146A includes an adder 148, which is a two-input adder. For example, the first adder tree 142A includes a two-stage adder 148 that can determine the sum of three inputs. The second adder tree 144A includes a three-stage adder 148 that can determine the sum of five inputs. The third adder tree 146A includes a four-stage adder 148 that can determine the sum of seven inputs. It should be noted that the adder circuit 140A is not limited to those including adder trees 142A, 144A, and 146A. In other embodiments, the adder circuit 140A may include other adder trees. For example, the adder circuit 140A may include a 9-input adder tree including a 4-stage adder 148. Thus, the adder circuit 140A (as well as the adder circuits 140B and 140C described later) may include any appropriate number of adder trees, each adder tree may include any appropriate number of adders (e.g., adder 148, or a 3-level adder, as described below) arranged in any appropriate number of stages.

[0034] An adder tree (for example, one of adder trees 142A, 144A, or 146A) may be used to sum the subproducts in column 90. Since each of the columns 90 can contain a different number of subproducts, adder trees capable of adding different amounts of input may be used. For example, the first adder tree 142A may be used to sum the subproducts of column 90 that have three (or fewer) subproducts. Since the various adder trees 142A, 144A, and 146A may have different amounts of input (e.g., vertical level) (and adder 148), a particular adder tree may be able to generate the column sum faster than other adder trees that handle more inputs. Furthermore, as mentioned above, the adder trees are independent of each other; that is, if each adder tree sums the subproducts 92 of column 90 without passing any values ​​to the adder tree for a different column 90, more adder circuits will be used to add the columns (for example, to reduce word growth).

[0035] Considering the generally unbalanced nature of adder trees (e.g., adder trees 142A, 144A, 146A), Figure 9 is described here to help reduce the latency associated with using independent adder trees. In particular, Figure 9 represents an adder circuit 140B including adder trees 142A, 144B, and 146B, where adder trees 144B and 146B are different embodiments of adder circuits 144A and 146A, respectively. More specifically, carry-out values ​​from lower-level adders (e.g., adders located to the right in Figure 9) (represented by diagonals 160 and 162) are added to the input (e.g., for the subproduct of the column immediately to the left of the column from which the carry-out value was emitted). Although an adder 164 is added to adder circuit 140B compared to adder circuit 140A in Figure 8, this may be advantageous because the delay of the multiplier circuit 26 (when performing the multiplication operation) is limited by the column with the longest delay.

[0036] With this in mind, the latency associated with the adder circuit 140A in Figure 8 can be further reduced by using a ternary adder, which is an adder that can add three values. For example, in Figure 10, the adder circuit 140C is generally similar to the adder circuit 140A in Figure 8, but the adders 180 (e.g., adders 180A, 180B) included in the adder trees 144C, 146C are ternary adders. Each adder 180 takes three inputs and outputs the sum of the inputs (and, if applicable, the carry-out value). The inputs that adder 180 takes include two values ​​associated with the same column 90 (e.g., two subproducts 92) and the carry-out value (represented by diagonals 182, 184) generated by other adders (e.g., adder 148 in the case of adder 180A, or adder 180A in the case of adder 180B). The carry-in value input to adder 180 is generally less precise than the other two inputs (e.g., a 1, 2, 3, or 4-bit value). For example, two of the inputs may be 26-bit values, and the third input may be a carry-in value containing 1, 2, 3, or 4 bits. However, since ternary addition requires one value that is generally much less precise than the other two values ​​being added (e.g., containing fewer bits), a “full-width” ternary adder capable of summing three values ​​with higher precision (e.g., 26 bits) can be avoided. In fact, as will be discussed later, a ternary adder (e.g., adder 180) may be implemented using a combination of a circuit containing a relatively low-precision ternary adder (or equivalent logic), a 2:2 compressor circuit, and an adder circuit. Thus, the circuit described later can be implemented in programmable logic devices such as FPGAs, regardless of whether the programmable logic device is configured to support ternary adders. For example, to support a three-value adder, a programmable logic device may utilize more wiring (e.g., for data routing) compared to supporting a two-value (i.e., two-input) adder.Furthermore, in some cases, FPGAs or other programmable logic devices may not contain sufficient wiring (or have a sufficiently high wiring density) to support a ternary adder configured to add three "full-width" values. As such, the circuits described later (for example, in relation to Figures 11 and 12) may be implemented on integrated circuit devices that do not support ternary adders.

[0037] With this in mind, Figure 11 represents an adder circuit 200 that may be included in the adder 180 of Figure 10. That is, the adder circuit 200 may be used as a ternary adder in an adder tree, such as an adder tree used to add the subproducts 92 or sums 96 of a column. The adder circuit 200 includes a ternary adder 202, a compressor circuit (e.g., a 2:2 compressor circuit) 204, and an adder circuit 206.

[0038] The three-level adder 202 may accept three n-bit inputs, where n is an integer value equal to the number of bits contained in the carry-out from an adder (e.g., adder 148 in Figure 10). One of the inputs is such a carry-out value, while the other two inputs are the n least significant bits of two values ​​to be added (e.g., value A and value B). For example, the other two inputs may be subproducts 92 of column 90, and such a column may contain more subproducts than the column from which the carry-out value is output. In any case, such a column contains subproducts higher than the column from which the carry-out value is received. The three-level adder 202 may output a value containing n bits, a 1-bit word growth (indicated by "1"), and the carry-out value (indicated by "cout"). Therefore, the three-value adder 202 may add the carry-out value having n bits to another part of the value that also contains n bits (for example, a subproduct, a value determined by adding up subproducts, or a combination thereof).

[0039] The ternary adder 202 may typically be implemented in several different ways depending on the value of n. For example, the ternary adder 202 may be implemented as a lookup table when n is a relatively small number of bits, such as 1 or 2 bits. The lookup table may be implemented in the soft logic of the integrated circuit device 12. As a more specific example, LUT 6 may be used when n is 2. In other embodiments, including embodiments targeting inputs having other n-bit values, other circuits of the integrated circuit device 12, such as logic implemented in the soft logic of the integrated circuit device 12 when the integrated circuit device 12 is an FPGA, may be used. An example of such logic is shown in Figure 12 and will be described in more detail below.

[0040] Continuing the description of the adder circuit 200, the compressor circuit 204 includes several half-adders (e.g., half-adder 208) used to logically shift one of the two inputs that is not a carry-out value. More specifically, the compressor circuit 204 may be a 2:2 compressor circuit that receives bits from inputs A and B (e.g., bits of the subproducts of the sequences to be added, or bits of the sum produced by adding the two subproducts) in addition to what is supplied to the ternary adder 202, and generates two new outputs NA and NB such that NA has the alignment of A and NB has the alignment of B shifted one position to the left. For example, the compressor circuit 204 may be configured such that a "0" is inserted at the least significant bit position of input B to generate output NB. Furthermore, each half-adder includes an XOR gate 210 and an AND gate 212. In the case of the half-adder 208, the AND gate 212 receives the word growth bit from the ternary adder (as indicated by "1").

[0041] Since the bits of the second output (e.g., output NB) are shifted left by one position relative to the second input (e.g., input B), the least significant bit of output NB can be considered "free". In other words, the output of the compressor circuit 204 supplied to the adder circuit 206 may be input NA (having the same alignment as input A) and input NB (having the alignment of input B, shifted left by one position). Furthermore, the carry-out bit from the ternary adder 202 (indicated by "cout") is supplied to the adder circuit 206 and can be treated as if it were the least significant bit of the input to be added.

[0042] The adder circuit 206 includes binary (i.e., 2-input) adders 214 (e.g., adders 214A to 214D) that add the bits received from the compressor circuit 204. In particular, each adder 214 may add two inputs (e.g., a 26-bit value) and a carry-in value (e.g., a carry-out value received as a carry-in value from the previous adder, or, in the case of adder 214D, a carry-out value from the ternary adder 202). Thus, the adder circuit 206 may be used to add the value of any bit in a bit position higher than n. For example, when n is equal to 2, the adder circuit 206 may be used to add the third least significant bit of the input with any higher bits of the input. In such a case, the adder circuit 206 may be used to perform addition (e.g., binary addition) on bits of the input that are not added by the ternary adder 202.

[0043] Before continuing to describe Figure 12, it should be noted that the adder circuit 200 in Figure 11 may be only a small part of the circuitry included in the ternary adder 202 in Figure 10. For example, in other embodiments, the compressor circuit 204 may include more half-adders 208 than those shown in Figure 11 (e.g., tens, hundreds, or thousands of half-adders 208), and the adder circuit 206 may include more adders 214 than those shown in Figure 11. For example, there may be the same number of adders 214 as there are half-adders 208 in the compressor circuit 204. In such a case, the adder circuit 200 may be configured to perform addition on values ​​having a specific number of bits. This can further reduce latency associated with performing modular multiplication operations and reduce the amount of area occupied by the integrated circuit device 12 by the adder circuit (or other circuitry used when performing multiplication operations).

[0044] Continuing with the drawings, Figure 12 is a block diagram of a ternary adder circuit 240 that may be used as the ternary adder 202 of Figure 11. More specifically, the ternary adder circuit 240 may be used to add three inputs, each having 5 bits (i.e., three inputs where n is equal to 5). As shown, the ternary adder circuit 240 includes various types of logic blocks, such as an XOR logic block 242, a majority voting function block 244 (for example, a circuit that outputs "1" if more than half of the inputs are true (e.g., have the value "1"), and an AND function block 246. Furthermore, the ternary adder circuit 240 includes an adder 248 that takes the outputs of several logic blocks as inputs and adds those inputs. As shown, the adder 248 may each take two inputs and a carry-in value to produce a sum and a carry-out value.

[0045] With the above description in mind, an example of the implementation of the multiplier circuit 26 will now be described. In this example, the integrated circuit device 12 may be a programmable logic device. More specifically, the programmable logic device may be an FPGA. The multiplier circuit 26 may be implemented using a combination of hardware and software logic of the FPGA. That is, a multiplication operation (e.g., modular multiplication) may be performed using a combination of hardware logic on the FPGA that is not generally modifiable or programmable by the end user and software logic on the FPGA that is modifiable or programmable by the end user. In this example, the multiplier circuit 26 may include one or more DSP blocks implemented in hardware logic that are used to multiply the inputs to produce subproducts. For example, as described above, a DSP block can multiply a generally lower precision value derived from two relatively high precision values ​​to be multiplied, and the subproduct is the value produced by the DSP block when performing a multiplication operation using generally lower precision values. As such, a DSP block may produce a sequence of the above subproducts.

[0046] The multiplier circuit may also include an adder circuit, such as an adder tree as described herein, which is used to sum a sequence of subproducts. The adder tree may be implemented in the hard logic or soft logic of the FPGA, but for the example described here, the adder tree is implemented in soft logic. Furthermore, routing circuits from the DSP block to the adder tree and the circuits that make up the adder tree itself (e.g., logic blocks) may be implemented using the soft logic of the FPGA. More specifically, there may be one adder tree for each sequence of subproducts that contains more than one subproduct.

[0047] As described above, an adder tree may include various types of adders, such as binary adders and ternary adders. Furthermore, adder trees for columns may be linked together in a communicative manner as described above, so that carry-out values ​​associated with a column can be supplied to other columns (e.g., binary or ternary adders in columns higher than the column from which the carry-out values ​​were generated). For example, an adder tree may include combinations of binary and ternary adders, including an implementation of a ternary adder shown in Figure 11, which includes a ternary adder circuit, a compressor circuit (2:2 compressor circuit), and a binary adder circuit. Furthermore, as shown in Figure 10 and described above, a ternary adder included in an adder tree may receive two values ​​that are either subproducts derived from subproducts (e.g., the sum of subproducts determined when determining the sum of the entire column of subproducts) or a combination thereof. A ternary adder may also receive a carry-in value, which is a carry-out value generated by an adder circuit in another adder tree. Furthermore, the adder tree can ultimately produce the sum of a sequence containing single-bit word growths (e.g., shown in Figure 7).

[0048] The multiplier circuit 26 may also include a lookup table that each receives the sum of a particular column. For example, the lookup table may receive a value containing more bits than the value being multiplied to produce the subproduct. That is, the output of each column having a rank higher than the input argument size (e.g., the sum) may be fed into a lookup table that performs a modulo operation and outputs the modulus of the input.

[0049] The multiplier circuit 26 may include additional adder circuits, which may include an adder tree used to add the modulus values ​​generated by the lookup table. Furthermore, the additional adder circuits may add other values ​​(e.g., sums from columns whose modulus has not been determined) to the modulus value. As described above (for example, in relation to Figure 6), the additional adder circuits may sum the modulus values ​​in an order relating to the number of subproducts of the column from which a given modulus value is generated. For example, columns with relatively fewer subproducts may be summed faster. That is, the modulus value of such a column may be generated faster than the modulus value of a column with a relatively larger number of subproducts.

[0050] With the above in mind, the integrated circuit device 12 may include a multiplier circuit 26 that can provide an interface for connecting to other integrated circuit devices. Furthermore, the integrated circuit device 12 may be a data processing system or a component included in a data processing system. For example, the integrated circuit device 12 may be a component of the data processing system 270 shown in Figure 13. The data processing system 270 may include a host processor 272 (e.g., a central processing unit (CPU)), memory and / or storage circuits 274, and a network interface 276. The data processing system 270 may include more or fewer components (e.g., electronic displays, user interface structures, application-specific integrated circuits (ASICs)). The host processor 272 may include any suitable processor, such as an INTEL Xeon processor or a reduced instruction processor (e.g., a Reduced Instruction Set Computer (RISC), an Advanced RISC Machine (ARM) processor), that can manage data processing requests to the data processing system 270 (for example, to perform encryption, decryption, machine learning, video processing, speech recognition, image recognition, data compression, database search ranking, bioinformatics, network security pattern identification, spatial navigation, cryptocurrency computation, etc.). The memory and / or storage circuit 274 may include random access memory (RAM), read-only memory (ROM), one or more hard drives, flash memory, etc. The memory and / or storage circuit 274 can hold data to be processed by the data processing system 270. In some cases, the memory and / or storage circuit 274 may also store a configuration program (bitstream) for programming the integrated circuit device 12. The network interface 276 may allow the data processing system 270 to communicate with other electronic devices. The data processing system 270 may include several different packages, or it may be contained within a single package on a single package substrate.For example, the components of the data processing system 270 may be located in one location (e.g., a data center) or in several different packages located in multiple locations. For example, the components of the data processing system 270 may be located in separate geographical locations or regions, such as cities, states, or countries.

[0051] For example, the data processing system 270 may be a part of a data center that handles a variety of different requests. For instance, the data processing system 270 may receive data processing requests via the network interface 276 to perform encryption, decryption, machine learning, video processing, speech recognition, image recognition, data compression, database search ranking, bioinformatics, network security pattern identification, spatial navigation, digital signal processing, or other specialized tasks.

[0052] Furthermore, in some embodiments, the multiplier circuit 26 and the data processing system 270 may be virtualized. That is, one or more virtual machines may be used to implement software-based representations of the multiplier circuit 26 and the data processing system 270 that emulate the functions of the multiplier circuit 26 and the data processing system 270 as described herein. For example, a system (e.g., including one or more computing devices) may include a hypervisor that manages resources associated with one or more virtual machines and may assign one or more virtual machines to emulate the multiplier circuit 26 or the data processing system 270 to perform the multiplication and other operations described herein.

[0053] Therefore, the techniques described herein enable multiplication (e.g., modular multiplication) to be performed faster (i.e., with reduced latency), and the circuits used to perform multiplication occupy less physical space on the integrated circuit device compared to other circuits that could also be used to perform multiplication. For example, three-level addition, when available, can significantly reduce the latency of the overall structure of the circuits used to perform (modular) multiplication operations. This can be half the latency of using a two-input adder. For example, a nine-element reduction would require four stages of two-input adders, but when a three-level adder is used in the manner described herein, only two stages are used. Thus, even if the three-level adder used may be routing-intensive, the three-level structures described herein, which are divided into a combinational part and a carry-based part, can significantly reduce latency. In fact, the number of stages in a nine-element reduction is the same as in the two-input case, but the combinational alternative stages can be deployed much more easily, thus resulting in lower latency. As such, the technical effects of this disclosure include performing modular multiplication with reduced latency while using circuits in which the amount of space used on the integrated circuit is reduced.

[0054] While the embodiments described herein are susceptible to various modifications and alternative forms, specific embodiments are shown as examples in the drawings and described in detail herein. However, it should be understood that this disclosure is not intended to be limited to any particular form disclosed. This disclosure should cover all modifications, equivalents, and alternatives that fall within the spirit and scope of this disclosure as defined by the subsequent appended claims.

[0055] The technologies presented and claimed herein clearly improve the art and, as such, are applied to and refer to physical objects and specific examples of an abstract, intangible, or purely theoretical practical nature. Furthermore, if any of the claims appended to the end of this specification contain one or more elements expressed as “means to ~(function)” or “steps to ~(function),” such elements are intended to be construed under 35 U.S.C. 112(f). However, if any claim contains elements expressed in any other way, such elements are not intended to be construed under 35 U.S.C. 112(f).

[0056] Exemplary embodiments of the present disclosure The following numbered annotations define specific examples of embodiments of this disclosure.

[0057] [Note 1] A multiplier circuit configured to determine multiple columns of a subproduct by multiplying multiple values, wherein the multiple columns of the subproduct include multiple subproducts, and each column of the multiple columns includes one or more subproducts from the multiple subproducts, An adder circuit configured to determine the sum of multiple sums, wherein each sum of the multiple sums is the sum of one of the multiple columns, and a first part of the adder circuit associated with the first column of the multiple columns is configured to receive a first value associated with the first column, a second value associated with the first column, and a third value associated with a second column of the multiple columns that is different from the first column, wherein the third value is a carry-out value generated by a second part of the adder circuit associated with the second column of the multiple columns. An integrated circuit device that contains [something].

[0058] [Note 2] Having one or more lookup tables configured to generate multiple modulus values ​​from a portion of the aforementioned sums, The integrated circuit device described in Appendix 1.

[0059] [Note 3] The circuit includes a second adder circuit configured to determine the sum of the plurality of modulus values, The integrated circuit device described in Appendix 2.

[0060] [Note 4] The aforementioned multiple modulus values ​​are A first modulus value associated with the third column of the plurality of columns having the first part of the plurality of subproducts, A second modulus value associated with the fourth column of the plurality of columns having a second portion of the plurality of subproducts, wherein the second portion of the plurality of subproducts includes more subproducts than the first portion of the plurality of subproducts, and the second modulus value A third modulus value associated with the fifth column of the plurality of columns having a third portion of the plurality of subproducts, wherein the third portion of the plurality of subproducts includes more subproducts than the second portion of the plurality of subproducts, and the third modulus value, A fourth modulus value associated with the sixth column of the plurality of columns having the fourth portion of the plurality of subproducts, wherein the fourth portion of the plurality of subproducts includes more subproducts than the third portion of the plurality of subproducts, and the fourth modulus value It has, The second adder circuit is configured to determine the first sum of the first modulus value and the second modulus value before the third modulus value, the fourth modulus value, or both are determined. The integrated circuit device described in Appendix 3.

[0061] [Note 5] The second adder circuit is, After determining the first sum, the second sum of the third modulus value and the fourth modulus value is determined. After determining the two sums mentioned above, determine the third sum of the first and second sums mentioned above. Structured in such a way The integrated circuit device described in Appendix 4.

[0062] [Note 6] The first part of the adder circuit is A three-value adder circuit configured to add the first part of the first value, the second part of the second value, and the third value, wherein the first part of the first value, the second part of the second value, and the third value each include a first number of bits, A compressor circuit is communicatively coupled to the three-value adder circuit and configured to receive the first remainder of the first value and the second remainder of the second value, wherein the first remainder of the first value and the second remainder of the second value each contain a second number of bits that are greater than the first number of bits, A binary adder circuit is configured to be communicatively connected to the compressor circuit and to output the sum of the first residual portion of the first value and the second residual portion of the second value. Having, The integrated circuit device described in Appendix 1.

[0063] [Note 7] The compressor circuit is configured to left-shift the bits of the second residual portion of the second value, The binary adder circuit is configured to receive a second carry-out value generated by the ternary adder circuit. The integrated circuit device described in Appendix 6.

[0064] [Note 8] The integrated circuit device has a field-programmable gate array (FPGA). The integrated circuit device described in Appendix 1.

[0065] [Note 9] The multiplier circuit has one or more digital signal processing (DSP) blocks of the FPGA. The integrated circuit device described in Appendix 8.

[0066] [Note 10] The multiplier circuit is implemented in the hard logic of the FPGA. The adder circuit is implemented in the software logic of the FPGA. The integrated circuit device described in Appendix 8.

[0067] [Note 11] The aforementioned adder circuit is, A three-value adder circuit implemented in the software logic of the FPGA, A compressor circuit implemented in the software logic of the FPGA, A binary adder circuit implemented in the software logic of the FPGA, or those combinations Having, The integrated circuit device described in Appendix 10.

[0068] [Note 12] The multiplier circuit of the integrated circuit device determines multiple columns of a subproduct by multiplying multiple values, wherein the multiple columns of the subproduct include multiple subproducts, and each column of the multiple columns includes one or more subproducts from the multiple subproducts. The adder circuit of the integrated circuit device determines multiple sums, and each of the multiple sums is the sum of one of the multiple columns. It has, Determining the sum of the aforementioned multiple means The first part of the adder circuit associated with the first column of the plurality of columns receives a first value associated with the first column, a second value associated with the first column, and a third value associated with a second column of the plurality of columns that is different from the first column, wherein the third value is a carry-out value generated by the second part of the adder circuit associated with the second column of the plurality of columns. The first part of the adder circuit determines the sum of the first part of the first value, the second part of the second value, and the third value. Having, method.

[0069] [Note 13] The aforementioned integrated circuit device has the capability to generate a plurality of modulus values ​​from a portion of the plurality of sums, The method described in Appendix 12.

[0070] [Note 14] The process involves adding the modulus values ​​in an order based on the latency associated with determining the sum of the aforementioned modulo values. The method described in Appendix 13.

[0071] [Note 15] The first part of the adder circuit determines the sum of the remainder of the first value and the remainder of the second value. The method described in Appendix 12.

[0072] [Note 16] The aforementioned integrated circuit device includes a programmable logic device. The method described in Appendix 12.

[0073] [Note 17] A programmable logic device configurable to be programmed to perform modular multiplication, When programmed, the programmable logic device is A multiplier circuit configured to determine multiple columns of a subproduct by multiplying multiple values, wherein the multiple columns of the subproduct include multiple subproducts, and each column of the multiple columns includes one or more subproducts from the multiple subproducts, An adder circuit, at least partially implemented in the programmable logic of the programmable logic device and configured to determine a plurality of sums, wherein each of the plurality of sums is the sum of one of the plurality of columns, and a first part of the adder circuit associated with the first column of the plurality of columns is configured to receive a first value associated with the first column, a second value associated with the first column, and a third value associated with a second column of the plurality of columns different from the first column, wherein the third value is a carry-out value generated by a second part of the adder circuit associated with the second column of the plurality of columns, and Having, Programmable logic device.

[0074] [Note 18] The multiplier circuit has a digital signal processing (DSP) circuit implemented in the non-programmable portion of the programmable logic device. Programmable logic devices as described in Appendix 17.

[0075] [Note 19] The third value has a first number of bits, The first portion of the adder circuit has a lookup table configured to receive a first input, a second input, and a third input, each having bits of the first number, The first input is the first part of the first value, the second input is the second part of the second value, and the third input is the third value. Programmable logic devices as described in Appendix 17.

[0076] [Note 20] The programmable logic device has a field-programmable gate array (FPGA). Programmable logic devices as described in Appendix 17. [Explanation of symbols]

[0077] 10 Systems 12. Integrated Circuit Devices 14 Design Software 16 Compilers 18 Hosts 20 Kernel Programs 22 Host Programs 24 Communication Links 26 Multiplier Circuit 42 Input / Output Circuit 42 46 Interconnected Resources 48 Programmable Logic 90 columns 92 Subproduct 92 96,124 sum 100 Multiplier Blocks 102 LUT 104,200 Adder Circuit 140A~C Adding Circuit 142A~C Adder Tree 144A~C Adder Tree 146A~C Adder Tree 202 Three-level adder 204 Compressor Circuit 206 Adder Circuit 270 Data Processing Systems

Claims

1. A multiplier circuit configured to determine multiple columns of a subproduct by multiplying multiple values, wherein the multiple columns of the subproduct include multiple subproducts, and each column of the multiple columns includes one or more subproducts from the multiple subproducts, An adder circuit configured to determine the sum of multiple sums, wherein each sum of the multiple sums is the sum of one of the multiple columns, and a first part of the adder circuit associated with the first column of the multiple columns is configured to receive a first value associated with the first column, a second value associated with the first column, and a third value associated with a second column of the multiple columns that is different from the first column, wherein the third value is a carry-out value generated by a second part of the adder circuit associated with the second column, One or more lookup tables configured to generate multiple modulo values ​​from a portion of the aforementioned sums, An integrated circuit device that contains [something].

2. The circuit includes a second adder circuit configured to determine the sum of the plurality of modulus values, The integrated circuit device according to claim 1.

3. The aforementioned multiple modulus values ​​are A first modulus value associated with the third column of the plurality of columns having a first portion of the plurality of subproducts, A second modulus value associated with the fourth column of the plurality of columns having a second portion of the plurality of subproducts, wherein the second portion of the plurality of subproducts includes more subproducts than the first portion of the plurality of subproducts, and the second modulus value A third modulus value associated with the fifth column of the plurality of columns having a third portion of the plurality of subproducts, wherein the third portion of the plurality of subproducts includes more subproducts than the second portion of the plurality of subproducts, and the third modulus value, A fourth modulus value associated with the sixth column of the plurality of columns having the fourth portion of the plurality of subproducts, wherein the fourth portion of the plurality of subproducts includes more subproducts than the third portion of the plurality of subproducts, and the fourth modulus value It has, The second adder circuit is configured to determine the first sum of the first modulus value and the second modulus value before the third modulus value, the fourth modulus value, or both are determined. The integrated circuit device according to claim 2.

4. The second adder circuit is, After determining the first sum, the second sum of the third modulus value and the fourth modulus value is determined. After determining the two sums mentioned above, the third sum of the first sum and the second sum is determined. Structured in such a way The integrated circuit device according to claim 3.

5. The first part of the adder circuit is A three-value adder circuit configured to add the first part of the first value, the second part of the second value, and the third value, wherein the first part of the first value, the second part of the second value, and the third value each include a first number of bits. A compressor circuit is communicatively coupled to the three-value adder circuit and configured to receive the first residual portion of the first value and the second residual portion of the second value, wherein the first residual portion of the first value and the second residual portion of the second value each contain a second number of bits that are greater than the first number of bits, A binary adder circuit is configured to be communicatively coupled to the compressor circuit and to output the sum of the first residual portion of the first value and the second residual portion of the second value. Having, An integrated circuit device according to any one of claims 1 to 4.

6. The compressor circuit is configured to left-shift the bits of the second residual portion of the second value, The binary adder circuit is configured to receive a second carry-out value generated by the ternary adder circuit. The integrated circuit device according to claim 5.

7. The integrated circuit device has a field-programmable gate array (FPGA). An integrated circuit device according to any one of claims 1 to 6.

8. The multiplier circuit has one or more digital signal processing (DSP) blocks of the FPGA, and the number of DSP blocks is determined based at least on the bit width that each DSP block can process and the number of bits in the value to be multiplied by the multiplier circuit. The integrated circuit device according to claim 7.

9. The multiplier circuit is implemented using the hard logic of the FPGA. The adder circuit is implemented in the software logic of the FPGA. The integrated circuit device according to claim 7.

10. The aforementioned adder circuit is, A three-value adder circuit implemented in the software logic of the FPGA, A compressor circuit implemented in the software logic of the FPGA, A binary adder circuit implemented in the software logic of the FPGA, or those combinations Having, The integrated circuit device according to claim 9.

11. The multiplier circuit of the integrated circuit device determines multiple columns of a subproduct by multiplying multiple values, wherein the multiple columns of the subproduct include multiple subproducts, and each column of the multiple columns includes one or more subproducts from the multiple subproducts. The adder circuit of the integrated circuit device determines multiple sums, and each of the multiple sums is the sum of one of the multiple columns. The aforementioned integrated circuit device generates multiple modulus values ​​from a portion of the multiple sums. It has, Determining the sum of the aforementioned multiple means The first part of the adder circuit associated with the first column of the plurality of columns receives a first value associated with the first column, a second value associated with the first column, and a third value associated with the second column of the plurality of columns that is different from the first column, wherein the third value is a carry-out value generated by the second part of the adder circuit associated with the second column of the plurality of columns. The first part of the adder circuit determines the sum of the first part of the first value, the second part of the second value, and the third value. Having, method.

12. The process involves adding the modulus values ​​in an order based on the latency associated with determining the sum of the aforementioned modulo values. The method according to claim 11.

13. The first part of the adder circuit determines the sum of the remainder of the first value and the remainder of the second value. The method according to claim 11 or 12.

14. The aforementioned integrated circuit device includes a programmable logic device. The method according to any one of claims 11 to 13.

15. A programmable logic device configurable to be programmed to perform modular multiplication, When programmed, the programmable logic device is A multiplier circuit configured to determine multiple columns of a subproduct by multiplying multiple values, wherein the multiple columns of the subproduct include multiple subproducts, and each column of the multiple columns includes one or more subproducts from the multiple subproducts, An adder circuit, at least partially implemented in the programmable logic of the programmable logic device and configured to determine a plurality of sums, wherein each of the plurality of sums is the sum of one of the plurality of columns, and a first part of the adder circuit associated with a first column of the plurality of columns is configured to receive a first value associated with the first column, a second value associated with the first column, and a third value associated with a second column of the plurality of columns that is different from the first column, wherein the third value is a carry-out value generated by a second part of the adder circuit associated with a second column of the plurality of columns, and Having, Programmable logic device.

16. The multiplier circuit has a digital signal processing (DSP) circuit implemented in the non-programmable portion of the programmable logic device. The programmable logic device according to claim 15.

17. The third value has a first number of bits, The first portion of the adder circuit has a lookup table configured to receive a first input, a second input, and a third input, each having a bit of the first number, The first input is the first part of the first value, the second input is the second part of the second value, and the third input is the third value. The programmable logic device according to claim 15 or 16.

18. The programmable logic device has a field-programmable gate array (FPGA). A programmable logic device according to any one of claims 15 to 17.

19. A means for determining multiple columns of a subproduct by multiplying multiple values, wherein the multiple columns of the subproduct include multiple subproducts, and each column of the multiple columns includes one or more subproducts from the multiple subproducts, A means for determining multiple sums, wherein each of the multiple sums is the sum of one of the multiple columns, means for generating multiple modulus values ​​from a portion of the aforementioned multiple sums, It has, The means for determining the sum of the aforementioned multiple sums is, A means for receiving a first value associated with the first column of the plurality of columns, a second value associated with the first column, and a third value associated with the second column of the plurality of columns that is different from the first column, wherein the third value is a carry-out value, the receiving means, Means for determining the sum of the first part of the first value, the second part of the second value, and the third value. Having, system.

20. The means for adding the plurality of modulus values ​​in an order based on the latency associated with determining the plurality of sums, The system according to claim 19.

21. A multiplier circuit configured to determine multiple columns of a subproduct by multiplying multiple values, wherein the multiple columns of the subproduct include multiple subproducts, and each column of the multiple columns includes one or more subproducts from the multiple subproducts, An adder circuit configured to determine multiple sums corresponding to the sum of one of the multiple columns, One or more lookup tables configured to generate multiple modulo values ​​from a portion of the aforementioned sums, A digital signal processing circuit having the following features.

22. The first part of the adder circuit associated with the first column among the plurality of columns is configured to receive a first value associated with the first column, a second value associated with the first column, and a third value associated with the second column among the plurality of columns that is different from the first column. The third value is the carry-out value generated by the second part of the adder circuit associated with the second column. The digital signal processing circuit according to claim 21.

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