Implementation for detecting faults or failures on the analog input path for a single analog input functional safety application

Abstract

To detect a failure or fault on an analog input path.SOLUTION: An analog fault detection system 100 comprises an analog fault detection circuit 104 comprising an input terminal 114, an input circuit path 116 coupled to the input terminal at a first end, and a first sampling switch 128 coupled to a second end of the input circuit path. The switch samples an input path voltage at the second end of the input circuit path to provide a first analog / digital converter (ADC) input voltage Vin_ADC1. The analog fault detection circuit further comprises a first ADC conversion circuit for converting the first ADC input voltage to a first digital ADC output Vout_ADC1 and a first broken wire detection circuit 138 coupled between the switch and the first ADC conversion circuit and adaptively pulls down or pulls up the first ADC input voltage in order to detect a fault associated with a first analog circuit path.SELECTED DRAWING: Figure 1

Description

Technical Field

[0002]

[0001] The present disclosure relates to analog inputs in electronic circuits, and more particularly to systems and methods for detecting faults or disorders on an analog input path from an analog source circuit to an analog / digital converter (ADC) in an electronic circuit.

Background Art

[0002] Functional safety is part of an overall safety strategy in many industries and aims to reduce the risk of harm to humans or operating equipment to an acceptable level. The requirement for systems to be functionally safe has increased significantly in recent years. From nuclear power plants to medical devices and automotive systems, a faultless system is the ultimate goal for some and an essential requirement for others. For example, in the world of sensing, obtaining incorrect or tampered data can lead to significant damage, depending on the system and the level of risk involved, and in some cases, it can be fatal. Similarly, with the advent of autonomous driving and autonomous vehicles, as automotive manufacturers compete to free drivers from their daily commutes, the role of functional safety in the electronic devices that enable this attractive future has become even more significant and important.

[0003] Hereinafter, some examples of circuits, devices, and / or methods will be described by way of example only. Reference will be made to the accompanying drawings in this regard.

Brief Description of the Drawings

[0004] [Figure 1] It is a diagram showing a simplified block diagram of an analog fault detection system according to one embodiment of the present disclosure. [Figure 2] It is a flowchart showing an algorithm used by an analog fault detection circuit to detect a fault in a first analog circuit path or a second analog circuit path. [Figure 3a] This figure shows one possible embodiment of the change over time of the first ADC input voltage Vin_ADC1 while an algorithm for detecting faults in the first analog circuit path is being executed. [Figure 3b] This figure shows another possible embodiment of the change over time of the first ADC input voltage Vin_ADC1 while an algorithm for detecting faults in the first analog circuit path is being executed. [Figure 4] This figure shows one possible implementation of an analog-to-digital converter (ADC) circuit related to an analog fault detection system according to one embodiment of the present disclosure. [Figure 5] This is a flowchart showing a method for an analog fault detection system according to one embodiment of the present disclosure. [Modes for carrying out the invention]

[0005] According to one embodiment of the present disclosure, an analog fault detection circuit is disclosed. The analog fault detection circuit includes an input terminal configured to be coupled to an analog source circuit, and an input circuit path having a first termination and a second termination, the first termination of which is coupled to the input terminal. The analog fault detection circuit further includes a first analog-to-digital converter (ADC) circuit, the first analog-to-digital converter (ADC) circuit including a first ADC converter circuit configured to convert a first ADC input voltage to a first digital ADC output, and a first ADC circuit path coupled between the second termination of the input circuit path and the first ADC converter circuit. The first ADC circuit path includes a first sampling switch, the first terminal of which is coupled to the second termination of the input circuit path. According to some embodiments, the first sampling switch is configured to sample the input path voltage at the second termination of the input circuit path to supply a first ADC input voltage at the second terminal of the first sampling switch. The first ADC circuit further includes a first disconnection detection circuit coupled between the first sampling switch and the first ADC conversion circuit, configured to adaptively pull down or pull up the first ADC input voltage to detect faults related to the first analog circuit path. According to some embodiments, the first analog circuit path includes an analog source circuit, an input circuit path, and the first ADC circuit path.

[0006] According to one embodiment of the present disclosure, an analog fault detection system is disclosed. The analog fault detection system includes an analog source circuit and an analog fault detection circuit. The analog fault detection circuit includes an input terminal configured to be coupled to the analog source circuit and an input circuit path having a first termination and a second termination, the first termination of which is coupled to the input terminal. The analog fault detection circuit further includes a first analog-to-digital converter (ADC) circuit, the first analog-to-digital converter (ADC) circuit including a first ADC converter circuit configured to convert a first ADC input voltage to a first digital ADC output and a first ADC circuit path coupled between the second termination of the input circuit path and the first ADC converter circuit. The first ADC circuit path includes a first sampling switch, the first terminal of which is coupled to the second termination of the input circuit path. According to some embodiments, a first sampling switch is configured to sample the input path voltage at a second termination of the input circuit path to supply a first ADC input voltage at a second terminal of the first sampling switch. The first ADC circuit further includes a first disconnection detection circuit coupled between the first sampling switch and the first ADC conversion circuit, which is configured to adaptively pull down or pull up the first ADC input voltage to detect a fault related to the first analog circuit path. According to some embodiments, the first analog circuit path includes an analog source circuit, an input circuit path, and a first ADC circuit path.

[0007] According to one embodiment of the present disclosure, a method for an analog fault detection circuit is disclosed. The method includes coupling an input terminal associated with the analog fault detection circuit to an analog source circuit and converting a first analog-to-digital converter (ADC) input voltage to a first digital ADC output using a first ADC converter circuit. The method further includes using a first sampling switch to sample the input path voltage at a second termination of the input circuit path to form a first ADC input voltage. According to some embodiments, the first termination of the input circuit path is coupled to an input terminal, and the second termination of the input circuit path is coupled to the first sampling switch. According to some embodiments, the first sampling switch is included in a first ADC circuit path coupled between the second termination of the input circuit path and the first ADC converter circuit. According to some embodiments, the method further includes using a first open circuit detection circuit coupled between the first sampling switch and the first ADC converter circuit to adaptively pull up or pull down the first ADC input voltage in order to detect a fault associated with the first analog circuit path. According to some embodiments, the first analog circuit path includes an analog source circuit, an input circuit path, and a first ADC circuit path.

[0008] Next, the present disclosure will be described with reference to the attached drawings. In this case, the same reference numerals throughout the drawings are used to refer to the same elements, and the illustrated structures and devices are not necessarily drawn to scale. The terms “component,” “system,” “interface,” “circuit,” “module,” and similar terms used herein are intended to refer to computer-related entities, hardware, software (e.g., running), and / or firmware. For example, a component may be a processor (e.g., a microprocessor, controller, or other processing unit), a process running on a processor, a controller, an object, an executable file, a program, a storage device, a computer, a tablet PC, and / or a user device (e.g., a mobile phone) equipped with a processing unit. For example, an application running on a server and the server itself may also be a component. One or more components may reside in a single process, one component may reside locally on a single computer, and / or may be distributed across two or more computers. In this specification, a set of elements or other sets of components may be described, and the term “set of” may be interpreted as “one or more.”

[0009] In another embodiment, one component may be a device having a specific function provided by mechanical parts operated by an electrical or electronic circuit, in which case the electrical or electronic circuit may be operated by a software application or firmware application run by one or more processors. The one or more processors may be located inside or outside the device and may run at least a portion of the software application or firmware application. In yet another embodiment, one component may be a device that provides a specific function via electronic components without using mechanical parts. These electronic components may contain one or more processors, which run software and / or firmware that at least partially provides the functionality of the electronic components.

[0010] The use of the word "exemplary" is intended to present the concept concretely. The term "or" as used in this application is intended to mean inclusive "or," not exclusive "or." That is, unless otherwise specified or evident from the context, "X uses A or B" is intended to mean any of the natural inclusive sortings. That is, if X uses A, if X uses B, or if X uses both A and B, "X uses A or B" is satisfied in any of the above examples. In addition, unless otherwise specified or evident from the context, singular indefinite articles used in this application and the attached claims should generally be interpreted as meaning "one or more." Furthermore, where the terms "inclusive," "contains," "having," "possessing," "equipped with," or their variants are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "contains."

[0011] The following detailed description refers to the accompanying drawings. The same reference numerals may be used in different drawings to identify identical or similar elements. The following description includes specific details, such as particular structures, architectures, interfaces, and techniques, for illustrative purposes only, not limitation, to provide a complete understanding of the various aspects of the various embodiments. However, as will be apparent to those skilled in the art who are interested in this disclosure, various aspects of the various embodiments can be implemented in other embodiments separate from those specific details. In some examples, descriptions of well-known devices, circuits, and methods have been omitted so as not to obscure the description of the various embodiments with unnecessary details.

[0012] As mentioned above, the role of functional safety in electronic equipment has become larger and more important than ever. ISO 31262 is a functional safety standard used in the automotive industry. The purpose of this standard is to reduce the hazards that may arise from failures and malfunctions of electrical and / or electronic systems in automobiles. Safety requirements for the development process depend on the automotive safety integrity level (ASIL) rating of the target application, which can range from ASIL-A to ASIL-D. Applications such as steering or braking systems are rated at the highest ASIL-D level. Failures in these types of systems can cause the vehicle to become uncontrollable, potentially resulting in fatal damage. In modern safety applications, there are numerous analog inputs that must meet the ASIL levels specified by ISO 31262. In many applications, although the source of the analog input is ASIL A / B, the signal distribution path from the source to the analog-to-digital converter (ADC) is not protected, or requires additional system-level safety mechanisms to cover failure modes. However, for functional safety (especially in single-analog input functional safety applications), it is essential to detect faults or failures in the signal distribution path from the source to the analog-to-digital converter (ADC). In some embodiments, the signal distribution path from the source to the ADC is further referred to as the analog signal path.

[0013] To achieve ASIL levels or functional safety for analog signal paths, some current implementations utilize redundant sources. Specifically, a first source is coupled to a first path (e.g., a mission channel), and a second source is coupled to a second path (e.g., a monitoring channel). Faults in the paths of the first or second source can be detected by validation against the results of various redundant channels. According to some embodiments, the first and second sources are homogeneous sources. Alternatively, according to other embodiments, the first and second sources are heterogeneous sources. According to some embodiments, both the first and second sources are analog sources. In such embodiments, faults in the paths of the first or second source are determined based on the comparison results of ADCs coupled to the first and second paths, respectively. Alternatively, according to other embodiments, the first source may include an analog input, and the second source may be a digital input. However, utilizing redundant sources for functional safety increases the area and power consumption of electronic circuits with analog inputs. Furthermore, using redundant sources limits the number of analog inputs that can be supported in an electronic circuit.

[0014] In some current implementations, to achieve an ASIL level or functional safety for an analog signal path, the same analog input (e.g., an analog source circuit) is connected to at least two ADC channels, each ADC channel containing a corresponding ADC. Each ADC channel further includes a fault detection circuit coupled between the analog input and a sampling switch associated with the individual ADC. The fault detection circuit is configured to adaptively pull up or pull down the input voltage to the sampling switch (or the voltage on the input side of the sampling switch) to detect faults in the analog signal path coupled between the analog input and the corresponding ADC. In some embodiments, a fault in each ADC channel is determined based on the digital ADC output of the individual channel. Specifically, a fault in each ADC channel is determined based on the difference between a first digital ADC output immediately after the pull-up or pull-down is deactivated and a second digital ADC output after a predetermined time has elapsed since the pull-up or pull-down was deactivated.

[0015] For example, if the input voltage to the sampling switch is pulled down and there is no fault in the analog input path, the second ADC output will return to the analog input voltage (supplied by the analog source) because the analog source is connected to the sampling switch. However, if the input voltage to the sampling switch is pulled down and there is a fault in the analog input path, the second ADC output will remain low because the analog source is partially or completely disconnected from the ADC input, thereby allowing the fault to be detected. However, coupling a fault detection circuit between the analog input and the sampling switch results in leakage, which affects the voltage in a capacitor coupled to the analog signal path (between the analog input and the fault detection circuit) (for example, this capacitor may be charged or discharged). Therefore, in such embodiments, even if there is a fault in the analog signal path, the second ADC output will be high due to leakage charge from the capacitor. As a result, fault detection becomes unreliable. To overcome the aforementioned drawbacks, a system and method for reliably detecting a fault or failure in an analog signal path while reducing leakage based on the use of a single analog input is disclosed herein.

[0016] Figure 1 shows a simplified block diagram of an analog fault detection system 100 according to one embodiment of the present disclosure. According to some embodiments, the analog fault detection system 100 includes a portion of an electronic system / circuit that receives an analog input (e.g., coupled to an analog input source). According to some embodiments, the analog fault detection system 100 facilitates the detection of faults or failures related to an analog signal / circuit path that couples an analog source circuit to an analog-to-digital converter (ADC) in an electronic circuit. In addition, according to some embodiments, the analog fault detection system 100 facilitates the detection of faults or failures related to an analog source circuit coupled to an electronic circuit. The analog fault detection system 100 includes an analog source circuit 102 and an analog fault detection circuit 104. According to some embodiments, the analog fault detection circuit 104 can be implemented on a single integrated chip (IC). Optionally, according to other embodiments, the analog fault detection circuit 104 can be implemented on one or more integrated chips (ICs).

[0017] The analog source circuit 102 includes an input source circuit 106 configured to supply an analog input voltage Vin_1. According to some embodiments, the analog source circuit 102 further includes a source circuit path 110 configured to couple the input source circuit 106 to an analog fault detection circuit 104. According to some embodiments, the source circuit path 110 includes an input resistor 108 and an input capacitor C0112. According to alternative embodiments, the source circuit path 110 may include only a conductor pattern and may not include any other components. The analog fault detection circuit 104 is configured to couple to the analog source circuit 102 to receive an analog input voltage Vin. According to some embodiments, the analog input voltage Vin is identical to the analog input voltage Vin_1. According to alternative embodiments, the analog input voltage Vin may differ somewhat from the analog input voltage Vin_1 due to a drop in the source circuit path 110. The analog fault detection circuit 104 is configured to couple to the analog source circuit 102 via an input terminal 114. According to some embodiments, the input terminal 114 is coupled to the source circuit path 110 for coupling with the analog source circuit 102.

[0018] The analog fault detection circuit 104 further includes an input circuit path 116, a first analog-to-digital converter (ADC) circuit 118, and a second ADC circuit 122. The input circuit path 116 includes a first termination and a second termination, the first termination being coupled to an input terminal 114, and the second termination being coupled to a common electrical node 120. According to some embodiments, the second termination of the input circuit path 116 coincides with the common electrical node 120. According to some embodiments, the first input circuit path 116 includes an electrostatic discharge (ESD) protection device 130, which is coupled to an associated ESD node 136. According to some embodiments, the ESD protection device 130 includes a first diode 132 coupled between the ESD node 136 and a positive voltage VDD. In addition, the ESD protection device 130 includes a second diode 134 coupled between the ESD node 136 and earth GND. Other implementations of the ESD protection device 130 are also included within the scope of this disclosure. According to some embodiments, the input circuit path 116 may further include other components coupled to it (e.g., resistors, capacitors, etc.). According to alternative embodiments, the input circuit path 116 may include a conductor pattern that does not have any components coupled to it.

[0019] The first ADC circuit 118 and the second ADC circuit 122 are coupled to the second end of the input circuit path 116 via a common electrical node 120. The first ADC circuit 118 includes a first ADC converter 124 and a first ADC circuit path 126 coupled between the second end of the input circuit path 116 (or the common electrical node 120) and the first ADC converter 124. The first ADC circuit path 126 includes a conductor path and may include one or more components coupled to this conductor path. The first ADC circuit path 126 includes a first sampling switch 128 having a first terminal and a second terminal, the first terminal being coupled to the second end of the input circuit path 116 or the common electrical node 120, and the second terminal being coupled to the first ADC converter 124 (via the first ADC circuit path 126). According to some embodiments, the first sampling switch 128 can be implemented using one or more metal oxide semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), etc. The first sampling switch 128 is configured to sample the input path voltage Vin_path at the second termination of the input circuit path 116 and supply the first ADC input voltage Vin_ADC1 at the second terminal of the first sampling switch 128. According to some embodiments, the input path voltage Vin_path can be the same as the analog input voltage Vin. According to alternative embodiments, the input path voltage Vin_path may differ from the analog input voltage Vin due to some voltage drop in the input circuit path 116. According to some embodiments, the first ADC input voltage Vin_ADC1 includes a sampled version of the input path voltage Vin_path (which is an analog voltage). According to some embodiments, the first ADC conversion circuit 124 is configured to convert the first ADC input voltage Vin_ADC1 into the first digital ADC output Vout_ADC1.

[0020] According to some embodiments, the first ADC circuit 118 further includes a first disconnection detection circuit 138 coupled between a first sampling switch 128 and a first ADC conversion circuit 124, configured to adaptively pull down or pull up the first ADC input voltage Vin_ADC1 to detect faults related to the first analog circuit path. According to some embodiments, the first analog circuit path includes an analog source circuit 102 (including an input source circuit 106 and a source circuit path 110), an input circuit path 116, and a first ADC circuit path 126. According to some embodiments, the first disconnection detection circuit 138 includes a first pull-up circuit branch 142 configured to pull up the first ADC input voltage Vin_ADC1 to a positive voltage VDD.

[0021] The first pull-up circuit branch 142 includes a first pull-up source circuit 148 and a first pull-up switch circuit 150. According to some embodiments, the first pull-up switch circuit 150 can be implemented using one or more metal oxide semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), etc. The first pull-up source circuit 148 is coupled to a positive power supply voltage VDD at a first termination and to the first pull-up switch circuit 150 at a different second termination. The first pull-up switch circuit 150 includes a first terminal and a second terminal, the first terminal being coupled in series to the second termination of the first pull-up source circuit 148, and the second terminal being coupled to an ADC node 146 in a first ADC circuit path 126 coupled between a first sampling switch 128 and a first ADC conversion circuit 124. According to some embodiments, the first pull-up source circuit 148 includes a current source. Alternatively, according to another embodiment, the first pull-up source circuit 148 may include a voltage source.

[0022] According to some embodiments, the first open circuit detection circuit 138 further includes a first pull-down circuit branch 144 configured to pull down a first ADC input voltage Vin_ADC1 to ground potential. The first pull-down circuit branch 144 includes a first pull-down source circuit 154 and a first pull-down switch circuit 152. According to some embodiments, the first pull-down switch circuit 152 can be implemented using one or more metal oxide semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), etc. The first pull-down source circuit 154 is coupled to ground voltage GND at a first termination and to the first pull-down switch circuit 152 at a different second termination. The first pull-down switch circuit 152 includes a first terminal and a second terminal, the first terminal being connected in series to the second termination of the first pull-down source circuit 154, and the second terminal being connected to an ADC node 146 in a first ADC circuit path 126 which is coupled between the first sampling switch 128 and the first ADC conversion circuit 124.

[0023] According to some embodiments, the first pull-down source circuit 154 includes a current source. Alternatively, according to other embodiments, the first pull-down source circuit 154 can include a voltage source. According to this embodiment, the disconnection detection circuit 138 is shown to include both the first pull-up circuit branch 142 and the first pull-down circuit branch 144. Alternatively, according to other embodiments, the disconnection detection circuit 138 can include only the first pull-up circuit branch 142 or only the first pull-down circuit branch 144. According to some embodiments, by coupling the first disconnection detection circuit 138 between the first sampling switch 128 and the first ADC conversion circuit 124, (since the first sampling switch 128 is open at half the time during sampling), the leakage from the first disconnection detection circuit 138 to the analog source circuit 102 can be reduced. Further, by using the first pull-up source circuit 148 and the first pull-down source circuit 154, a current controlled via the first pull-up circuit branch 142 and the first pull-down circuit branch 144 is supplied, thereby further reducing the leakage to the analog source circuit 102.

[0024] The second ADC circuit 122 includes a second ADC converter 158 and a second ADC circuit path 160 coupled between the second termination (or common electrical node 120) of the input circuit path 116 and the second ADC converter 158. The second ADC circuit path 160 includes a conductor path and may include one or more components coupled to this conductor path. Specifically, the second ADC circuit path 160 includes a second sampling switch 162 having a first terminal and a second terminal, the first terminal being coupled to the second termination or common electrical node 120 of the input circuit path 116 and the second terminal being coupled to the second ADC converter 158 (via the second ADC circuit path 160). The second sampling switch 162 is configured to sample the input path voltage Vin_path at the second termination of the input circuit path 116 and supply the second ADC input voltage Vin_ADC2 at the second terminal of the second sampling switch 162. According to some embodiments, the second ADC input voltage Vin_ADC2 includes a sampled version of the input path voltage Vin_path (which is an analog voltage). According to some embodiments, the second ADC conversion circuit 158 ​​is configured to convert the second ADC input voltage Vin_ADC2 to a second digital ADC output Vout_ADC2.

[0025] According to some embodiments, the second ADC circuit 122 further includes a second open circuit detection circuit 164 coupled between the second sampling switch 162 and the second ADC conversion circuit 158, configured to adaptively pull down or pull up the second ADC input voltage Vin_ADC2 to detect faults related to the second analog circuit path. According to some embodiments, the second analog circuit path includes an analog source circuit 102 (including an input source circuit 106 and a source circuit path 110), an input circuit path 116, and a second ADC circuit path 160. According to some embodiments, the second open circuit detection circuit 164 includes a second pull-up circuit branch 166 configured to pull up the second ADC input voltage Vin_ADC2 to a positive voltage VDD.

[0026] The second pull-up circuit branch 166 includes a second pull-up source circuit 170 and a second pull-up switch circuit 172. According to some embodiments, the second pull-up switch circuit 172 can be implemented using one or more metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), etc. The second pull-up source circuit 170 is coupled to the positive supply voltage VDD at the first terminal and is coupled to the second pull-up switch circuit 172 at a different second terminal. The second pull-up switch circuit 172 includes a first terminal and a second terminal. The first terminal is serially coupled to the second terminal of the second pull-up source circuit 170, and the second terminal is coupled to an ADC node 178 within a second ADC circuit path 160 coupled between the second sampling switch 162 and the second ADC conversion circuit 158. According to some embodiments, the second pull-up source circuit 170 includes a current source. Alternatively, according to other embodiments, the second pull-up source circuit 170 can include a voltage source.

[0027] According to some embodiments, the second open circuit detection circuit 164 further includes a second pull-down circuit branch 168 configured to pull down the second ADC input voltage Vin_ADC2 to ground potential. The second pull-down circuit branch 168 includes a second pull-down source circuit 176 and a second pull-down switch circuit 174. According to some embodiments, the second pull-down switch circuit 174 can be implemented using one or more metal oxide semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), etc. The second pull-down source circuit 176 is coupled to ground voltage GND at a first termination and to the second pull-down switch circuit 174 at a different second termination. The second pull-down switch circuit 174 includes a first terminal and a second terminal, the first terminal being connected in series to the second termination of the second pull-down source circuit 176, and the second terminal being connected to an ADC node 178 in a second ADC circuit path 160 which is coupled between the second sampling switch 162 and the second ADC conversion circuit 158.

[0028] According to some embodiments, the second pull-down source circuit 176 includes a current source. Optionally according to other embodiments, the second pull-down source circuit 176 may include a voltage source. According to this embodiment, the second open circuit detection circuit 164 is shown to include both a second pull-up circuit branch 166 and a second pull-down circuit branch 168. Optionally according to other embodiments, the second open circuit detection circuit 164 may include only the second pull-up circuit branch 166, or only the second pull-down circuit branch 168. According to some embodiments, leakage from the second open circuit detection circuit 164 to the analog source circuit 102 can be reduced by coupling the second open circuit detection circuit 164 between the second sampling switch 162 and the second ADC conversion circuit 158 ​​(since the second sampling switch 162 is open at half the sampling time). Furthermore, by using the second pull-up source circuit 170 and the second pull-down source circuit 176, controlled current is supplied via the second pull-up circuit branch 166 and the second pull-down circuit branch 168, thereby further reducing leakage to the analog source circuit 102.

[0029] According to some embodiments, if the first disconnection detection circuit 138 includes only the first pull-up branch 142, then the second disconnection detection circuit 164 also includes only the second pull-up branch 166. Similarly, according to some embodiments, if the first disconnection detection circuit 138 includes only the first pull-down branch 144, then the second disconnection detection circuit 164 also includes only the second pull-down branch 168. However, other configurations of the first disconnection detection circuit 138 and the second disconnection detection circuit 164 are also possible, for example, the first disconnection detection circuit 138 includes only the first pull-up branch 142, and the second disconnection detection circuit 164 includes only the second pull-down branch 168, and vice versa. Furthermore, if the first disconnection detection circuit 138 includes both a pull-up branch and a pull-down branch, then the second disconnection detection circuit 164 also includes both a pull-up branch and a pull-down branch. In embodiments where the first disconnection detection circuit 138 and the second disconnection detection circuit 164 include both pull-up and pull-down branches, either the pull-up branches of both the first disconnection detection circuit 138 and the second disconnection detection circuit 164 are activated / deactivated for fault detection, or the pull-down branches of both the first disconnection detection circuit 138 and the second disconnection detection circuit 164 are activated / deactivated. However, according to other embodiments, the first disconnection detection circuit 138 and the second disconnection detection circuit 164 may be activated / deactivated differently.

[0030] According to some embodiments, the analog fault detection circuit 104 further includes a first fault detection circuit 180 coupled to the output side of the first ADC conversion circuit 124 and configured to detect faults in the first analog circuit path based on a first digital ADC output Vout_ADC1. As previously described, according to some embodiments, the first analog circuit path includes an analog source circuit 102 (including an input source circuit 106 and a source circuit path 110), an input circuit path 116, and a first ADC circuit path 126. Furthermore, according to some embodiments, the analog fault detection circuit 104 further includes a second fault detection circuit 182 coupled to the output side of the second ADC conversion circuit 158 ​​and configured to detect faults in the second analog circuit path based on a second digital ADC output Vout_ADC2. As described earlier, according to some embodiments, the second analog circuit path includes an analog source circuit 102 (including an input source circuit 106 and a source circuit path 110), an input circuit path 116, and a second ADC circuit path 160. According to some embodiments, the analog fault detection circuit 104 further includes a fault comparison circuit 184 configured to compare the results of the first fault detection circuit 180 with the results of the second fault detection circuit 182. According to some embodiments, the fault comparison circuit 184 is further configured to indicate a fault based on the comparison.

[0031] For example, if a fault is identified by either the first fault detection circuit 180 or the second fault detection circuit 182, the fault comparison circuit 184 can indicate that a fault has been identified, for example, by activating an alarm or supplying an error message. According to some embodiments, if a fault is identified by either the first fault detection circuit 180 or the second fault detection circuit 182, it can represent a fault related to the analog source circuit 102 or the input circuit path 116 (both of which are common to the first fault detection circuit 180 and the second fault detection circuit 182). Furthermore, if no fault is identified by either the first fault detection circuit 180 or the second fault detection circuit 182, the fault comparison circuit 184 can supply a message indicating that no fault exists. Furthermore, if a fault is identified by only one of the first fault detection circuit 180 or the second fault detection circuit 182, the fault comparison circuit 184 can further supply an error message or an alarm. According to some embodiments, if a fault is identified by only one of the first fault detection circuit 180 and the second fault detection circuit 182, it can represent a fault related to the first ADC circuit path 126 or the second ADC circuit path 160. In such embodiments, an error message from the fault comparison circuit can indicate that the fault is related to the ADC circuit path. In such embodiments, the corresponding ADC can be reset to correct the fault. According to this embodiment, the analog fault detection circuit 104 is shown to include a first ADC circuit 118 and a second ADC circuit 122 coupled to the second end of the input circuit path 116. However, according to other embodiments, two or more ADC circuits can be coupled to the second end of the input circuit path 116. Furthermore, according to some alternative embodiments, only one ADC circuit (e.g., the first ADC circuit 118) can be coupled to the second end of the input circuit path 116. However, in such embodiments, the fault comparison circuit 184 cannot be included.Rather, according to such an embodiment, a fault detection circuit can detect a fault related to the analog circuit path based on the corresponding digital ADC output, and generate an alarm / display based on that fault.

[0032] Figure 2 shows a flowchart of algorithm 200 used by the analog fault detection circuit 104 to detect faults in a first or second analog circuit path. To determine faults associated with the first analog circuit path, algorithm 200 can be implemented using the first open circuit detection circuit 138 and the first fault detection circuit 180. Similarly, to determine faults associated with the second analog circuit path, algorithm 200 can be implemented using the second open circuit detection circuit 164 and the second fault detection circuit 182. In this specification, algorithm 200 is described with reference to the first open circuit detection circuit 138 and the first fault detection circuit 180 of the analog fault detection circuit 104, but algorithm 200 is equally applicable to the second open circuit detection circuit 164 and the second fault detection circuit 182, and this algorithm 200 should not be construed as being limited to these.

[0033] According to some embodiments, algorithm 200 is executed at predetermined time intervals (e.g., once per running cycle) to cover both persistent and random faults. According to some embodiments, algorithm 200 is executed using a first open circuit 138 and a first fault detection circuit 180, and simultaneously using a second open circuit 164 and a second fault detection circuit 182. Alternatively, according to other embodiments, algorithm 200 is executed using the first open circuit 138 and the first fault detection circuit 180, and at a different time, algorithm 200 is executed using the second open circuit 164 and the second fault detection circuit 182. Referring to Figure 2, algorithm 200 starts in step 202. In step 204, the first open circuit 138 is activated to pull up or pull down the first ADC input voltage Vin_ADC1. Specifically, the first pull-up circuit branch 142 is activated / enabled to pull up the first ADC input voltage Vin_ADC1 to VDD, and the first pull-down circuit branch 144 is configured to pull down the first ADC input voltage Vin_ADC1 to GND. According to some embodiments, the step of activating / enabling the first pull-up circuit branch 142 includes the step of turning on the first pull-up switch circuit 150, and the step of activating / enabling the first pull-down circuit branch 144 includes the step of turning on the first pull-down switch circuit 152.

[0034] In step 206, after a predetermined activation time, the first open circuit detection circuit 138 is deactivated / disabled. Specifically, the first pull-up circuit branch 142 or the first pull-down circuit branch 144, which was activated / enabled in step 204, is deactivated / disabled. According to some embodiments, the step of deactivating / disabling the first pull-up circuit branch 142 includes the step of turning off the first pull-up switch circuit 150, and the step of deactivating / disabling the first pull-down circuit branch 144 includes the step of turning off the first pull-down switch circuit 152. In step 208, after deactivating the first open circuit detection circuit 138, the first fault detection circuit 180 is used to measure and store a first measurement of the first digital ADC output Vout_ADC1. According to some embodiments, the first disconnection detection circuit 138 is deactivated and a first measurement is taken after a predetermined deactivation time. In step 210, after the first disconnection detection circuit 138 is deactivated, the first fault detection circuit 180 is used to measure and store a second measurement of the first digital ADC output Vout_ADC1. According to some embodiments, the second measurement includes the value of the first digital ADC output Vout_ADC1 measured after a predetermined waiting time following the measurement of the first measurement. In step 212, the first fault detection circuit 180 is used to compare the first measurement and the second measurement for the purpose of detecting a fault in the first analog circuit path.

[0035] According to some embodiments, if there is no fault in the analog circuit path, there will be a sufficient deviation (for example, within a predetermined deviation range) between the first measurement and the second measurement. However, if there is a fault in the analog circuit path, the first measurement and the second measurement will show similar values ​​(within a predetermined expected range). Further details on this will be presented in the following embodiments. Thus, according to some embodiments, the first fault detection circuit 180 identifies a fault in the first analog circuit path if the first measurement and the second measurement show similar values. Figure 3a shows one possible embodiment of the change over time of the first ADC input voltage Vin_ADC1 while the algorithm 200 for detecting a fault in the first analog circuit path is being executed. In particular, Figure 3a shows the waveform of the first ADC input voltage Vin_ADC1 for one embodiment in which the first analog circuit path is interrupted or intermittently interrupted. In this embodiment, algorithm 200 is executed by pulling down Vin_ADC1 using the first open circuit detection circuit 138. However, in other embodiments, algorithm 200 can be executed by pulling up Vin_ADC1 using the first open circuit detection circuit 138. When algorithm 200 is executed to detect a similar fault in a second analog circuit path, the waveform associated with the second ADC input voltage Vin_ADC2 also shows a similar change. Therefore, this will not be described again in this specification.

[0036] Waveform 300 depicts the expected change in Vin_ADC1 over time during normal operation (i.e., when algorithm 200 is not being executed) and when there are no faults in the first analog circuit path. Waveform 310 further depicts the change in Vin_ADC1 over time when algorithm 200 is being executed and a fault occurs in the first analog circuit path at time 301 (i.e., when the first analog circuit path is interrupted or intermittently interrupted). Waveform 320 further depicts the change in Vin_ADC1 over time when algorithm 200 is being executed and when there are no faults in the first analog circuit path. At 302, the pull-down is enabled using the first disconnection detection circuit 138. As can be seen in Figure 3a, both waveforms 310 and 320 show the voltage drop from V1 to V2 after the pull-down is enabled. After a predetermined activation time, the pull-down is disabled at 304. As can be seen from waveforms 310 and 320, Vin_ADC1 becomes constant at the lower voltage V2 after 304.

[0037] At 306, the first measurement of Vin_ADC1 is stored. Specifically, the first measurement of Vin_ADC1 is measured / stored after 304, after a predetermined deactivation time. As can be seen in Figure 3a, both waveforms 310 and 320 have a voltage V2 at 306. At 308, the second measurement of Vin_ADC1 is stored. The second measurement is measured / stored after a predetermined waiting time after the first measurement is taken. If there is no fault in the first analog circuit path, Vin_ADC1 will return to the previous level (i.e., V1) before the pull-down was enabled. However, as can be seen in Figure 3a, waveform 310 shows a voltage of V3 at 308, which is very close to the pull-down voltage V2. In other words, due to a fault, Vin_ADC1 does not return to the previous level voltage (i.e., V1) before the pull-down was enabled. In contrast, waveform 320 shows a voltage of V4 at 308, which is very close to the previous voltage level (i.e., V1) before the pull-down was enabled. Therefore, if the first measurement and the second measurement show similar values, the first fault detection circuit 180 detects a fault in the first analog circuit path. On the other hand, if the first measurement and the second measurement show a sufficient deviation (for example, within a predetermined range), the first fault detection circuit 180 identifies that there is no fault in the analog circuit path.

[0038] Figure 3b shows another possible embodiment of the change over time of the first ADC input voltage Vin_ADC1 while algorithm 200 is being executed to detect a fault in the first analog circuit path. In particular, Figure 3b shows the waveform of the first ADC input voltage Vin_ADC1 for one embodiment in which the input source circuit 106 is shorted to VDD. In other words, a fault in the first analog circuit path includes the input source circuit 106 being shorted to VDD. According to alternative embodiments, the fault may also include the input source circuit 106 being shorted to GND. According to this embodiment, algorithm 200 is executed by pulling down Vin_ADC1 using the first open circuit detection circuit 138. However, according to other embodiments, algorithm 200 can be executed by pulling up Vin_ADC1 using the first open circuit detection circuit 138. When algorithm 200 is executed to detect a similar fault in the second analog circuit path, the waveform associated with the second ADC input voltage Vin_ADC2 also shows a similar change. Therefore, this specification will not explain this matter again.

[0039] Waveform 350 depicts the expected change in Vin_ADC1 over time during normal operation (i.e., when algorithm 200 is not being executed) and when there are no faults in the first analog circuit path. Waveform 360 further depicts the change in Vin_ADC1 over time when algorithm 200 is being executed and a fault occurs in the first analog circuit path at time 351 (i.e., the input source circuit 106 is short-circuited to VDD). Waveform 370 further depicts the change in Vin_ADC1 over time when algorithm 200 is being executed and when there are no faults in the first analog circuit path. At 352, the pull-down is enabled using the first open circuit detection circuit 138. As can be seen from Figure 3b, due to the fault at 351 (i.e., the input source circuit 106 is short-circuited to VDD), even though the pull-down is enabled, the short-circuit current is significantly larger than the pull-down current, so waveform 360 remains at VDD. However, waveform 370 shows a voltage drop from V1 to V2 after the pull-down is enabled, as no fault is present. After a predetermined activation time, the pull-down is disabled at 354. Due to the fault, waveform 360 remains at VDD. In contrast, waveform 370, i.e., Vin_ADC1, remains constant at the lowered voltage V2 after 354.

[0040] At 356, the first measurement of Vin_ADC1 is stored. Specifically, the first measurement of Vin_ADC1 is measured / stored after 354, following a predetermined deactivation time. As can be seen in Figure 3b, waveform 360 remains at VDD, and waveform 370 has a voltage V2 at 356. At 358, the second measurement of Vin_ADC1 is stored. The second measurement is measured / stored after a predetermined waiting time following the measurement of the first measurement. If there is no fault in the first analog circuit path, Vin_ADC1 will return to its previous level (i.e., V1) before the pull-down was enabled. However, as can be seen in Figure 3b, due to a short circuit (i.e., fault), waveform 360 remains at VDD. In contrast, waveform 370 shows a voltage of V3 at 358, which is very close to the previous voltage level (i.e., V1) before the pull-down was enabled. Therefore, if the first measurement and the second measurement are similar values, the first fault detection circuit 180 detects a fault in the first analog circuit path. Conversely, if the first measurement and the second measurement show a sufficient deviation (for example, within a predetermined range), the first fault detection circuit 180 identifies that there is no fault in the analog circuit path.

[0041] Figure 4 shows one possible implementation of an analog-to-digital converter (ADC) circuit 410 associated with an analog fault detection system 400 according to one embodiment of the present disclosure. According to some embodiments, the ADC circuit 410 corresponds to the first ADC circuit 124 or the second ADC circuit 158 ​​in Figure 1. In this embodiment, the ADC circuit 410 includes a successive approximation (SAR) ADC with sample-and-hold. However, other implementations of the ADC circuit 410 are also within the scope of the present disclosure. According to some embodiments, the ADC circuit 410 is configured to generate a digital ADC output Vout_ADC (similar to Vout_ADC2 or Vout_ADC2 in Figure 1).

[0042] Figure 5 shows a flowchart of Method 500 of an analog fault detection system according to one embodiment of the present disclosure. This method will be described herein with reference to the analog fault detection system 100 of Figure 1. In step 502, an input terminal (e.g., input terminal 114 in Figure 1) associated with an analog fault detection circuit (e.g., analog fault detection circuit 104 in Figure 1) is coupled to an analog source circuit (e.g., analog source circuit 102 in Figure 1). In step 504, a first sampling switch (e.g., first sampling switch 128 in Figure 1) is used to sample the input path voltage (e.g., input path voltage Vin_path in Figure 1) at the second termination of an input circuit path (e.g., input circuit path 116 in Figure 1) to form a first ADC input voltage (e.g., first ADC input voltage Vin_ADC1 in Figure 1). According to some embodiments, the first termination of the input circuit path is coupled to an input terminal, and the second termination of the input circuit path is coupled to a first sampling switch.

[0043] In step 506, a first ADC conversion circuit (e.g., the first ADC conversion circuit 124 in Figure 1) is used to convert the first ADC input voltage to a first digital ADC output (e.g., the first digital ADC output Vout_ADC1 in Figure 1). According to some embodiments, a first sampling switch is included in a first ADC circuit path (e.g., the first ADC circuit path 126 in Figure 1) coupled between the second termination of the input circuit path and the first ADC conversion circuit. In step 508, the first ADC input voltage is pulled up or pulled down by activating a first disconnection detection circuit (e.g., the first disconnection detection circuit 138 in Figure 1) coupled between the first sampling switch and the first ADC conversion circuit. According to some embodiments, the first ADC input voltage is pulled up or pulled down to detect a fault related to the first analog circuit path. According to some embodiments, the first analog circuit path includes an analog source circuit, an input circuit path, and the first ADC circuit path. In step 510, the first disconnection detection circuit is deactivated after a predetermined activation time. In step 512, a first fault detection circuit (e.g., the first fault detection circuit 180 in Figure 1) is used to detect a fault in the first analog circuit path based on the first digital ADC output. According to some embodiments, the first fault detection circuit is configured to detect a fault based on a comparison between a first measurement of the first digital ADC output and a second measurement of the first digital ADC output, as previously described with respect to Figure 2.

[0044] In step 514, a second sampling switch (e.g., the second sampling switch 162 in Figure 1) is used to sample the input path voltage at the second termination of the input circuit path to form a second ADC input voltage (e.g., the second ADC input voltage Vin_ADC2 in Figure 1). According to some embodiments, the second termination of the input circuit path is coupled to the second sampling switch. In step 516, a second ADC converter (e.g., the second ADC converter 158 in Figure 1) is used to convert the second ADC input voltage to a second digital ADC output (e.g., the second digital ADC output Vout_ADC2 in Figure 1). According to some embodiments, the second sampling switch is included in a second ADC circuit path (e.g., the second ADC circuit path 160 in Figure 1) coupled between the second termination of the input circuit path and the second ADC converter. In step 518, the second ADC input voltage is pulled up or pulled down by activating a second open circuit (e.g., the second open circuit 164 in Figure 1) coupled between the second sampling switch and the second ADC conversion circuit. According to some embodiments, the second ADC input voltage is pulled up or pulled down to detect faults related to the second analog circuit path. According to some embodiments, the second analog circuit path includes an analog source circuit, an input circuit path, and a second ADC circuit path, as previously described.

[0045] In step 520, the second open circuit is deactivated after a predetermined activation time. In step 522, a second fault detection circuit (e.g., the second fault detection circuit 182 in Figure 1) is used to detect a fault in the second analog circuit path based on the second digital ADC output. According to some embodiments, the second fault detection circuit is configured to detect a fault based on a comparison of a first measurement of the second digital ADC output with a second measurement of the second digital ADC output, as previously described with respect to Figure 2. According to some embodiments, the first open circuit is activated / deactivated, and the second open circuit is activated / deactivated simultaneously or at the same time. Alternatively, the first open circuit is activated / deactivated, and the second open circuit is activated / deactivated at a different time. In step 524, a fault comparison circuit (for example, fault comparison circuit 184 in Figure 1) is used to compare the results of the first fault detection circuit with the results of the second fault detection circuit.

[0046] Although this method has been illustrated and described as a series of actions or events, it is obvious that the order in which such actions or events are illustrated should not be interpreted as limiting. For example, some actions may occur in a different order and / or simultaneously with other actions or events, different from those illustrated and / or described herein. In addition, not all of the illustrated actions may be required to implement one or more aspects or embodiments of the disclosure herein. Furthermore, one or more of the actions shown herein may be performed in one or more separate actions and / or stages.

[0047] The embodiments may include a method, means for carrying out an operation or block of the method, and at least one machine-readable medium, wherein the machine-readable medium includes instructions that, when executed by a machine, cause the machine to perform an operation of the method or an operation of a device or system for simultaneous communication using multiple communication technologies, in accordance with the embodiments and examples described herein.

[0048] Embodiment 1 is an analog fault detection circuit comprising an input terminal configured to be coupled to an analog source circuit, an input circuit path having a first termination and a second termination, the first termination of which is coupled to the input terminal, and a first analog-to-digital converter (ADC) circuit, the first analog-to-digital converter (ADC) circuit comprising a first ADC converter circuit, a first ADC circuit path, and a first open circuit detection circuit, the first ADC converter circuit configured to convert a first ADC input voltage to a first digital ADC output, the first ADC circuit path coupled between the second termination of the input circuit path and the first ADC converter circuit, the first terminal of the first ADC circuit path is coupled to the input The circuit includes a first sampling switch coupled to the second termination of the circuit path, the first sampling switch being configured to sample the input path voltage at the second termination of the input circuit path in order to supply the first ADC input voltage at a second terminal of the first sampling switch, the first open circuit detection circuit being coupled between the first sampling switch and the first ADC conversion circuit being configured to adaptively pull down or pull up the first ADC input voltage in order to detect faults related to the first analog circuit path, and the first analog circuit path including the analog source circuit, the input circuit path and the first ADC circuit path.

[0049] Embodiment 2 is an analog fault detection circuit including the protected object of Embodiment 1, with or without elements, wherein the first open circuit includes a first pull-up circuit branch configured to pull up the first ADC input voltage, or a first pull-down circuit branch configured to pull down the first ADC input voltage, or both.

[0050] Embodiment 3 is an analog fault detection circuit including the protected objects of Embodiments 1 to 2, with or without elements, wherein the first pull-up circuit branch includes a first pull-up source circuit coupled to a positive power supply voltage at a first termination, and a first pull-up switch circuit having a first terminal and a second terminal, the first terminal being coupled in series to a different second termination of the first pull-up source circuit, and the second terminal being coupled to an ADC node in the first ADC circuit path coupled between the first sampling switch and the first ADC conversion circuit.

[0051] Embodiment 4 is an analog fault detection circuit including the protected object of Embodiments 1 to 3, with or without elements, wherein the first pull-down circuit branch includes a first pull-down source circuit coupled to an earth circuit at a first termination, and a first pull-down switch circuit having a first terminal and a second terminal, the first terminal being coupled in series to a different second termination of the first pull-down source circuit, and the second terminal being coupled to the ADC node in the first ADC circuit path coupled between the first sampling switch and the first ADC conversion circuit.

[0052] Embodiment 5 is an analog fault detection circuit including the protected objects of Embodiments 1 to 4, with or without the elements, further comprising a first fault detection circuit coupled to the output side of the first ADC converter circuit and configured to detect faults in the first analog circuit path based on the first digital ADC output.

[0053] Embodiment 6 is an analog fault detection circuit including the protected objects of Embodiments 1 to 5, with or without elements, wherein the first open circuit is activated to detect a fault in the first analog circuit path, the first ADC input voltage is pulled up or pulled down, and then the first open circuit is deactivated after a predetermined activation time, the first fault detection circuit is configured to compare a first measurement of the first digital ADC output with a second measurement of the first digital ADC output after deactivation, the second measurement including a value measured after a predetermined waiting time following the measurement of the first measurement.

[0054] Example 7 is an analog fault detection circuit including the protected object of Examples 1 to 6, with or without elements, further comprising a second ADC circuit, the second ADC circuit comprising a second ADC converter circuit, a second ADC circuit path, and a second open circuit, wherein the second ADC converter circuit is configured to convert a second ADC input voltage to a second digital ADC output, the second ADC circuit path is coupled between the second termination of the input circuit path and the second ADC converter circuit, the second ADC circuit path includes a second sampling switch whose first terminal is coupled to the second termination of the input circuit path, and the second The sampling switch is configured to sample the input path voltage at the second termination of the input circuit path in order to supply the second ADC input voltage at the second terminal of the second sampling switch, and the second open circuit detection circuit is coupled between the second sampling switch and the second ADC conversion circuit and is configured to adaptively pull down or pull up the second ADC input voltage in order to detect faults related to the second analog circuit path, and the second analog circuit path includes the analog source circuit, the input circuit path and the second ADC circuit path.

[0055] Embodiment 8 is an analog fault detection circuit including the protected object of Embodiments 1 to 7, with or without the element, wherein the second open circuit includes a second pull-up circuit branch configured to pull up the second ADC input voltage, or a second pull-down circuit branch configured to pull down the second ADC input voltage, or both.

[0056] Embodiment 9 is an analog fault detection circuit including the protected objects of Embodiments 1 to 8, with or without elements, wherein the second pull-up circuit branch includes a second pull-up source circuit coupled to a positive power supply voltage at a first termination, and a second pull-up switch circuit having a first terminal and a second terminal, the first terminal being coupled in series to a different second termination of the second pull-up source circuit, and the second terminal being coupled to an ADC node in the second ADC circuit path coupled between the second sampling switch and the second ADC conversion circuit.

[0057] Example 10 is an analog fault detection circuit including the protected objects of Examples 1 to 9, with or without elements, wherein the second pull-down circuit branch includes a second pull-down source circuit coupled to an earth circuit at a first termination, and a second pull-down switch circuit having a first terminal and a second terminal, the first terminal being coupled in series to a different second termination of the second pull-down source circuit, and the second terminal being coupled to the ADC node in the second ADC circuit path coupled between the second sampling switch and the second ADC conversion circuit.

[0058] Example 11 is an analog fault detection circuit including the protected objects of Examples 1 to 10, with or without elements, and further includes a second fault detection circuit coupled to the output side of the second ADC converter circuit and configured to detect faults in the second analog circuit path based on the second digital ADC output.

[0059] Embodiment 12 is an analog fault detection circuit including the protected objects of Embodiments 1 to 11, with or without elements, wherein the second open circuit is activated to detect a fault in the second analog circuit path, the second ADC input voltage is pulled up or pulled down, and then the second open circuit is deactivated after a predetermined activation time, the second fault detection circuit is configured to compare a first measurement of the second digital ADC output with a second measurement of the second digital ADC output after deactivation, the second measurement including a value measured after a predetermined waiting time following the measurement of the first measurement.

[0060] Example 13 is an analog fault detection circuit including the protected objects of Examples 1 to 12, with or without elements, further comprising a fault comparison circuit configured to compare the results of the first fault detection circuit with the results of the second fault detection circuit.

[0061] Embodiment 14 is an analog fault detection system comprising an analog source circuit and an analog fault detection circuit, the analog fault detection circuit comprising an input terminal coupled to the analog source circuit, an input circuit path having a first termination and a second termination, the first termination of which is coupled to the input terminal, and a first analog-to-digital converter (ADC) circuit, the first analog-to-digital converter (ADC) circuit comprising a first ADC converter circuit, a first ADC circuit path, and a first open circuit detection circuit, the first ADC converter circuit being configured to convert a first ADC input voltage to a first digital ADC output, the first ADC circuit path being coupled between the second termination of the input circuit path and the first ADC converter circuit, and the first The ADC circuit path includes a first sampling switch, the first terminal of which is coupled to the second termination of the input circuit path, the first sampling switch being configured to sample the input path voltage at the second termination of the input circuit path in order to supply the first ADC input voltage at the second terminal of the first sampling switch, the first open circuit detection circuit being coupled between the first sampling switch and the first ADC conversion circuit being configured to adaptively pull down or pull up the first ADC input voltage in order to detect faults related to the first analog circuit path, and the first analog circuit path includes the analog source circuit, the input circuit path and the first ADC circuit path.

[0062] Embodiment 15 is an analog fault detection system including the protected object of Embodiment 14, wherein the first open circuit includes a first pull-up circuit branch configured to pull up the first ADC input voltage, or a first pull-down circuit branch configured to pull down the first ADC input voltage, or both.

[0063] Embodiment 16 is an analog fault detection system comprising the protected objects of Embodiments 14 to 15, with or without elements, wherein the first pull-up circuit branch comprises a first pull-up source circuit coupled to a positive power supply voltage at a first termination, and a first pull-up switch circuit having a first terminal and a second terminal, the first terminal being coupled in series to a different second termination of the first pull-up source circuit, and the second terminal being coupled to an ADC node in the first ADC circuit path coupled between the first sampling switch and the first ADC conversion circuit.

[0064] Example 17 is an analog fault detection system including the protected objects of Examples 14 to 16, with or without elements, wherein the first pull-down circuit branch includes a first pull-down source circuit coupled to an earth circuit at a first termination, and a first pull-down switch circuit having a first terminal and a second terminal, the first terminal being coupled in series to a different second termination of the first pull-down source circuit, and the second terminal being coupled to the ADC node in the first ADC circuit path coupled between the first sampling switch and the first ADC conversion circuit.

[0065] Example 18 is an analog fault detection system including the protected objects of Examples 14 to 17, with or without elements, wherein the analog fault detection circuit further includes a first fault detection circuit coupled to the output side of the first ADC converter circuit and configured to detect faults in the first analog circuit path based on the first digital ADC output.

[0066] Example 19 is an analog fault detection system including the protected objects of Examples 14 to 18, with or without elements, wherein the analog fault detection circuit further includes a second ADC circuit, the second ADC circuit includes a second ADC converter circuit, a second ADC circuit path, and a second open circuit detection circuit, the second ADC converter circuit is configured to convert a second ADC input voltage to a second digital ADC output, the second ADC circuit path is coupled between the second termination of the input circuit path and the second ADC converter circuit, the second ADC circuit path has a second sampling switch with a first terminal coupled to the second termination of the input circuit path A second sampling switch is configured to sample the input path voltage at the second termination of the input circuit path in order to supply the second ADC input voltage at the second terminal of the second sampling switch; a second open circuit is coupled between the second sampling switch and the second ADC conversion circuit and is configured to adaptively pull down or pull up the second ADC input voltage in order to detect faults related to the second analog circuit path; and the second analog circuit path includes the analog source circuit, the input circuit path and the second ADC circuit path.

[0067] Example 20 is an analog fault detection system including the protected objects of Examples 14 to 19, with or without the elements, wherein the second open circuit includes a second pull-up circuit branch configured to pull up the second ADC input voltage, or a second pull-down circuit branch configured to pull down the second ADC input voltage, or both.

[0068] Example 21 is an analog fault detection system including the protected objects of Examples 14 to 20, with or without elements, wherein the second pull-up circuit branch includes a second pull-up source circuit coupled to a positive power supply voltage at a first termination, and a second pull-up switch circuit having a first terminal and a second terminal, the first terminal being coupled in series to a different second termination of the second pull-up source circuit, and the second terminal being coupled to an ADC node in the second ADC circuit path coupled between the second sampling switch and the second ADC conversion circuit.

[0069] Example 22 is an analog fault detection system including the protected objects of Examples 14 to 21, with or without elements, wherein the second pull-down circuit branch includes a second pull-down source circuit coupled to an earth circuit at a first termination, and a second pull-down switch circuit having a first terminal and a second terminal, the first terminal being coupled in series to a different second termination of the second pull-down source circuit, and the second terminal being coupled to the ADC node in the second ADC circuit path coupled between the second sampling switch and the second ADC conversion circuit.

[0070] Example 23 is an analog fault detection system including the protected objects of Examples 14 to 22, with or without elements, wherein the analog fault detection circuit further includes a second fault detection circuit coupled to the output side of the second ADC converter circuit and configured to detect faults in the second analog circuit path based on the second digital ADC output.

[0071] Example 24 is an analog fault detection system including the protected objects of Examples 14 to 23, with or without elements, wherein the analog fault detection circuit further includes a fault comparison circuit configured to compare the results of the first fault detection circuit with the results of the second fault detection circuit.

[0072] Example 25 is a method for an analog fault detection circuit, the method comprising the steps of: coupling an input terminal associated with the analog fault detection circuit to an analog source circuit; using a first ADC converter circuit to convert a first analog-to-digital converter (ADC) input voltage to a first digital ADC output; and using a first sampling switch to sample the input path voltage at a second termination of the input circuit path to form the first ADC input voltage, wherein the first termination of the input circuit path is coupled to the input terminal and the second termination of the input circuit path is The steps include: coupling to the first sampling switch, the first sampling switch being included in a first ADC circuit path coupled between the second termination of the input circuit path and the first ADC converter; and adaptively pulling up or pulling down the first ADC input voltage using a first open circuit coupling between the first sampling switch and the first ADC converter to detect a fault related to the first analog circuit path, wherein the first analog circuit path includes the analog source circuit, the input circuit path and the first ADC circuit path.

[0073] Example 26 is a method comprising the protected object of Example 25, wherein the first open circuit includes a first pull-up circuit branch configured to pull up the first ADC input voltage, or a first pull-down circuit branch configured to pull down the first ADC input voltage, or both.

[0074] Example 27 is a method including the protected objects of Examples 25 to 26, with or without elements, wherein the first pull-up circuit branch includes a first pull-up source circuit coupled to a positive supply voltage at a first termination, and a first pull-up switch circuit having a first terminal and a second terminal, the first terminal being coupled in series to a different second termination of the first pull-up source circuit, and the second terminal being coupled to an ADC node in the first ADC circuit path coupled between the first sampling switch and the first ADC conversion circuit.

[0075] Example 28 is a method including the protected objects of Examples 25 to 27, with or without elements, wherein the first pull-down circuit branch includes a first pull-down source circuit coupled to an earth circuit at a first termination, and a first pull-down switch circuit having a first terminal and a second terminal, the first terminal being coupled in series to a different second termination of the first pull-down source circuit, and the second terminal being coupled to the ADC node in the first ADC circuit path coupled between the first sampling switch and the first ADC conversion circuit.

[0076] Example 29 is a method comprising the protected objects of Examples 25 to 28, with or without elements, wherein the method further comprises the step of activating the first open circuit to pull up or pull down the first ADC input voltage, and then deactivating the first open circuit after a predetermined activation time in order to detect a fault related to the first analog circuit path.

[0077] Example 30 is a method including the protected objects of Examples 25 to 29, with or without elements, further comprising the step of detecting a fault in the first analog circuit path using a first fault detection circuit coupled to the output side of the first ADC converter circuit, based on the first digital ADC output after deactivation of the first open circuit.

[0078] Example 31 is a method including the protected objects of Examples 25 to 30, with or without elements, wherein the step of detecting a fault in the first analog circuit path using the first fault detection circuit includes the step of comparing a first measurement of the first digital ADC output with a second measurement of the first digital ADC output after deactivating the first open circuit, wherein the second measurement includes a value measured after a predetermined waiting time following the measurement of the first measurement.

[0079] While the present invention has been illustrated and described in relation to one or more implementations, modifications and / or changes can be made to the illustrated embodiments without departing from the spirit and scope of the appended claims. In particular, with respect to the various functions performed by the above-described components or structures (assemblies, devices, circuits, systems, etc.), the terms used to describe such components (including references to “means”) are intended, unless otherwise stated, to correspond to any component or structure that performs a particular function of the aforementioned component (for example, functionally equivalent) to the disclosed structure that performs the function in the specific implementations of the present invention illustrated herein.

[0080] The foregoing descriptions of the illustrated embodiments of this disclosure, including those in the abstract, are not intended to be exhaustive or to limit the disclosed embodiments to the precise forms disclosed. While certain embodiments and examples are described herein for illustrative purposes only, various modifications are possible that fall within the scope of such embodiments and examples, as will be obvious to those skilled in the art.

Claims

1. An analog fault detection circuit, wherein the analog fault detection circuit is An input terminal configured to be coupled to an analog source circuit, An input circuit path having a first termination and a second termination, the first termination being coupled to the input terminal, The first analog-to-digital converter (ADC) circuit, Includes, The first analog-to-digital converter (ADC) circuit includes a first ADC conversion circuit, a first ADC circuit path, and a first disconnection detection circuit. The first ADC conversion circuit is configured to convert the first ADC input voltage into a first digital ADC output. The first ADC circuit path is coupled between the second termination of the input circuit path and the first ADC conversion circuit, and the first ADC circuit path includes a first sampling switch whose first terminal is coupled to the second termination of the input circuit path, and the first sampling switch is configured to sample the input path voltage at the second termination of the input circuit path in order to supply the first ADC input voltage at the second terminal of the first sampling switch. The first disconnection detection circuit is coupled between the first sampling switch and the first ADC conversion circuit and is configured to adaptively pull down or pull up the first ADC input voltage to detect faults related to the first analog circuit path, the first analog circuit path includes the analog source circuit, the input circuit path and the first ADC circuit path, The analog fault detection circuit further includes a first fault detection circuit coupled to the output side of the first ADC conversion circuit and configured to detect faults in the first analog circuit path based on the first digital ADC output. The analog fault detection circuit further includes a second ADC circuit, the second ADC circuit includes a second ADC conversion circuit, a second ADC circuit path, and a second open circuit detection circuit. The second ADC conversion circuit is configured to convert the second ADC input voltage into a second digital ADC output. The second ADC circuit path is coupled between the second termination of the input circuit path and the second ADC conversion circuit, and the second ADC circuit path includes a second sampling switch whose first terminal is coupled to the second termination of the input circuit path, and the second sampling switch is configured to sample the input path voltage at the second termination of the input circuit path in order to supply the second ADC input voltage at the second terminal of the second sampling switch. The second disconnection detection circuit is coupled between the second sampling switch and the second ADC conversion circuit and is configured to adaptively pull down or pull up the second ADC input voltage to detect faults related to the second analog circuit path, the second analog circuit path includes the analog source circuit, the input circuit path and the second ADC circuit path, The analog fault detection circuit further includes a second fault detection circuit coupled to the output side of the second ADC conversion circuit and configured to detect faults in the second analog circuit path based on the second digital ADC output. The analog fault detection circuit further includes a fault comparison circuit configured to compare the result of the first fault detection circuit with the result of the second fault detection circuit. Analog fault detection circuit.

2. The first disconnection detection circuit includes a first pull-up circuit branch configured to pull up the first ADC input voltage, or includes a first pull-down circuit branch configured to pull down the first ADC input voltage, or includes both. The analog fault detection circuit according to claim 1.

3. The first pull-up circuit branch includes a first pull-up source circuit coupled to a positive power supply voltage at a first termination, and a first pull-up switch circuit having a first terminal and a second terminal, wherein the first terminal is coupled in series to a different second termination of the first pull-up source circuit, and the second terminal is coupled to an ADC node in the first ADC circuit path coupled between the first sampling switch and the first ADC conversion circuit. The analog fault detection circuit according to claim 2.

4. The first pull-down circuit branch includes a first pull-down source circuit coupled to an earth circuit at a first termination, and a first pull-down switch circuit having a first terminal and a second terminal, wherein the first terminal is coupled in series to a different second termination of the first pull-down source circuit, and the second terminal is coupled to an ADC node in the first ADC circuit path coupled between the first sampling switch and the first ADC conversion circuit. The analog fault detection circuit according to claim 2.

5. To detect a fault in the first analog circuit path, the first open circuit is activated, the first ADC input voltage is pulled up or pulled down, and then, after a predetermined activation time, the first open circuit is deactivated, and the first fault detection circuit is configured to compare a first measurement of the first digital ADC output with a second measurement of the first digital ADC output after deactivation, wherein the first measurement is measured after deactivation, and the second measurement includes a value measured after a predetermined waiting time following the measurement of the first measurement. The analog fault detection circuit according to claim 1.

6. The second disconnection detection circuit includes a second pull-up circuit branch configured to pull up the second ADC input voltage, or includes a second pull-down circuit branch configured to pull down the second ADC input voltage, or includes both. The analog fault detection circuit according to claim 1.

7. The second pull-up circuit branch includes a second pull-up source circuit coupled to a positive power supply voltage at a first termination, and a second pull-up switch circuit having a first terminal and a second terminal, wherein the first terminal is coupled in series to a different second termination of the second pull-up source circuit, and the second terminal is coupled to an ADC node in the second ADC circuit path coupled between the second sampling switch and the second ADC conversion circuit. The analog fault detection circuit according to claim 6.

8. The second pull-down circuit branch includes a second pull-down source circuit coupled to a ground circuit at a first termination, and a second pull-down switch circuit having a first terminal and a second terminal, wherein the first terminal is coupled in series to a different second termination of the second pull-down source circuit, and the second terminal is coupled to an ADC node in the second ADC circuit path coupled between the second sampling switch and the second ADC conversion circuit. The analog fault detection circuit according to claim 6.

9. To detect a fault in the second analog circuit path, the second open circuit is activated, the second ADC input voltage is pulled up or pulled down, and then, after a predetermined activation time, the second open circuit is deactivated, and the second fault detection circuit is configured to compare a first measurement of the second digital ADC output with a second measurement of the second digital ADC output after deactivation, wherein the first measurement is taken after deactivation, and the second measurement includes a value taken after a predetermined waiting time following the measurement of the first measurement. The analog fault detection circuit according to claim 1.

10. An analog fault detection system, wherein the analog fault detection system is Analog source circuit and, Analog fault detection circuit and Includes, The analog fault detection circuit is, The input terminal coupled to the analog source circuit, An input circuit path having a first termination and a second termination, the first termination being coupled to the input terminal, The first analog-to-digital converter (ADC) circuit, Includes, The first analog-to-digital converter (ADC) circuit includes a first ADC conversion circuit, a first ADC circuit path, and a first disconnection detection circuit. The first ADC conversion circuit is configured to convert the first ADC input voltage into a first digital ADC output. The first ADC circuit path is coupled between the second termination of the input circuit path and the first ADC conversion circuit, and the first ADC circuit path includes a first sampling switch whose first terminal is coupled to the second termination of the input circuit path, and the first sampling switch is configured to sample the input path voltage at the second termination of the input circuit path in order to supply the first ADC input voltage at the second terminal of the first sampling switch. The first disconnection detection circuit is coupled between the first sampling switch and the first ADC conversion circuit and is configured to adaptively pull down or pull up the first ADC input voltage to detect faults related to the first analog circuit path, the first analog circuit path includes the analog source circuit, the input circuit path and the first ADC circuit path, The analog fault detection circuit further includes a first fault detection circuit coupled to the output side of the first ADC conversion circuit and configured to detect faults in the first analog circuit path based on the first digital ADC output. The analog fault detection circuit further includes a second ADC circuit, the second ADC circuit includes a second ADC conversion circuit, a second ADC circuit path, and a second open circuit detection circuit. The second ADC conversion circuit is configured to convert the second ADC input voltage into a second digital ADC output. The second ADC circuit path is coupled between the second termination of the input circuit path and the second ADC conversion circuit, and the second ADC circuit path includes a second sampling switch whose first terminal is coupled to the second termination of the input circuit path, and the second sampling switch is configured to sample the input path voltage at the second termination of the input circuit path in order to supply the second ADC input voltage at the second terminal of the second sampling switch. The second disconnection detection circuit is coupled between the second sampling switch and the second ADC conversion circuit and is configured to adaptively pull down or pull up the second ADC input voltage to detect faults related to the second analog circuit path, the second analog circuit path includes the analog source circuit, the input circuit path and the second ADC circuit path, The analog fault detection circuit further includes a second fault detection circuit coupled to the output side of the second ADC conversion circuit and configured to detect faults in the second analog circuit path based on the second digital ADC output. The analog fault detection circuit further includes a fault comparison circuit configured to compare the result of the first fault detection circuit with the result of the second fault detection circuit. Analog fault detection system.

11. The first disconnection detection circuit includes a first pull-up circuit branch configured to pull up the first ADC input voltage, or includes a first pull-down circuit branch configured to pull down the first ADC input voltage, or includes both. The analog fault detection system according to claim 10.

12. The first pull-up circuit branch includes a first pull-up source circuit coupled to a positive power supply voltage at a first termination, and a first pull-up switch circuit having a first terminal and a second terminal, wherein the first terminal is coupled in series to a different second termination of the first pull-up source circuit, and the second terminal is coupled to an ADC node in the first ADC circuit path coupled between the first sampling switch and the first ADC conversion circuit. The analog fault detection system according to claim 11.

13. The first pull-down circuit branch includes a first pull-down source circuit coupled to an earth circuit at a first termination, and a first pull-down switch circuit having a first terminal and a second terminal, wherein the first terminal is coupled in series to a different second termination of the first pull-down source circuit, and the second terminal is coupled to an ADC node in the first ADC circuit path coupled between the first sampling switch and the first ADC conversion circuit. The analog fault detection system according to claim 11.

14. The second disconnection detection circuit includes a second pull-up circuit branch configured to pull up the second ADC input voltage, or includes a second pull-down circuit branch configured to pull down the second ADC input voltage, or includes both. The analog fault detection system according to claim 10.

15. The second pull-up circuit branch includes a second pull-up source circuit coupled to a positive power supply voltage at a first termination, and a second pull-up switch circuit having a first terminal and a second terminal, wherein the first terminal is coupled in series to a different second termination of the second pull-up source circuit, and the second terminal is coupled to an ADC node in the second ADC circuit path coupled between the second sampling switch and the second ADC conversion circuit. The analog fault detection system according to claim 14.

16. The second pull-down circuit branch includes a second pull-down source circuit coupled to a ground circuit at a first termination, and a second pull-down switch circuit having a first terminal and a second terminal, wherein the first terminal is coupled in series to a different second termination of the second pull-down source circuit, and the second terminal is coupled to an ADC node in the second ADC circuit path coupled between the second sampling switch and the second ADC conversion circuit. The analog fault detection system according to claim 14.

17. A method for an analog fault detection circuit, the method comprising the following steps, namely: The steps include: coupling the input terminals related to the analog fault detection circuit to the analog source circuit; The steps include: using a first ADC conversion circuit to convert the input voltage of a first analog-to-digital converter (ADC) to the output of a first digital ADC; A step of using a first sampling switch to sample the input path voltage at the second termination of the input circuit path to form the first ADC input voltage, wherein the first termination of the input circuit path is coupled to the input terminal, the second termination of the input circuit path is coupled to the first sampling switch, and the first sampling switch is included in a first ADC circuit path coupled between the second termination of the input circuit path and the first ADC conversion circuit, A step of adaptively pulling up or pulling down the first ADC input voltage using a first disconnection detection circuit coupled between the first sampling switch and the first ADC conversion circuit in order to detect a fault related to the first analog circuit path, wherein the first analog circuit path includes the analog source circuit, the input circuit path and the first ADC circuit path. Includes, The method further includes the step of detecting a fault in the first analog circuit path based on the first digital ADC output, using a first fault detection circuit coupled to the output side of the first ADC conversion circuit. The aforementioned method, The steps include: using a second ADC conversion circuit to convert the second ADC input voltage to the second digital ADC output; A step of using a second sampling switch to sample the input path voltage at the second termination of the input circuit path to form the second ADC input voltage, wherein the second termination of the input circuit path is coupled to the second sampling switch, and the second sampling switch is included in a second ADC circuit path coupled between the second termination of the input circuit path and the second ADC conversion circuit, A step of adaptively pulling up or pulling down the second ADC input voltage using a second open circuit coupled between the second sampling switch and the second ADC conversion circuit in order to detect a fault related to the second analog circuit path, wherein the second analog circuit path includes the analog source circuit, the input circuit path and the second ADC circuit path. It further includes, The method further includes the step of detecting a fault in the second analog circuit path based on the second digital ADC output, using a second fault detection circuit coupled to the output side of the second ADC conversion circuit. The method further includes the step of comparing the results of the first fault detection circuit with the results of the second fault detection circuit. method.

18. The first disconnection detection circuit includes a first pull-up circuit branch configured to pull up the first ADC input voltage, or includes a first pull-down circuit branch configured to pull down the first ADC input voltage, or includes both. The method according to claim 17.

19. The first pull-up circuit branch includes a first pull-up source circuit coupled to a positive power supply voltage at a first termination, and a first pull-up switch circuit having a first terminal and a second terminal, wherein the first terminal is coupled in series to a different second termination of the first pull-up source circuit, and the second terminal is coupled to an ADC node in the first ADC circuit path coupled between the first sampling switch and the first ADC conversion circuit. The method according to claim 18.

20. The first pull-down circuit branch includes a first pull-down source circuit coupled to an earth circuit at a first termination, and a first pull-down switch circuit having a first terminal and a second terminal, wherein the first terminal is coupled in series to a different second termination of the first pull-down source circuit, and the second terminal is coupled to an ADC node in the first ADC circuit path coupled between the first sampling switch and the first ADC conversion circuit. The method according to claim 18.

21. The first open circuit is activated to pull up or pull down the first ADC input voltage, and the method further includes the step of deactivating the first open circuit after a predetermined activation time in order to detect a fault related to the first analog circuit path. The method according to claim 17.

22. Based on the first digital ADC output after deactivation of the first disconnection detection circuit, a fault in the first analog circuit path is detected using a first fault detection circuit coupled to the output side of the first ADC conversion circuit. The method according to claim 21.

23. The step of detecting a fault in the first analog circuit path using the first fault detection circuit includes the step of comparing a first measurement of the first digital ADC output with a second measurement of the first digital ADC output after deactivation of the first open circuit detection circuit, wherein the first measurement is measured after deactivation, and the second measurement includes a value measured after a predetermined waiting time following the measurement of the first measurement. The method according to claim 22.

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