Semiconductor equipment

Abstract

To properly calibrate an object circuit.SOLUTION: An object circuit includes an adjustment circuit for changing characteristics of the object circuit according to a digital value to be supplied from a calibration circuit. A calibration operation includes an evaluation operation for repetitively performing a plurality of unit operations with respect to the object circuit. The calibration circuit evaluates the characteristics of the object circuit while changing the digital value in the respective operations, so as to derive, as a calibration candidate value, the digital value when minimizing a difference between the characteristics of the object circuit and target characteristics based on the evaluation result. When the plurality of calibration candidate values derived by the plurality of unit operations satisfy a predetermined condition, the characteristics of the object circuit are calibrated with the use of an actual calibration value based on the calibration candidate values. When the calibration candidate values are deviated from the predetermined condition, the evaluation operation is re-performed or a predetermined error signal is output.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices. [Background technology]

[0002] In many semiconductor devices, a circuit is installed in the target circuit to adjust its characteristics in order to bring its characteristics closer to the ideal, and the characteristics of the target circuit are then calibrated. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2019-161382 [Overview of the project] [Problems that the invention aims to solve]

[0004] When searching for the optimal values ​​to bring the characteristics of a target circuit closer to ideal, noise or other interference can interfere, potentially leading to the incorrect discovery of unsuitable values. Applying unsuitable values ​​to the target circuit and performing calibration may result in worse characteristics than before calibration. The development of technologies to achieve proper calibration is therefore highly anticipated.

[0005] This disclosure aims to provide a semiconductor device that contributes to the proper calibration of equipment. [Means for solving the problem]

[0006] The semiconductor device according to this disclosure comprises a target circuit and a calibration circuit configured to perform calibration operations on the target circuit, wherein the target circuit has an adjustment circuit configured to change the characteristics of the target circuit in accordance with a digital value supplied from the calibration circuit, the calibration operation includes an evaluation operation in which a plurality of unit operations are repeatedly performed on the target circuit, the calibration circuit evaluates the characteristics of the target circuit while changing the digital value in each unit operation, derives a digital value as a calibration candidate value that minimizes the difference between the characteristics of the target circuit and the target characteristics based on the evaluation result, the calibration circuit calibrates the characteristics of the target circuit using an actual calibration value based on the plurality of calibration candidate values ​​when the plurality of calibration candidate values ​​derived in the plurality of unit operations satisfy predetermined conditions, and re-executes the evaluation operation or outputs a predetermined error signal when the plurality of calibration candidate values ​​deviate from the predetermined conditions.

[0007] Other semiconductor devices relating to this disclosure include a plurality of target circuits and a calibration circuit configured to perform calibration operations on the plurality of target circuits, each target circuit having an adjustment circuit configured to change the characteristics of the target circuit according to a digital value supplied from the calibration circuit, the calibration operation includes an evaluation operation that performs a unit operation for each target circuit, the calibration circuit evaluates the characteristics of the target circuit for each target circuit while changing a corresponding digital value in the corresponding unit operation, derives a digital value as a calibration candidate value that minimizes the difference between the characteristics of the target circuit and the target characteristics based on the evaluation result, derives a plurality of calibration candidate values ​​for the plurality of target circuits through the unit operation for each target circuit, the calibration circuit calibrates the characteristics of each target circuit using the corresponding calibration candidate value as the actual calibration value when the plurality of calibration candidate values ​​satisfy predetermined conditions, and re-executes the evaluation operation or outputs a predetermined error signal when the plurality of calibration candidate values ​​deviate from the predetermined conditions. [Effects of the Invention]

[0008] This disclosure makes it possible to provide a semiconductor device that contributes to the proper calibration of equipment. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a schematic overall diagram of the system according to the embodiment of this disclosure. [Figure 2] Figure 2 is an external perspective view of a semiconductor device according to an embodiment of the present disclosure. [Figure 3] Figure 3 is a diagram showing the configuration of a current sensor according to a first embodiment belonging to the embodiments of this disclosure. [Figure 4] Figure 4 is a diagram showing a schematic configuration of an operational amplifier relating to a first embodiment belonging to the embodiments of this disclosure. [Figure 5] Figure 5 shows the configuration of the input stage in an operational amplifier and the configuration of the adjustment circuit, relating to a first embodiment of the embodiments of this disclosure. [Figure 6] Figure 6 is a diagram relating to a first embodiment belonging to the embodiments of this disclosure, showing the relationship between the digital signal input to the DAC and the analog voltage output from the DAC. [Figure 7] Figure 7 is a diagram showing the structure of a digital signal input to a DAC, relating to a first embodiment of the embodiments of this disclosure. [Figure 8] Figure 8 is a flowchart of the calibration operation relating to a first embodiment belonging to the embodiments of this disclosure. [Figure 9] Figure 9 is a modified flowchart of a calibration operation relating to a first embodiment belonging to the embodiments of this disclosure. [Figure 10] Figure 10 is a flowchart of a unit operation relating to a first embodiment belonging to the embodiments of this disclosure. [Figure 11] Figure 11 is a diagram showing the configuration of a current sensor according to a second embodiment belonging to the embodiments of this disclosure. [Figure 12] Figure 12 is a diagram showing the configuration of a current sensor according to a second embodiment belonging to the embodiments of this disclosure. [Figure 13] Figure 13 is a diagram of a calibration circuit configuration relating to a second embodiment belonging to the embodiments of this disclosure. [Figure 14]Figure 14 is a flowchart of the calibration operation relating to a second embodiment belonging to the embodiments of this disclosure. [Figure 15] Figure 15 is a modified flowchart of a calibration operation relating to a second embodiment belonging to the embodiments of this disclosure. [Figure 16] Figure 16 is an overall system configuration diagram relating to a fourth embodiment belonging to the embodiments of this disclosure. [Figure 17] Figure 17 is a configuration diagram of a semiconductor device including a DC / DC converter, relating to a fifth embodiment belonging to the embodiments of this disclosure. [Figure 18] Figure 18 is a configuration diagram of a semiconductor device including an oscillator circuit, relating to a fifth embodiment belonging to the embodiments of this disclosure. [Modes for carrying out the invention]

[0010] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the referenced drawings, the same parts will be denoted by the same reference numerals, and redundant descriptions relating to the same parts will be omitted as a general rule. In addition, in this specification, for the sake of simplification of the description, symbols or reference numerals that refer to information, signals, physical quantities, functional parts, circuits, elements, or components may be indicated, and the names of the information, signals, physical quantities, functional parts, circuits, elements, or components corresponding to such symbols or reference numerals may be omitted or abbreviated. For example, “V” described later REF The reference voltage referred to by (see Figure 3) is the reference voltage V REF It is sometimes written as, and the voltage V REF These abbreviations may also be used, but they all refer to the same thing.

[0011] First, some terms used in the description of the embodiments of this disclosure will be explained. Ground refers to a reference conductive part having a reference potential of 0V (zero volts), or the potential of 0V itself. The reference conductive part may be formed using a conductor such as metal. The potential of 0V is sometimes referred to as the ground potential. In the embodiments of this disclosure, voltages shown without specifying a reference represent the potential as seen from ground.

[0012] Level refers to the level of electric potential. For any signal or voltage of interest, a high level has a higher potential than a low level. For any signal or voltage of interest, being at a high level strictly means that the signal or voltage has a high level, and being at a low level strictly means that the signal or voltage has a low level. The level for a signal is sometimes expressed as the signal level, and the level for a voltage is sometimes expressed as the voltage level.

[0013] Unless otherwise specified, connections between multiple parts that form a circuit, such as arbitrary circuit elements, wiring, and nodes, can be understood to refer to electrical connections.

[0014] Figure 1 shows a schematic overall configuration of the system SYS according to the embodiment of this disclosure. The system SYS comprises a semiconductor device 1 and an MCU (Micro Controller Unit) 2.

[0015] Figure 2 is an external perspective view of semiconductor device 1. Semiconductor device 1 is an electronic component comprising a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and a plurality of external terminals exposed from the housing to the outside of semiconductor device 1. Semiconductor device 1 is formed by enclosing the semiconductor chip in a housing (package) made of resin. Note that the number of external terminals and the type of housing shown in Figure 2 are merely examples, and they can be designed arbitrarily.

[0016] In the following description, unless otherwise specified, "external terminals" refers to external terminals provided on the semiconductor device 1. Terminals built into the semiconductor device 1 are called internal terminals. Internal terminals are terminals that are not exposed from the housing of the semiconductor device 1, such as terminals on a semiconductor integrated circuit. Wiring provided on the outside of the semiconductor device 1 is called external wiring. The MCU2 is an external device for the semiconductor device 1. One or more external terminals are connected to the MCU2 through one or more external wires, thereby enabling the transmission and reception of necessary signals between the semiconductor device 1 and the MCU2.

[0017] A power supply voltage (positive DC voltage) of 1 or higher is supplied to the semiconductor device 1 from a voltage source not shown, and each circuit within the semiconductor device 1 is driven based on the supplied power supply voltage. Although not specifically shown, a ground terminal, which is a type of external terminal, is connected to ground. Each circuit within the semiconductor device 1 can operate with reference to the ground potential.

[0018] The semiconductor device 1 has a memory circuit MM. The memory circuit MM may be a memory classified as a register. Setting information is stored in the memory circuit MM, and the semiconductor device 1 performs operations according to the setting information. The MCU 2 can write desired setting information to the memory circuit MM by sending a predetermined command to the semiconductor device 1.

[0019] The semiconductor device 1 includes a target circuit whose characteristics are to be calibrated, and the characteristics of the target circuit are calibrated through the execution of a calibration operation. Specific examples of the target circuit and specific examples of the calibration operation will be described in the following multiple embodiments. In this embodiment, the matters described above apply to each of the following embodiments unless otherwise specified and without contradiction. In the event of any contradiction between the matters described above and those described in each embodiment, the description in each embodiment may take precedence. Furthermore, unless there is a contradiction, the matters described in any of the multiple embodiments shown below can be applied to any other embodiment (i.e., it is possible to combine any two or more embodiments from the multiple embodiments).

[0020] <<First Example>> A first embodiment will be described. Figure 3 shows the configuration of the current sensor 100 according to the first embodiment. The semiconductor device 1 according to the first embodiment has the current sensor 100. The current sensor 100 is formed by a semiconductor integrated circuit in the semiconductor device 1.

[0021] The current sensor 100 includes an amplifier circuit 10, a comparator 20, a logic circuit 30, and a reference voltage setting circuit 40. Terminals AINP, AINN, AOUT, and REF are four external terminals provided in the semiconductor device 1. However, any one or more of the terminals AINP, AINN, AOUT, and REF may be internal terminals. Terminals AINP, AINN, and AOUT may be understood to be included in the components of the current sensor 100, or may be understood to be connected to the current sensor 100 without being included in the components of the current sensor 100.

[0022] Wiring WR S is an external wiring. The current flowing on the wiring WR S is represented by the symbol "I S ". The current flowing on the wiring WR S is provided with a sense resistor R SNS in series. The first end of the sense resistor R SNS is connected to the terminal AINP, and the second end of the sense resistor R SNS is connected to the terminal AINN and also connected to the ground. The current I S flows through the sense resistor R SNS . Therefore, a voltage drop represented by the product of the value of the current I SNS and the resistance value of the sense resistor R S occurs across both ends of the sense resistor R SNS (and thus between the terminals AINP and AINN).

[0023] The current sensor 100 detects the current I S based on the voltage ΔV between the terminals AINP and AINN, and outputs a signal SOUT indicating the detection result from the terminal AOUT. The voltage ΔV represents the voltage of the terminal AINP as seen from the potential of the terminal AINN. The terminal AOUT is connected to the MCU2 through the wiring WR AOUT which is an external wiring. That is, the signal SOUT is output from the terminal AOUT to the MCU2. The signal SOUT is an analog voltage signal indicating the output voltage V A of the amplifier circuit 10. Therefore, an analog output voltage V A is applied to the terminal AOUT. However, in the current sensor 100, the analog output voltage V AA configuration that converts the signal to a digital signal and outputs it to the MCU2 could also be adopted.

[0024] current I S To detect current I S This refers to detecting the magnitude and orientation of current I. S The direction is current I S It is expressed in terms of polarity, and current I S The polarity of a resistor is positive and negative. Sense resistor R SNS From the first end to the sense resistor R SNS Current I flowing toward the second end (ground) S Assuming the polarity is positive, the current I is in the opposite direction. S Assume the polarity is negative. Current I S The voltage corresponding to the magnitude and orientation is the output voltage V. A This is the result. Furthermore, current I S When the polarity is fixed to either positive or negative, the current sensor 100 is the current I S Magnitude (current I) S It may also be acceptable to only detect the value of ).

[0025] Voltage V at terminal REF REF_IN It receives a supply of voltage V. REF_IN This is a positive DC voltage supplied from an external voltage source of the semiconductor device 1. The reference voltage setting circuit 40 is connected to terminal REF, and the voltage V REF_IN Based on the reference voltage V REF The reference voltage setting circuit 40 sets and outputs the voltage V based on the reference voltage setting information stored in the memory circuit MM, for example. REF_IN 1 / 2 of the voltage or voltage V REF_IN A voltage of 1 / 4 of the reference voltage V REF Set to the reference voltage V. REF The value of can be arbitrary, and “V REF_IN =V REF "That's fine."

[0026] The amplifier circuit 10 is a differential amplifier circuit comprising an operational amplifier AMP and resistors R1 to R4. The voltage ΔV corresponds to the input voltage of the amplifier circuit 10. The operational amplifier AMP has an inverting input terminal, a non-inverting input terminal, and an output terminal. Specifically, one end of resistor R1 is connected to terminal AINN, and the other end of resistor R1 is connected to the inverting input terminal of the operational amplifier AMP. One end of resistor R2 is connected to the inverting input terminal of the operational amplifier AMP, and the other end of resistor R2 is connected to the output terminal of the operational amplifier AMP. One end of resistor R3 is connected to terminal AINP, and the other end of resistor R3 is connected to the non-inverting input terminal of the operational amplifier AMP. One end of resistor R4 is connected to the non-inverting input terminal of the operational amplifier AMP. The other end of resistor R4 is connected to the reference voltage V REF It is connected to the wiring to which the reference voltage V is applied. REF The output terminal of the operational amplifier AMP corresponds to the output terminal of the amplification circuit 10, and the output terminal of the operational amplifier AMP (and therefore the output terminal of the amplification circuit 10) is connected to terminal AOUT. Current I is received from the output terminal of the operational amplifier AMP. S The corresponding voltage V A The following will be output.

[0027] Here, the resistance values ​​of resistors R1 and R3 are assumed to be equal, and the resistance values ​​of resistors R2 and R4 are assumed to be equal. Assuming that the offset voltage described later is zero, if the voltage ΔV is zero, then "V A =V REF " and if "ΔV>0", then "V A >V REF " and if "ΔV<0", then "V A <V REF "When "ΔV>0" or "ΔV<0", as the absolute value of the voltage ΔV increases, the voltage V A and reference voltage V REF The gap between them will increase.

[0028] Furthermore, the operational amplifier AMP is powered by the amplifier power supply voltage V generated within the semiconductor device 1. PAMP It is driven based on the following: Amplifier power supply voltage V PAMPis a positive DC voltage and may be generated, for example, using a bandgap reference. Furthermore, the amplification factor of the amplifier circuit 10 may be variable. For example, resistors R1 and R3 can be configured as variable resistors, and the amplification factor of the amplifier circuit 10 can be changed by changing the resistance value of each variable resistor. For example, the amplification factor of the amplifier circuit 10 may be set based on amplification factor setting information stored in the memory circuit MM.

[0029] The comparator 20 has an inverting input terminal, a non-inverting input terminal, and an output terminal. The comparator 20 compares the voltage applied to its non-inverting input terminal with the voltage applied to its inverting input terminal and outputs a signal CMP from its output terminal according to the comparison result. The signal CMP can be high level or low level. The inverting input terminal of the comparator 20 is connected to a reference voltage V REF It is connected to the wiring to which the reference voltage V is applied. REF The non-inverting input terminal of comparator 20 receives the output voltage V of the operational amplifier AMP. A It is connected to the wiring to which the voltage V is applied, and the output voltage V A It receives. Therefore, comparator 20 receives "V A >V REF If the following is true (i.e., voltage V A The reference voltage V REF If it is higher than (V), it outputs a high-level signal CMP, A <V REF If the following is true (i.e., reference voltage V REF Voltage V A If it is higher than (V), it outputs a low-level signal CMP. A =V REF When the condition is met, the signal CMP will be either high or low. The output signal CMP of comparator 20 is supplied to logic circuit 30.

[0030] The logic circuit 30 has the function of calibrating the offset voltage of the amplifier circuit 10 based on the signal CMP. In this embodiment, the offset voltage of the amplifier circuit 10 will be simply referred to as the offset voltage. The calibration of the offset voltage is achieved by a calibration circuit CRB1 having a comparator 20 and the logic circuit 30. The offset voltage is the voltage V when the voltage ΔV is zero. A and V REF This is the difference between the two. The amplification circuit 10 is provided with an adjustment circuit for adjusting the offset voltage, and the logic circuit 30 can calibrate the offset voltage through the control of the adjustment circuit. The logic circuit 30 sends a digital signal DAC to the adjustment circuit. IN The following will be output.

[0031] Figure 4 shows a schematic configuration of the operational amplifier AMP. The operational amplifier AMP comprises an input stage 11 and an output stage 12. The input stage 11 is connected to the non-inverting input terminal and the inverting input terminal of the operational amplifier AMP, and a voltage V corresponding to the voltage between the non-inverting input terminal and the inverting input terminal is connected. A It generates '. Output stage 12 has a voltage V A Based on ', voltage V A This is generated and output from the output terminal of the operational amplifier AMP. At this time, due to the action of an imaginary short, the output stage 12 generates a voltage V such that the potential difference between the non-inverting input terminal and the inverting input terminal of the operational amplifier AMP approaches zero. A This generates the following: As a result, in the amplifier circuit 10, if the input voltage ΔV is zero and the offset voltage is zero, then the output voltage V A The reference voltage is V ERF This is equal to:

[0032] Figure 5 shows the circuit diagrams of the input stage 11 and the adjustment circuit 13. The adjustment circuit 13 may be understood as being built into the operational amplifier AMP, or as being connected to the operational amplifier AMP. In the configuration of Figure 5, the input stage 11 comprises transistors 111 and 112, a constant current source 113, and resistors 114 and 115. The adjustment circuit 13 comprises a DAC 131, a constant current source 132, and transistors 133 and 134. Transistors 111, 112, 133, and 134 are P-channel type MOSFETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor".

[0033] A differential input pair is formed by transistors 111 and 112. Transistors 111 and 112 are formed to have the same structure and electrical characteristics as each other. It is preferable that transistors 133 and 134 also be formed to have the same structure and electrical characteristics as each other. Resistors 114 and 115 are formed to have the same resistance value as each other.

[0034] The sources of transistors 111 and 112 are connected to each other. The constant current source 113 is powered by the power supply voltage V PAMP A constant current I is applied from the node where the current is applied to the node where the sources of transistors 111 and 112 are connected. CC1 The gates of transistors 111 and 112 are connected to the non-inverting and inverting input terminals of the operational amplifier AMP, respectively. The drain of transistor 111 is connected to the first terminal of resistor 114, and the second terminal of resistor 114 is connected to ground. The drain of transistor 112 is connected to the first terminal of resistor 115, and the second terminal of resistor 115 is connected to ground. The voltage at the first terminal of resistor 115 as seen from the potential at the first terminal of resistor 114 is voltage V A It is supplied to the output stage 12 (see Figure 4) as '.

[0035] The sources of transistors 133 and 134 are connected to each other. The constant current source 132 is powered by the power supply voltage V PAMPA constant current I is supplied from the node to which the addition is made toward the node where the sources of the transistors 133 and 134 are connected to each other. The drain of the transistor 133 is connected to the drain of the transistor 111. The drain of the transistor 134 is connected to the drain of the transistor 112. CC2

[0036] DAC131 is a digital / analog converter that converts the digital signal DAC IN supplied from the logic circuit 30 into an analog signal and outputs it. The analog signal output from DAC131 is an analog voltage signal, and the analog voltage represented by the analog voltage signal is referred to by the symbol "DAC OUT ". DAC131 can be said to be a circuit that converts the digital signal DAC IN into the analog voltage DAC OUT and outputs it. DAC131 supplies the analog voltage DAC OUT to the gate of the transistor 133. A predetermined bias voltage Vb is applied to the gate of the transistor 134. For example, the voltage at the center in the variable range of the analog voltage DAC OUT may be set as the bias voltage Vb.

[0037] The circuit operation of FIG. 5 will be described. For convenience of explanation, first, assume that "I CC2 = 0" and the transistors 111 and 112 operate ideally. In addition, it is considered that there is no difference in the resistance values of the resistors 114 and 115. In this case, if the potential difference between the non-inverting input terminal and the inverting input terminal of the operational amplifier AMP is zero, the drain current values of the transistors 111 and 112 are the same and the voltage V A ' becomes 0V. When the potential difference between the non-inverting input terminal and the inverting input terminal of the operational amplifier AMP is not zero, a difference occurs in the drain current values of the transistors 111 and 112 according to the potential difference, and as a result, the voltage V A ' becomes a positive or negative voltage. Thus, when the potential difference between the non-inverting input terminal and the inverting input terminal of the operational amplifier AMP is zero, the voltage V ATransistors 111 and 112 are formed aiming at making ‘ CC2 ’ be 0V. However, actually, due to manufacturing variations etc., deviations may occur in the electrical characteristics of transistors 111 and 112. As a result, when the above potential difference is zero, a difference occurs in the drain current values of transistors 111 and 112, and under the assumption that “I A =0”, the voltage V

[0038] ’ may not become 0V. OUT The adjustment circuit 13 works to cancel the above difference in the drain current values. That is, by installing the adjustment circuit 13, the combined current of the drain currents of transistors 111 and 133 flows through the resistor 114, and the combined current of the drain currents of transistors 112 and 134 flows through the resistor 115. By adjusting the voltage DAC A ’, the drain current of the transistior 133 changes. Therefore, when the input voltage ΔV (see Fig. 3) to the amplifier circuit 10 is zero, the voltage V A ’ becomes 0V (that is, the output voltage V REF of the amplifier circuit 10 coincides with the reference voltage V OUT ), and if the voltage DAC

[0039] is set, the offset voltage becomes zero. IN Fig. 6 shows the relationship between the digital signal DAC OUT and the analog voltage DAC IN . The DAC 131 is an m-bit digital / analog converter. As shown in Fig. 7, the digital signal DAC IN is a digital signal for m bits from the first bit to the mth bit. m can be any integer greater than or equal to 2. For example, “m = 10”. The ith bit in the digital signal DAC IN is referred to as bit B[i]. i represents any integer greater than or equal to 1 and less than or equal to m. It is assumed that bit B[i] is the upper bit of bit B[i + 1] (here, i represents a natural number less than or equal to (m - 1)). Therefore, among bits B[1] to B[m] in the digital signal DAC

[0040] <0), bit B[1] is the most significant bit and bit B[m] is the least significant bit. Digital signal DAC IN Each bit in this has a binary value of either 0 or 1. The binary value of bit B[i] is represented by the symbol "VAL[i]". Furthermore, m bits of digital signal DAC IN The value of is called the digital value D_VAL. When considered in decimal, the digital value D_VAL is the decimal equivalent of bit B[1] (2 m-1 ×VAL[1]) and the decimal equivalent value corresponding to bit B[2] (2 m-2 ×VAL[2]) and the decimal equivalent value corresponding to bit B[3] (2 m-3 ×VAL[3]) and..., the decimal equivalent value (2) corresponding to bit B[m] 0 It is the sum of ×VAL[m]) and .

[0041] Analog Voltage DAC OUT The analog voltage DAC is expressed as the product of a digital value D_VAL and a unit voltage of a predetermined magnitude, and increases linearly as the digital value D_VAL increases. OUT This changes, and as a result, the offset voltage changes through the change in the drain current of transistor 133. In this way, the adjustment circuit 13 controls the digital signal DAC supplied from the logic circuit 30. IN The offset voltage of the amplifier circuit 10 is changed accordingly (and therefore according to the digital value D_VAL). Increasing the amount of change in the digital value D_VAL increases the amount of change in the drain current of transistor 133, and as a result, the amount of change in the offset voltage also increases.

[0042] The calibration circuit CRB1 can perform a calibration operation OP1. Calibration operation OP1 is performed on the amplifier circuit 10 to calibrate the offset voltage. For example, the calibration circuit CRB1 performs calibration operation OP1 in response to a predetermined start signal from the MCU2 being received by the semiconductor device 1. Alternatively, calibration operation OP1 may be performed when the power supply voltage to the semiconductor device 1 is started and the semiconductor device 1 starts up, regardless of the signal from the MCU2. In any case, during the period in which calibration operation OP1 is performed, the current I SAssume that this value is kept at zero.

[0043] Figure 8 shows the flowchart of the calibration operation OP1. In Figure 8, j represents a variable managed and updated by the logic circuit 30. In the calibration operation OP1, first, in step S11, the variable j is set to "1". In the following step S12, the j-th unit operation is performed on the amplifier circuit 10. Details of the unit operation will be described later, but the logic circuit 30 derives a calibration candidate value during the unit operation. The calibration candidate value corresponds to a candidate for the digital value D_VAL used to calibrate the offset voltage. The calibration candidate value derived in the j-th unit operation is represented by the symbol "D_A[j]".

[0044] In step S13, following step S12, the logic circuit 30 determines whether "j=n" is true or false. n is a predetermined integer value of 2 or more. For example, "n=3". If "j=n" is true (Y in step S13), the process proceeds to step S15. If "j=n" is false (N in step S13), the process proceeds to step S14, where 1 is added to the variable j, and then the process returns to step S12. As a result, by the time the process proceeds to step S15, the calibration candidate values ​​D_A[1] to D_A[n] have been derived. Calibration operation OP1 includes evaluation operation OP1a, and evaluation operation OP1a consists of the processes in steps S11 to S14. In evaluation operation OP1a, a unit operation is repeatedly executed n times on the amplifier circuit 10, thereby deriving the calibration candidate values ​​D_A[1] to D_A[n].

[0045] In step S15, the logic circuit 30 determines whether a predetermined normal termination condition is met based on the calibration candidate values ​​D_A[1] to D_A[n] (in other words, it determines whether the calibration candidate values ​​D_A[1] to D_A[n] satisfy the normal termination condition). The normal termination condition in the first embodiment is a condition whose success or failure depends on the variation in the calibration candidate values ​​D_A[1] to D_A[n]. Therefore, the logic circuit 30 determines whether a normal termination condition is met based on the variation in the calibration candidate values ​​D_A[1] to D_A[n].

[0046] More specifically, the logic circuit 30 identifies the maximum and minimum values ​​among the calibration candidate values ​​D_A[1] to D_A[n]. The difference between the identified maximum and minimum values ​​is then set to the specified value VAL. THA The logic circuit 30 determines that the normal termination condition is met when the following conditions are met (i.e., it determines that the calibration candidate values ​​D_A[1] to D_A[n] satisfy the normal termination condition): The difference between the identified maximum and minimum values ​​is the specified value VAL. THA When it exceeds this value, the logic circuit 30 determines that the normal termination condition is not met. Default value VAL THA It has a predetermined positive value (for example, 2 or 3). As a variation, the logic circuit 30 derives the variance of the calibration candidate values ​​D_A[1] to D_A[n], and the derived variance is the specified value VAL THA You may also determine that the normal termination condition is met when the following conditions are met, and that the normal termination condition is not met when the following conditions are not met.

[0047] In step S15, if the normal termination condition is met (Y in step S15), the process proceeds to step S16. In step S16, the logic circuit 30 sets the actual calibration value D_R based on the average of the calibration candidate values ​​D_A[1] to D_A[n]. That is, the average value of the calibration candidate values ​​D_A[1] to D_A[n] is set to the actual calibration value D_R. In this case, if the sum of the calibration candidate values ​​D_A[1] to D_A[n] is not divisible by the value "n", the average value of the calibration candidate values ​​D_A[1] to D_A[n] can be derived by truncating or rounding the decimal part. In step S17 following step S16, the logic circuit 30 sets the actual calibration value D_R as the digital value D_VAL in the digital signal DAC. IN Output to DAC131.

[0048] Upon completion of step S17, the calibration operation OP1 is completed and the offset voltage is calibrated. After step S17, the voltage DAC OUT The voltage is maintained at the voltage corresponding to the actual calibration value D_R (i.e., the voltage obtained by converting the actual calibration value D_R into an analog voltage signal using DAC131), and the offset voltage is zero or a voltage that is sufficiently close to zero.

[0049] During the execution period of calibration operation OP1, semiconductor device 1 is in a standby state, and after the completion of calibration operation OP1, semiconductor device 1 transitions to the operational state. In the operational state, current I S The wiring WR S The current I flows from the amplifier circuit 10, which has been calibrated using the actual calibration value D_R. S The corresponding voltage V A The following is output. And the voltage V A The signal SOUT, which represents this, is supplied to the MCU2.

[0050] If the normal termination condition is not met in step S15, the process proceeds to step S18 (N of step S15). The failure of the normal termination condition is equivalent to the calibration candidate values ​​D_A[1] to D_A[n] deviating from the normal termination condition. In step S18, the logic circuit 30 discards the calibration candidate values ​​D_A[1] to D_A[n] derived in the evaluation operation OP1a consisting of steps S11 to S14, and then returns to step S11. Therefore, if step S18 is reached, the evaluation operation OP1a is executed again, and the calibration candidate values ​​D_A[1] to D_A[n] are re-derived in the re-executed evaluation operation OP1a.

[0051] Furthermore, if the normal termination condition is not met in step S15, the process may proceed to step S18a, as shown in Figure 9. In step S18a, the logic circuit 30 executes error processing and completes the calibration operation OP1. Error processing includes outputting a predetermined error signal from the semiconductor device 1 to the MCU 2. The error signal indicates that the calibration operation OP1 did not complete normally. Alternatively, the error signal indicates that some kind of abnormality has been detected in the semiconductor device 1. The flowchart in Figure 8 may be used, and the above error processing may be performed only if the normal termination condition is not met even after repeating the evaluation operation OP1a L times (L is any integer greater than or equal to 2).

[0052] In the calibration operation OP1, the circuit whose characteristics are to be calibrated is referred to as the target circuit. In each unit operation, the calibration circuit CRB1 evaluates the characteristics of the target circuit while changing the digital value D_VAL, and derives the digital value that minimizes the difference between the characteristics of the target circuit and the target characteristics as the calibration candidate value based on the evaluation results. In this embodiment, the target circuit is an amplifier circuit 10, and the characteristic of the target circuit to be calibrated is the offset voltage; therefore, the target characteristic is represented by the target voltage. Here, the target voltage represents the target value of the offset voltage (ideal offset voltage), which is 0V. That is, in the unit operation in this embodiment, the offset voltage is evaluated while changing the digital value D_VAL, and the digital value D_VAL that minimizes the difference between the offset voltage and the target voltage (in other words, the digital value D_VAL that minimizes the offset voltage) is derived as the calibration candidate value based on the evaluation results.

[0053] The calibration circuit CRB1 derives candidate calibration values, which form the basis of the actual calibration value, through binary search during unit operation. In binary search, digital signal DAC IN For each bit in the expression, from the most significant bit (B[1]) to the least significant bit (B[m]), a binary value suitable for calibrating the offset voltage is identified.

[0054] During the binary search process, it may not be possible to find an ideal binary value due to reasons such as noise interference in the semiconductor device 1. In particular, when searching for a calibration binary value for relatively higher bits, it is possible that an inappropriate binary value may be selected as the calibration value due to the influence of noise. In this case, if the offset voltage calibration is performed using the result as is, the offset voltage may increase compared to before calibration. Taking this into consideration, in this embodiment, the unit operation is performed multiple times, and candidate calibration values ​​(calibration candidate values) are derived in each unit operation. When the variation between the multiple calibration candidate values ​​is small, it is determined that a calibration candidate value unaffected by noise has been obtained, and the actual calibration value to be used is set based on the multiple calibration candidate values. This makes it possible to perform proper calibration that is less susceptible to the influence of noise.

[0055] Figure 10 shows a flowchart of the unit operation. As mentioned above, in binary search, the digital signal DAC IN For each bit in the equation, from the most significant bit (B[1]) to the least significant bit (B[m]), a binary value suitable for offset voltage calibration is identified. In order to identify a binary value suitable for offset voltage calibration for each bit, the logic circuit 30 classifies each bit B[1] to B[m] into one of the following in a unit operation: a bit to be evaluated, an unevaluated bit, or an evaluated bit.

[0056] The bits to be evaluated are the bits that are evaluated and set to determine the correct binary value in this case (the bits that are evaluated to determine whether the correct binary value is 0 or 1). Evaluated bits are the bits after the correct binary value has been evaluated and set. Unevaluated bits are the bits before the correct binary value has been evaluated and set.

[0057] A single unit operation will be explained with reference to Figure 10. Note that the variable i referred to in the explanation of the unit operation is a variable managed and updated by the logic circuit 30. In the unit operation, first in step S101, the logic circuit 30 sets the most significant bit, bit B[1], as the bit to be evaluated, and sets bits B[2] to B[m] as unevaluated bits. In the following step S102, the value 1 is assigned to the variable i, and then the process proceeds to step S103.

[0058] In step S103, the logic circuit 30 sets the binary value of the bit to be evaluated to "1" and sets the binary values ​​of all unevaluated bits to "0". In step S103, which is executed when "i=1", the binary value VAL[1] of bit B[1], which is the bit to be evaluated, is set to "1", and the binary values ​​VAL[2] to VAL[m] of the unevaluated bits B[2] to B[m] are all set to "0". After step S103, the process proceeds to step S104.

[0059] In step S104, the DAC has a digital signal with current binary values ​​VAL[1] to VAL[m]. IN The logic circuit 30 outputs to the DAC131. Then, the digital signal DAC has the current binary values ​​VAL[1]~VAL[m]. IN Voltage DAC corresponding to OUT With the output signal from DAC131, the logic circuit 30 acquires the output signal CMP from comparator 20. In step S105, following step S104, the logic circuit 30 checks whether the acquired signal CMP is high level. If the acquired signal CMP is high level (Y in step S105), the process proceeds to step S106; however, if the acquired signal CMP is low level (N in step S105), the process proceeds to step S107.

[0060] High-level signal CMP is necessary for achieving zero offset voltage in current voltage DACs. OUT This means that the value is too high. Therefore, when the signal CMP is at a high level, in order to achieve a zero offset voltage, the binary value VAL[i] of the bit to be evaluated B[i] should be set to "0". For this reason, in step S106, the binary value VAL[i] of the bit to be evaluated B[i] is set to "0". After step S106, the process proceeds to step S108.

[0061] Low-level signal CMP is necessary for achieving zero offset voltage in the current voltage DAC. OUT This means that it is too low. Therefore, when the signal CMP is at a low level, in order to achieve a zero offset voltage, the binary value VAL[i] of the bit being evaluated B[i] should be set to "1". For this reason, in step S107, the binary value VAL[i] of the bit being evaluated B[i] is set to "1". However, since the binary value VAL[i] is set to "1" in step S103, in step S107 it is sufficient to keep the binary value VAL[i] at "1". After step S107, proceed to step S108.

[0062] The processing in steps S103 to S107 corresponds to the process of identifying a binary value (VAL[i]) suitable for offset voltage calibration with respect to the bit B[i] to be evaluated. A binary value suitable for offset voltage calibration is a binary value among the values ​​of "0" or "1" that is suitable for reducing the difference between the offset voltage and the target voltage (target value of the offset voltage; 0V). Since the target voltage is 0V, the binary value suitable for reducing the difference between the offset voltage and the target voltage is the binary value suitable for reducing the offset voltage. When the signal CMP acquired in step S104 is at a high level, setting the binary value VAL[i] of the bit B[i] to be evaluated to "0" reduces the above difference more than setting it to "1", so "0" is suitable for reducing the above difference. Conversely, when the signal CMP acquired in step S104 is at a low level, setting the binary value VAL[i] of the bit B[i] to be evaluated to "1" reduces the above difference more than setting it to "0", so "1" is suitable for reducing the above difference. As will become clear from the explanation below, the processing in steps S103 to S107 is performed bit by bit. Therefore, in unit operation by binary search, the digital signal DAC IN Bit by bit, from the most significant bit (B[1]) to the least significant bit (B[m]), a binary value suitable for reducing the difference between the offset voltage and the target voltage (target value of the offset voltage; 0V) is identified.

[0063] In step S108, the logic circuit 30 sets (classifies) the currently evaluated bit as an evaluated bit. In a single unit operation, once a bit is set as an evaluated bit, it remains as an evaluated bit thereafter, and the binary value of the evaluated bit remains unchanged. After step S108, the process proceeds to step S109.

[0064] In step S109, the logic circuit 30 determines the truth or falsehood of “i = m”. If “i = m” holds (Y in step S109), it proceeds to step S114. If “i = m” does not hold (N in step S109), it proceeds to step S110, adds 1 to the variable i, and then proceeds to step S111. In step S111, the logic circuit 30 determines the truth or falsehood of “i < m”. If “i < m” holds (Y in step S111), it proceeds to step S112. If “i < m” does not hold (N in step S111), it proceeds to step S113.

[0065] At the stage of proceeding to step S112, two or more bits are not evaluated bits. In step S112, the logic circuit 30 sets the uppermost bit among the bits that are not evaluated bits as the evaluation target bit, and sets the other bits as unevaluated bits. That is, in step S112, the logic circuit 30 sets bit B[i] as the evaluation target bit, and sets bits B[i + 1] to B[m] as unevaluated bits. After step S112, it returns to step S103 and the processes after step S103 described above are executed.

[0066] For example, in step S103 executed when “i = 2”, “1” is set to the binary value VAL[2] of bit B[2] which is the evaluation target bit, and “0” is set to all of the binary values VAL[3] to VAL[m] of bits B[3] to B[m] which are unevaluated bits. When “i = 2”, the binary value VAL[1] of the evaluated bit B[1] has the value set in the previous step S106 or S107. And when “i = 2”, after the processes of steps S104 and S105, the binary value VAL[2] of bit B[2] is set to “1” or “0” by step S106 or S107, and then bit B[2] is set as an evaluated bit in step S108. The same applies when the variable i is 3 or more.

[0067] At the stage where the process proceeds to step S113, "i=m" and bits B[1] to B[m-1] are set as evaluated bits, with only bit B[m] not being set as an evaluated bit. Therefore, in step S113, the logic circuit 30 sets bit B[m] as the bit to be evaluated. After step S113, the process returns to step S103 and the subsequent processing described above is executed. In step S103, which is executed when "i=m", the binary value VAL[m] of bit B[m], which is the bit to be evaluated, is set to "1". When "i=m", there are no bits that are classified as unevaluated bits.

[0068] When "i=m", the binary values ​​VAL[1]~VAL[m-1] of the evaluated bits B[1]~B[m-1] have the values ​​set in the previously executed steps S106 or S107. For example, consider the case where "m=4", and when "i=1", the first step S103~S105 is completed and the process proceeds to step S106, setting the evaluated bit B[1] to "0", when "i=2", the second step S103~S105 is completed and the process proceeds to step S107, setting the evaluated bit B[2] to "1", and when "i=3", the third step S103~S105 is completed and the process proceeds to step S107, setting the evaluated bit B[3] to "1". In this case, if "i=m=4", then in step S104, a digital signal DAC having "(VAL[1],VAL[2],VAL[3],VAL[4])=(0,1,1,1)" is generated. IN This is output from the logic circuit 30 to the DAC131. Then, the digital signal DAC has "(VAL[1],VAL[2],VAL[3],VAL[4])=(0,1,1,1)". IN Voltage DAC corresponding to OUT With the output signal from DAC131, the logic circuit 30 will acquire the output signal CMP from comparator 20.

[0069] When "i=m", after processing in steps S104 and S105, the binary value VAL[m] of bit B[m] is set to "1" or "0" in step S106 or S107, and then in step S108, bit B[m] is set to the evaluated bit.

[0070] When "i=m", step S109 is reached, and the process transitions to step S114. At the stage of reaching step S114, all bits B[1] to B[m] are set to evaluated bits. In step S114, the logic circuit 30 sets the digital value D_VAL, which is represented by the binary values ​​VAL[1] to VAL[m] of the evaluated bits B[1] to B[m], as the calibration candidate value, and completes one unit operation. The calibration candidate value set in step S114 corresponds to the calibration candidate value D_A[j] in the calibration operation OP1 shown in Figure 8. By repeating the unit operation shown in Figure 10 n times, the calibration candidate values ​​D_A[1] to D_A[n] are obtained.

[0071] <<Second Example>> A second embodiment will now be described. Figure 11 shows the configuration of the current sensor 200 according to the second embodiment. The semiconductor device 1 according to the second embodiment has the current sensor 200. The current sensor 200 is formed by a semiconductor integrated circuit in the semiconductor device 1. The current sensor 200 includes a comparator 220, a logic circuit 230, and a reference voltage setting circuit 40. Terminal REF is an external terminal provided on the semiconductor device 1. The reference voltage setting circuit 40 according to the second embodiment is the same as the reference voltage setting circuit 40 according to the first embodiment, and the voltage V supplied to terminal REF REF_IN Based on the reference voltage V REF Set and output the following.

[0072] In the second embodiment, the system SYS (see Figure 1) is provided with first to k-th blocks BLK, where k is any integer greater than or equal to 2. Each block BLK has the same configuration as the others. Each block BLK includes an amplification circuit 10, terminals AINP, AINN and AOUT, and wiring WR S and WR AOUT And, sense resistance R SNSIt has, and each wiring WR S The current flowing through it is represented by the symbol "I S Referenced in “. The amplification circuit 10 in each block BLK is a component of the current sensor 200 and is therefore provided in the semiconductor device 1. The terminals AINP, AINN and AOUT in each block BLK are external terminals of the semiconductor device 1. The wiring WR in each block BLK S and WR AOUT This is wiring provided outside the semiconductor device 1 (i.e., external wiring). Sense resistor R in each block BLK SNS This is a resistor located outside of semiconductor device 1.

[0073] The amplification circuit 10 in each block BLK is the same as the amplification circuit 10 in the first embodiment, and therefore has the same configuration and operates the same as the amplification circuit 10 in the first embodiment. In addition, the amplification circuit 10 in each block BLK is connected to terminals AINP, AINN, and AOUT and wiring WR S and WR AOUT and sense resistance R SNS The connection relationship is as follows: Amplifier circuit 10 in the first embodiment, terminals AINP, AINN and AOUT, and wiring WR S and WR AOUT and sense resistance R SNS The connection relationship is the same as that in the first embodiment. That is, the amplifier circuit 10 and terminals AINP, AINN and AOUT and wiring WR S and WR AOUT and sense resistance R SNS k sets of such circuit sets are provided in the system SYS according to the second embodiment. The matters described in the first embodiment regarding the above circuit sets also apply to the circuit sets in each block BLK of the second embodiment, to the extent that they do not contradict each other.

[0074] The current sensor 200 measures the current I based on the voltage ΔV between terminals AINP and AINN for each block BLK. S It detects the detection and outputs a signal SOUT indicating the detection result from terminal AOUT. In each block BLK, the voltage ΔV represents the voltage at terminal AINP as seen from the potential of terminal AINN. In each block BLK, terminal AOUT is the external wiring WRAOUT It is connected to the MCU2 via this. In other words, for each block BLK, the signal SOUT is output to the MCU2 from terminal AOUT. In each block BLK, the signal SOUT is the output voltage V of the amplification circuit 10. A This is an analog voltage signal indicating the analog output voltage V. Therefore, the AOUT terminal has an analog output voltage V. A In each block BLK, the voltage ΔV corresponds to the input voltage of the amplification circuit 10, and current I is drawn from the output terminal of the operational amplifier AMP in the amplification circuit 10. S The corresponding voltage V A The output is V. A A configuration that converts the signal to a digital signal and outputs it to the MCU2 could also be adopted.

[0075] Hereafter, as needed (see Figure 12), the p-th block BLK will be denoted as block BLK[p]. Here, p represents an integer between 1 and k, inclusive. Also, as needed (see Figure 12), the amplifier circuit 10 in block BLK[p], terminals AINP, AINN, AOUT, and wiring WR will be denoted. S , wiring WR AOUT , sense resistance R SNS , current I S , voltage ΔV, voltage V A The signal SOUT is connected to the following terminals: amplifier circuit 10[p], terminal AINP[p], terminal AINN[p], terminal AOUT[p], and wiring WR. S [p], wiring WR AOUT [p], sense resistance R SNS [p], current I S [p], voltage ΔV[p], voltage V A [p] is denoted as the signal SOUT[p].

[0076] The current sensor 200 is equipped with a calibration circuit CRB2. The calibration circuit CRB2 has the function of calibrating the offset voltages of each of the amplifier circuits 10[1] to 10[k]. The offset voltage of amplifier circuit 10[p] is the voltage V when the voltage ΔV[p] is zero. A [p] and V REFIt is the difference between them. Assuming that the offset voltage of the amplifier circuit 10[p] is zero, if the voltage ΔV[p] is zero then "V A [p]=V REF " and if "ΔV[p]>0", then "V A [p]>V REF " and if "ΔV[p]<0", then "V A [p] <V REF When "ΔV[p]>0" or "ΔV[p]<0", the voltage V increases as the absolute value of the voltage ΔV[p] increases. A [p] and reference voltage V REF The gap between them will increase.

[0077] Each amplifier circuit 10 is provided with an adjustment circuit 13 (see Figure 5) for adjusting the offset voltage, and the logic circuit 230 can calibrate the offset voltage for each amplifier circuit 10 through the control of the adjustment circuit 13. From the logic circuit 230, for each block BLK, a digital signal DAC is sent to the adjustment circuit 13 of the amplifier circuit 10 (more specifically to the DAC 131 within the adjustment circuit 13). IN The following is output. A digital signal DAC is output from the logic circuit 230 to the adjustment circuit 13 of the amplification circuit 10[p]. IN In particular, digital signal DAC IN It is denoted as [p].

[0078] Digital signal DAC for each block BLK IN The configuration is as described in the first embodiment (see Figure 7). For each block BLK, the adjustment circuit 13 receives a digital signal DAC supplied from the logic circuit 230. IN The offset voltage of the amplification circuit 10 is changed accordingly (and therefore according to the digital value D_VAL). In each block BLK, increasing the amount of change in the digital value D_VAL will increase the amount of change in the offset voltage. Digital signal DAC IN The digital value D_VAL at [p] (see Figure 6) will be specifically referred to as the digital value D_VAL[p].

[0079] The calibration circuit CRB2 comprises a logic circuit 230 and one or more comparators 220. The total number of comparators 220 provided in the calibration circuit CRB2 may be less than k, but here, as shown in Figure 13, it is assumed that k comparators 220 are provided in the calibration circuit CRB2. When it is necessary to distinguish the k comparators 220 from each other, the k comparators 220 are denoted as comparators 220[1] to 220[k]. Comparators 220[1] to 220[k] are each the same as comparator 20 according to the first embodiment. Each comparator 220 compares the voltage applied to its non-inverting input terminal with the voltage applied to its inverting input terminal and outputs a signal CMP from its output terminal according to the comparison result. The signal CMP has a high level or a low level. The signal CMP output from comparator 220[p] is specifically denoted as signal CMP[p].

[0080] Each inverting input terminal of comparator 220[1]~220[k] has a reference voltage V REF It is connected to the wiring to which the reference voltage V is applied. REF The non-inverting input terminal of comparator 220[p] receives the output voltage V of amplifier circuit 10[p]. A [p] is connected to the wiring to which the voltage V is applied. A [p] is received. Therefore, comparator 220[p] is “V A [p]>V REF If the following is true (i.e., voltage V A [p] is the reference voltage V REF If it is higher than ( ), it outputs a high-level signal CMP[p], “V A [p] <V REF If the following is true (i.e., reference voltage V REF Voltage V A If it is higher than [p], it outputs a low-level signal CMP[p]. A [p]=V REF When the condition is met, the signal CMP[p] will be either high or low. The output signal CMP of each comparator 220 is supplied to the logic circuit 230.

[0081] The calibration circuit CRB2 can perform calibration operation OP2. Calibration operation OP2 is performed on the amplifier circuits 10[1] to 10[k] to calibrate each offset voltage of the amplifier circuits 10[1] to 10[k]. For example, the calibration circuit CRB2 performs calibration operation OP2 in response to a predetermined start signal from the MCU2 being received by the semiconductor device 1. Alternatively, calibration operation OP2 may be performed when the power supply voltage to the semiconductor device 1 is started and the semiconductor device 1 is started up, regardless of the signal from the MCU2. In any case, during the period in which calibration operation OP2 is performed, the current I S [1]~I S Assume that all values ​​of [k] are kept zero.

[0082] Figure 14 shows a flowchart of the calibration operation OP2. In the calibration operation OP2, first, the evaluation operation OP2a is executed in step S21. In the evaluation operation OP2a, unit operations are performed individually for the amplifier circuits 10[1] to 10[k]. The unit operations performed for one amplifier circuit 10 are the same as those described in the first embodiment, and the explanation of unit operations described in the first embodiment applies to the second embodiment. When applying this, one should read “logic circuit 30” in the description of the first embodiment as “logic circuit 230,” and when applying the explanation of the first embodiment to the unit operation for amplifier circuit 10[p], one should read “comparator 20” and “signal CMP” in the first embodiment as “comparator 220[p]” and “signal CMP[p],” respectively.

[0083] The evaluation operation OP2a derives calibration candidate values ​​D_B[1] to D_B[k] in the logic circuit 230. The calibration candidate value D_B[p] corresponds to a candidate digital value D_VAL[p] for calibrating the offset voltage of the amplifier circuit 10[p]. When the unit operation in Figure 10 is performed on the amplifier circuit 10[p], the calibration candidate value set in step S114 is the calibration candidate value D_B[p]. The unit operation in Figure 10 is performed on each of the amplifier circuits 10[1] to 10[k], thereby deriving the calibration candidate values ​​D_B[1] to D_B[k]. After step S21, proceed to step S22.

[0084] Furthermore, if the configuration shown in Figure 13 is adopted, unit operations for the amplifier circuits 10[1] to 10[k] can be performed simultaneously (i.e., in parallel). In the evaluation operation OP1a of the first embodiment, time is required to perform n unit operations sequentially in order to obtain all the necessary calibration candidate values. In contrast, in the evaluation operation OP2a of the second embodiment, all the necessary calibration candidate values ​​can be obtained in the execution time of one unit operation. Therefore, the time required for calibration can be reduced compared to the first embodiment.

[0085] In step S22, the logic circuit 230 determines whether a predetermined normal termination condition is met based on the calibration candidate values ​​D_B[1] to D_B[k] (in other words, it determines whether the calibration candidate values ​​D_B[1] to D_B[k] satisfy the normal termination condition). The normal termination condition in the second embodiment is a condition whose success or failure depends on the variation in the calibration candidate values ​​D_B[1] to D_B[k]. Therefore, the logic circuit 230 determines whether the normal termination condition is met based on the variation in the calibration candidate values ​​D_B[1] to D_B[k].

[0086] More specifically, the logic circuit 230 identifies the maximum and minimum values ​​among the calibration candidate values ​​D_B[1] to D_B[k]. The difference between the identified maximum and minimum values ​​is then set to the specified value VAL. THB The logic circuit 230 determines that the normal termination condition is met when the following conditions are met (i.e., it determines that the calibration candidate values ​​D_B[1] to D_B[k] satisfy the normal termination condition). On the other hand, the difference between the identified maximum and minimum values ​​is the specified value VAL. THB When it exceeds this value, the logic circuit 230 determines that the normal termination condition is not met. Default value VAL THB It has a predetermined positive value (e.g., 2 or 3). As a variation, the logic circuit 230 derives the variance of the calibration candidate values ​​D_B[1] to D_B[k], and the derived variance is the specified value VAL THB You may also determine that the normal termination condition is met when the following conditions are met, and that the normal termination condition is not met when the following conditions are not met.

[0087] In step S22, if the normal termination condition is met (Y in step S22), the process proceeds to step S23. In step S23, the logic circuit 230 sets the calibration candidate values ​​D_B[1] to D_B[k] to actual calibration values ​​D_R[1] to D_R[k], respectively. In step S24 following step S23, the logic circuit 230 sets a digital signal DAC for each amplification circuit 10, where the actual calibration value D_R[p] is set as the digital value D_VAL[p]. IN [p] is output to the DAC131 of the amplification circuit 10[p]. Therefore, the digital signal DAC has the actual calibration value D_R[1] as the digital value D_VAL[1]. IN [1] is output to the DAC131 of the amplification circuit 10[1], and the actual calibration value D_R[2] is used as the digital value D_VAL[2] in the digital signal DAC. IN [2] is output to the DAC131 of the amplification circuit 10[2]. The same applies to amplification circuits 10[3] to 10[k].

[0088] Upon completion of step S24, the calibration operation OP2 is completed and the offset voltage is calibrated. After the processing of step S24, for each amplifier circuit 10, the voltage DAC within amplifier circuit 10[p] is calibrated. OUT The voltage is maintained at a level corresponding to the actual calibration value D_R[p] (i.e., the voltage obtained by converting the actual calibration value D_R[p] into an analog voltage signal in the DAC131 within the amplification circuit 10[p]), and the offset voltage of the amplification circuit 10[p] becomes zero or a voltage sufficiently close to zero.

[0089] During the execution period of calibration operation OP2, semiconductor device 1 is in a standby state, and after the completion of calibration operation OP2, semiconductor device 1 transitions to the operational state. In the operational state, for each block BLK, current I S The wiring WR S The current I flows from the amplifier circuit 10, which has been calibrated using the actual calibration value D_R. S The corresponding voltage V A The following is output. Then, a voltage V is output for each block BLK. A The signal SOUT, which represents this, is supplied to the MCU2.

[0090] In step S22, if the normal termination condition is not met, the process proceeds to step S25 (N of step S22). The failure of the normal termination condition is equivalent to the calibration candidate values ​​D_B[1] to D_B[k] deviating from the normal termination condition. In step S25, the logic circuit 230 discards the calibration candidate values ​​D_B[1] to D_B[k] derived in the evaluation operation OP2a, and then returns to step S21. Therefore, if step S25 is reached, the evaluation operation OP2a is executed again, and the calibration candidate values ​​D_B[1] to D_B[k] are re-derived in the re-executed evaluation operation OP2a.

[0091] Furthermore, if the normal termination condition is not met in step S22, the process may proceed to step S25a, as shown in Figure 15. In step S25a, the logic circuit 230 performs error processing and completes the calibration operation OP2. Error processing includes outputting a predetermined error signal from the semiconductor device 1 to the MCU 2. The error signal indicates that the calibration operation OP2 did not complete normally. Alternatively, the error signal indicates that some kind of abnormality has been detected in the semiconductor device 1. The flowchart in Figure 14 may be used, and the above error processing may be performed only if the normal termination condition is not met even after repeating the evaluation operation OP2a L times (L is any integer greater than or equal to 2).

[0092] When the circuit whose characteristics are to be calibrated in the calibration operation OP2 is referred to as the target circuit, the calibration circuit CRB2 evaluates the characteristics of the target circuit for each target circuit while changing the digital value D_VAL in the corresponding unit operation, and derives the digital value that minimizes the difference between the characteristics of the target circuit and the target characteristics as the calibration candidate value based on the evaluation result. In this embodiment, each amplifier circuit 10 is the target circuit, the characteristic of the target circuit to be calibrated is the offset voltage, and therefore the target characteristic is represented by the target voltage. Here, the target voltage represents the target value of the offset voltage (ideal offset voltage), which is 0V. That is, for each target circuit, in the corresponding unit operation, the offset voltage is evaluated while changing the digital value D_VAL, and the digital value D_VAL that minimizes the difference between the offset voltage and the target voltage (in other words, the digital value D_VAL that minimizes the offset voltage) is derived as the calibration candidate value based on the evaluation result.

[0093] The calibration circuit CRB2 derives candidate calibration values, which form the basis of the actual calibration value, for each target circuit in the corresponding unit operation using binary search. In binary search, digital signal DAC IN For each bit in the expression, from the most significant bit (B[1]) to the least significant bit (B[m]), a binary value suitable for calibrating the offset voltage is identified.

[0094] During the binary search process, it may not be possible to find an ideal binary value due to reasons such as noise interference in the semiconductor device 1. In particular, when searching for a calibration binary value for relatively higher bits, it is possible that an inappropriate binary value may be selected as the calibration value due to the influence of noise. In this case, if the offset voltage calibration is performed using the result as is, the offset voltage may increase compared to before calibration. Taking this into consideration, in this embodiment, unit operations are performed individually for multiple target circuits with the same configuration (amplifier circuits 10[1] to 10[k] in this embodiment), and candidate calibration values ​​(calibration candidate values) are derived for each target circuit. When the variation between the multiple calibration candidate values ​​is small, it is determined that a calibration candidate value unaffected by noise has been obtained, and the obtained calibration candidate value is used as the actual calibration value for each target circuit. This makes it possible to perform proper calibration that is less affected by noise.

[0095] <<Third Example>> A third embodiment will be described. In the third embodiment, a modification technique applicable to the second embodiment will be described.

[0096] In the second embodiment, when the configuration shown in Figure 13 is adopted, as described above, unit operations for the amplifier circuits 10[1] to 10[k] can be performed simultaneously (i.e., in parallel). However, the unit operations for any two of the amplifier circuits 10[1] to 10[k] may be performed at different timings.

[0097] In the second embodiment, the total number of comparators 220 provided in the calibration circuit CRB2 may be less than k. In this case, the less than k comparators 220 can be used in a time-division manner to perform unit operation on the amplification circuits 10[1] to 10[k].

[0098] For example, if "k=4", the comparator 220 provided in the calibration circuit CRB2 may consist only of comparators 220[1] and 220[2]. In this case, a voltage V is applied to the non-inverting input terminal of comparator 220[1]. A [1] and VA A selector that selectively inputs either of [2] and a voltage V to the non-inverting input terminal of comparator 220[2] A [3] and V A A selector for selectively inputting either [4] is provided in the calibration circuit CRB2. Then, in the evaluation operation OP2a, after performing unit operations on the amplifier circuits 10[1] and 10[3], unit operations on the amplifier circuits 10[2] and 10[4] should be performed. At this time, when the unit operations on the amplifier circuits 10[1] and 10[3] are performed, voltage V is applied to the non-inverting input terminals of the comparators 220[1] and 220[2], respectively. A [1] and V A When [3] is input and unit operation is performed on the amplifier circuits 10[2] and 10[4], voltage V is applied to the non-inverting input terminals of comparators 220[1] and 220[2], respectively. A [2] and V A You should enter [4].

[0099] Alternatively, for example, if "k=3", the comparator 220 provided in the calibration circuit CRB2 may be only comparator 220[1]. In this case, a voltage V is applied to the non-inverting input terminal of comparator 220[1]. A [1]~V A A selector is provided in the calibration circuit CRB2 to selectively input one of [3]. Then, in the evaluation operation OP2a, the unit operation for amplifier circuit 10[1], the unit operation for amplifier circuit 10[2], and the unit operation for amplifier circuit 10[3] are performed in order. At this time, when the unit operation for amplifier circuit 10[p] is performed, a voltage V is applied to the non-inverting input terminal of comparator 220[1]. A You just need to enter [p] (where p is an integer between 1 and 3).

[0100] It is also possible to perform the calibration operation OP1 according to the first embodiment on the current sensor 200 according to the second embodiment. In this case, the calibration operation OP1 can be performed individually on the amplification circuits 10[1] to 10[k]. However, when calibrating multiple amplification circuits 10 having the same configuration, such as the current sensor 200, using the calibration operation OP2 according to the second embodiment is likely to shorten the time required for calibration.

[0101] <<Fourth Example>> A fourth embodiment will be described. As an example of a semiconductor device 1 including a current sensor 200, a gate driver 1a is shown in Figure 16. The system SYS according to the fourth embodiment is a motor drive system comprising a gate driver 1a, an MCU (Micro Controller Unit) 2, and a motor 3. In the gate driver 1a, "k=3" and a current sensor 200 (see Figure 12) having amplification circuits 10[1] to 10[3] is built into the gate driver 1a.

[0102] Motor 3 is a three-phase brushless DC motor equipped with three phase coils L[1] to L[3]. Motor 3 has a stator and a rotor equipped with permanent magnets, and coils L[1] to L[3] are provided on the stator. Here, it is assumed that coils L[1] to L[3] are connected in a star configuration. Coils L[1] to L[3] may also be connected in a delta configuration. However, coils L[1], L[2], and L[3] are the coils for the first phase, second phase, and third phase, respectively. The first phase, second phase, and third phase correspond to the U phase, V phase, and W phase, respectively.

[0103] The system SYS includes three phase half-bridge circuits HB[1] to HB[3] and three phase sense resistors R SNS [1]~R SNS[3] is provided. The half-bridge circuits HB[1], HB[2], and HB[3] are each provided between the power supply wiring to which the power supply voltage VPWR is applied and ground. The power supply voltage VPWR is a predetermined positive DC voltage. The half-bridge circuits HB[1], HB[2], and HB[3] each consist of a high-side transistor and a low-side transistor connected in series with each other. Each transistor in the half-bridge circuits HB[1] to HB[3] is configured as an N-channel MOSFET.

[0104] The power supply voltage VPWR is applied to the drain of each high-side transistor. In the half-bridge circuit HB[p], the sources of the high-side transistors and the drains of the low-side transistors are connected in common at node ND[p], where p is an integer between 1 and 3. The source of the low-side transistors in the half-bridge circuit HB[p] is connected to the sense resistor R. SNS It is connected to ground via [p]. Nodes ND[1], ND[2], and ND[3] are connected to one end of coil L[1], one end of coil L[2], and one end of coil L[3], respectively. The other ends of coils L[1] to L[3] are connected to each other at the neutral point NP. The current flowing through coils L[1], L[2], and L[3] is divided by the sense resistor R SNS [1], R SNS [2], R SNS It passes through [3]. As a result, the current sensor 200 in the gate driver 1a can detect the current flowing through coils L[1], L[2] and L[3], and signals SOUT[1]~SOUT[3] indicating the detection result are output from the gate driver 1a to the MCU2 via terminals AOUT[1]~AOUT[3].

[0105] MUC2 can generate drive control signals based on signals SOUT[1] to SOUT[3] and supply them to gate driver 1a. Based on the supplied drive control signals, gate driver 1a controls the on / off state of a total of six transistors in half-bridge circuits HB[1] to HB[3] by driving the gates of those six transistors. As a result, current is supplied to coils L[1] to L[3] through half-bridge circuits HB[1] to HB[3], driving motor 3.

[0106] <<Example 5>> A fifth embodiment will be described. In the fifth embodiment, the modification techniques for each of the above-mentioned items will be explained.

[0107] In the fourth embodiment, a gate driver 1a was given as an example of the semiconductor device 1, but the semiconductor device 1 according to this disclosure may be any semiconductor device comprising a target circuit whose characteristics are to be calibrated and a calibration circuit that performs calibration operations.

[0108] For example, semiconductor device 1 may be a semiconductor device equipped with a DC / DC converter 10b and a calibration circuit CRBb as shown in Figure 17. The DC / DC converter 10b has a DC input voltage V IN to other DC output voltage V OUT It is converted and output. In the DC / DC converter 10b, the output voltage V OUT The predetermined target output voltage V TG It is required that the output be as close as possible to the specified value, and to satisfy this requirement, an adjustment circuit 13b is provided within the DC / DC converter 10b.

[0109] In the DC / DC converter 10b, the output voltage V OUT Feedback control is performed so that the corresponding feedback voltage matches the reference voltage generated in the DC / DC converter 10b. Here, the feedback voltage is determined using a voltage divider circuit including a variable resistor, which is used to control the output voltage V OUTIt is assumed that the value will be multiplied by J. A variable resistor in the voltage divider circuit is provided in the adjustment circuit 13b, and the value of J is changed by changing the resistance value of the variable resistor. The variable resistor in the adjustment circuit 13b is a digital potentiometer, and the resistance value of the variable resistor in the adjustment circuit 13b is set based on a multi-bit digital signal from the calibration circuit CRBb.

[0110] The calibration operation OP1 according to the first embodiment can be used with a semiconductor device including such a DC / DC converter 10b and calibration circuit 13b. In this case, the circuit whose characteristics should be calibrated is the DC / DC converter 10b, and the characteristics of the circuit to be calibrated are the output voltage V OUT Therefore, the target characteristic (the target characteristic of the target circuit) is the target output voltage V TG It is represented as follows.

[0111] Calibration operation OP1 controls the output voltage V OUT and target output voltage V TG Calibration can be achieved to reduce (preferably minimize) the difference between them. If multiple DC / DC converters 10b are provided in the semiconductor device 1, calibration operation OP2 can also be used. In calibration operation OP1 or OP2, the output voltage V OUT The target output voltage is V TG Whether it is higher or lower compared to is determined by the high-precision reference voltage and output voltage V generated using a bandgap reference, etc. OUT It should be judged by comparison with the above.

[0112] Alternatively, for example, the semiconductor device 1 may be a semiconductor device equipped with an oscillator circuit 10c and a calibration circuit CRBc as shown in Figure 18. The oscillator circuit 10c generates and outputs a clock signal CLK. The clock signal CLK has a frequency f CLK This is a square wave signal having the frequency f. In the oscillation circuit 10c, CLK The predetermined target frequency f TG It is required that the output be as close as possible to the specified value, and in order to satisfy this requirement, an adjustment circuit 13c is provided within the oscillation circuit 10c.

[0113] The oscillator circuit 10c is an oscillator comprising an oscillator resistor and an oscillator capacitor, and the frequency f CLK The frequency f depends on the resistance value of the oscillation resistor and the capacitance value of the oscillation capacitor. Here, the oscillation resistor is a variable resistor provided in the adjustment circuit 13c. In this case, the resistance value of the variable resistor in the adjustment circuit 13c is set (changed) based on the multi-bit digital signal from the calibration circuit CRBc, thereby changing the frequency f CLK The frequency f is set (changed) variably. Alternatively, the oscillation capacitance is a variable capacitance provided in the adjustment circuit 13c. In this case, the capacitance value of the variable capacitance of the adjustment circuit 13c is set (changed) variably based on the multi-bit digital signal from the calibration circuit CRBc, thereby changing the frequency f CLK This setting is variable (changed).

[0114] The calibration operation OP1 according to the first embodiment can be used with a semiconductor device including such an oscillator circuit 10c and a calibration circuit 13b. In this case, the circuit whose characteristics should be calibrated is the oscillator circuit 10c, and the characteristics of the circuit to be calibrated are the frequency f CLK Therefore, the target characteristic (the target characteristic of the target circuit) is the target frequency f TG It is represented as follows.

[0115] Calibration operation OP1 determines the frequency f CLK and target frequency f TG Calibration can be achieved to reduce (preferably minimize) the difference between them. If multiple oscillation circuits 10c are provided in the semiconductor device 1, calibration operation OP2 can also be used. In calibration operation OP1 or OP2, the frequency f CLK The target frequency f TG Whether it is higher or lower compared to the frequency f CLK and the reference clock signal CLK REF This can be determined by comparing it with the frequency of the reference clock signal CLK. REF The target frequency f TG A rectangular wave signal having the following characteristics, supplied to the calibration circuit CRBc from outside the calibration circuit CRBc.

[0116] With respect to any signal or voltage, the relationship between their high and low levels can be the reverse of that described above, without undermining the main point stated above.

[0117] The channel types of the FETs (field-effect transistors) shown in each embodiment are illustrative. Without compromising the main points mentioned above, the channel type of any FET can be changed between P-channel and N-channel types.

[0118] As long as no inconvenience arises, any transistor described above may be any type of transistor. For example, any transistor described above as a MOSFET can be replaced with a junction FET, an IGBT (Insulated Gate Bipolar Transistor), or a bipolar transistor, as long as no inconvenience arises. Any transistor has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain and the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector and the other is the emitter, and the control electrode is the gate. In a bipolar transistor that does not belong to the IGBT category, one of the first and second electrodes is the collector and the other is the emitter, and the control electrode is the base.

[0119] The embodiments of this disclosure can be modified in various ways as appropriate within the scope of the technical idea set forth in the claims. The embodiments described above are merely examples of embodiments of this disclosure, and the meaning of the terms in this disclosure or each constituent element is not limited to those described above. The specific numerical values ​​given in the above description are merely examples and can, of course, be changed to various numerical values.

[0120] <<Note>> A note is provided regarding this disclosure in which specific configuration examples are shown in the embodiments described above.

[0121] A semiconductor device relating to one aspect of this disclosure (see Figures 1 to 9) comprises a target circuit (10) and a calibration circuit (CRB1) configured to perform a calibration operation (OP1) on the target circuit, wherein the target circuit has an adjustment circuit (13) configured to change the characteristics of the target circuit according to a digital value (D_VAL) supplied from the calibration circuit, the calibration operation includes an evaluation operation (OP1a) which repeatedly performs a plurality of unit operations on the target circuit, and the calibration circuit changes the characteristics of the target circuit while changing the digital value in each unit operation The system evaluates the characteristics of the target circuit and derives a digital value (D_A[j]) that minimizes the difference between the characteristics of the target circuit and the target characteristics based on the evaluation results as a calibration candidate value. The calibration circuit then calibrates the characteristics of the target circuit using an actual calibration value (D_R) based on the multiple calibration candidate values ​​when the multiple calibration candidate values ​​(D_A[1] to D_A[n]) derived from the multiple unit operations satisfy predetermined conditions. If the multiple calibration candidate values ​​deviate from the predetermined conditions, the system either re-executes the evaluation operation (see Figure 8) or outputs a predetermined error signal (see Figure 9) (first configuration).

[0122] Due to the influence of noise and other factors, appropriate calibration values ​​may not be obtained. Considering this, the semiconductor device according to the first configuration performs a unit operation multiple times, and derives candidate calibration values ​​(calibration candidate values) for each unit operation. If noise or other factors are present, it is expected that abnormal values ​​will be included among the multiple calibration candidate values. Therefore, the success or failure of predetermined conditions is determined based on the multiple calibration candidate values, and when the multiple calibration candidate values ​​satisfy the predetermined conditions, the characteristics of the target circuit are calibrated using the actual calibration values ​​based on the multiple calibration candidate values. This enables proper calibration that is less susceptible to the influence of noise and other factors.

[0123] In relation to the semiconductor device according to the first configuration described above, the calibration circuit may be configured to derive the calibration candidate value by binary search in each unit operation (second configuration).

[0124] In binary research, if noise or other influences occur during the evaluation process of the higher bits, the discrepancy between the required calibration value and the ideal value becomes very large. However, by employing a method that determines the success or failure of predetermined conditions based on multiple calibration candidate values, calibration with values ​​affected by noise or other influences can be avoided.

[0125] The semiconductor device relating to the second configuration described above, wherein the digital value is a digital signal (DAC) consisting of m bits from the first bit to the mth bit. IN The value of (m is an integer greater than or equal to 2), the i-th bit is the higher-order bit of the (i+1)-th bit (i is a natural number less than or equal to (m-1)), each bit has a binary value of 0 or 1, and the calibration circuit may be configured (third configuration) to identify the binary value suitable for reducing the difference bit by bit from the first bit to the m-th bit in each unit operation, thereby deriving the calibration candidate value.

[0126] With respect to the semiconductor device relating to the first configuration described above, the calibration circuit may be configured to determine whether the predetermined conditions are met based on the variation of the plurality of calibration candidate values ​​(fourth configuration).

[0127] This makes it possible to determine, for example, that a predetermined condition is not met when an abnormal value is included among multiple calibration candidate values ​​due to the influence of noise or other factors.

[0128] With respect to the semiconductor device relating to the fourth configuration described above, when the difference between the minimum value and the maximum value among the plurality of calibration candidate values ​​is less than or equal to a specified value, the predetermined condition is met, and the calibration circuit may be configured to set the actual calibration value based on the average of the plurality of calibration candidate values ​​(fifth configuration).

[0129] The present invention relates to a semiconductor device according to any of the above configurations 1 to 5, wherein the target circuit is an amplification circuit, the characteristic of the target circuit is the offset voltage of the amplification circuit, and the calibration circuit may be configured to derive the digital value that minimizes the offset voltage of the amplification circuit in each unit operation as the calibration candidate value (configuration 6).

[0130] A semiconductor device relating to another aspect of the present disclosure (see Figures 11 to 15) comprises a plurality of target circuits (10[1] to 10[k]) and a calibration circuit (CRB2) configured to perform a calibration operation (OP2) on the plurality of target circuits, wherein each target circuit has an adjustment circuit (13) configured to change the characteristics of the target circuit according to a digital value (D_VAL[p]) supplied from the calibration circuit, the calibration operation includes an evaluation operation (OP2a) that performs a unit operation for each target circuit, and the calibration circuit evaluates the characteristics of the target circuit for each target circuit while changing the corresponding digital value in the corresponding unit operation, and evaluates Based on the results, the digital value that minimizes the difference between the characteristics of the target circuit and the target characteristics is derived as a calibration candidate value (D_B[p]). After unit operation for each target circuit, multiple calibration candidate values ​​(D_B[1] to D_B[k]) are derived for the multiple target circuits. The calibration circuit, when the multiple calibration candidate values ​​satisfy predetermined conditions, uses the corresponding calibration candidate value as the actual calibration value (D_R[p]) to calibrate the characteristics of each target circuit. When the multiple calibration candidate values ​​deviate from the predetermined conditions, the evaluation operation is re-executed (see Figure 14) or a predetermined error signal is output (see Figure 15) (the seventh configuration).

[0131] Due to the influence of noise and other factors, proper calibration values ​​may not be obtained. Considering this, in the semiconductor device according to the seventh configuration, unit operations are performed for each of the multiple target circuits, and candidate calibration values ​​(calibration candidate values) are derived for each target circuit. If the influence of noise or other factors is present, it is expected that abnormal values ​​will be included among the multiple calibration candidate values. Therefore, the success or failure of predetermined conditions is determined based on the multiple calibration candidate values, and when the multiple calibration candidate values ​​satisfy the predetermined conditions, each calibration candidate value is used as the actual calibration value to calibrate the characteristics of each target circuit. This enables proper calibration that is less susceptible to the influence of noise and other factors.

[0132] With respect to the semiconductor device relating to the seventh configuration described above, the calibration circuit may be configured to derive the calibration candidate value by binary search in the corresponding unit operation for each target circuit (eighth configuration).

[0133] In binary research, if noise or other influences occur during the evaluation process of the higher bits, the discrepancy between the required calibration value and the ideal value becomes very large. However, by employing a method that determines the success or failure of predetermined conditions based on multiple calibration candidate values, calibration with values ​​affected by noise or other influences can be avoided.

[0134] Regarding the semiconductor device relating to the eighth configuration described above, in each target circuit, the digital value is a digital signal (DAC) consisting of m bits from the first bit to the mth bit. IN The value of (m is an integer greater than or equal to 2), the i-th bit is the higher-order bit of the (i+1)-th bit (i is a natural number less than or equal to (m-1)), each bit has a binary value of 0 or 1, and the calibration circuit may be configured (9th configuration) to identify the binary value suitable for reducing the difference bit by bit from the first bit to the m-th bit in the corresponding unit operation for each target circuit, thereby deriving the calibration candidate value.

[0135] With respect to the semiconductor device relating to the seventh configuration described above, the calibration circuit may be configured to determine whether the predetermined conditions are met based on the variation of the plurality of calibration candidate values ​​(the tenth configuration).

[0136] This makes it possible to determine, for example, that a predetermined condition is not met when an abnormal value is included among multiple calibration candidate values ​​due to the influence of noise or other factors.

[0137] With respect to the semiconductor device relating to the above-described 10th configuration, if the difference between the minimum value and the maximum value among the plurality of calibration candidate values ​​is less than or equal to a specified value, the predetermined condition may be satisfied (11th configuration).

[0138] The present invention relates to a semiconductor device according to any of the above configurations 7 to 11, wherein each target circuit is an amplification circuit, the characteristic of each target circuit is the offset voltage of each amplification circuit, and the calibration circuit may be configured to derive the digital value that minimizes the offset voltage of the amplification circuit in the corresponding unit operation for each target circuit as the calibration candidate value (configuration 12). [Explanation of Symbols]

[0139] SYS System 1 Semiconductor device 2 MCU MM memory circuit 100, 200 Current Sensor 10, 10[1]~10[k] Amplifier Circuit 20, 220, 220[1]~220[k] comparators 30,230 Logic Circuits 40. Reference voltage setting circuit AMP (Operational Amplifier) R SNS , R SNS [1]~R SNS [k] Sense resistance R1~R4 resistance CRB1, CRB2 calibration circuit 11 input stages 12 Output Stages 13 Adjustment circuit 111, 112, 133, 134 transistors 113, 132 constant current source 114, 115 resistors 131 DAC 1a Gate driver 3 motors L[1]~L[3] Coil HB[1]~HB[3] Half-bridge circuit 10b DC / DC converter 10c oscillator circuit 13b, 13c adjustment circuit CRBb, CRBc calibration circuit

Claims

1. The system comprises a target circuit and a calibration circuit configured to perform calibration operations on the target circuit, The target circuit has an adjustment circuit configured to change the characteristics of the target circuit in accordance with the digital value supplied from the calibration circuit. The calibration operation includes an evaluation operation in which a plurality of unit operations are repeatedly performed on the target circuit. The calibration circuit evaluates the characteristics of the target circuit while changing the digital value in each unit operation, and derives the digital value that minimizes the difference between the characteristics of the target circuit and the target characteristics based on the evaluation result as a calibration candidate value. The calibration circuit, when the multiple calibration candidate values ​​derived from the multiple unit operations satisfy predetermined conditions, calibrates the characteristics of the target circuit using the actual calibration values ​​based on the multiple calibration candidate values, and when the multiple calibration candidate values ​​deviate from the predetermined conditions, it re-executes the evaluation operation or outputs a predetermined error signal. Semiconductor equipment.

2. The calibration circuit derives the calibration candidate value by binary search in each unit operation. The semiconductor device according to claim 1.

3. The aforementioned digital value is the value of m bits of the digital signal from the 1st bit to the mth bit (where m is an integer greater than or equal to 2), and the ith bit is the higher-order bit of the (i+1)th bit (where i is a natural number less than or equal to (m-1)). Each bit has a binary value of 0 or 1. The calibration circuit, in each unit operation, identifies a binary value suitable for reducing the difference bit by bit, from the first bit to the m bits, and thereby derives the calibration candidate value. The semiconductor device according to claim 2.

4. The calibration circuit determines whether the predetermined conditions are met based on the variation in the plurality of calibration candidate values. The semiconductor device according to claim 1.

5. When the difference between the minimum value and the maximum value among the plurality of calibration candidate values ​​is less than or equal to a specified value, the predetermined condition is met, and the calibration circuit sets the actual calibration value based on the average of the plurality of calibration candidate values. The semiconductor device according to claim 4.

6. The aforementioned circuit is an amplification circuit, The characteristic of the target circuit is the offset voltage of the amplification circuit, The calibration circuit derives the digital value that minimizes the offset voltage of the amplification circuit in each unit operation as the calibration candidate value. The semiconductor device according to any one of claims 1 to 5.

7. The system comprises multiple target circuits and a calibration circuit configured to perform calibration operations on the multiple target circuits, Each target circuit has an adjustment circuit configured to change the characteristics of the target circuit in accordance with the digital value supplied from the calibration circuit. The calibration operation includes an evaluation operation in which a unit operation is performed for each of the target circuits. The calibration circuit evaluates the characteristics of each target circuit by changing the corresponding digital value in the corresponding unit operation, and derives the digital value that minimizes the difference between the characteristics of the target circuit and the target characteristics based on the evaluation result as a calibration candidate value. After the unit operation for each of the target circuits, multiple calibration candidate values ​​are derived for the multiple target circuits. The calibration circuit, when the plurality of calibration candidate values ​​satisfy predetermined conditions, uses the corresponding calibration candidate value as the actual calibration value to calibrate the characteristics of each target circuit. When the plurality of calibration candidate values ​​deviate from the predetermined conditions, the calibration circuit either re-executes the evaluation operation or outputs a predetermined error signal. Semiconductor equipment.

8. The calibration circuit derives the calibration candidate value by binary search in the corresponding unit operation for each target circuit. The semiconductor device according to claim 7.

9. In each target circuit, the digital value is the value of m bits of digital signals from the 1st bit to the mth bit (where m is an integer greater than or equal to 2), the ith bit is the higher bit of the (i+1)th bit (where i is a natural number less than or equal to (m-1)), Each bit has a binary value of 0 or 1. The calibration circuit, for each target circuit, identifies the binary value suitable for reducing the difference bit by bit from the first bit to the m bits in the corresponding unit operation, and thereby derives the calibration candidate value. The semiconductor device according to claim 8.

10. The calibration circuit determines whether the predetermined conditions are met based on the variation in the plurality of calibration candidate values. The semiconductor device according to claim 7.

11. The predetermined condition is met when the difference between the minimum value and the maximum value among the plurality of calibration candidate values ​​is less than or equal to a specified value. The semiconductor device according to claim 10.

12. Each target circuit is an amplification circuit, The characteristic of each target circuit is the offset voltage of each amplification circuit. The calibration circuit derives the digital value that minimizes the offset voltage of the amplification circuit in the corresponding unit operation for each target circuit as the calibration candidate value. or the semiconductor device according to any one of claims 7 to 11.

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