Semiconductor modules and electronic devices

Abstract

To bond an IC chip and a bridge more densely.SOLUTION: A method for manufacturing a semiconductor module includes sealing a first die having a first die electrode, a second die having a second die electrode, a first connection portion connected to the first die electrode, and a second connection portion connected to the second die electrode with a sealing body, and then mounting a bridge having a first bridge electrode and a second bridge electrode on the structure sealed with the sealing body. The first die and the second die 42 are electrically connected via the bridge.SELECTED DRAWING: Figure 21

Description

Technical Field

[0004] , , , , ,

[0005] , , , ,

[0001] The present invention relates to a semiconductor module and an electronic device.

Background Art

[0002] There is a technology for connecting a plurality of IC (Integrated Circuit) chips. For example, Patent Document 1 describes a semiconductor package in which two IC chips are connected by a bridge (nested component) molded together with an interposer. Patent Document 2 describes a semiconductor package in which two IC chips are electrically connected through a bridge integrally formed with an interposer via an underfill material.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] As a result of the inventor of the present application examining a semiconductor package including a plurality of IC chips connected via a bridge and a semiconductor module using the same, it has been found that there is room for improvement in the semiconductor package and the semiconductor module described above. For example, when two IC chips are electrically connected through a bridge integrated with an interposer, it is difficult to perform high-precision alignment between the respective terminals of the two IC chips and the terminals of the bridge. In this case, the densification of the terminal portion for electrically connecting the IC chip and the bridge is restricted.

[0005] The present invention was made in such circumstances, and one exemplary objective of a certain aspect thereof is to provide a technique that enables higher-density coupling of IC chips and bridges. [Means for solving the problem]

[0006] A method for manufacturing a semiconductor module according to one embodiment includes the steps of: (a) forming a first connection portion on the first surface of a first support, which includes a first columnar connection portion extending out of the plane of the first surface, and a second connection portion on the first surface, which includes a second columnar connection portion extending out of the plane of the first surface; (b) preparing a first semiconductor die having a first IC chip and a first die electrode connected to the first IC chip, and a second semiconductor die having a second IC chip and a second die electrode connected to the second IC chip, and mounting the first semiconductor die and the second semiconductor die on the first support such that the first die electrode is positioned on the first connection portion and the second die electrode is positioned on the second connection portion; and (c) the (b (d) After step (c), a step of sealing the first semiconductor die, the second semiconductor die, the first connection portion, and the second connection portion with a first sealant; (c) After step (c), a step of removing the first support and exposing a portion of the first columnar connection portion and a portion of the second columnar connection portion from the first sealant; (e) A step of preparing a bridge including a first bridge electrode connected to the first connection portion and a second bridge electrode connected to the second connection portion, and after step (d), mounting the bridge on the structure sealed with the first sealant such that the first bridge electrode is positioned on the first columnar connection portion and the second bridge electrode is positioned on the second columnar connection portion.

[0007] Another embodiment of the method for manufacturing a semiconductor module is a step of (a) forming a first insulating layer on the first surface of a first support, and then forming a first opening and a second opening in the first insulating layer; (b) forming a first connection portion including a first columnar connection portion formed in the first opening, and a second connection portion including a second columnar connection portion formed in the second opening; and (c) preparing a first semiconductor die having a first IC chip, a first die electrode connected to the first IC chip, and a second insulating layer sealing the first die electrode, and a second semiconductor die having a second IC chip, a second die electrode connected to the second IC chip, and a third insulating layer sealing the second die electrode, so that the first die electrode is placed on the first connection portion and the second die electrode is placed on the second connection portion. The process includes: (d) mounting the first semiconductor die and the second semiconductor die on the first support; (c) after step (c), sealing the first semiconductor die and the second semiconductor die with a first sealant; (e) after step (d), removing the first support and exposing a portion of the first columnar connection and a portion of the second columnar connection from the first insulating layer; and (f) preparing a bridge including a first bridge electrode connected to the first connection and a second bridge electrode connected to the second connection, and after step (e), mounting the bridge on a structure sealed with the first sealant such that the first bridge electrode is positioned on the first columnar connection and the second bridge electrode is positioned on the second columnar connection. In step (c), the first insulating layer and the second insulating layer are joined to each other, and the first die electrode is sealed by the first insulating layer and the second insulating layer. In step (c) above, the first insulating layer and the third insulating layer are joined to each other, and the second die electrode is sealed by the first insulating layer and the third insulating layer.

[0008] Another embodiment of the semiconductor module includes a first semiconductor die having a first IC chip and a first die electrode connected to the first IC chip, a second semiconductor die having a second IC chip and a second die electrode connected to the second IC chip, a first connection portion electrically connected to the first die electrode, a second connection portion electrically connected to the second die electrode, a bridge having a first bridge electrode connected to the first connection portion and a second bridge electrode connected to the second connection portion, and a first encapsulant that encapsulates the first semiconductor die and the second semiconductor die. The first connection portion includes a first columnar connection portion disposed between the first semiconductor die and the bridge and extending in a direction from one of the first semiconductor die and the bridge toward the other. The first connection portion includes a second columnar connection portion disposed between the first semiconductor die and the bridge and extending in a direction from one of the first semiconductor die and the bridge toward the other. The first bridge electrode and the second bridge electrode are exposed from the first encapsulant. Each of the first columnar connecting portion and the second columnar connecting portion is sealed in the first sealing body.

[0009] Another aspect of the present invention relates to an electronic device. The electronic device comprises a first die having a first electrode, a second die having a second electrode, a first connector electrically connected to the first electrode, a second connector electrically connected to the second electrode, and a bridge electrically connected to the first connector and the second connector. The first connector has a columnar connector extending from the bridge toward the first die.

[0010] Another aspect of the present invention relates to an electronic module. The electronic module comprises the above-mentioned electronic device, a wiring layer in which wiring is provided inside, and a columnar connector for electrically connecting the wiring and the electronic device.

[0011] Another aspect of the present invention relates to a method for manufacturing an electronic device. The method for manufacturing an electronic device includes a forming step of forming a first connection portion and a second connection portion on a support, which include a columnar columnar connection portion protruding from the support; a die bonding step of bonding a first electrode of a first die to the first connection portion and a second electrode of a second die to the second connection portion; a sealing step of sealing the first die, the second die, and the first connection portion with a resin; and a bridge bonding step of bonding a bridge to the lower part of the first connection portion and the lower part of the second connection portion.

[0012] Furthermore, any combination of the above components, and any conversion of the expression of the present invention between methods, apparatus, systems, recording media, computer programs, etc., are also valid embodiments of the present invention. be. [Effects of the Invention]

[0013] According to the above-described embodiment, the IC chip and the bridge can be coupled at a higher density. [Brief explanation of the drawing]

[0014] [Figure 1] This is a schematic diagram of a chip integration system according to one embodiment. [Figure 2] Figure 1 is a perspective view showing an example of the configuration of a chip integrated unit. [Figure 3] Figure 2 is an explanatory diagram showing an example of the configuration of a chip integrated circuit. [Figure 4] Figure 3 is an enlarged cross-sectional view showing an example configuration of a portion of the chip integration module shown. [Figure 5] Figure 3 is a schematic diagram illustrating an example of the configuration of an optical module. [Figure 6] This is an explanatory diagram showing an overview of a method for manufacturing a chip integrated module, which is an example of a study based on one embodiment. [Figure 7] Figure 4 is an explanatory diagram illustrating the general manufacturing process of the chip integrated module shown. [Figure 8] Figure 7 is an enlarged cross-sectional view showing details of the connection part formation process. [Figure 9] It is an enlarged cross-sectional view showing details of the connection part forming process following FIG. 8. [Figure 10] It is an enlarged cross-sectional view showing details of the connection part forming process following FIG. 9. [Figure 11] It is an enlarged cross-sectional view showing details of the connection part forming process following FIG. 10. [Figure 12] It is an enlarged cross-sectional view showing details of the connection part forming process following FIG. 11. [Figure 13] It is an enlarged cross-sectional view showing details of the semiconductor die mounting process shown in FIG. 7. [Figure 14] It is an enlarged cross-sectional view showing details of the semiconductor die mounting process following FIG. 13. [Figure 15] It is an enlarged cross-sectional view showing details of the semiconductor die mounting process following FIG. 14. [Figure 16] It is an enlarged cross-sectional view showing details of the first encapsulation process shown in FIG. 7. [Figure 17] It is an enlarged cross-sectional view showing details of the support removal process shown in FIG. 7. [Figure 18] It is an enlarged cross-sectional view showing details of the connection part exposure process shown in FIG. 7. [Figure 19] It is an enlarged cross-sectional view showing details of the connection part exposure process following FIG. 18. <000…​​​​​​​​​​​​​​​​​​​​​This is an enlarged cross-sectional view showing other variations of the sealant shown in Figure 4. [Figure 28] This is an enlarged cross-sectional view of a chip integration module, which is a modified version of Figure 4. [Figure 29] Figure 28 is an explanatory diagram illustrating the general manufacturing process of the chip integrated module shown. [Figure 30] Figure 29 is an enlarged cross-sectional view showing details of the insulating layer formation process. [Figure 31] This is an enlarged cross-sectional view showing details of the insulating layer formation process following Figure 30. [Figure 32] Figure 29 is an enlarged cross-sectional view showing details of the connection part formation process. [Figure 33] Figure 29 is an enlarged cross-sectional view showing details of the semiconductor die mounting process. [Figure 34] This is an enlarged cross-sectional view showing details of the semiconductor die mounting process, following Figure 33. [Figure 35] This is an enlarged cross-sectional view showing details of the semiconductor die mounting process, following Figure 34. [Figure 36] Figure 29 is an enlarged cross-sectional view showing details of the sealing process. [Figure 37] Figure 29 is an enlarged cross-sectional view showing details of the connection part exposure process. [Figure 38] This is an enlarged cross-sectional view showing the details of the connection part exposure process, following Figure 37. [Figure 39] Figure 29 is an enlarged cross-sectional view showing details of the bridge mounting process. [Figure 40] This is an enlarged cross-sectional view showing details of the bridge mounting process, following Figure 39. [Figure 41] This is an enlarged cross-sectional view showing details of the bridge mounting process, following Figure 40. [Figure 42] Figure 3 is an explanatory diagram showing a modified example of the chip assembly shown. [Figure 43] Figure 3 is an explanatory diagram showing other modifications of the chip assembly shown. [Figure 44] This is a cross-sectional view showing a modified version of the bridge shown in Figure 4. [Figure 45]Figure 44 is a cross-sectional view showing an overview of the wiring layer formation process, which is part of the bridge manufacturing process. [Figure 46] Figure 44 is a cross-sectional view showing an overview of the wiring layer transfer process, which is part of the bridge manufacturing process. [Figure 47] Figure 44 is a cross-sectional view showing an overview of the support removal process, which is part of the bridge manufacturing process. [Figure 48] This is an explanatory diagram showing other variations of the bridge shown in Figure 4. [Figure 49] This figure shows a modified version of Figure 4, illustrating a partial configuration of a chip integration module. [Figure 50] This figure shows the configuration of a chip integrated module according to the first modified example of the chip integrated module shown in Figure 49. [Figure 51] This figure shows the configuration of a chip integrated module according to a second modified example of the chip integrated module shown in Figure 49. [Figure 52] This figure shows the configuration of a chip integrated module according to a third modified example of the chip integrated module shown in Figure 49. [Figure 53] This figure shows the configuration of a chip integrated module according to a fourth modified example of the chip integrated module shown in Figure 49. [Figure 54] This figure shows the configuration of a chip integrated module according to a fifth modified example of the chip integrated module shown in Figure 49. [Figure 55] This diagram illustrates a method for manufacturing a chip integrated module according to another embodiment. [Figure 56] This diagram illustrates a method for manufacturing a chip integrated module according to the same embodiment. [Figure 57] This diagram illustrates a method for manufacturing a chip integrated module according to the same embodiment. [Figure 58] This diagram illustrates a method for manufacturing a chip integrated module according to the same embodiment. [Figure 59] This diagram illustrates a method for manufacturing a chip integrated module according to the same embodiment. [Figure 60] This diagram illustrates a method for manufacturing a chip integrated module according to the same embodiment. [Figure 61] This figure illustrates a sixth modified method for manufacturing a chip integrated module, relative to the method shown in Figures 55 to 60. [Figure 62] This figure illustrates a sixth modified method for manufacturing a chip integrated module, relative to the method shown in Figures 55 to 60. [Figure 63] This figure illustrates a sixth modified method for manufacturing a chip integrated module, relative to the method shown in Figures 55 to 60. [Figure 64] This figure illustrates a sixth modified method for manufacturing a chip integrated module, relative to the method shown in Figures 55 to 60. [Figure 65] This figure illustrates a seventh modified example of a chip integrated module manufacturing method, as shown in Figures 55 to 60. [Figure 66] This figure illustrates a seventh modified example of a chip integrated module manufacturing method, as shown in Figures 55 to 60. [Figure 67] This figure illustrates the eighth modified method for manufacturing a chip integrated module, as shown in Figures 55 to 60. [Figure 68] This figure illustrates the eighth modified method for manufacturing a chip integrated module, as shown in Figures 55 to 60. [Figure 69] This figure illustrates the eighth modified method for manufacturing a chip integrated module, as shown in Figures 55 to 60. [Figure 70] This figure illustrates a method for manufacturing an optical module according to one embodiment. [Figure 71] This figure illustrates a method for manufacturing an optical module according to the same embodiment. [Figure 72] This figure illustrates a method for manufacturing an optical module according to the same embodiment. [Figure 73] This figure illustrates a method for manufacturing an optical module according to the same embodiment. [Figure 74] This figure illustrates a method for manufacturing an optical module according to the same embodiment. [Figure 75] This figure illustrates a method for manufacturing a chip assembly according to another embodiment. [Figure 76] This figure illustrates a method for manufacturing a chip assembly according to the same embodiment. [Figure 77] This figure illustrates a method for manufacturing a chip assembly according to the same embodiment. [Figure 78] This figure illustrates a method for manufacturing a chip assembly according to the same embodiment. [Figure 79] This figure illustrates a method for manufacturing a chip assembly according to the same embodiment. [Figure 80] This figure shows an example configuration of an integrated circuit chip, which is one embodiment of the design. [Modes for carrying out the invention]

[0015] Embodiments of the present invention will be described below with reference to the drawings. In the following description, a structure in which circuit elements such as transistors and wiring are formed on a semiconductor substrate will be called an IC chip. IC chips include superconducting integrated circuits (quantum computers), etc. A structure having a wiring layer stacked on the main surface of an IC chip will be called a semiconductor die. In some cases, a rewiring layer may be formed on the IC chip, in which case the rewiring layer is included in the wiring layer. A structure in which multiple semiconductor dies are sealed together by a encapsulant will be called a chip integration module. A chip integration module will also include a bridge that electrically connects multiple semiconductor dies to each other. A structure in which multiple modules, including chip integration modules, are integrated will be called a chip assembly. A chip assembly may include modules such as optical modules in addition to chip integration modules. A chip assembly may include multiple chip integration modules. Furthermore, a chip assembly may include a wide-area wiring layer that electrically connects multiple modules, and a heat dissipation mechanism or heat dissipation member that has the function of dissipating heat generated in each module to the outside. The part of the chip assembly excluding the heat dissipation components will be called the integration layer. In the following description, a chip integration module will be taken up as an example of a semiconductor module. Furthermore, we will consider an integrated layer as an example of a semiconductor package.

[0016] However, the scope of semiconductor modules and semiconductor packages is not limited to the above definitions. For example, as shown in Figure 1 later, the chip assembly 10 is a single electronic component (module) incorporated into the chip integration system 1. In this case, the chip assembly 10 can be considered as a semiconductor module incorporated into the chip integration system 1. Furthermore, the chip integration module, integration layer, and chip assembly described below may each include an IC chip and be distributed as a packaged semiconductor package. Therefore, each form of the chip integration module, integration layer, and chip assembly can be considered as a semiconductor package.

[0017] <Chip Integration System> Figure 1 is a schematic diagram of a chip integration system according to one embodiment of the present invention. The chip integration system 1 according to this embodiment comprises a plurality of chip assemblies 10. These chip assemblies 10 are connected to each other by optical wiring 110. Optical wiring may be used to connect, for example, different chip assemblies, but if the chip assemblies are large in scale, it may also be used to connect different parts within the chip assemblies. The chip integration system 1 can be used, for example, in an artificial intelligence system that highly integrates various processors and memory. Although Figure 1 shows two chip assemblies 10a and 10b, the chip integration system 1 may comprise three or more chip assemblies 10, or it may consist of only one chip assembly 10.

[0018] The chip assembly 10 is an assembly that contains multiple chip integration modules internally. The size of the chip integration modules is not particularly limited, but examples include sizes ranging from approximately 50 mm square to as large as approximately 300 mm square. Here, a chip integration module is a semiconductor module that contains multiple IC chips. In Figure 1, the areas in the chip assembly 10 where the chip integration modules are arranged are shown by dashed lines. In the example shown in Figure 1, eight chip integration modules are arranged vertically and eight horizontally, and the chip assembly 10 contains a total of 64 chip integration modules. However, the number of chip modules contained in the chip assembly 10 is not limited to this, and may be 63 or less, or 65 or more.

[0019] Furthermore, the chip assembly 10 according to this embodiment includes optical transceiver modules (hereinafter referred to as "optical modules"). The chip assembly 10 according to this embodiment includes, for example, six optical modules. In the example shown in Figure 1, the chip assembly 10a includes optical modules 11a, 12a, 13a, 14a, 15a, and 16a. The chip assembly 10b includes optical modules 11b, 12b, 13b, 14b, 15b, and 16b. Optical modules 11a to 16a and optical modules 11b to 16b shown in Figure 1 correspond to optical modules 11 to 16 shown in Figure 2, which will be described later. These optical modules are connected by optical wiring 110 to optical modules provided in the same chip assembly 10, or to optical modules provided in other chip assembly 10s. Optical fibers are a typical example of optical wiring, but are not limited to this; for example, optical wiring using a planar panel or sheet equipped with an optical waveguide, or optical wiring using free space, can also be used. In the chip integration system 1 according to this embodiment, signals in the chip integration body 10 are transmitted by light, so signals are transmitted at a higher speed than when signals are transmitted by electrical signals alone.

[0020] <Chip integrator> Figure 2 is a perspective view showing an example configuration of the chip assembly shown in Figure 1. The chip assembly 10 according to this embodiment comprises an integration layer (also called a semiconductor package or electronic module) 100, optical modules 11 to 16 arranged on the upper surface of the integration layer 100, a heat dissipation mechanism 20 arranged on the upper surface of the integration layer 100, and external terminals 30 arranged on the lower surface of the integration layer 100.

[0021] The integrated layer 100 has a stacked structure and is a layer containing multiple chip integrated modules (also called semiconductor modules or electronic devices). The detailed configuration of the integrated layer 100 will be described later with reference to Figure 3.

[0022] The heat dissipation mechanism 20 is a mechanism for dissipating heat generated in the chip assembly 10. The heat dissipation mechanism 20 has the function of dissipating heat generated during operation by, for example, the multiple IC chips embedded in the integration layer 100 and the IC chips of each of the optical modules 11 to 16. In other words, the heat dissipation mechanism 20 can dissipate heat generated during operation by, for example, the integrated circuit chips of the integration layer 100 and the integrated circuit chips of the optical modules 11 to 16 (see Figure 2).

[0023] The external terminal 30 is a terminal that is electrically connected to one of the optical modules 11 to 16 or to the chip integration module 40 (see Figure 3, described later). In the example shown in Figure 2, the external terminal 30 is a solder ball and constitutes a part of the electrical signal transmission path. In this embodiment, the external terminal 30 can be used to supply power to the optical module or chip integration module, or to input and output electrical signals to and from the outside. The shape of the external terminal may be spherical as shown in Figure 2, or it may be a pin shape, a pad shape, or various other shapes.

[0024] Figure 3 is an explanatory diagram showing an example of the configuration of the chip assembly shown in Figure 2. Figure 3 shows the cross-sectional structure of the chip assembly, but the hatching has been omitted for clarity. Furthermore, Figure 3 illustrates two of the 64 chip integration modules shown in Figure 1.

[0025] Each of the optical modules 11 to 16 shown in Figure 2 comprises an optical transceiver, a connector, and a heat dissipation member. For example, the optical module 13 shown in Figure 3 comprises an optical transceiver 130, a connector 132, and a heat dissipation member 136. The heat dissipation member 136 comprises a support plate (heat spreader) fixed on the optical transceiver 130 and a plurality of heat dissipation fins fixed on the support plate and protruding away from the optical transceiver 130.

[0026] The optical transceiver 130 is a photoelectric conversion component that has the function of converting an optical signal received via the optical wiring 110 (see Figure 1) into an electrical signal, and the function of converting an electrical signal into an optical signal and transmitting the optical signal to the outside via the optical wiring 110. A connector 132 is connected to the underside of the optical transceiver 130. The connector 132 is also connected to an electrode 140 formed on the surface of the integrated layer 100 via solder 138. The optical transceiver 130 can send and receive electrical signals with the integrated layer 100 via the connector 132. By using a connector, the optical transceiver can be easily attached and detached, and can be quickly replaced, for example, in the event of a failure of the optical transceiver.

[0027] Furthermore, a heat dissipation member 136 is positioned on the upper surface of the optical transceiver 130. The heat dissipation member 136 can dissipate heat from, for example, the optical transceiver 130. The heat dissipation member 136 is equipped with a heat spreader on its upper surface, which has heat dissipation fins that achieve a large surface area in a small volume. The heat dissipation fins can dissipate heat from, for example, the optical transceiver 130.

[0028] The heat dissipation mechanism 20 is supported by a support member 210 located on the surface of the integrated layer 100. The heat dissipation mechanism 20 comprises a support plate fixed to the support member 210 and a plurality of heat dissipation fins fixed on the support plate and protruding away from the chip integration module 40. The heat dissipation mechanism 20 is thermally connected to the chip integration module 40 (in other words, each of the plurality of IC chips) located inside the integrated layer 100 (more specifically, inside the chip layer 104) via the support member 210. The support member 210 is, for example, a thermal interface material (TIM) and is thermally connected to the IC chips located inside the integrated layer 100.

[0029] The integrated layer 100 shown in Figure 3 comprises a wide-area wiring layer 102, a chip layer 104, and a connection layer 106.

[0030] The wide-area wiring layer 102 is a layer having a laminated structure composed of multiple layers. Each of the multiple layers of the wide-area wiring layer 102 comprises a conductor pattern such as wiring and an insulating layer covering the conductor pattern. The insulating layer is made of, for example, an insulating resin. The conductor pattern such as wiring is formed on the underlying insulating layer. Two wirings provided in layers adjacent to each other in the thickness direction are electrically connected by conductor vias. In the example shown in Figure 3, the wide-area wiring layer 102 has four layers, and an external terminal 30 is formed on the wiring provided in the bottom layer (the layer furthest from the chip layer 104). In addition, the wiring provided in the top layer of the wide-area wiring layer 102 (the layer closest to the chip layer 104) is electrically connected to an electrode provided in the chip layer 104.

[0031] The chip layer 104 is a layer comprising an insulating encapsulant 105 and various conductors and functional devices embedded in the encapsulant 105. The encapsulant 105 contains, for example, conductor posts 146 and multiple chip integration modules 40. In the example shown in Figure 3, an electrode 148 is provided on the underside of the conductor post 146, and the conductor post 146 is electrically connected via the electrode 148 to the wiring located in the uppermost layer of the wide-area wiring layer 102.

[0032] In the example shown in Figure 3, the chip integration module 40 is electrically connected to the wiring located in the top layer of the wide-area wiring layer 102 via conductive tall pillars 401 and electrodes 403. Details of the configuration of the chip integration module 40 will be described later with reference to Figure 4.

[0033] The connecting layer 106 is a layer that connects the components arranged on the surface of the integrated layer 100 to the chip layer 104. For example, the connecting layer 106 has a conductive via 142 and an electrode 144 that connect the conductive post 146 of the chip layer 104 to the electrode 140 electrically connected to the optical transceiver 130.

[0034] Furthermore, the connecting layer 106 has metal contact portions 222 that are thermally connected to each of the multiple chip integration modules 40, and the contact portions 222 are connected to coupling portions 220 provided inside the support member 210 of the heat dissipation mechanism 20. In this way, the chip integration modules 40 according to this embodiment are thermally connected to the heat dissipation mechanism 20 via the contact portions 222 and the coupling portions 220.

[0035] <Chip Integrated Module> Figure 4 is an enlarged cross-sectional view showing an example of the configuration of a part of the chip integration module shown in Figure 3. As shown in Figure 4, the chip integration module 40 according to this embodiment comprises a semiconductor die 41, a semiconductor die 42, and a encapsulant 45 that encapsulates the semiconductor die 41 and the semiconductor die 42. The chip integration module 40 also comprises a bridge 43 that electrically connects the semiconductor die 41 and the semiconductor die 42. Furthermore, the chip integration module 40 comprises a connection part 47 that electrically connects the semiconductor die 41 and the bridge 43, and a connection part 48 that electrically connects the semiconductor die 42 and the bridge 43. Each of the connection parts 47 and 48 is encapsulated in the encapsulant 45. The semiconductor die 41 is electrically connected to the outside of the chip integration module 40 (for example, the external terminal 30 shown in Figure 3) via a connection part 49.

[0036] The semiconductor die 41 has an IC chip 411 having a main surface 411t, and insulating layers 412 and 413 laminated on the main surface 411t of the IC chip 411. The semiconductor die 41 has wirings 414 and 415 electrically connected to the IC chip 411. The semiconductor die 41 also has a die electrode 416 connected to the wiring 414, and a die electrode 417 connected to the wiring 415. In the example shown in Figure 4, the semiconductor die 41 has two insulating layers 412 and 413. However, the total number of insulating layers on the semiconductor die 41 is not limited to two, and it may have, for example, three or more insulating layers.

[0037] The IC chip 411 includes, for example, a semiconductor substrate such as silicon, as well as circuit elements such as transistors and diodes. Various integration configurations are possible for the circuit elements within the IC chip 411. For example, the circuit elements may be formed two-dimensionally or three-dimensionally on the main surface 411t of the IC chip, or the semiconductor substrate itself may be stacked in multiple layers, with circuit elements formed on each layer and connected by through-silicon vias (TSVs) that penetrate the semiconductor substrate.

[0038] The semiconductor die 42 has an IC chip 421 having a main surface 421t, and insulating layers 422 and 423 laminated on the main surface 421t of the IC chip 421. The semiconductor die 42 has wiring 425 electrically connected to the IC chip 421. The semiconductor die 42 also has die electrodes 427 connected to the wiring 425. In the example shown in Figure 4, the semiconductor die 42 has two insulating layers 422 and 423. However, the total number of insulating layers in the semiconductor die 42 is not limited to two layers; for example, it may have three or more insulating layers and two or more wiring layers. Furthermore, the structure of the semiconductor die 42 is similar to, for example, the structure of the semiconductor die 41 described above.

[0039] The bridge 43 has a chip 431 having a main surface 431t, and insulating layers 432 and 433 laminated on the main surface 431t of the chip 431. The bridge 43 has wiring 434 formed on the insulating layer 432. The chip 431 is formed from a semiconductor substrate such as a silicon wafer, but in a modified example, it may be formed from an inorganic material such as glass. However, the total number of insulating layers on the bridge 43 is not limited to two layers, and for example, it may have three or more insulating layers and two or more wiring layers. Also, if the chip 431 has a circuit, it may be electrically connected to the wiring 434. The bridge 43 has a bridge electrode 436 connected to a connection part 47, and a bridge electrode 437 connected to a connection part 48. The bridge electrode 436 and the bridge electrode 437 are electrically connected to each other via the wiring 434.

[0040] The bridge 43 in this embodiment is a pillar-suspended bridge. The wiring 434 in this embodiment is electrically connected to the chip 431, and the wiring 434 and chip 431 function together as a bridge. However, as will be described later, the bridge 43 can function as a bridge circuit if it has the function of electrically connecting the semiconductor die 41 and the semiconductor die 42. For this reason, in modified cases, there may be no chip 431, or the chip 431 and the wiring 434 may not be electrically connected. Also, in the example shown in Figure 4, the bridge 43 has two insulating layers 432 and 433. However, the total number of insulating layers that the bridge 43 has is not limited to two, and for example, there may be three or more insulating layers.

[0041] The connection portion 47 includes a columnar connection portion 472. In the example shown in Figure 4, the connection portion 47 has a columnar connection portion 472, a solder layer 473 connecting the columnar connection portion 472 and the die electrode 417, and a solder layer 474 connecting the columnar connection portion 472 and the bridge electrode 436.

[0042] The connection portion 48 includes a columnar connection portion 482. In the example shown in Figure 4, the connection portion 48 has a columnar connection portion 482, a solder layer 483 connecting the columnar connection portion 482 and the die electrode 427, and a solder layer 484 connecting the columnar connection portion 482 and the bridge electrode 437.

[0043] In this embodiment, each of the columnar connecting portion 472 and columnar connecting portion 482 is a columnar conductor of μm size (also called a "micropillar"). The main body portions of each of the columnar connecting portion 472 and columnar connecting portion 482 are made of a metal material mainly composed of copper, for example. At the joint interface between the columnar connecting portion 472 and the solder layer 473, and at the joint interface between the columnar connecting portion 472 and the solder layer 474, an alloy layer is formed of a metal material, such as gold, which has higher oxidation resistance than the main body portion, in other words, has a larger free energy for metal oxide formation, and solder, such as one mainly composed of tin. The alloy layer is formed when the metal film formed at the joint interface between the columnar connecting portion and the solder layer reacts with the solder layer during the joining of the columnar connecting portion 472 to the solder layers 473 and 474. Details of the alloy layer will be described later.

[0044] Similarly, a bonding film made of a metallic material such as gold, which has higher oxidation resistance than the main body, is formed at the bonding interface between the columnar connecting portion 482 and the solder layer 483, and at the bonding interface between the columnar connecting portion 482 and the solder layer 484. However, when the columnar connecting portion 482 is bonded to the solder layers 483 and 484, an alloy layer with the solder layers 483 and 484 is formed near the bonding film, and the original components of the bonding film may be diffused into the solder layer.

[0045] In the example shown in Figure 4, the connection portion 49 has an electrode 492 connected to the tall pillar 401 and a solder layer 493 connecting the electrode 492 and the die electrode 426. In the example shown in Figure 4, the tall pillar 401 connected to the electrode 492 is not included in the chip integration module 40 and is therefore shown by a dotted line. However, as a modified example, the tall pillar 401 can also be considered as part of the chip integration module 40.

[0046] In this embodiment, in the example shown in Figure 4, each of the bridge electrodes 436 and 437 is sealed in a separate seal 44 formed independently of the seal 45. The seal 44 is, for example, an underfill resin. However, as a modification, a seal that seals the chip 431 and the bridge electrodes 436 and 437 together can also be used. Alternatively, as another modification, the portion of the seal 44 may be replaced with the seal 105 shown in Figure 3. As shown in Figure 4, the structure in which the connection portion 47 and the connection portion 48 are sealed in the seal 45 and the bridge 43 is exposed from the seal 45 is a structure obtained by the manufacturing method of the chip integrated module 40 described below. Details of why the structure shown in Figure 4 is obtained will be described later.

[0047] In this embodiment, an example was described in which the bridge 43 is a semiconductor die including a chip 431. However, there are cases where the bridge does not include a chip 431 and is mainly composed of wiring 434, insulating layers 432, 433 in which the wiring is embedded, and bridge electrodes 436, 437. Also, in this embodiment, each of the connection portion 47 and connection portion 48 has one columnar connection portion 472, 482. However, depending on the distance between the semiconductor die 41 and the bridge 43, each of the connection portion 47 and connection portion 48 may have two or more stacked columnar connection portions. The cross-sectional shape and cross-sectional area of ​​the stacked columnar connection portions may differ.

[0048] <Optical Module> Figure 5 is a schematic diagram illustrating an example configuration of the optical module shown in Figure 3. The optical module 13 according to this embodiment mainly comprises an optical system mechanism 131, an optical transceiver 130, and a connector 132. The optical module 13 also has a mechanism for transmitting optical signals to the outside (hereinafter also referred to as the "transmission mechanism 13T") and a mechanism for receiving optical signals from the outside (hereinafter also referred to as the "receiving mechanism 13R"). In Figure 5, the transmission mechanism 13T is shown on the left side of the paper and the receiving mechanism 13R is shown on the right side, but there are various modifications to the positional relationship between the transmission mechanism 13T and the receiving mechanism 13R other than the configuration shown in Figure 5. Furthermore, in the following, the structure of the transmission mechanism 13T will be described, and the part of the structure of the receiving mechanism 13R that is common to the structure of the transmission mechanism 13T may be omitted from the description.

[0049] The optical system mechanism 131 of the transmitting mechanism 13T includes an optical fiber 600, a lens 601, a reflection mechanism (a mirror in Figure 5) 602, and a lens 603. Light incident on the lens 603 from the optical transceiver 130 passes through the lens 603 and is reflected by the reflection mechanism 602. The reflected light passes through the lens 601 and enters the optical fiber 600. As a result, the optical signal is transmitted to the outside via the optical fiber 600.

[0050] The optical system mechanism 131 of the receiving mechanism 13R includes an optical fiber 610, a lens 611, a reflection mechanism (a mirror in Figure 5) 612, and a lens 613. Light emitted from the optical fiber 610 passes through the lens 611 and is reflected by the reflection mechanism 612. The reflected light passes through the lens 613 and enters the optical transceiver 130. As a result, the optical signal received by the optical fiber 610 is converted into an electrical signal, and various processing is carried out. The lenses and reflection mechanisms constituting the optical system mechanism 131 can be added or removed as appropriate based on design requirements. For example, there may be a configuration in which the optical fiber does not pass through the lenses or reflection mechanisms, but is directly coupled to the optical element chip of the optical transceiver, and in some cases to the light-emitting element or photodetector.

[0051] The optical transceiver 130 mainly includes a chip layer 620, a wiring layer 630, two optical element chips 605 and 615 arranged on the wiring layer 630, a light-emitting element 606, and a light-receiving element 616. In this embodiment, the two optical element chips 605 and 615, the light-emitting element 606, and the light-receiving element 616 are electrically connected to the wiring layer 630, and the connection is sealed with an underfill resin 607 or the like. In other words, in this embodiment, the two optical element chips 605 and 615, the light-emitting element 606, and the light-receiving element 616 are fixed by a fixing member (underfill resin 607) made of resin or the like.

[0052] The wiring layer 630 according to this embodiment is configured, for example, as a two-layer structure. Conductor patterns such as wiring and electrodes are formed on each layer of the wiring layer 630. The chip layer 620 includes an optical element driving chip 621 and an optical element driving chip 622. The optical element driving chips 621 and 622 are chips that control the driving of the optical element chip 605 and the optical element chip 615, respectively. The optical element driving chips 621 and 622 may also include functions to convert the electrical signal levels (voltage, current) required for the optical element to properly convert light / electricity with the electrical signal levels entering and leaving the optical transceiver.

[0053] The light-emitting element 606 of the transmission mechanism is provided on the surface of the optical element chip 605 and is an element that emits an optical signal in response to an electrical signal transmitted from the optical element chip 605. The optical signal emitted by the light-emitting element 606 is incident on the lens 603 of the optical system mechanism 131.

[0054] The optical element chip 605 is connected to an electrode 631 formed in the upper layer of the wiring layer 630 via an electrode terminal 608 and a solder layer 609, and the optical element driver chip 621 is connected to an electrode 633 formed in the lower layer of the wiring layer 630 via an electrode terminal 623 and a solder layer 634. Thus, the optical element chip 605 and the optical element driver chip 621 are electrically connected via the wiring layer 630. This structure enables multi-parallel and short-distance connections between the optical element chip and the optical element driver chip through approximately vertical electrical connections within the wiring layer 630. This enables broadband signal transmission between a two-dimensional array of optical elements and the optical element driver chip. Note that the solder layer 634 is not necessarily required depending on the manufacturing method of the optical transceiver. Furthermore, by arranging the electrode terminal 608, conductor via 632, and electrode terminal 623 in an approximately straight line, the length of the electrical connection path between the optical element chip and the optical element driver chip can be minimized, resulting in an excellent electrical connection with low parasitic impedance.

[0055] A metal layer 629 made of metal is formed on the lower surface of the optical element drive chip 621. The metal layer 629 is thermally connected to a conductive via 641 provided on the connector 132 via a coupling member 640. As a result, the heat generated by the optical element drive chip 621 when it is operating is dissipated through the coupling member 640 in the direction of the arrow schematically shown in Figure 5 (from the metal layer 629 toward the connector 132). Although the presence of the metal layer 629 is desirable for heat dissipation, the effect can still be obtained even if it is not present.

[0056] The conductive via 641 of the connector 132 is connected to the electrode 140 formed on the surface of the connecting layer 106 via the solder layer 642. Furthermore, as shown in Figure 3, the electrode 140 is connected to the electrode 148, which is connected to the conductive post 146 formed on the chip layer 104, via the conductive via 142. Therefore, the heat dissipated by the connector 132 is dissipated through the conductive post 146.

[0057] An electrode terminal 624 is formed on the upper surface of the optical element driving chip 621. This electrode terminal 624 is connected to an electrode 626 formed on the underside of the wiring layer 630 via a solder layer or a conductor connection part 625. Wiring 635 is also formed on the wiring layer 630. Wiring 635 is connected to electrode 626, which is electrically connected to the optical element driving chip 621, via a conductor via 636. Wiring 635 is also connected to electrode 627, which is coupled to a conductor post 628 formed on the chip layer 620, via a conductor via 637.

[0058] The conductor post 628 is electrically connected to the conductor via 644 of the connector 132 via the coupling member 643. In the example shown in Figure 5, the coupling member 643 transmits electrical signals to each other, for example, between the optical transceiver 130 and the connector 132. However, in a modified configuration, the transmission direction of electrical signals between the optical transceiver 130 and the connector 132 may be unidirectional. That is, in the case of the transmitting mechanism 13T, electrical signals are transmitted from the connector 132 towards the optical transceiver 130, and in the case of the receiving mechanism 13R, electrical signals are transmitted from the optical transceiver 130 towards the connector 132.

[0059] <Manufacturing method for chip-integrated modules> Next, a method for manufacturing the chip integrated module 40 shown in Figures 3 and 4 will be described. Before describing the method for manufacturing the chip integrated module according to this embodiment, an overview of the manufacturing method considered by the present inventors will be briefly explained. Figure 6 is an explanatory diagram showing an overview of a method for manufacturing the chip integrated module, which is an example considered for this embodiment.

[0060] In the manufacturing method of the chip integrated module shown in Figure 6, first, as shown in the upper part of Figure 6, a plurality of semiconductor dies 51 and a bridge structure 52 are prepared. The bridge structure 52 is a structure in which a plurality of bridges 520 and a plurality of connection parts 521 are each sealed by a sealant 523. In the example shown in Figure 6, a plurality of tall pillars 401 are sealed in the sealant 523 together with a plurality of bridges 520.

[0061] Next, as shown in the middle section of Figure 6, multiple semiconductor dies 51 are mounted on the bridge structure 52. At this time, multiple die electrodes 511 of the semiconductor dies 51 and multiple connection parts 521 of the bridge structure 52 are joined together.

[0062] Next, as shown in the lower part of Figure 6, the multiple semiconductor dies 51 and the bridge structure 52 are integrated by sealing the multiple semiconductor dies 51 with a encapsulant 512 to obtain a chip integrated module 50.

[0063] In the example shown in Figure 6, by pre-integrating multiple bridge structures 52, the process of electrically connecting multiple semiconductor dies 51 and multiple bridges 520 can be made more efficient.

[0064] However, it was found that the manufacturing method shown in Figure 6 has the following concerns. Specifically, it was found that it is difficult to improve the positional accuracy of each of the multiple connection parts 521 due to the contraction or expansion of the sealing body 523 that constitutes the bridge structure 52. As a countermeasure to this problem, one possible method is to increase the area of ​​the bonding interface of each of the multiple connection parts 521 to increase the margin that can be tolerated for positional misalignment. However, in this case, the arrangement pitch of adjacent connection parts 521 also needs to be increased, which hinders the densification of the connection parts 521. In other words, the densification of the terminal portion that electrically connects the semiconductor die 51 and the bridge 520 is restricted.

[0065] As described above, the difficulty in improving the positional accuracy of each of the multiple connection points 521 is thought to be due to the large volume of the sealant 523. One possible measure is to reduce the coefficient of thermal expansion of the sealant 523 by mixing inorganic filler particles, as described later, into the sealant 523, but this measure also has its limitations.

[0066] Based on the above findings, the inventors of this invention have discovered a method for manufacturing a chip integrated module according to this embodiment. The details of the manufacturing method will be described later, but the method for manufacturing a chip integrated module according to this embodiment involves preparing a structure in which multiple semiconductor dies and multiple connection parts are integrated by a encapsulant, and mounting multiple bridges on the general structure. The volume of the encapsulant in the structure in which multiple semiconductor dies and multiple connection parts are integrated can be made smaller than the volume of the encapsulant 523 in the bridge structure 52 shown in Figure 6. In particular, by reducing the gap between adjacent IC chips, the effects of thermal contraction and thermal expansion can be reduced. As a result, the method for manufacturing a chip integrated module according to this embodiment can improve the positional accuracy of each of the multiple connection parts, so that the density of the terminal portion that electrically connects the semiconductor dies and bridges can be increased.

[0067] The details of the manufacturing method of the chip integrated module according to this embodiment will be described below. Figure 7 is an explanatory diagram showing an overview of the manufacturing process of the chip integrated module shown in Figure 4. As shown in Figure 7, the manufacturing method of the chip integrated module according to this embodiment includes a connection part formation step, a semiconductor die mounting step, a first encapsulation step, a support removal step, a connection part exposure step, a bridge mounting step, and a second encapsulation step.

[0068] The connection part formation process shown in Figure 7 includes the steps shown in Figures 8 to 12. Each of Figures 8 to 12 is an enlarged cross-sectional view showing the details of the connection part formation process shown in Figure 7. In the connection part formation process, as shown in Figure 11, a connection part 47 including a columnar connection part 472 extending out of the plane of the upper surface 70t is formed on the upper surface 70t of the support 70, and a connection part 48 including a columnar connection part 482 extending out of the plane of the upper surface 70t is formed.

[0069] In detail, first, a support 70 having an upper surface 70t is prepared as shown in Figure 8. A release layer 71 and a seed layer 72 are pre-formed on the upper surface 70t of the support 70. The material of the support 70 is not particularly limited as long as it is a plate with sufficient rigidity to not impair workability in each step up to the support removal step shown in Figure 7. For example, it can be a semiconductor substrate such as a silicon wafer, a plate made of an inorganic material such as glass or sapphire substrate, or a resin plate. However, considering the expansion due to heating during connection, it is desirable that the coefficient of linear expansion of the support be close to that of the semiconductor die.

[0070] The release layer 71 is a functional layer that enables the release of the support 70 in the support removal process shown in Figure 7. Various materials are selected depending on the method used, such as a method of release using an energy beam such as a laser or a mechanical release method. The seed layer 72 is a seed film that serves as a base for forming conductive members such as connection parts 47, 48, and 49 by a plating method. The seed layer 72 can be formed, for example, by depositing copper on the release layer 71 by a sputtering method.

[0071] Next, as shown in Figure 9, a resist mask 73 is formed on the upper surface 70t of the support 70, more specifically, on the seed layer 72. Multiple openings 73H are formed in the resist mask 73, for example, using photolithography technology.

[0072] Next, as shown in Figure 10, the connecting parts 47, 48, and 49 are formed by depositing a metal film within the opening 73H of the resist mask 73 by a plating method or the like. Since a seed layer 72 is already formed on the upper surface 70t of the support 70, the columnar connecting part 472, which is part of the connecting part 47, the columnar connecting part 482, which is part of the connecting part 48, and the electrode 492, which is part of the connecting part 49, can be formed by a plating method, for example. In the example shown in Figure 10, the columnar connecting part 472 comprises a main body part 472A and a metal film 472B. The columnar connecting part 482 comprises a main body part 482A and a metal film 482B. The electrode 492 comprises a main body part 492A and a metal film 492B. Each of the main body parts 472A, 482A, and 492A is made of, for example, copper, and each of the metal films 472B, 482B, and 492B is made of, for example, gold, a metal material with higher oxidation resistance than copper. Each of the metal films 472B, 482B, and 492B prevents oxidation of the bonding surfaces of the copper main body parts 472A, 482A, and 492A, respectively, and has the function of enabling fluxless solder bonding in the semiconductor die mounting process described later.

[0073] Next, as shown in Figure 11, the resist mask 73 (see Figure 10) is removed. Removing the resist mask 73 exposes the sides of each of the connection portions 47, 48, and 49 and a portion of the top surface of the seed layer 72. In the state shown in Figure 11, the process can proceed to the semiconductor die mounting process shown in Figure 7, but it is preferable to include a step of forming an oxide film 72A on the exposed sides of each of the connection portions 47, 48, and 49 and the seed layer 72, as shown in Figure 12. By forming the oxide film 72A before the semiconductor die mounting process, it is possible to prevent solder from wetting and spreading to the sides of the connection portions during the semiconductor die mounting process, which would destabilize the joint shape. If the process includes a step of forming an oxide film 72A on the exposed sides of each of the connection portions 47, 48, and 49 and the seed layer 72, then, as shown in Figure 4, each of the sides of the connection portions 47, 48, and 49 is covered with the oxide film 72A. If the oxide film 72A is not formed in this step, then, for example, as shown in Figure 24 later, the oxide film 72A shown in Figure 4 may not be formed.

[0074] Methods for forming the oxide film 72A include the following: For example, with the resist mask 73 shown in Figure 10 removed, the material is exposed to an oxygen-containing atmosphere until the oxide film 72A shown in Figure 12 is formed. Alternatively, a method for forming the oxide film 72A in a shorter time is to heat the sides of the connection parts 47, 48, and 49 and the exposed surface of the seed layer 72 in an oxygen-containing atmosphere. Note that in Figure 12, the oxide film 72A is shown as thick for clarity, but it is sufficient for the oxide film 72A to be formed thinly on the sides of the connection parts 47, 48, and 49 and the exposed surface of the seed layer 72.

[0075] The semiconductor die mounting process shown in Figure 7 includes the steps shown in Figures 13 to 15. Each of Figures 13 to 15 is an enlarged cross-sectional view showing the details of the semiconductor die mounting process shown in Figure 7. In the semiconductor die mounting process, as shown in Figure 15, a semiconductor die 41 having an IC chip 411 and a die electrode 417 connected to the IC chip 411, and a semiconductor die 42 having an IC chip 421 and a die electrode 427 connected to the IC chip 421 are prepared. In the semiconductor die mounting process, the semiconductor die 41 and the semiconductor die 42 are mounted on the support 70 such that the die electrode 417 is positioned on the connection portion 47 and the die electrode 427 is positioned on the connection portion 48.

[0076] For details, first, prepare semiconductor dies 41 and 42 as shown in Figure 13. The detailed structures of semiconductor dies 41 and 42 have already been explained using Figure 4, so a redundant explanation will be omitted. Next, as shown in Figure 13, align semiconductor dies 41 and 42 with the support 70 so that die electrodes 417 are placed on connection portion 47 and die electrodes 427 are placed on connection portion 48. A solder layer 473 is formed on die electrode 417 of semiconductor die 41. A solder layer 493 is formed on die electrode 416 of semiconductor die 41. A solder layer 483 is formed on die electrode 427 of semiconductor die 42.

[0077] Next, as shown in Figure 14, the die electrode 417 of the semiconductor die 41 is pressed against the connection portion 47 via the solder layer 473. At this time, the die electrode 416 of the semiconductor die 41 is pressed against the connection portion 49 via the solder layer 493. Similarly, the die electrode 427 of the semiconductor die 42 is pressed against the connection portion 48 via the solder layer 483. In this process, the solder layer 473 and the columnar connection portion 472 of the connection portion 47 are temporarily joined by solid-phase diffusion bonding. Similarly, the solder layer 493 and the electrode 492 of the connection portion 49 are temporarily joined by solid-phase diffusion bonding. Similarly, the solder layer 483 and the columnar connection portion 482 of the connection portion 48 are temporarily joined by solid-phase diffusion bonding.

[0078] Next, the bonding interfaces between the solder layer 473 and the metal film 472B of the columnar connector 472, the bonding interface between the solder layer 493 and the metal film 492B of the electrode 492, and the bonding interface between the solder layer 483 and the metal film 482B of the columnar connector 482, as shown in Figure 14, are heated to the melting temperature of the solder and held there. This allows a liquid phase to be generated at each bonding interface. As shown in Figure 15, alloy layers 472D, 482D, and 492D are formed at each bonding interface. If the temperature at which the liquid phase is generated is maintained, the elements in the liquid phase diffuse towards the alloy layer, raising the melting point of the liquid phase. As a result, the liquid phase solidifies. This type of bonding method is called liquid-phase diffusion bonding. When combining temporary bonding by solid-phase diffusion bonding and bonding by liquid-phase diffusion bonding, as in this embodiment, a strong and thermally stable bonding state can be achieved in the solder bonding process without using flux. In the case of reflow bonding using flux, there is a high possibility that flux residue will remain around the joint in the case of fine joints like those in this embodiment. On the other hand, in this embodiment, no flux residue remains, so the cleaning process can be omitted. Furthermore, the process of cleaning and removing flux residue becomes difficult as the connection area becomes finer and denser. In this embodiment, since there is no need to clean the flux residue, finer and denser connection areas can be achieved. Depending on the size and arrangement of the joint area, other bonding process options may include conventional soldering (brazing), soldering using flux, and solid-phase diffusion bonding between metals.

[0079] When performing solder joints, it is preferable to suppress the wetting and spreading of the solder components of each solder layer to the sides of the columnar joint. If the solder components wetting and spreading occur on the sides of the columnar joint or on the upper surface of the seed layer 72, the shape of the joint will not be stable, or the solder is likely to adversely affect the seed layer or the release layer. In this embodiment, as described above, an oxide film 72A is formed on the sides of the columnar joint and the exposed surface of the seed layer 72. In this case, the wetting and spreading of the solder components can be suppressed, so that the die electrode and the joint can be joined with a small amount of solder.

[0080] In the first sealing step shown in Figure 7, after the semiconductor die mounting step, the semiconductor die 41, semiconductor die 42, connection part 47, and connection part 48 are sealed with a sealing body 45, as shown in Figure 16. Figure 16 is an enlarged cross-sectional view showing details of the first sealing step shown in Figure 7. In this step, the semiconductor die 41, semiconductor die 42, connection part 47, and connection part 48 are integrated by the sealing body 45. In the example shown in Figure 16, the connection part 49 is also sealed with the sealing body 45. The sealing body 45 can be exemplified by a resin material including, for example, a thermosetting resin. As a modification of the sealing body 45, as will be described later, the resin may contain a large number of inorganic filler particles.

[0081] In the chip integration module 40 shown in Figure 4, the separation distance between semiconductor die 41 and semiconductor die 42 is narrow. For example, in the example shown in Figure 16, the separation distance G1 between semiconductor die 41 and semiconductor die 42 is shorter than the shortest distance G2 from the upper surface 70t of the support 70 to the portion of semiconductor die 41 excluding the die electrodes 416 and 417. Furthermore, the IC chip, which makes up the majority of semiconductor die 41 and semiconductor die 42, is made of a semiconductor material with a very low coefficient of thermal expansion compared to the encapsulant 45. Therefore, even if the encapsulant 45 undergoes thermal expansion or contraction, the positions of the die electrodes 416, 417, and 427 are less affected. In addition, each of the connection parts 47, 48, and 49 is already fixed to the semiconductor die 41 or semiconductor die 42 before the first encapsulation process. Therefore, each of the connection parts 47, 48, and 49 can maintain high positional accuracy even when encapsulated by the encapsulant 45. Therefore, the problem of difficulty in improving the positional accuracy of each of the multiple connection points 521 of the bridge structure 52, as explained using Figure 6, is less likely to occur in this embodiment.

[0082] In the support removal process shown in Figure 7, after the first sealing process, the support 70 (see Figure 16) is removed as shown in Figure 17. Figure 17 is an enlarged cross-sectional view showing details of the support removal process shown in Figure 7. In this process, by applying energy to the release layer 71 with a laser or the like, the release layer 71 is decomposed (ablated), significantly reducing the adhesion of the release layer 71 to the support, and thus the support 70 can be easily removed. In the support removal process, it is also possible to remove the release layer by mechanical stress.

[0083] In the connection exposure step shown in Figure 7, after the support removal step, a portion (bottom surface) of the columnar connection portion 472 and a portion (bottom surface) of the columnar connection portion 482 are exposed from the sealant 45, as shown in Figure 18. Figure 18 is an enlarged cross-sectional view showing details of the connection exposure step shown in Figure 7. In this step, the release layer 71 and seed layer 72 shown in Figure 17 are removed, for example, by etching. In this step, the portion of the oxide film 72A shown in Figure 17 that is formed on the upper surface of the seed layer 72 is removed. In the example shown in Figure 18, a portion (bottom surface) of the electrode 492 is also exposed from the sealant 45 in this step.

[0084] In this process, as shown in Figure 19, it is preferable to expose the connection portion from the sealant 45 and then form metal films 472C, 482C, and 492C on the exposed surfaces of each connection portion. Figure 19 is an enlarged cross-sectional view showing details of the connection portion exposure process following Figure 18. As shown in Figure 19, in this process, a metal film 472C is formed on the exposed surface of the columnar connection portion 472 from the sealant 45. Similarly, a metal film 482C is formed on the exposed surface of the columnar connection portion 482 from the sealant 45. A metal film 492C is formed on the exposed surface of the electrode 492 from the sealant 45. Each of the metal films 472C, 482C, and 492C has the function of preventing oxidation of the bonding surfaces of the copper main body portions 472A, 482A, and 492A, and the function of enabling bonding in a low-temperature process by undergoing a eutectic reaction with tin-based solder in the semiconductor die mounting process described later. For example, each of the metal films 472C, 482C, and 492C, like the metal films 472B, 482B, and 492B, is made of a metal material (such as gold) that has higher oxidation resistance than the material of the main body parts 472A, 482A, and 492A. Gold can be used as an example of a metal material that has the above functions. By providing the metal films 472C, 482C, and 492C, the solder joint described above can be performed in the bridge mounting process shown in Figure 7.

[0085] The bridge mounting process shown in Figure 7 includes the steps shown in Figures 20 to 22. Each of Figures 20 to 22 is an enlarged cross-sectional view showing the details of the bridge mounting process shown in Figure 7. In the bridge mounting process, as shown in Figure 22, a bridge 43 is prepared, including a bridge electrode 436 connected to a connection portion 47 and a bridge electrode 437 connected to a connection portion 48. In the bridge mounting process, after the connection portion exposure step, the bridge 43 is mounted on a structure sealed with a sealant 45 such that the bridge electrode 436 is positioned on the columnar connection portion 472 and the bridge electrode 437 is positioned on the columnar connection portion 482.

[0086] For details, first, prepare the bridge 43 as shown in Figure 20. The detailed structure of the bridge 43 has already been explained using Figure 4, so a redundant explanation will be omitted. Next, as shown in Figure 20, align the bridge 43 with the structure sealed by the sealant 45 so that the bridge electrode 436 is placed on the columnar connection portion 472 and the bridge electrode 437 is placed on the columnar connection portion 482. A solder layer 474 is formed on the bridge electrode 436. A solder layer 484 is formed on the bridge electrode 437.

[0087] Next, as shown in Figure 21, the bridge electrode 436 of the bridge 43 is pressed against the columnar connection portion 472 of the connection portion 47 via the solder layer 474. At this time, the bridge electrode 437 of the bridge 43 is pressed against the columnar connection portion 482 of the connection portion 48 via the solder layer 484. In this step, the solder layer 474 and the columnar connection portion 472 of the connection portion 47 (more specifically, the metal film 472C of the columnar connection portion 472) are temporarily joined by solid-phase diffusion bonding. Similarly, the solder layer 484 and the columnar connection portion 482 of the connection portion 48 (more specifically, the metal film 482C of the columnar connection portion 482) are temporarily joined by solid-phase diffusion bonding.

[0088] Next, the bonding interface between the solder layer 474 and the metal film 472C of the columnar connection portion 472, and the bonding interface between the solder layer 484 and the metal film 482C of the columnar connection portion 482, as shown in Figure 21, are joined by liquid-phase diffusion bonding. The method of liquid-phase diffusion bonding is as described above, so a redundant explanation will be omitted. By liquid-phase diffusion bonding, the metal films 472C and 482C shown in Figure 21 become alloy layers 472E and 482E, respectively, formed by a eutectic reaction between tin, the main component of the solder layer, and the material of the metal film (e.g., gold), as shown in Figure 22. In addition, if it is possible to clean the flux residue, including in the semiconductor die mounting process described above, solder reflow processing using flux may be performed instead of the combination of solid-phase diffusion bonding and liquid-phase diffusion bonding described above.

[0089] However, as in this embodiment, if the solder layers 473, 483 that join the columnar connection portions 472, 782 and the die electrodes 417, 427 in the bridge mounting process are already sealed with a sealant 45, it is particularly preferable to apply liquid-phase diffusion bonding from the viewpoint of preventing the melting of the sealed solder layers 473, 483. With liquid-phase diffusion bonding, the interface between the solder layer 474 and the columnar connection portion 472, and the interface between the solder layer 484 and the columnar connection portion 482 can be joined at a temperature lower than the melting point of the solder layers 473, 483.

[0090] In the second sealing step shown in Figure 7, after the bridge mounting step, the bridge electrodes 436 and 437 are sealed with a sealant 44, as shown in Figure 23. Figure 23 is an enlarged cross-sectional view showing details of the second sealing step shown in Figure 7. In the example shown in Figure 23, the sealant 44 is an underfill resin embedded between the bridge 43 and the sealant 45. By sealing the bridge electrodes 436 and 437 with the sealant 44, a portion of the columnar connection parts 472 and 482 exposed from the sealant 45 can be protected.

[0091] However, the embodiment shown in Figure 23 can be modified in various ways. For example, the second sealing step shown in Figure 7 may be omitted, and the semiconductor module in the state shown in Figure 22 may be shipped as a product. Alternatively, as shown as a modification in Figure 24, the bridge electrodes 436 and 437 may be sealed together with the conductor tall pillar 401 using the sealing body 105. This sealing step is generally called mold underfill (MUF). In this modification, a step of forming the tall pillar 401 is required before the second sealing step. For example, it is preferable to perform the tall pillar formation step after the connection part exposure step and before the bridge mounting step. The method for forming the tall pillar 401 can be the same as the connection part formation step described using Figures 8 to 12. That is, a resist mask is formed on the lower surface 45b of the sealing body 45 shown in Figure 24. An opening is formed in the resist mask at a position that overlaps with a part of the connection part 49. The tall pillar 401 is formed by depositing a metal film in this opening of the mask by a plating method or the like. In this case, the tall pillar 401 is formed directly on the electrode 492.

[0092] In the modified example shown in Figure 24, the entire chip layer 104, the entire integration layer 100, or the entire chip assembly 10 shown in Figure 3 can also be considered as a semiconductor module.

[0093] As shown in Figure 7, in a manufacturing method in which multiple semiconductor dies are integrated by a first encapsulation step and then a bridge mounting step is performed, each of the multiple die electrodes and multiple connection parts can be positioned with high positional accuracy, so that the IC chip and bridge can be coupled at a higher density. Furthermore, as explained using Figure 4, the structure in which each of the connection part 47, connection part 48, semiconductor die 41, and semiconductor die 42 is encapsulated by a single encapsulant 45 is a structure obtained by manufacturing using the manufacturing method described with reference to Figures 7 to 24.

[0094] <Modified example of a sealing body> Next, modified examples relating to the sealants 45 and 44 shown in Figure 4 will be described. Figures 25 to 27 are enlarged cross-sectional views showing modified examples of the sealants shown in Figure 4.

[0095] The chip integration module 40A shown in Figure 25 differs from the chip integration module 40 shown in Figure 4 in its sealants 45A and 44A. The sealant 45A contains multiple filler particles 451, and the sealant 44A contains multiple filler particles 441. The average particle size of the multiple filler particles 451 is larger than the average particle size of the multiple filler particles 441. As shown in this modified example, by including multiple filler particles 451 with a large average particle size in the sealant 45A, the coefficient of linear expansion of the sealant 45A as a whole can be reduced. As a result, the positional accuracy of the connection portion 47 and the connection portion 48 can be further improved in the bridge mounting process described using Figures 7 and 20 to 22. The multiple filler particles 451 are pre-mixed into the sealing resin used in the first sealing process shown in Figure 7. Similarly, the multiple filler particles 441 are pre-mixed into the sealing resin used in the second sealing process shown in Figure 7.

[0096] The chip integration module 40B shown in Figure 26 differs from the chip integration module 40 shown in Figure 4 in its encapsulants 45B and 44B. Encapsulation 45B contains multiple filler particles 452, and encapsulation 44B contains multiple filler particles 442. The filling rate of multiple filler particles 452 in encapsulation 45B is greater than the filling rate of multiple filler particles 442 in encapsulation 44B. The "filling rate of filler particles 452" is defined as the total volume of multiple filler particles 452 included in the total volume of encapsulation 45B, which includes the resin 453 and multiple filler particles 452. The "filling rate of filler particles 442" is defined as the total volume of multiple filler particles 442 included in the total volume of encapsulation 44B, which includes the insulating resin 443 and multiple filler particles 442.

[0097] However, when calculating the filling rate, for example, cross-sections of two or more randomly selected areas of the sealant 45A can be imaged, and the ratio of the cross-sectional area of ​​the filler particles 452 to the cross-sectional area of ​​the sealant 45A can be measured in each imaged area, and the average value for each area can be considered as the "filling rate of filler particles 452". The same applies to the "filling rate of filler particles 442". As shown in this modified example, by increasing the filling rate of multiple filler particles 452 in the sealant 45B, the coefficient of linear expansion of the sealant 45B as a whole can be reduced. As a result, the positional accuracy of the connection part 47 and the connection part 48 can be further improved in the bridge mounting process described using Figures 7 and 20 to 22. The multiple filler particles 452 are pre-mixed in the sealing resin used in the first sealing process shown in Figure 7. Similarly, the multiple filler particles 442 are pre-mixed in the sealing resin used in the second sealing process shown in Figure 7.

[0098] The chip integration module 40C shown in Figure 27 differs from the chip integration module 40 shown in Figure 4 in its encapsulant 45B. The encapsulant 45B contains multiple filler particles 452, while the encapsulant 44 is an insulating resin 443 that does not contain filler particles. As shown in this modified example, regardless of the presence or absence of filler particles in the encapsulant 44, if filler particles are included in the encapsulant 45B, the coefficient of linear expansion of the encapsulant 45B as a whole can be reduced. As a result, the positional accuracy of the connection portion 47 and the connection portion 48 can be further improved in the bridge mounting process described using Figures 7 and 20 to 22.

[0099] <Examples of manufacturing methods> Next, a modified example of the manufacturing method for the chip integrated module 40 described using Figures 7 to 23 will be explained. Figure 28 is an enlarged cross-sectional view of the chip integrated module, which is another modified example of Figure 4. The chip integrated module 40D shown in Figure 28 differs from the chip integrated module 40 shown in Figure 4 in that the connection portions 47 and 48 are sealed in an insulating layer 81, and the die electrodes 416 and 417 of the semiconductor die 41 and the die electrode 427 of the semiconductor die 42 are each sealed in an insulating layer 82 that is in close contact with the insulating layer 81. Furthermore, the chip integrated module 40D differs from the chip integrated module 40 shown in Figure 4 in that the bridge electrodes 436 and 437 of the bridge 43 are each sealed in an insulating layer 84 that is in close contact with the insulating layer 81.

[0100] The manufacturing method for the chip integrated module 40D shown in Figure 28 will be described below. In the following description, the differences from the manufacturing method for the chip integrated module 40 described using Figures 7 to 23 will be explained, and common steps may be omitted from the explanation. Figure 29 is an explanatory diagram showing an overview of the manufacturing process for the chip integrated module shown in Figure 28. As shown in Figure 29, the manufacturing method for the chip integrated module of this modified example includes an insulating layer formation step, a connection part formation step, a semiconductor die mounting step, a sealing step, a support removal step, a connection part exposure step, and a bridge mounting step.

[0101] The insulating layer formation process shown in Figure 29 includes the steps shown in Figures 30 and 31. Figures 30 and 31 are enlarged cross-sectional views showing details of the insulating layer formation process shown in Figure 29. In the insulating layer formation process, as shown in Figure 30, an insulating layer 81 is formed on the upper surface 70t of the support 70, and then, as shown in Figure 31, openings 81H1 and 81H2 are formed in the insulating layer 81. In the example shown in Figure 31, an opening 81H3 for forming the connection portion 49 shown in Figure 28 is also formed. The insulating layer 81 is joined to the insulating layer 82 shown in Figure 28 in the semiconductor die mounting process described later. For this reason, it is preferable to use an insulating material with high heat resistance in addition to electrical insulating properties for the insulating material used in the insulating layer 82. Examples of such materials include organic insulating materials such as polyimide and PBO (polybenzoxazole). The support 70, release layer 71, and seed layer 72 shown in Figures 30 and 31 have already been explained using Figure 8, so redundant explanations will be omitted.

[0102] In the connection part formation process shown in Figure 29, as shown in Figure 32, a connection part 47 including a columnar connection part 472 formed within the opening 81H1 and a connection part 48 including a columnar connection part 482 formed within the opening 81H2 are formed. Figure 32 is an enlarged cross-sectional view showing details of the connection part formation process shown in Figure 29. In the example shown in Figure 32, an electrode 492 constituting the connection part 49 is formed within the opening 81H3. This modified example differs from the manufacturing method described using Figure 10 in that an insulating layer 81 is used as a mask instead of the resist mask 73 described using Figure 10. The structures of the columnar connection parts 472, 482 and the electrode 492 are as described using Figure 10, so redundant explanations are omitted.

[0103] As described above, in this modified example, the insulating layer 81 is used as a mask to form the connection portions 47, 48, and 49. Therefore, the step of removing the resist mask 73 as described using Figure 11, and the step of forming the oxide film 72A as described using Figure 12, are not applied in this modified example.

[0104] The semiconductor die mounting process shown in Figure 29 includes the steps shown in Figures 33 to 35. Each of Figures 33 to 35 is an enlarged cross-sectional view showing the details of the semiconductor die mounting process shown in Figure 29. In the semiconductor die mounting process, as shown in Figure 35, a semiconductor die 41 having an IC chip 411 and a die electrode 417 connected to the IC chip 411, and a semiconductor die 42 having an IC chip 421 and a die electrode 427 connected to the IC chip 421 are prepared. In the semiconductor die mounting process, the semiconductor die 41 and the semiconductor die 42 are mounted on the support 70 such that the die electrode 417 is positioned on the connection portion 47 and the die electrode 427 is positioned on the connection portion 48.

[0105] For details, first, prepare semiconductor dies 41 and 42 as shown in Figure 33. This modified example differs from the semiconductor die mounting process described using Figures 13 to 15 in that an insulating layer 82 is formed on the upper surface (die electrode formation surface) of semiconductor die 41, and an insulating layer 83 is formed on the upper surface (die electrode formation surface) of semiconductor die 42. Insulating layer 82 is an insulating layer that is joined to insulating layer 81 in this process. Considering the bonding properties with insulating layer 81, it is particularly preferable that the materials of insulating layers 82 and 83 be made of the same material as insulating layer 81. The detailed structures of semiconductor dies 41 and 42 other than the differences described above have already been explained using Figure 4, so a redundant explanation will be omitted.

[0106] Next, as shown in Figure 33, the semiconductor die 41 and semiconductor die 42 are aligned with the support 70 so that the die electrode 417 is positioned on the connection portion 47 and the die electrode 427 is positioned on the connection portion 48. A solder layer 473 is formed on the die electrode 417 of the semiconductor die 41. A solder layer 483 is formed on the die electrode 427 of the semiconductor die 42. In this modified example, in the sealing process shown in Figure 29, the sealing body 45 does not come into contact with the connection portions 47, 48, and 49, respectively. For this reason, it is preferable that the solder layer 493 is formed on the bonding surface of electrode 492, which has a relatively larger area compared to die electrode 416. This makes it possible to reduce the volume of the void around the solder layer 493 after the semiconductor die mounting process. On the other hand, from the viewpoint of preventing oxidation of the bonding surface of die electrode 416, it is preferable that a solder layer is also formed on die electrode 416.

[0107] Next, as shown in Figure 34, the die electrode 417 of the semiconductor die 41 is pressed against the connection portion 47 via the solder layer 473. At this time, the die electrode 416 of the semiconductor die 41 is pressed against the solder layer 493. Similarly, the die electrode 427 of the semiconductor die 42 is pressed against the connection portion 48 via the solder layer 483. In this step, the solder layer 473 and the columnar connection portion 472 of the connection portion 47 are temporarily joined by solid-phase diffusion bonding. Similarly, the solder layer 493 and the electrode 492 of the connection portion 49 are temporarily joined by solid-phase diffusion bonding. Similarly, the solder layer 483 and the columnar connection portion 482 of the connection portion 48 are temporarily joined by solid-phase diffusion bonding. At this point, the insulating layer 81 is in contact with the insulating layers 82 and 83 respectively, but they are not yet joined.

[0108] Next, the bonding interfaces between the solder layer 473 and the metal film 472B of the columnar connection portion 472, the bonding interface between the solder layer 493 and the metal film 492B of the electrode 492, and the bonding interface between the solder layer 483 and the metal film 482B of the columnar connection portion 482 are bonded by the liquid-phase diffusion bonding described above. In this case, as shown in Figure 35, alloy layers 472D, 482D, and 492D are formed at each bonding interface by a eutectic reaction. The details of liquid-phase diffusion bonding have already been explained, so a redundant explanation will be omitted.

[0109] Furthermore, in this modified example, during the semiconductor die mounting process, insulating layer 81 and insulating layer 82 are joined to each other, and the die electrode 417 is sealed by insulating layer 81 and insulating layer 82. Also, during the semiconductor die mounting process, insulating layer 81 and insulating layer 83 are joined to each other, and the die electrode 427 is sealed by insulating layer 81 and insulating layer 83. The timing at which insulating layer 81 is joined to insulating layer 82 and insulating layer 83 can be approximately the same as the timing at which liquid-phase diffusion bonding is performed. That is, when the solder layer 473 and the metal film 472B shown in Figure 34 are heated to the temperature at which a eutectic reaction occurs, insulating layers 81, 82, and 83 are also heated together. As a result, the materials constituting insulating layers 81, 82, and 83 soften, and their contact interfaces are joined. As a principle of joining insulating layers, bonding by dehydration polymerization of hydroxyl groups on the surface of the insulating layers (fusion bonding) can be used, and depending on the material, bonding by softening and melting can also be used. When using the fusion bonding method, it is desirable to activate the surface of the insulating layer with plasma before joining the insulating layers together.

[0110] In this modified example, the connections 47, 48, and 49 are surrounded by an insulating layer 81. This suppresses the wetting and spreading of solder components when performing liquid-phase diffusion bonding. Therefore, even in this modified example, the die electrode and the connections can be joined with a small amount of solder.

[0111] In the sealing process shown in Figure 29, after the semiconductor die mounting process, the semiconductor die 41 and semiconductor die 42 are sealed with a sealing body 45, as shown in Figure 36. Figure 36 is an enlarged cross-sectional view showing details of the sealing process shown in Figure 29. In this process, the semiconductor die 41 and semiconductor die 42 are integrated by the sealing body 45. In this modified example, since the connection parts 47, 48, and 49 are already sealed, strictly speaking, the semiconductor die 41 and semiconductor die 42 are integrated via an insulating layer 81. In this process, sealing with the sealing body 45 improves the rigidity of the integrated structure of the semiconductor die 41 and semiconductor die 42.

[0112] In this modified example, the volume of the sealant 45 is even smaller than the volume of the sealant 45 shown in Figure 4. Therefore, even if the sealant 45 undergoes thermal expansion or contraction, the connection parts 47, 48, and 49 can maintain high positional accuracy even when sealed by the sealant 45.

[0113] In the support removal process shown in Figure 29, the support 70 shown in Figure 36 is removed after the sealing process. The method for removing the support 70 is the same as the support removal process described using Figure 17, so redundant explanations are omitted.

[0114] In the connection exposure process shown in Figure 29, after the support removal process, a portion (bottom surface) of the columnar connection portion 472 and a portion (bottom surface) of the columnar connection portion 482 are exposed from the insulating layer 81, as shown in Figure 37. Figure 37 is an enlarged cross-sectional view showing details of the connection exposure process shown in Figure 29. In this process, the peeling layer 71 and seed layer 72 shown in Figure 36 are removed, for example, by etching. In the example shown in Figure 37, a portion (bottom surface) of the electrode 492 is also exposed from the insulating layer 81 in this process.

[0115] In this process, as shown in Figure 38, it is preferable to expose the connection portion from the insulating layer 81 and then form metal films 472C, 482C, and 492C on the exposed surface of each connection portion. Figure 38 is an enlarged cross-sectional view showing the details of the connection portion exposure process following Figure 37. As shown in Figure 38, in this process, a metal film 472C is formed on the exposed surface of the columnar connection portion 472 from the sealant 45. Similarly, a metal film 482C is formed on the exposed surface of the columnar connection portion 482 from the sealant 45. A metal film 492C is formed on the exposed surface of the electrode 492 from the sealant 45. Details of the metal films 472C, 482C, and 492C have already been explained using Figure 19, so redundant explanations will be omitted.

[0116] The bridge mounting process shown in Figure 29 includes the steps shown in Figures 39 to 41. Each of Figures 39 to 41 is an enlarged cross-sectional view showing the details of the bridge mounting process shown in Figure 29. In the bridge mounting process, as shown in Figure 41, a bridge 43 is prepared, including a bridge electrode 436 connected to a connection portion 47 and a bridge electrode 437 connected to a connection portion 48. In the bridge mounting process, after the connection portion exposure step, the bridge 43 is mounted on a structure sealed with a sealant 45 such that the bridge electrode 436 is positioned on the columnar connection portion 472 and the bridge electrode 437 is positioned on the columnar connection portion 482.

[0117] For details, first, prepare the bridge 43 as shown in Figure 39. In this modified example, an insulating layer 84 is formed on the upper surface (bridge electrode formation surface) of the bridge 43, and each of the bridge electrodes 436 and 437 is sealed by the insulating layer 84, which differs from the semiconductor die mounting process described using Figures 13 to 15. The detailed structure of the bridge 43, excluding the above differences, has already been described using Figure 4, so a redundant explanation will be omitted.

[0118] Next, as shown in Figure 39, the bridge 43 and the structure sealed with the sealant 45 are aligned so that the bridge electrode 436 is positioned on the columnar connection portion 472 and the bridge electrode 437 is positioned on the columnar connection portion 482. A solder layer 474 is formed on the bridge electrode 436. A solder layer 484 is formed on the bridge electrode 437.

[0119] Next, as shown in Figure 40, the bridge electrode 436 of the bridge 43 is pressed against the columnar connection portion 472 of the connection portion 47 via the solder layer 474. At this time, the bridge electrode 437 of the bridge 43 is pressed against the columnar connection portion 482 of the connection portion 48 via the solder layer 484. In this step, the solder layer 474 and the columnar connection portion 472 of the connection portion 47 (specifically the metal film 472C of the columnar connection portion 472) are temporarily joined by solid-phase diffusion bonding. Similarly, the solder layer 484 and the columnar connection portion 482 of the connection portion 48 (specifically the metal film 482C of the columnar connection portion 482) are temporarily joined by solid-phase diffusion bonding.

[0120] In this modified example, the insulating layer 81 and the insulating layer 84 are in contact with each other at this point. However, at this point, the insulating layer 81 and the insulating layer 84 are not yet joined together.

[0121] Next, the bonding interface between the solder layer 474 and the metal film 472C of the columnar connection portion 472, and the bonding interface between the solder layer 484 and the metal film 482C of the columnar connection portion 482, as shown in Figure 40, are joined by liquid-phase diffusion bonding. The method of liquid-phase diffusion bonding is as described above, so a redundant explanation will be omitted. By liquid-phase diffusion bonding, the metal films 472C and 482C shown in Figure 40 become alloy layers 472E and 482E (see Figure 41), respectively, formed by a eutectic reaction between tin, the main component of the solder layer, and the material of the metal film (e.g., gold).

[0122] Furthermore, in this modified example, the insulating layer 81 and insulating layer 84 are joined to each other during the bridge mounting process. The timing of the joining of insulating layer 81 and insulating layer 84 is the timing of liquid-phase diffusion bonding. That is, when the solder layer 474 and the metal film 472C shown in Figure 40 are heated to the temperature at which a eutectic reaction occurs, insulating layer 81 and insulating layer 84 are also heated together. As a result, the materials constituting insulating layer 81 and insulating layer 84 soften, and their contact interfaces are joined. As a principle of joining insulating layers, the aforementioned bonding by dehydration polymerization of hydroxyl groups on the surfaces of the insulating layers (fusion bonding) can also be used.

[0123] Although this modified example was described using insulating layers 81 to 84 shown in Figure 28, it is possible to partially apply the configuration example shown in Figure 4, or the modified example described using Figure 24. For example, instead of insulating layer 84 shown in Figure 28, bridge electrodes 436 and 437 may each be sealed with the sealant 44 shown in Figure 4, or the sealant 105 shown in Figure 24.

[0124] Furthermore, although this modified example uses an example where the upper surface of the bridge 43 is covered with an insulating layer 84, there are cases where the insulating layer 84 is not formed. For example, if a functional insulating film called NCF (Non Conductive Film) is used instead of the insulating layer 84, the NCF is positioned after the process shown in Figure 38 so as to cover the insulating layer 81 and the connection parts 47 and 48. In this case, during the bridge mounting process, the bridge 43 with the structure shown in Figure 20 is pressed toward the NCF so that the bridge electrodes 436 and 437 each penetrate the NCF and contact the connection part 47 or 48. By performing the solid-phase diffusion bonding and liquid-phase diffusion bonding described above in this state, a structure similar to the chip integrated module 40D shown in Figure 28 can be obtained.

[0125] <Method for manufacturing chip assemblies> Next, a method for manufacturing a chip assembly will be described using Figure 3. First, a wide-area wiring layer 102 is formed on a support (not shown). The method for forming the wide-area wiring layer 102 is not particularly limited, and for example, a build-up method can be used. Next, a plurality of electrodes 403 and tall pillars 401 are formed on the wide-area wiring layer 102. The method for forming the electrodes 403 and tall pillars 401 can be applied by adapting the connection part formation process described using Figures 8 to 12. In this process, electrodes 148 and conductor posts 146 are also formed. If electrodes 148 and electrodes 403 have the same thickness, they can be formed together at the same time. On the other hand, since conductor posts 146 and tall pillars 401 have different thicknesses, they are formed separately.

[0126] Next, the chip integration module 40 is mounted on the tall pillar 401. The tall pillar 401 is connected to the connection part 49 shown in Figure 4. The method of connecting the tall pillar 401 and the connection part 49 is not particularly limited, but for example, they can be connected via a solder layer (not shown). In this case, from the viewpoint of preventing the solder layer inside the chip integration module 40 from remelting, it is preferable to use liquid phase diffusion bonding.

[0127] Next, the various components formed on the chip layer 104 are sealed with the sealant 105. In the example shown in Figure 3, the conductor post 146, electrode 148, chip integration module 40, tall pillar 401, and electrode 403 are each sealed with the sealant 105. After that, a support (not shown) is removed from the wide-area wiring layer 102. Furthermore, the upper part of the sealant 105 is ground so that the conductor post 146 and chip integration module 40 are exposed.

[0128] Next, a connection layer 106 is formed on the encapsulant 105. More specifically, the connection layer 106 is formed on the encapsulant 105 such that the wiring included in the connection layer 106 is connected to the exposed portion of the conductor post 146 or the exposed portion of the chip integration module 40. For example, an electrode 140 formed on the connection layer 106 is connected to the conductor post 146 through a conductor via 142.

[0129] Next, a heat dissipation mechanism 20 is mounted on the contact portion 222. Furthermore, an optical module 13, to which optical fibers 600 (see Figure 5) and optical fibers 610 (see Figure 5) are connected, is connected to the electrode 140. The heat dissipation member 136 is pre-connected to the optical module 13. Next, by mounting multiple external terminals 30 on the wide-area wiring layer 102, the chip assembly 10 shown in Figure 3 is obtained.

[0130] <Modified form of chip assembly> Next, a modified version of the chip assembly shown in Figure 3 will be described. Figures 42 and 43 are explanatory diagrams showing modified versions of the chip assembly shown in Figure 3. The chip assembly 10A shown in Figure 42 differs from the chip assembly 10 shown in Figure 3 in that a portion of the optical module 13 is embedded in the chip layer 104 of the integration layer 100. More specifically, the connector 132 portion of the optical module 13 is sealed by a sealant 105. The connector 132 and the electrode 148 are connected via a conductive via 142. When the connector 132 portion is embedded in the chip layer 104, the overall height of the chip assembly 10A can be reduced, and the signal transmission characteristics can be improved by shortening the distance from the chip assembly module to the optical transceiver compared to the case in Figure 3. In addition, since the optical transceiver 130 is exposed from the chip layer 104 and the connection layer 106, the optical transceiver 130 can be easily attached and detached.

[0131] The chip assembly 10B shown in Figure 43 differs from the chip assembly 10 shown in Figure 3 in that the optical module 13 is located on the back surface 100b of the integration layer 100. The integration layer 100 has a front surface 100f on which the heat dissipation mechanism 20 is mounted, and a back surface 100b on the opposite side of the front surface 100f. The optical module 13 is mounted on the back surface 100b. By placing the optical module 13 on the back surface 100b, the distance between the heat dissipation mechanism 20 and the optical module 13 is increased, thereby reducing the thermal influence from the heat dissipation mechanism 20. In addition, in the example shown in Figure 43, the optical module 13 is positioned in a location that overlaps with the chip integration module 40 in the thickness direction of the integration layer 100. In this case, the distance between the chip integration module 40 and the optical module 13 is reduced, which can improve the transmission efficiency of electrical signals.

[0132] <Modified examples of measures to reduce parasitic capacity occurring in bridges> In the signal transmission path via the bridge 43 shown in Figure 4, signals are transmitted at extremely high speeds. In the case of high-speed signal transmission paths, it is preferable to reduce the electrical parasitic capacitance introduced into the transmission path. Below, a technique for reducing the parasitic capacitance occurring between the chip 431 and the wiring 434 shown in Figure 4 will be described as a modified example. Figure 44 is a cross-sectional view showing a modified example of the bridge shown in Figure 4.

[0133] The bridge 43A shown in Figure 44 differs from the bridge 43 shown in Figure 4 in that it further comprises an insulating layer 438 between the insulating layer 432 and the chip 431. In other respects, it is the same as the bridge 43 shown in Figure 4. The bridge 43A comprises a chip 431, insulating layers 438, 432, and 433 sequentially laminated on the chip 431, and wiring 434 sandwiched between insulating layers 432 and 438 and connected to bridge electrodes 436 and 437, respectively. The insulating layer 438 is a thick insulating layer. The thickness of the insulating layer 438 is greater than the thickness of the insulating layer 432 and the insulating layer 433. The insulating layer 438 has a surface 438t that adheres to the insulating layer 432 and a surface 438b that adheres to the chip 431. Each of surfaces 438t and 438b has an adhesive function, and the insulating layer 438 is bonded and fixed to the insulating layer 432 and the tip 431 via the adhesive function of surfaces 438t and 438b. The entire insulating layer 438 may be an adhesive layer.

[0134] In the case of bridge 43A, where an insulating layer 438 is interposed between the insulating layer 432 and the chip 431, the separation distance between the wiring 434 and the chip 431 can be increased. As a result, compared to bridge 43 shown in Figure 4, the parasitic capacitance between the chip 431 and the wiring 434 can be reduced.

[0135] In the case of bridge 43A, which is provided with an insulating layer 438, warping deformation of the bridge is more likely to occur compared to bridge 43 shown in Figure 4. Warping deformation of the bridge is caused by film formation stress (resin curing shrinkage and thermal shrinkage) that occurs when forming the insulating layer 438. From the viewpoint of reducing this warping deformation, it is desirable to use a material with a low elastic modulus for the insulating layer 438. Also, from the same viewpoint, it is preferable to use a resin material with a lower curing temperature and thermal decomposition temperature compared to insulating layers 432 and 433. For example, if insulating layers 432 and 433 are made of polyimide resin and insulating layer 438 is made of epoxy resin, then since insulating layer 438 is made of a resin material with a lower curing temperature and thermal decomposition temperature compared to insulating layers 432 and 433, warping deformation of bridge 43A can be suppressed.

[0136] The bridge 43A shown in Figure 44 is manufactured, for example, as follows. Figures 45-47 are cross-sectional views showing an overview of the manufacturing process of the bridge shown in Figure 44. The manufacturing method of bridge 43A includes the wiring layer formation step shown in Figure 45, the wiring layer transfer step shown in Figure 46, the support removal step shown in Figure 47, and the bridge electrode formation step shown in Figure 44.

[0137] First, in the wiring layer formation process, an insulating layer 433, wiring 434, and insulating layer 432 are sequentially formed on the support 80 shown in Figure 45. Specifically, in the wiring layer formation process, the support 80 shown in Figure 45 is prepared. A release layer 81A and a seed layer 82A are pre-formed on the upper surface 80t of the support 80. The material of the support 80 is not particularly limited as long as it is a plate with sufficient rigidity to not impair workability in each process up to the support removal process described later. For example, it can be a semiconductor substrate such as a silicon wafer, a plate made of inorganic materials such as glass or sapphire substrates, or a resin plate. The release layer 81A is the same as the release layer 71 described using Figure 8, and the seed layer 82A is the same as the seed layer 72 described using Figure 8, so redundant explanations are omitted.

[0138] Furthermore, in the wiring layer formation process, after preparing the support 80, an insulating layer 433 is deposited on the seed layer 82A. Next, an opening is formed in a part of the insulating layer 433, and wiring 434 is formed within the opening. Although redundant explanations will be omitted, the method for forming the opening and the method for forming the wiring 434 within the opening can be formed by using the photolithography technique described with reference to Figures 9 and 10. Next, by forming an insulating layer 432 so as to cover the insulating layer 433 and the wiring 434, the structure shown in Figure 45 is obtained.

[0139] Next, in the wiring layer transfer process, as shown in Figure 46, the insulating layer 432 on the support 80 and the chip 431 are bonded together via the insulating layer 438. Note that Figure 46 illustrates an example in which individual chips 431 are bonded. However, as a variation, in this process, instead of chips 431, a silicon wafer before individualization, a glass substrate before individualization, or a sapphire substrate before individualization may be bonded. When a substrate in an individualized state is bonded in this process, after the bridge electrode formation process, an individualization process is performed in which the substrate is diced to obtain multiple bridges 43A (see Figure 44). In this variation, a large number of bridges 43A can be manufactured at once, which is preferable from the viewpoint of improving manufacturing efficiency. Including these variations, this process can be expressed as follows: In the wiring layer transfer process, the insulating layer 432 on the support 80 and the substrate are bonded together via the insulating layer 438. The term "substrate" here includes not only the chip shown in Figure 46, but also semiconductor substrates such as silicon wafers before piece formation, glass substrates before piece formation, or sapphire substrates before piece formation. As explained using Figure 44, since the surfaces 438t and 438b of the insulating layer 438 each have adhesive properties, the insulating layer 432 on the support 80 and the chip 431 are bonded and fixed via the insulating layer 438. In this modified example, the chip 431 and the wiring 434 are not electrically connected. If the portion of the chip 431 is not connected to other circuits, the portion of the chip 431 shown in Figure 44 may be replaced with a substrate on which an integrated circuit has not been formed (for example, a semiconductor substrate or a glass substrate). Alternatively, as will be described later, the portion of the chip 431 may be removed to form a bridge.

[0140] Next, in the support removal process, as shown in Figure 47, the release layer 81A (see Figure 46) is decomposed by applying energy to it. After the support removal process, the conductive parts connected to the bridge electrode 437 and the bridge electrode 436 (conducting part 437A connected to the bridge electrode 437 and conducting part 436A connected to the bridge electrode 436) are exposed. Conducting part 436A and conducting part 437A each function as a contactor for electrically connecting the wiring board and the bridge electrode. In this process, the release layer 81A and seed layer 82A shown in Figure 46 are removed, for example, by etching.

[0141] Next, in the bridge electrode formation process, as shown in Figure 44, a bridge electrode 437 is formed on the conductor portion 437A connected to the wiring 434, and a bridge electrode 436 is formed on the conductor portion 436A connected to the wiring 434. In this process, a solder layer 474 is formed on the tip surface of the bridge electrode 436, and a solder layer 484 is formed on the tip of the bridge electrode 437.

[0142] By performing the above process on a large size such as a wafer or panel, and then dividing it into bridges of a predetermined size, the bridge 43A shown in Figure 44 can be formed. Bridge 43A can be used to replace, for example, the bridge 43 shown in Figure 4. When bridge 43 is replaced with bridge 43A, the parasitic capacitance between the chip 431 and the wiring 434 is reduced, making it particularly suitable for transmitting high-speed signals. In this modified example, bridge 43A shown in Figure 44 and bridge 43B shown in Figure 48, which will be described later, will be explained as modified versions of bridge 43 shown in Figure 4. However, bridge 43A and bridge 43B can be replaced with bridge 43 shown in any of the chip integration modules 40A shown in Figure 25, chip integration module 40B shown in Figure 26, chip integration module 40C shown in Figure 27, and chip integration module 40D shown in Figure 28.

[0143] Figure 48 is a cross-sectional view showing another modification of the bridge shown in Figure 4. Bridge 43B shown in Figure 48 differs from bridge 43 shown in Figure 4 in that the portion corresponding to chip 431 has been removed. In the case of bridge 43B, since chip 431 is not located near wiring 434, the effect of parasitic capacitance on wiring 434 can be further reduced.

[0144] However, bridge 43B has lower rigidity compared to bridge 43 shown in Figure 4 and bridge 43A shown in Figure 44. For this reason, in the manufacturing process of the chip integrated module 40E, it is preferable to carry out each step in the same manner as the manufacturing method described using Figures 20 to 23, with the insulating layer 433 held on the chip 431 until the semiconductor die 41 and semiconductor die 42 are joined to bridge 43B and the areas around bridge electrodes 436 and bridge electrodes 437 are sealed. After that, it is preferable to use a manufacturing method to remove the chip 431 in the state shown in Figure 23. As a method for removing the chip 431, for example, if the chip 431 is made of silicon, it can be removed by dry etching, etc. If it is made of an inorganic material such as glass, a method can be used in which a release layer is interposed between the chip 431 and the insulating layer 433, and the chip 431 is removed by decomposing (ablating) the release layer with an energy beam such as a laser. As a modified method of manufacturing bridge 43B, the manufacturing method described using Figures 44 to 47 may also be used.

[0145] <Other variations of chip-integrated modules> Figure 49 shows a partial configuration of a chip integration module, which is a modified example of Figure 4. As shown in Figure 49, the chip integration module 40E according to this embodiment includes a first die 41E, a second die 42E, a bridge 43E, and sealing members 45E and 46E that seal them. The first die 41E is connected to the bridge 43E via a first connection part 47E. The bridge 43E is connected to the second die 42E via a second connection part 48E. Furthermore, the first die 41E is connected to the outside of the chip integration module 40E via a third connection part 49E.

[0146] The first die 41E comprises a first integrated circuit chip 402E, die electrodes 408E, 410E, wiring 404E, 406E connected to the first integrated circuit chip 402E, and insulating layers 412E, 414E in which the wiring 404E, 406E is embedded. The wiring 404E, 406E is separate from the wiring layer included in the first integrated circuit chip 402E. More specifically, the wiring 404E, 406E may be thick-film wiring using an insulating film of organic (and possibly inorganic) resin, and is known as a redistribution layer (RDL). The wiring provided by the second die and bridge is also called redistribution. Furthermore, the second integrated circuit chip 420 and the third integrated circuit chip 442E, described later, may have a similar configuration to the first integrated circuit chip 402E.

[0147] The second die 42E comprises a second integrated circuit chip 420E, a die electrode 424E, wiring 422E connected to the second integrated circuit chip 420E, and insulating layers 426E, 428E in which the wiring 422E is embedded.

[0148] The bridge 43E comprises a third integrated circuit chip 442E, bridge electrodes 446E, 448E, wiring 444E connected to the third integrated circuit chip 442E, and insulating layers 450E, 452E in which the wiring 444E is embedded. In this embodiment, the wiring 444E constitutes part of the bridge electrically connected to the first connection 47E and the second connection 48E. The bridge according to this embodiment is a pillar-suspended bridge. The wiring 444E according to this embodiment is electrically connected to the third integrated circuit chip 442E, and the wiring 444E and the third integrated circuit chip 442E function together as a bridge.

[0149] The first connection portion 47E includes columnar connection portions 474E and 472E. In this embodiment, the columnar connection portions are μm-sized columnar conductors (also called "micropillars"). The columnar connection portions 472E and 474E are columnar conductors formed to extend from the bridge 43E toward the first die 41E. In this embodiment, the cross-sectional area of ​​the portion of the columnar connection portion 472E connected to the columnar connection portion 474E is larger than the cross-sectional area of ​​the portion of the columnar connection portion 474E connected to the columnar connection portion 472E. In this modified example, the columnar connection portion 474E is connected to the die electrode 408E via solder 478E. The columnar connection portion 472E is also connected to the bridge electrode 446E via solder 476E.

[0150] The second connection portion 48E includes columnar connection portions 480E and 482E. The columnar connection portions 480E and 482E are columnar conductors formed to extend from the bridge 43E to the second die 42E. In this modified example, the cross-sectional area of ​​the portion of the columnar connection portion 480E connected to the columnar connection portion 482E is larger than the cross-sectional area of ​​the portion of the columnar connection portion 482E connected to the columnar connection portion 480E. In this modified example, the columnar connection portion 482E is connected to the die electrode 424E via solder 486E. The columnar connection portion 480E is also connected to the bridge electrode 448E via solder 484E.

[0151] The third connection portion 49E includes a columnar connection portion 492E. The columnar connection portion 492E is a columnar conductor formed to extend outward from the first die 41E. The columnar connection portion 492E is connected to the die electrode 410E via solder 490E. The columnar connection portion 492E is also connected to an electrode pad 494E that is connected to the outside (for example, the wide-area wiring layer 102). In addition to (or instead of) the configuration shown in Figure 49, the third connection portion 49E may include various structures. For example, the third connection portion 49E may include various structures that can be connected to the wide-area wiring layer 102 (see Figure 3), such as deep vias, tall pillars, and columnar connection portions, which are provided below the electrode pad 494E.

[0152] In this modified example, an example was described in which the bridge is a die containing an integrated circuit chip. However, the bridge may not contain an integrated circuit chip and may consist mainly of wiring and an insulating layer in which that wiring is embedded. Furthermore, in this embodiment, an example was described in which the die and the bridge are connected by two columnar connectors of different diameters. However, the die and the bridge may be connected by one columnar connector, or by three or more columnar connectors.

[0153] (First variation) Figure 50 shows the configuration of a chip integrated module according to a first modified example of the chip integrated module shown in Figure 49. Among the configurations of the chip integrated module 40F shown in Figure 50, those that are substantially the same as those of the chip integrated module 40E shown in Figure 49 are denoted by the same reference numerals, and their descriptions are omitted as appropriate.

[0154] The chip integration module 40F according to the first modification differs from the chip integration module 40E described above (see Figure 49) in the configuration of the first connection part, the second connection part, and the third connection part. Specifically, in the first modification example, the columnar connection part or electrode pad is directly connected to other electrodes or wiring without the use of solder. More specifically, in the first connection part according to the first modification, the columnar connection part 502F is connected to the die electrode 408E and the bridge electrode 446E. In the second connection part, the columnar connection part 504 is connected to the die electrode 424E and the bridge electrode 448E. Furthermore, in the third connection part, the electrode pad 494E is connected to the die electrode 410E. Here, the columnar connection part and the die electrode or bridge electrode, or the die electrode and the electrode pad, may be connected by various known techniques relating to hybrid bonding.

[0155] In the first modified example, various conductors are embedded in an insulator. Specifically, die electrodes 408E, 410E, and 424E are embedded in the insulating film 510F. Electrode pads 494E and columnar connectors 502F and 504F are embedded in the insulating layer 512F. Furthermore, bridge electrodes 446E and 448E are embedded in the insulating film 514F. The first die 41E and the second die 42E are sealed with insulating resin 506F. By selecting appropriate material systems and process conditions in various known hybrid bonding techniques, the die electrode 408E and the columnar connector 502F, and the insulating film 510F and the insulating layer 512F can be connected and joined. Similarly, for bridges, the bridge electrodes 446E and 448E can be connected and joined to the insulating layer 512F, and the insulating film 514F and the insulating layer 512F can be connected and joined.

[0156] In the first modified example, an example was described in which the bridge includes an integrated circuit chip, but the bridge is not limited to this example and does not necessarily have to include an integrated circuit chip. For example, instead of an integrated circuit chip, the bridge may include a solid chip made of various materials such as silicon and glass.

[0157] (Second variation) Figure 51 shows the configuration of a chip integrated module according to a second modification of the chip integrated module shown in Figure 49. In the chip integrated module 40G according to the second modification, a deep via 520G is formed in the insulating resin 524G that seals the bridge 43E, and the first die 41E is electrically connected to an external conductor through this deep via 520G. More specifically, the deep via 520G is connected to the electrode pad 494E connected to the bridge 43E, and solder 522G, which is connected to an external conductor, may be formed at the end of the deep via 520G. Here, the deep via 520G may be formed such that its diameter increases from the electrode pad 494E toward the solder 522G. In addition, in the second modification, the lower surface of the third integrated circuit chip 442E may be exposed.

[0158] In the second modification, the bridge, including bridge 43E, is sealed with insulating resin 524G. Therefore, in the second modification, the bridge is protected by insulating resin 524G. It is also possible to seal (underfill) the connection between the bridge and other components at the same time as sealing the bridge. Furthermore, by making the portion of the die where the terminals are formed flat, it is possible to make the pitch of the connection portion with the wide-area wiring layer narrower.

[0159] (Third variation) Figure 52 is a diagram illustrating a third modified chip integration module relative to the chip integration module shown in Figure 49. Figure 52 shows the vicinity of the deep via 520G and a portion of the third integrated circuit chip 442E of chip integration module H, which is a modified version of chip integration module 40G shown in Figure 51. The third modified version will mainly be described in terms of the differences from the chip integration module 40G of the second modified version. Furthermore, the chip integration module of the third modified version may have the same configuration as the chip integration module 40G of the second modified version. That is, configurations not shown in Figure 52 may be substantially the same as those shown in Figure 51. In the chip integration module 40H of the third modified version, unlike the second modified version, the lower surface of the third integrated circuit chip 442E is not exposed. More specifically, the lower side of the third integrated circuit chip 442E is covered with insulating resin 525G.

[0160] (Fourth variation) Figure 53 shows a chip integrated module according to a fourth modification of the chip integrated module shown in Figure 49. In the chip integrated module 40K according to the fourth modification, a wiring layer 570 is formed below the insulating resin 524 in which the bridge 43E is embedded. The first die 41E and the bridge 43E are connected to the wiring formed in this wiring layer 570K.

[0161] The wiring layer 570K according to the fourth modification has various conductors embedded in the insulating layer, specifically, wiring 578K and electrodes 576 embedded in the insulating layers 572K and 574K. These wiring 578K and electrodes 576K may be electrically connected to an external conductor. According to the fourth modification, for example, it is possible to arrange terminals on the bridge. Also, for example, it is possible to directly supply power to the bridge from an external source.

[0162] The third integrated circuit chip 564K according to the fourth modified example includes a functional element 566K having various functions in the region enclosed by the dashed line. This functional element 566K is connected to an electrode 576K formed in the wiring layer 570K via a via 568K formed inside the third integrated circuit chip 564K. In this embodiment, the bridge electrode 446E is connected to the wiring 443K, and the bridge electrode 448E is connected to the wiring 444E. Thus, in the fourth modified example, the first die 41E and the second die 42E are connected via the functional element 566K.

[0163] Furthermore, the electrode pad 494E, which is electrically connected to the first die 41E, is connected to the wiring 578K of the wiring layer 570K via the tall pillar 560K. Unlike the deep via 520G (see Figure 51) described in the second modified example, the tall pillar 560K may have a substantially constant cross-sectional area from the electrode pad 494E to the wiring 578K.

[0164] (Fifth variation) Figure 54 shows a chip integrated module according to a fifth modification of the chip integrated module shown in Figure 49. In the chip integrated module 40M according to the fifth modification, the bridge mainly consists of wiring. Specifically, the bridge 580M according to the fifth modification has various types of wiring and an insulating layer in which the wiring is embedded, but does not have an integrated circuit chip.

[0165] Bridge 580M has wiring 588M embedded in the insulating layer 582M, which is connected to bridge electrodes 446E and 448E. Additionally, wirings 589M and 590 are embedded in the insulating layers 582M, 584M, and 586M. These wirings 589M and 590M are connected to electrode 576 of wiring layer 570K via contact via 592M.

[0166] <Other variations in the manufacturing method of chip-integrated modules> Referring to Figures 55 to 60, other variations of the manufacturing method for chip integrated modules will be described.

[0167] First, a flat support plate 800 is prepared, with a release film 802 formed on its surface as shown in Figure 55. Various conductors are then formed on this release film 802 (forming step). Various materials can be used as the support, including glass, silicon, and metal. For example, columnar connecting portions 806 and 808 are formed on the release film 802, protruding from the surface of the support plate 800. Electrode pads 804 and 809 may also be formed on the release film 802.

[0168] Next, as shown in Figure 56, a plurality of dies, including a first die 81E and a second die 82E, are joined to various conductors formed on the release film 802. The first die 81E has a first integrated circuit chip 810, a wiring layer 812 formed on its surface, and various electrodes including die electrodes 814 and 816 formed on its surface. The second die 82E has a second integrated circuit chip 820, a wiring layer 822 formed on its surface, and various electrodes including die electrodes 824 and 826 formed on its surface.

[0169] In this embodiment, die electrodes formed on the die are bonded to various conductors (die bonding step). For example, die electrodes 814 and 816 of the first die 81E are bonded to electrode pad 804 and columnar connecting portion 806, respectively. Also, die electrodes 824 and 826 of the second die 82E are bonded to electrode pad 809 and columnar connecting portion 808, respectively. The die electrodes may be connected to the electrode pad or columnar connecting portion via solder, or they may be bonded by hybrid bonding without the use of solder.

[0170] Next, as shown in Figure 57, the various conductors and multiple dies formed on the release film 802 are sealed with resin 818 (sealing member) (sealing step). The space between the first die 81E and the second die 82E and the release layer may be pre-sealed before the sealing step with resin 818 by, for example, injection and curing using capillary action with liquid underfill resin (Capillary Underfill) or with an insulating resin such as NCF (Non Conductive Film), or it may be sealed simultaneously in the sealing step with resin 818 (Mold Underfill). As a result, the multiple dies are fixed in a state where they are bonded to the columnar connection part and the metal pad.

[0171] Next, as shown in Figure 58, the release film 802 and the support 800 are removed, and the release film remaining on the electrode pads and other parts is removed. Various methods can be used to remove the support, such as mechanically peeling off the support, peeling off the release film by irradiating it with laser light, or, in some cases, removing the support by grinding or etching. In the case of grinding or etching, the release film may not be necessary. Furthermore, the resin 818 on the surface side of the die is ground. This exposes the die. In the following, using the method described with reference to Figures 55 to 58, various conductors and multiple dies are embedded as shown in Figure 58, and the ground resin is also referred to as the intermediate 84E.

[0172] Next, as shown in Figure 59, the bridge is connected to the multiple columnar connection points (bridge connection step). In this embodiment, each of the multiple dies including the bridge 83E is used as a bridge, and the bridge is connected to the lower part of each of the multiple columnar connection points. In this embodiment, the bridge 83E has a third integrated circuit chip 830, a wiring layer 832 formed on its surface, and bridge electrodes (including bridge electrodes 834 and 836) formed thereon.

[0173] The bridge electrode 834 of bridge 83E is coupled to a columnar connector 806 connected to the first die 81E. Furthermore, the bridge electrode 836 of bridge 83E is bonded to a columnar connector 808 connected to the second die 82E. As a result, bridge 83E functions as a bridge electrically connected to the first die 81E and the second die 82E, forming a structure that characterizes a pillar-suspended bridge. The bridge electrode may be bonded to the columnar connector via solder, or it may be bonded by hybrid bonding without solder.

[0174] Next, as shown in Figure 60, the resin 818 is cut so that it is divided into individual chip integration modules 80. This forms each chip integration module individually.

[0175] In the manufacturing method of the chip integrated module according to this embodiment, as explained with reference to Figure 57, the first die, the second die, and the columnar connecting portion are fixed with resin, and then the subsequent processes are carried out. Therefore, in the subsequent processes, the positional relationship of the multiple dies does not shift, and it becomes possible to connect the integrated circuit chips with higher precision. Furthermore, simpler processes and handling become possible. In addition, it becomes possible to form external terminals directly beneath the integrated circuit chip, and excellent characteristics in terms of power integrity (PI) and signal integrity (SI) can be expected. Moreover, since stable relative positional accuracy of the dies can be ensured regardless of the size of the module, according to this embodiment, it becomes easy to expand to large-scale chip integration of panel-scale.

[0176] (Sixth variation) Figures 61 to 64 are diagrams illustrating a sixth modified method for manufacturing a chip integrated module, compared to the manufacturing method shown in Figures 55 to 60. The sixth modified method describes a manufacturing method for a chip integrated module having a configuration similar to the chip integrated module 40F of the second modified method, which was described with reference to Figure 50.

[0177] First, multiple intermediate bodies 84E embedded in resin 818 are prepared in the same manner as described above, referring to Figures 55 to 58.

[0178] Referring to Figure 61, the next steps will be described. First, the bridge is connected to the columnar connection. The bridge according to the sixth modified example has a wiring layer 946 and an integrated circuit chip 948. The wiring layer 946 has wiring (not shown in Figure 61), and this wiring is connected to a plurality of bridge electrodes. These bridge electrodes are connected to the columnar connection. For example, bridge electrode 942 is connected to columnar connection 806, and bridge electrode 944 is connected to columnar connection 808. As a result, bridge electrodes 942, 944, the wiring layer 946, and the integrated circuit chip function as a bridge.

[0179] Furthermore, resin encapsulation is performed to cover the die electrodes, wiring layers, and integrated circuit chip (Figure 61). Then, the integrated circuit chip is exposed by grinding or other methods (Figure 62).

[0180] Referring to Figure 62, the next step will be described. In Figure 61, the underside of the integrated circuit chip is covered with resin 940. The underside of the integrated circuit chip and the resin 940 on the underside are ground away. As a result, the underside of the integrated circuit chip is exposed, as shown in Figure 62.

[0181] Referring to Figure 63, the next step will be described. In this step, via openings 950 are formed in the resin 940 in which the integrated circuit chip is embedded. For example, the openings 950 may be formed in the resin by irradiating the resin 940 with a laser. The openings 950 may be formed such that, for example, electrode pads 809 connected to the integrated circuit chip are exposed. The via openings 950 that are formed may also be formed such that their diameter increases as they move downward from the electrode pads 809.

[0182] Referring to Figure 64, the next step will be described. In this step, metal is formed in the openings formed in the resin 940 by, for example, plating, and solder is provided at its ends. As a result, as shown in Figure 64, deep vias 952 with solder 954 at their ends are formed in the resin 940. Furthermore, by cutting the resins 818 and 940, they can be individually assembled into chip integration modules of the desired size.

[0183] In the sixth modification, an example was described in which the lower surface of the integrated circuit chip and the resin 940 on the lower surface are ground. However, the method is not limited to this, and an opening 950 may be formed without grinding the resin 940, and a deep via with solder at its end may be formed therein. This may result in the production of the chip integrated module described in the third modification.

[0184] (Seventh variation) Referring to Figures 65 to 66, the manufacturing method of the chip integrated module according to the seventh modified example will be described. In the seventh modified example, first, an intermediate 84E is manufactured as described with reference to Figures 55 to 58.

[0185] Referring to Figure 65, the next step will be described. In this step, a tall pillar 962 is formed on the electrode pad 809 embedded in the resin 818, and a bridge is joined to the connection part. The bridge according to the seventh modified example has a wiring layer 964 and an integrated circuit chip 966. The wiring layer 964 has wiring, and the bridge electrodes provided on the surface of this wiring are connected to, for example, the columnar connection parts 806 and 808, thereby functioning as a bridge.

[0186] Furthermore, the formed tall pillars and the bridges connected to the columnar joints are sealed with resin (Figure 64). Then, the tall pillars and bridges are exposed by grinding or other means (Figure 65).

[0187] Referring to Figure 66, the next step will be described. In this step, the resin 960 encapsulating the tall pillars and bridges, the tall pillars, and the integrated circuit chips are ground. As a result, the surfaces of the tall pillars and integrated circuit chips are exposed on the surface of the resin 960, as shown in Figure 66. Furthermore, by cutting the resins 818 and 960, a chip integration module of the desired size can be fabricated.

[0188] (Variation 8) Referring to Figures 67 to 69, the manufacturing method of the chip integrated module according to the eighth modified example will be described. In the eighth modified example, first, an intermediate 84E is prepared as described with reference to Figures 55 to 58.

[0189] Referring to Figure 67, the next step will be described. In this step, a bridge is joined to the connection portion embedded in the resin 818. The bridge according to the eighth modified example has a wiring layer 986 and an integrated circuit chip 988. The wiring layer 986 has wiring. Bridge electrodes provided on the surface of this wiring are connected to the columnar connection portions 806 and 808, so that the bridge electrodes and the wiring layer 986 function as a bridge.

[0190] Furthermore, the wiring layer 986 and the bridge electrode formed on the wiring layer 986 are sealed with resin. As a result, as shown in Figure 67, the die electrode and the wiring layer 986 are sealed with resin 980 With the bridge secured in place, it is connected to the columnar connection point.

[0191] Referring to Figure 68, the next step will be described. In this step, the integrated circuit chip 988 is removed from the wiring layer 986. Furthermore, by cutting the resin 818, a chip integrated module of the desired size can be fabricated.

[0192] Referring to Figure 69, the process of removing the integrated circuit chip 988 from the wiring layer 986 will be described in detail. In the eighth modified example, a peeling layer 996 is provided between the integrated circuit chip 988 and the insulating layer 994 of the wiring layer. By irradiating this peeling layer 996 with energy particles 981 (for example, laser light), at least a portion of the peeling layer 996 can be decomposed (altered). By moving the area irradiated with energy particles in the scanning direction indicated by the arrow, the peeling layer 996 can be decomposed entirely. This allows the integrated circuit chip 988 to be removed from the insulating layer 994.

[0193] In this example, we have described how to decompose the delamination layer 996 by scanning the area to which energy particles are irradiated. However, the method is not limited to this; the energy particles may be irradiated onto the entire delamination layer 996 at once without scanning.

[0194] <Manufacturing method for optical modules> A method for manufacturing an optical module according to one embodiment of the present invention will be described with reference to Figures 70 to 74.

[0195] First, a support 850 is prepared on which a release layer 852 is formed on its surface. Next, as shown in Figure 70, a wiring layer 860 is formed on the surface of the release layer 852. This wiring layer 860 may have a two-layer structure, and more specifically, it may have substantially the same configuration as the wiring layer 630 described with reference to Figure 5. In this embodiment, a plurality of conductive vias are formed in the upper layer of the wiring layer 630, and an electrode is coupled to each conductive via. For example, electrode 862 to which a conductive post is connected is coupled to conductive via 861, and electrode 864 to which an optical element driving chip is connected is coupled to conductive via 863.

[0196] Next, as shown in Figure 71, the conductor post 870 and the optical element driving chip 880 are coupled to the electrodes. For example, the conductor post 870 is coupled to electrode 862. The optical element driving chip 880 also has a plurality of electrode terminals 874. The electrode terminals 874 are connected to electrodes 872 formed on the surface of the wiring layer 860 via solder 782.

[0197] Next, as shown in Figure 72, the multiple conductor posts 870 and the optical element drive chip 880 are sealed with resin 882. This fixes the multiple conductor posts 870 and the optical element drive chip 880 in place.

[0198] Next, the release layer 852 and the support 850 are removed, and the release layer 852 remaining on the underside of the wiring layer 860 is removed. Furthermore, the upper surface of the resin 882 is ground to form a metal layer 884 on the upper surface of the optical element drive chip 880, as shown in Figure 73.

[0199] Next, as shown in Figure 74, the entire assembly is inverted so that the metal layer 884 is on the bottom, and the optical element chip 890 is bonded to the upper surface of the wiring layer 860. The optical element chip 890 is provided with a light-emitting element 892, a light-receiving element 894, and a plurality of electrode terminals 896. The optical element chip 890 is bonded to the wiring layer 860 by bonding each of the plurality of electrode terminals 896 to the electrode 866 of the wiring layer 860 via solder 868. Furthermore, the lower side of the optical element chip 890, the light-emitting element 892, the light-receiving element 894, and the plurality of electrode terminals 896 are sealed with resin 898. This completes the fabrication of the optical module 89.

[0200] <Modified Method of Manufacturing Chip Assembly> A method for manufacturing a chip assembly according to another embodiment will be described with reference to Figures 75 to 79.

[0201] First, as shown in Figure 75, a support 900 with a release layer 902 formed on its surface is prepared, and various conductors are formed on the surface of the release layer 902. Specifically, electrodes 906 to which conductor posts are connected and columnar connection parts 908 (tall pillars) to which chip integration modules are connected are formed.

[0202] Next, as shown in Figure 76, various components are formed on the various conductors formed on the release layer 902. For example, a conductor post 907 may be formed on the electrode 906, or a chip integration module 909 may be connected to the columnar connection portion 908. The chip integration module 909 may be connected to the columnar connection portion 908 by solder provided on the columnar connection portion 908. If the thickness of the bridge of the chip integration module is sufficiently thin, the columnar connection portion 908 can be replaced with a solder bump that is lower in height.

[0203] Next, as shown in Figure 77, the various formed components are sealed with resin. Specifically, the conductor posts 907, columnar connectors 908, and chip integration modules 909 may be sealed with resin 914. After that, the support 900 is removed from the wiring layer 904 together with the release layer 902. Furthermore, the resin 914 is ground down so that the conductor posts 907 and chip integration modules 909 are exposed.

[0204] Next, as shown in Figure 78, a wiring layer 912 is formed on the resin 914. More specifically, the wiring layer 912 is formed on the resin 914 such that the wiring contained in the wiring layer 912 is connected to the exposed portion of the conductor post 907 or the exposed portion of the chip integration module 909. For example, an electrode 916 formed on the wiring layer 912 may be connected to the conductor post 907 through a conductor via. Also, a contact metal 918 may be connected to the chip integration module 909 through a conductor via.

[0205] Next, as shown in Figure 79, a heat dissipation mechanism 922 is mounted on the contact metal 918. Furthermore, an optical module 917, to which optical wiring 920 is connected, is connected to the electrode 916. This completes the fabrication of the chip assembly according to this embodiment.

[0206] <Integrated Circuit Chip> Figure 80 shows an example of the configuration of an integrated circuit chip according to one embodiment. The integrated circuit chip 35 includes a wiring layer 350, a transistor 370, and a connecting layer 390 that connects the wiring layer 350 and the transistor 370.

[0207] The wiring layer 350 has a five-layer laminated structure, and each layer has a film that insulates the layers, wiring embedded in the film, and vias that connect the wiring of adjacent layers above and below each other. For example, the wiring 352 of the second layer and the wiring 354 of the third layer are connected via 353, and the wiring 354 is embedded in an insulating film 356. The film of each layer may be made of, for example, BPSG (Boron-Phosphorous Silicate Glass). The wiring of each layer may be made of, for example, a metal such as copper. Note that the wiring in the upper layers (for example, the fifth and fourth layers) does not need to be as fine as the wiring in the other layers, as it serves as power or ground.

[0208] Although several representative embodiments have been described above with reference to the drawings, there are various further modifications to the embodiments and modifications described above. Parts of the embodiments can be appropriately modified as long as they do not contradict the above description. Furthermore, for example, parts of the embodiments and modifications described above can be combined with parts of other embodiments.

[0209] In the above embodiment, examples in which various columnar connecting portions are oriented approximately perpendicular to the surface of the die were mainly described. However, the columnar connecting portions are not limited to this, and may be formed to face any direction as long as they extend toward other dies. Furthermore, the various dimensions, cross-sectional shape, aspect ratio (ratio of the dimension in the cross-sectional direction to the dimension in the direction perpendicular thereto), etc., of the columnar connecting portions can be appropriately set according to requirements such as performance and reliability, and the manufacturing process that can be selected.

[0210] In the above embodiment, when the bridge includes a chip, an example was mainly described in which the bridge includes wiring and the chip is connected to the bridge electrodes via this wiring. However, the bridge does not have to include wiring, and the chip may be directly connected to the bridge electrodes. Furthermore, the above embodiments primarily described examples in which various dies (for example, a first die and a second die) include wiring. However, the dies are not limited to this and do not need to include wiring. In this case, the integrated circuit chip on the die may be directly connected to the die electrodes.

[0211] In the above embodiment, a thin-film wiring layer formed on the support 900 was used as the wiring 904, but the wiring 904 is not limited to this and can also be various known interposers or wiring substrates. [Industrial applicability]

[0212] This invention is widely applicable to semiconductor modules and the like.

Claims

1. A first semiconductor die having a first IC chip and a first die electrode connected to the first IC chip, A second semiconductor die having a second IC chip and a second die electrode connected to the second IC chip, A first connection portion electrically connected to the first die electrode, A second connection portion electrically connected to the second die electrode, A bridge having a first bridge electrode connected to the first connection part and a second bridge electrode connected to the second connection part, A first encapsulant that encapsulates the first semiconductor die and the second semiconductor die, Equipped with, The aforementioned bridge, Tips and, A first insulating layer, a second insulating layer, and a third insulating layer are sequentially laminated on the chip, A wiring is sandwiched between the second insulating layer and the third insulating layer and connected to the first bridge electrode and the second bridge electrode, It has, The first bridge electrode and the second bridge electrode are exposed from the first encapsulant. Each of the first and second connecting portions is sealed in the first sealing body. A semiconductor module in which the thickness of the first insulating layer is greater than the thickness of the second insulating layer.

2. A first semiconductor die having a first IC chip and a first die electrode connected to the first IC chip, A second semiconductor die having a second IC chip and a second die electrode connected to the second IC chip, A first connection portion electrically connected to the first die electrode, A second connection portion electrically connected to the second die electrode, A bridge having a first bridge electrode connected to the first connection part and a second bridge electrode connected to the second connection part, A first encapsulant that encapsulates the first semiconductor die and the second semiconductor die, Equipped with, The first bridge electrode and the second bridge electrode are exposed from the first encapsulant. Each of the first and second connecting portions is sealed in the first sealing body. The first connection portion is connected to the first bridge electrode via the first bridge-side solder, The semiconductor module is such that the second connection portion is connected to the second bridge electrode via the second bridge-side solder.

3. In claim 1 or claim 2, A semiconductor module in which the first bridge electrode and the second bridge electrode are each sealed in a second encapsulant.

4. In claim 3, The first encapsulant comprises a plurality of first filler particles, The second encapsulant comprises a plurality of second filler particles, A semiconductor module in which the average particle size of the plurality of first filler particles is greater than the average particle size of the plurality of second filler particles.

5. In claim 1 or claim 2, A semiconductor module in which the sides of the first connection portion and the sides of the second connection portion are covered with an oxide film.

6. In claim 1 or claim 2, The first connection part is, The first upper surface facing the first die electrode, A first lower surface located on the opposite side of the first upper surface and facing the first bridge electrode, It has, The second connection part is, The second upper surface facing the second die electrode, A second lower surface located on the opposite side of the second upper surface and facing the second bridge electrode, It has, A semiconductor module in which the first lower surface and the second lower surface are each exposed from the first encapsulant.

7. In claim 6, The joint between the first upper surface of the first connection portion and the first die electrode is sealed in the first sealing body. A semiconductor module in which the junction between the second upper surface of the second connection portion and the second die electrode is sealed in the first encapsulant.

8. In claim 1 or claim 2, The first connection portion is connected to the first die electrode via the first die side solder, A semiconductor module in which the second connection portion is connected to the second die electrode via the second die side solder.

9. In claim 1, The first connection portion is connected to the first bridge electrode via the first bridge-side solder, The semiconductor module is such that the second connection portion is connected to the second bridge electrode via the second bridge-side solder.

10. A first semiconductor die having a first IC chip and a first die electrode connected to the first IC chip, A second semiconductor die having a second IC chip and a second die electrode connected to the second IC chip, A first connection portion electrically connected to the first die electrode, A second connection portion electrically connected to the second die electrode, A bridge having a first bridge electrode connected to the first connection part and a second bridge electrode connected to the second connection part, A first encapsulant that encapsulates the first semiconductor die and the second semiconductor die, Equipped with, The first die electrode is formed to protrude from the first IC chip, The second die electrode is formed to protrude from the second IC chip, The first bridge electrode and the second bridge electrode are exposed from the first encapsulant. The first connection portion is connected to the first bridge electrode via the first bridge-side solder, The second connection portion is connected to the second bridge electrode via the second bridge side solder, Each of the first and second connection portions is sealed with an insulating layer on at least a portion of its side circumference. electronic equipment.

11. In claim 10, The first connection part is, The first upper surface facing the first die electrode, A first lower surface located on the opposite side of the first upper surface and facing the first bridge electrode, It has, The second connection part is, The second upper surface facing the second die electrode, A second lower surface located on the opposite side of the second upper surface and facing the second bridge electrode, It has, An electronic device in which the first upper surface, the first lower surface, the second upper surface, and the second lower surface are each exposed from the insulating layer.

12. In claim 10, The first connection portion has a conductive path between the first die electrode and the first bridge electrode in the thickness direction of the insulating layer, The second connection portion has a conductive path between the second die electrode and the second bridge electrode in the thickness direction of the insulating layer, in an electronic device.

13. In claim 10, The first connection portion is connected to the first die electrode via the first die side solder, An electronic device in which the second connection portion is connected to the second die electrode via the second die side solder.

Images