Integrated circuit device

Abstract

To provide an integrated circuit device that performs, only once when power supply is connected first, a memory load operation that is performed at switching from a low-power mode to a high-power mode and thereby reduces the current amount used for memory loading.SOLUTION: An integrated circuit device according to the present invention is characterized by including: a memory for storing trim data; a sleep register for inputting trim data to a sleep function block; a normal register for inputting trim data to a normal function block; a memory controller for loading the trim data stored in the memory into the sleep register or the normal register; and a wake controller for loading the trim data stored in the normal register into the sleep register via the memory controller at a first self-wakeup time after power supply is connected, so as to ensure that the memory is loaded only once after power supply is connected.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to an integrated circuit device.

Background Art

[0002] Generally, an integrated circuit that diagnoses and manages the state of a battery operates by receiving power from the battery.

[0003] If the current consumption of the battery of the integrated circuit is large, it may affect the life and performance of the battery.

[0004] To minimize such an impact, the integrated circuit sleep uses a mode ( Low power mode ) and switches to a mode ( normal ) only when necessary. High Power Mode

[0005] However, each time the integrated circuit switches from a mode to a mode, it performs a memory load operation. sleep from the mode to normal As a result, the current consumption of the battery may increase and the life of the battery may decrease, the time taken for mode switching may increase, and there is a risk that mode switching may fail.

[0006] The background art of the present invention is disclosed in "Battery Diagnosis Device and Method" of Patent Document 1.

[0007]

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0009] The present invention was made to improve the above-mentioned problems, and an object according to one aspect of the present invention is, sleep From Mode normal The objective is to provide an integrated circuit device that reduces the amount of current used for memory loading by performing the memory load operation, which is performed when switching to a different mode, only once when the power supply is connected. [Means for solving the problem]

[0010] An integrated circuit device according to one aspect of the present invention includes a non-volatile memory for storing trim data, a volatile sleep register located in a sleep domain to which power is supplied in sleep mode and normal mode, a volatile normal register located in a normal domain to which power is supplied only in normal mode, and a memory controller for loading the trim data between the memory, the sleep register, and the normal register, wherein the memory controller loads the trim data stored in the memory into the sleep register during self-wake-up after power is connected, and loads the trim data stored in the sleep register into the normal register during external wake-up after self-wake-up. The trim data is clock frequency or current information that allows the corresponding functional block to achieve maximum performance within its specified power range. .

[0011] An integrated circuit device according to one aspect of the present invention further comprises The system includes a sleep function block located in the sleep domain and receiving the trim data input from the sleep register, a normal function block located in the normal domain and receiving the trim data input from the normal register, and a wake controller. When the wake controller is connected to power and receives a stabilization completion signal from the sleep function block, Normal domain You may turn on the power.

[0012] The memory controller of the present invention is The data stored in the memory during the self-wake-up process The trim data is loaded into the sleep register and the normal register. The aforementioned sleep mode Switching to Previously, the trim data stored in the normal register may be loaded into the sleep register.

[0013] The sleep register of the present invention is In the sleep mode and the normal modeIt may hold the trim data.

[0014] The normal register of the present invention In the aforementioned normal mode may hold the trim data.

Advantages of the Invention

[0015] An integrated circuit device according to an aspect of the present invention sleep from the mode normal performs the memory load operation performed at the time of switching to the mode only once at the first time when the power supply is connected, sleep and reduces the amount of current used for memory load in the mode.

[0016] Another integrated circuit device according to another aspect of the present invention normal shortens the switching time to the mode so as to be able to quickly respond to a fault situation.

[0017] Still another integrated circuit device according to still another aspect of the present invention applies trim data to a functional block in advance to increase wake-up robustness.

Brief Description of the Drawings

[0018] [Figure 1] It is a system configuration diagram to which an integrated circuit device according to an embodiment of the present invention is applicable. [Figure 2] It is a block configuration diagram of an integrated circuit device according to an embodiment of the present invention. [Figure 3] It is a diagram showing a self-wake-up sequence of an integrated circuit device according to an embodiment of the present invention. [Figure 4] It is a diagram showing an external wake-up sequence of an integrated circuit device according to an embodiment of the present invention. [Figure 5] It is a diagram showing a memory load sequence according to an embodiment of the present invention. [Figure 6] It is a diagram showing an example of shortening the normal mode switching time according to an embodiment of the present invention. [Figure 7]This figure shows an example of pre-application of trim data according to one embodiment of the present invention. [Modes for carrying out the invention]

[0019] Hereinafter, an integrated circuit device according to one embodiment of the present invention will be described in detail with reference to the attached drawings. In this process, the thickness of lines and the size of components shown in the drawings may be exaggerated for clarity and convenience of explanation. Furthermore, the terms described later are defined in consideration of the function in the present invention, and these may vary depending on the intent or convention of the user or operator. Therefore, the definitions of such terms must be based on the content throughout this specification.

[0020] Figure 1 is a system configuration diagram to which an integrated circuit device according to one embodiment of the present invention can be applied.

[0021] Referring to Figure 1, multiple ICs 10 are connected to the battery 20, allowing for the diagnosis of the battery's condition.

[0022] Each of the multiple IC10s constantly draws current from the battery 20.

[0023] To reduce the battery's current consumption, IC10, sleep From mode, only when necessary. normal Switch to mode.

[0024] IC10 is sleep From Mode normal Each time the mode is switched, a memory load operation is performed, but such a memory load operation consumes a large amount of current.

[0025] Therefore, it is necessary to limit memory load operations to reduce current consumption.

[0026] An integrated circuit device according to one embodiment of the present invention, after the power supply is first connected, sleep From Mode normalThe memory load operation performed when switching to a new mode is performed only once, when the power is connected.

[0027] Figure 2 is a block diagram of an integrated circuit device according to one embodiment of the present invention, Figure 3 is a diagram showing the self-wake-up sequence of an integrated circuit device according to one embodiment of the present invention, Figure 4 is a diagram showing the external wake-up sequence of an integrated circuit device according to one embodiment of the present invention, Figure 5 is a diagram showing the memory load sequence according to one embodiment of the present invention, and Figure 6 is a diagram according to one embodiment of the present invention normal Figure 7 shows an example of shortening the mode switching time, and Figure 7 shows an example of pre-application of trim data according to one embodiment of the present invention.

[0028] Referring to Figure 2, an integrated circuit device according to one embodiment of the present invention includes a sleep function block 110, a sleep register 120, a wake controller 130, a normal function block 210, a memory 220, a memory controller 230, and a normal register 240.

[0029] The sleep function block 110, the sleep register 120, and the wake controller 130 operate in a sleep domain 100 that remains in an always-on state.

[0030] The wake controller 130, normal function block 210, memory 220, memory controller 230, and normal registers 240 operate in a normal domain 200 that is repeatedly switched on and off.

[0031] The sleep function block 110 may also be an analog function block that operates in sleep mode.

[0032] The sleep function block 110 can operate by applying the trim data stored in the sleep register 120.

[0033] Trim data may also include clock frequency and current information that allows a functional block to achieve maximum performance within its specified power range.

[0034] The sleep function block 110 can recognize the wake-up signal.

[0035] The sleep function block 110 can transmit a stabilization completion signal (Power OK) to the wake controller 130 during the first self-wake-up sequence after the power supply is connected.

[0036] The normal function block 210 may also be an analog function block that operates in normal mode.

[0037] The normal function block 210 can operate by applying the trim data stored in the normal register 240.

[0038] The sleep register 120 is, It is volatile, It can receive a constant power supply and retain trim data.

[0039] The sleep register 120 allows the trim data from the sleep register 120 to be applied to the sleep function block 110 by inputting the trim data to the sleep function block 110.

[0040] Sleep register 120 is for self-wake-up. rear , sleep Before entering the mode, trim data can be received and stored from the normal register 240 in response to a control command from the memory controller 230.

[0041] The sleep register 120 can load trim data into the normal register 240 in response to a control command from the memory controller 230 when an external wake-up occurs.

[0042] When power is applied, the wake controller 130 can receive a stabilization completion signal from the sleep function block 110.

[0043] Upon receiving the stabilization completion signal, the wake controller 130 can turn on the normal power supply for the normal domain 200. That is, the wake controller 130 can turn on the power supply for the memory 220, the memory controller 230, the normal register 240, and the normal function block 210.

[0044] The wake controller 130 is configured to perform a memory load operation only once, when power is connected.

[0045] In other words, after the power is connected, during the first self-wake-up, the wake controller 130 will The memory controller 230 is instructed to load the trim data stored in memory 220 into the sleep register 120 and the normal register 240. The wake controller 130 also performs sleep after self-wake-up. mode Switch to Before that, memory controller 230 to , trim data stored in normal register 240 of Sleep register 120 to load Make it run .

[0046] Furthermore, during external wake-up after self-wake-up, the wake controller 130 controls the memory controller 230. to , trim data stored in sleep register 120 of Normal register 240 to load Make it run .

[0047] In other words, as shown in Figure 5, by an external wake-up signal sleep From Mode normal By not performing a memory load operation each time the mode is switched, and instead performing a memory load only once during self-wake-up after the power is turned on, current consumption can be significantly reduced.

[0048] Memory 220 can store trim data.

[0049] The memory 220, in response to a control instruction from the memory controller 230, processes the trim data. Sleep register 120 or Normal register 240 load It is possible.

[0050] Memory 220 is, It is non-volatile, Trim data is retained even when the power is turned off.

[0051] Normal register 240 can store trim data.

[0052] Normal register 240 is, It is volatile, Trim data can be retained while both constant power and normal power are supplied.

[0053] The normal register 240 allows the normal function block to apply the trim data from the normal register 240 by inputting trim data into it.

[0054] Normal register 240 is self-wake-up. rear , sleep mode Switch to Before that, trim data can be loaded into the sleep register 120 in accordance with a control instruction from the memory controller 230.

[0055] The normal register 240, when an external wake-up occurs, responds to the control instructions of the memory controller 230. sleep Register 120 From trim data load It can be stored in this way.

[0056] Trim data stored in memory 220 during self-wake-up. teeth Load into sleep register 120 and normal register 240. So It is possible.

[0057] When trim data is loaded into the sleep register 120, the trim data stored in the sleep register 120 is applied to the sleep function block 110 from that point onward.

[0058] When trim data is loaded into the normal register 240, the trim data stored in the normal register 240 is applied to the normal function block 210 from that point onward.

[0059] From then on, sleep Mode Switch Previously, the memory controller 230 transferred the trim data stored in the normal register 240 to the sleep register 120. load Therefore, the sleep register 120 will hold the trim data. normal From Mode sleep Mode Switching However, the sleep function block 110 maintains the state in which the trim data stored in the sleep register 120 is applied. In contrast, the normal function block 210 is in a state where no power is applied, so the trim data is not applied. Tona ru.

[0060] This will be explained in detail with reference to Figures 3 and 4.

[0061] Referring to Figure 3, after the power supply is connected, during self-wake-up, the sleep function block 110 transmits a stabilization completion signal to the wake controller 130.

[0062] Upon receiving a stabilization completion signal from the sleep function block 110, the wake controller 130 turns on the power to the normal domain 200. This turns on the normal power to the normal function block 210, the normal register 240, the memory controller 230, and the memory 220.

[0063] When the normal power is turned on, the wake controller 130 causes the memory controller 230 to start operating.

[0064] The memory controller 230 loads the trim data stored in memory 220 into the sleep register 120 and the normal register 240.

[0065] When trim data is loaded into the sleep register 120, the trim data stored in the sleep register 120 is applied to the sleep function block 110 from that point onward.

[0066] When trim data is loaded into the normal register 240, the trim data stored in the normal register 240 is applied to the normal function block 210 from that point onward.

[0067] From then on, sleep Mode Switch Previously, the memory controller 230 loads the trim data stored in the normal register 240 into the sleep register 120. In this case, the sleep register 120 holds the trim data, normal From Mode sleep Mode Switching However, the sleep function block 110 maintains the state in which the trim data stored in the sleep register 120 is applied. In contrast, the normal function block 210 is in a state in which no power is applied, and therefore the trim data is not applied. Na ru.

[0068] Referring to Figure 4, when an external wake-up occurs after self-wake-up, the sleep function block 110 is already in a state where the trim data of the sleep register 120 has been applied due to the self-wake-up.

[0069] When the sleep function block 110 receives a wake-up signal, it notifies the wake controller 130 that the wake-up signal has been transmitted.

[0070] The wake controller 130 turns on the power to the normal domain 200. This turns on the normal power to the normal function block 210, normal registers 240, memory controller 230, and memory 220.

[0071] When the normal power is turned on, the memory controller 230 loads the trim data stored in the sleep register 120 into the normal register 240. As a result, the normal function block 210 applies the trim data stored in the normal register 240.

[0072] In other words, as shown in Figure 5, when the memory controller 230 self-wakes up, sleep mode Switches to Previously, the trim data stored in the normal register 240 is loaded into the sleep register 120. Subsequently, when the system is externally woken up, the trim data from the sleep register 120 is uploaded to the normal register 240, so that memory loading occurs only once after the power is connected. sleep This mode can reduce the amount of current used for memory loading.

[0073] Furthermore, as shown in Figure 6, the memory load time of each IC 10 connected to the battery 20 can be reduced, thus shortening the memory load time by the number of ICs 10, and thereby shortening the fault response time.

[0074] For example, if the time required to load 2k bits of memory is approximately 1ms, and 20 IC10s are installed, the total memory load time can be reduced by 20ms.

[0075] Furthermore, as shown in Figure 7, wake-up robustness can be improved by pre-applying trim data.

[0076] For example, if the frequency of the 100kHz oscillator that recognizes the wake-up pulse frequency is off, the oscillator may not wake up. However, in this embodiment, the problem of not being woken up can be resolved by preloading trim data into the sleep register 120. [Explanation of Symbols]

[0077] 10 ICs, 20 batteries, 100 sleep domains, 110 sleep function blocks, 120 sleep registers, 130 wake controllers, 200 normal domains, 210 normal function blocks, 220 memory, 230 memory controllers, 240 normal registers.

Claims

1. Non-volatile memory for storing trim data, A volatile sleep register located in the sleep domain to which power is supplied in sleep mode and normal mode, A volatile normal register located in the normal domain, which is powered only in normal mode, The system includes a memory controller that loads the trim data between the memory, the sleep register, and the normal register. The memory controller loads the trim data stored in the memory into the sleep register during self-wake-up after power is connected, and loads the trim data stored in the sleep register into the normal register during external wake-up after self-wake-up. The trim data is clock frequency or current information that allows the corresponding functional block to achieve maximum performance within its specified power range, in an integrated circuit device.

2. A sleep function block located in the sleep domain and receiving the trim data input from the sleep register, A normal function block located in the normal domain and receiving the trim data input from the normal register, It has a wake controller, The integrated circuit apparatus according to claim 1, wherein the wake controller turns on the power to the normal domain when power is connected and a stabilization completion signal is received from the sleep function block.

3. The integrated circuit device according to claim 1, wherein the memory controller loads the trim data stored in the memory into the sleep register and the normal register when the self-wake-up occurs, and loads the trim data stored in the normal register into the sleep register before switching to the sleep mode.

4. The integrated circuit apparatus according to claim 1, wherein the sleep register holds the trim data in the sleep mode and the normal mode.

5. The integrated circuit apparatus according to claim 1, wherein the normal register holds the trim data in the normal mode.

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