configurable reduced memory startup

Abstract

To provide a settable reduction memory start-up for efficient Qos on a computing platform.SOLUTION: A system, a device and a method can provide a technique for validating a first rank set in a memory module on the basis of a battery state and a user interface during a boot sequence, and invalidating a second rank set in the memory module on the basis of the battery state and the user interface during the boot sequence. The technique may generate a map between a system address space and a first bank set in the first rank set, and exclude a second bank set in the first rank set from the map.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] This application claims the benefit of priority to Indian Provisional Patent Application No. 2020041033777, filed on August 6, 2020.

[0002] Embodiments generally relate to computer memory. More particularly, embodiments relate to configurable reduced memory startup for efficient quality of service (QoS) on a computing platform.

Background Art

[0003] With the increasing memory requirements from end users, recent computing device manufacturers are designing computing devices such as laptops, desktops, server systems, and phones with large amounts of memory. In addition to the increased bill of materials (BOM) cost of the platform, there are other important issues including increased total cost of ownership (TCO), such as power consumption to keep large platform memory operating regardless of usage / demand, energy certification issues (e.g., SERT compliance), increased defects from large amounts of memory, boot time delays due to bottlenecks related to memory training, increased battery level requirements for powering on the entire memory bank, etc. These issues can be problematic in both client devices (e.g., having limited battery, form factor) and servers (TCO, energy compliance, etc.).

Brief Description of the Drawings

[0004] Various advantages of the embodiments will become apparent to those skilled in the art by reading the following specification and the appended claims, and by referring to the following drawings:

[0005] [Figure 1] A block diagram of an example of a state machine according to an embodiment. [Figure 2] This is a flowchart of an example of a boot flow according to one embodiment. [Figure 3] This is a flowchart of an example of the operation flow according to one embodiment. [Figure 4] This is a flowchart of an example of an operation flow for disabling the refresh to an unused rank according to one embodiment. [Figure 5] This is an illustration of an example of the operation flow from configurable min-memory-startup (CMMS) to normal mode according to one embodiment. [Figure 6] This is a flowchart illustrating an example of a method for operating the BIOS (basic input output system) in a computing system with improved performance according to one embodiment. [Figure 7] This is a flowchart illustrating one example of how to operate a memory controller in a high-performance computing system. [Figure 8] This is a flowchart illustrating an example of a method for transitioning to normal mode according to one embodiment. [Figure 9] This is a block diagram of an example of a performance-enhanced computing system according to one embodiment. [Figure 10] This is an illustration of an example of a semiconductor device according to one embodiment. [Figure 11] This is a block diagram of an example of a processor according to one embodiment. [Figure 12] This is a block diagram of an example of a multiprocessor-based computing system according to one embodiment. [Modes for carrying out the invention]

[0006] Existing solutions may maintain the entire system memory in a fully functional mode during system boot or active operation, regardless of active memory usage. Self-refresh mode is the only power-saving mode widely used when the system transitions to a low-power state. Existing solutions lack efficient minimum memory management, resulting in increased TCO, energy certification issues, and increased defects per million (DPM). Consequently, quality can degrade, booting can become slower, and the limited battery capacity on mobile devices can be used inefficiently.

[0007] The embodiment proposes a configurable minimum memory startup (CMMS) for efficient quality of service (QoS) on a computing platform that addresses the aforementioned challenges of large memory across client devices, IoT (Internet of Things) components, edge devices, and cloud configurations. As a result, significant platform improvements are delivered to customers / partners as well as a better total cost of ownership (TCO).

[0008] The embodiment addresses the issue of whether memory is utilized to its fullest extent by all end users in all scenarios. In some scenarios, only a small number of users fully utilize the memory (for example, memory may not be fully utilized for most of the time).

[0009] CMMS technology includes the following:

[0010] - System OS (operating system) settings or system administration settings that provide a user interface for configuring / customizing CMMS mode. System administrators / users may provide a selection of memory bank configurations to be turned on during or after boot for efficient platform booting with limited battery level thresholds.

[0011] - A power delivery system (PMIC / power management integrated circuit, Punit) having the ability to sense the remaining battery charge status and current charge rate and determine the minimum platform memory configuration block that should be turned on as quickly as possible to power on the device in CMMS mode without damaging the device.

[0012] - Initial UEFI (Unified Extensible Firmware Interface) platform initialization (PI) driver that monitors the mobile device battery during reboot.

[0013] If the battery is functioning correctly, this technology can start up all hardware and may be invoked by the main mobile OS.

[0014] <In the case of a normal battery, read EFI_MIN_MEMORY_STARTUP_POLICY and power only the elements for which the corresponding configuration bits are claimed.

[0015] - UEFI recognizes CMMS mode and exposes the availability of appropriate memory resources within the platform to the drivers. Therefore, the entire system stack, from FW (firmware) to UI (user interface), is dynamically adjusted to be in CMMS mode.

[0016] - It supports a seamless dynamic transition from CMMS mode to the main OS operating mode with full functionality and device support, provided that a reboot is not required and sufficient battery and thermal thresholds are met.

[0017] The following is an example of the settings running in the initial environment. If the battery is critical and not charged, the system will shut down. If the battery is critical and charging, the system will boot into charging mode. If it is a battery > CMMS_requirement, it boots into the MPS (Min Power Startup) mode. If it is a battery > normal_boot_requirement, it boots into the normal mode.

[0018] The CMMS technology involves a system that identifies key memory banks to support fast boot based on a discovery approach of UEFI BIOS usage patterns for various CMMS profiles.

[0019] The CMMS technology provides maximum power savings for use cases where power is more important and extra memory is not critical, extending battery life. Also, the CMMS technology enables the extension of battery life under battery degradation scenarios. Furthermore, the CMMS technology may be used to obtain energy certification. Additional advantages include overall improved TCO savings, faster boot, optimal boot, and scalable memory configuration based on system requirements (e.g., dynamic switch from CMMS to normal mode), enabling hot swap of memory with non-correctable errors while in the CMMS mode (e.g., avoiding the use of a specific bank), etc.

[0020] FIG. 1 shows a system architecture and a state machine 21 for the proposed CMMS mode. In the illustrated example, a power-on event causes the system to transition from an off state 20 to a first state 22 where UEFI determines the battery level. If the battery level is below a critical threshold, the system returns from the first state 22 to the off state 20. If the battery level is greater than the critical threshold but less than the normal boot threshold and greater than the minimum power startup threshold, the system transitions from the first state 22 to a second state 24 corresponding to the CMMS configuration (e.g., the PMIC / Punit automatically turns off power to the rails). When the battery level exceeds both the critical threshold and the normal boot threshold, the system transitions from the second state 24 to a third state 26 corresponding to the normal boot configuration. Also, the system may transition from the first state 22 to the third state 26 in response to the battery level exceeding both the critical threshold and the normal boot threshold. In one embodiment, when the battery level drops below the critical threshold, the system is caused to transition from the second state 24 or the third state 26 to the off state 20.

[0021] FIG. 2 shows a high-level boot operation flow 30 (e.g., intermediate blocks represent newly advantageous functionality). In the illustrated example, a power-on event occurs at block 32 where the BIOS takes control and starts the minimum power mode at block 34. In one embodiment, block 36 limits the use of the memory map BIOS to a few segments. Additionally, block 38 may maintain unused memory segments in the PASR (partial array self-refresh) mode, disable refresh, or turn off the power to the unused memory segments completely. Block 40 may continue the remainder of the pre-boot phase where block 42 boots to the charging OS.

[0022] Figure 3 shows the process 50 from the user interface to the UEFI configuration platform PMIC for CMMS mode. In the illustrated example, block 52 establishes the thermal and power startup configuration settings. Illustrated block 54 performs thermal and power management, which may involve exchanging thermistor values ​​with PMIC block 56 coupled to the battery and charging unit 58. Block 54 sends a thermal "credit" (e.g., burst disabled) message to Punit block 60. In one embodiment, block 60 powers one or more IP (intellectual property) blocks (e.g., functional domains) based on the boot mode and configures the IP blocks to operate at a specific frequency. Punit block 60 can send power status messages to power management block 62.

[0023] In one example, PMIC block 56 exchanges boot mode information with UEFI 64 (64a-64g). UEFI block 64a determines the battery level, which UEFI block 64b may then determine is sufficient for normal operating mode. If so, UEFI block 64c sets the boot mode to normal full power mode, and UEFI block 64d exposes the appropriate IP block configuration (e.g., based on the selected boot mode) to the OS and / or drivers. If UEFI block 64b determines that the battery level is insufficient for normal operating mode, UEFI block 64e determines that the battery level is sufficient for CMMS startup. If the battery level is sufficient for CMMS startup, UEFI block 64f sets the boot mode to CMMS, and the flow proceeds to UEFI block 64d. If UEFI block 64e determines that the battery level is insufficient for CMMS startup, UEFI block 64g may boot to charging OS.

[0024] Figure 5 shows an example of the boot flow 70 in CMMS mode versus normal mode, illustrating the transition from CMMS to normal mode. In the illustrated example, pre-EFI initialization 72 uses battery level and minimum power policy. In addition, transient system load (TSL) and runtime (RT) sequences 74 execute the final OS boot loader, final OS environment, and OS-enabled applications.

[0025] The example CMMS mode involves the following power-saving configuration:

[0026] Disable refreshing unused ranks / banks (Figure 4)

[0027] The Memory Reference Code (MRC, e.g., the memory initialization code) may disable refresh to unused ranks (e.g., train unused ranks, but keep refresh disabled). Since unused ranks are not used for booting, refresh may only be enabled when they are handed over to the OS. This functionality can also be achieved by modifying the memory controller (MC). For example, the MC monitors traffic to each bank / rank. According to JEDEC (Joint Electron Device Engineering Council), a bank is a block of memory within a DRAM (dynamic random access memory) chip, and a rank is a block of memory on a module (e.g., what was previously called a double-sided or double-bank module is now called a double-rank module). If a bank / rank has not encountered a single write command, it has no valid content, and therefore the MC may intelligently conserve power by not issuing a refresh to such a bank / rank.

[0028] Modifications to the scheduler logic in the memory controller (MC) may maintain a track of writes to banks and / or ranks, and enable refresh and self-refresh only when a bank or rank encounters a write. Existing solutions offer software (SW) control to enable / disable refresh at the rank level. The proposed modification would allow the MC to decide to control refresh at the bank granularity, providing greater power savings (for example, the system implementation could employ two different memory mapping schemes: one for low battery / high power saving scenarios and another for normal boot / run scenarios).

[0029] A power-saving memory mapping scheme may choose to map contiguous blocks of DRAM space from only a small number of banks in a rank to the system address space. In this case, the memory controller schedules "writes" (write operations) only to the small number of banks mapped to the system space. All other banks are idle, and no writes would occur to those banks. The modified memory controller scheduler logic disables refreshing banks that have not been written to. Therefore, more power is saved than with existing solutions when the rank is actively used. In other words, the greater power savings come from the subset of banks in the rank that are not refreshed.

[0030] A power control electronic switch may be added to the power supply path to individual ranks within the DIMM or platform. This switch allows a switch (e.g., BIOS) to completely disable power to unused ranks within the DIMM (dual inline memory module) or the entire DIMM (if supported by the platform implementation).

[0031] Completely turn off the power to the rank or DIMM.

[0032] In a memory-down configuration, the DRAM device (and therefore the ranks) may be powered off (e.g., using platform control). For DIMMs, modifications may be made to the DIMM specification to provide independent power control to individual ranks. Platform modifications may be made to independently control power to individual DIMMs and to perform DIMM-level power-offs. A downside to such an approach may be that a JEDEC initialization sequence may be required to initialize the DRAM upon power-on (e.g., some minimal training may be performed based on the DIMM type). Thus, such an approach may involve more latency. One potential option to mitigate high latency is to cache the initialization vectors and reuse the cached vectors across configuration modes / profiles.

[0033] To share platform and policy information, the following policy objects may be defined:

[0034]

number

[0035]

number

[0036] In one embodiment, the full OS exposes the above configuration via a friendly UI (Figure 1) that ultimately executes a UEFI->SetVariable() call, and during a reduced-performance reboot, the CMMS driver uses this policy to determine which hardware to power on and how to parameterize the user interface.

[0037] More specifically, Figure 4 shows method 80 in which power-on and BIOS startup occur in block 82. In one embodiment, block 84 checks the battery status, where block 86 may determine whether the battery status is at a critical level. If the battery status is not at a critical level, illustrated block 88 proceeds to a normal boot in full performance configuration. Otherwise, block 90 may determine whether there are multiple ranks or multiple DIMMs. If so, block 92 enables selective DIMM / rank enablement based on a configured policy (e.g., only one DIMM per rank). Block 92 may also disable power to other ranks / DIMMs. Illustrated block 94 uses the BIOS to perform DDR training and / or memory initialization. If block 90 determines that there are neither multiple ranks nor multiple DIMMs, method 80 can bypass block 92 and proceed directly to block 94.

[0038] Block 96 may provide a way to map memory contiguously to as few banks as possible. In one embodiment, block 98 enables normal memory operation and refreshes the memory controller. When the BIOS is executed, block 100 hands control over the charging OS and battery-critical software. In addition, the memory controller monitors writes to banks in block 102 and determines in block 104 whether a write has occurred with respect to the monitored bank. If so, in block 106, the memory controller enables a refresh to the bank that encountered the data write. The illustrated method 80 then returns to block 102. If it is determined in block 104 that no write has occurred with respect to the monitored bank, method 80 may bypass block 106 and proceed directly to block 102. Blocks 92, 96, 102, 104, and 106, which are not present in conventional systems, provide significant performance advantages.

[0039] Figure 6 shows a method 110 for operating a BIOS in an improved computing system. Method 110 may be implemented in one or more modules as a set of logic instructions stored in mechanical or computer-readable storage media such as random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), firmware, flash memory, configurable logic such as programmable logic arrays (PLAs), field-programmable gate arrays (FPGAs), composite programmable logic devices (CPLDs), fixed-function logic hardware using circuit technologies such as application-specific integrated circuits (ASICs), complementary metal-oxide-semiconductor (CMOS), transistor-transistor logic (TTL) technology, or any combination thereof.

[0040] For example, computer program code for performing the operations shown in this method may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as JAVA®, SMALLTALK®, and C++, and conventional procedural programming languages ​​such as the C programming language and similar programming languages. Additionally, logical instructions may include assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, state setting data, integrated circuit configuration data, and state information that personalizes other structural components specific to electronic circuits and / or hardware (e.g., host processor, central processing unit / CPU, microcontroller, etc.).

[0041] The illustrated processing block 112 provides enabling a first rankset in the memory module during the boot sequence, based on the battery status and user interface. In one example, block 114 disables a second rankset in a memory module during the boot sequence based on the battery state and the user interface. In one embodiment, the battery state indicates that the battery charge level is below a normal threshold and above a reduced (e.g., minimum) memory startup threshold. In one example, the user interface includes a configuration object structure that defines one or more of the following: memory properties, memory configuration, performance configuration, UI element configuration, storage configuration, or hot-swap configuration. The illustrated processing block 116 also generates a map between the system address space and the first bank set of the first rankset, and block 118 excludes the second bank set of the first rankset from the map. In one embodiment, the map is associated with a low battery mapping scheme.

[0042] Figure 7 shows a method 120 for operating a memory controller in an improved computing system. Method 120 may be implemented in one or more modules as a set of logic instructions stored in mechanical or computer-readable storage media such as RAM, ROM, PROM, firmware, flash memory, configurable logic such as PLA, FPGA, CPLD, fixed-function logic hardware using circuit technology such as ASIC, CMOS, TTL technology, or any combination thereof. Illustrated block 122 provides monitoring of write activity with respect to a first bank set, and block 124 disables refreshing in one or more banks of the first bank set based on the write activity.

[0043] Figure 8 shows method 130 for transitioning to normal mode. Method 130 may be implemented in one or more modules as a set of logic instructions stored in mechanical or computer-readable storage media such as RAM, ROM, PROM, firmware, flash memory, configurable logic such as PLA, FPGA, CPLD, fixed-function logic hardware using circuit technology such as ASIC, CMOS, TTL technology, or any combination thereof.

[0044] The illustrated processing block 132 detects changes in battery state. Block 132 may also provide the collection of telemetry (e.g., usage) data during CMMS mode, where the telemetry data is associated with a first rankset and a second rankset. Such an approach may further extend scalability by supporting the development of future extensions. In one embodiment, block 134 enables a second rankset in response to a change, and block 136 incorporates a second bankset into the map in response to a change. In an embodiment, this change indicates that the battery charge state is greater than a normal threshold.

[0045] Figure 9 shows a computing system 150 including an executable program instruction 170, which, when executed by one or more of the host processor 152, the graphics processor 160, or the input / output module (IO) 158, causes the computing system 150 to perform one or more of the methods 110 (Figure 6), 120 (Figure 7), and / or method 130 (Figure 8) already described. In one embodiment, the instruction 170 is retrieved from a memory module 156 (e.g., a DIMM) and / or mass storage 168. Additionally, the graphics processor 160, the host processor 152, and / or the IO module 158 are integrated into a system-on-a-chip (SoC) 162, which is also coupled to a display 164 and / or a network controller 166 (wireless, wired). The illustrated system 150 also includes a battery 157.

[0046] Figure 10 shows a semiconductor package device 172. The illustrated device 172 includes one or more substrates 174 (e.g., silicon, sapphire, gallium arsenide) and logic 176 coupled to the substrates 174 (e.g., transistor arrays and other integrated circuit / IC components). The logic 176 may be implemented, at least partially, as configurable logic or fixed-function logic hardware. In one example, the logic 176 implements one or more embodiments of the methods 110 (Figure 6), 120 (Figure 7), and / or 130 (Figure 8) already described.

[0047] In one example, logic 176 includes a transistor channel region located (e.g., embedded) within the substrate 174. Therefore, the interface between logic 176 and the substrate 174 does not have to be a step junction. Logic 176 may also be considered to include an epitaxial layer grown on the initial wafer of the substrate 174.

[0048] Figure 11 illustrates a processor core 200 according to one embodiment. The processor core 200 may be the core of any type of processor, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, or another device for executing code. Although only one processor core 200 is illustrated in Figure 11, alternatively, the processor element may include multiple processor cores 200 as illustrated in Figure 11. The processor core 200 may be a single-threaded core, and in at least one embodiment, the processor core 200 may be multi-threaded in that it may include multiple hardware thread contexts (or “logical processors”) per core.

[0049] Figure 11 also illustrates a memory 270 coupled to the processor core 200. The memory 270 may be any of the broad types of memory (including various layers of the memory hierarchy) that are well known to those skilled in the art or otherwise available. The memory 270 may contain one or more code 213 instructions executed by the processor core 200, and the code 213 may implement one or more embodiments of the methods 110 (Figure 6), 120 (Figure 7), and / or 130 (Figure 8) already described. The processor core 200 follows the instruction sequence of the program indicated by the code 213. Each instruction enters the front-end portion 210 and may be processed by one or more decoders 220. The decoders 220 may, as their output, generate microoperations such as fixed-width microoperations of a predetermined format, or other instructions, microinstructions, or control signals that reflect the original code instructions. Furthermore, the illustrated front-end portion 210 includes register renaming logic 225 and scheduling logic 230, which generally allocate resources and queue operations corresponding to translation instructions for execution.

[0050] The processor core 200 is shown to include execution logic 250 having a set of execution units 255-1 to 255-N. Some embodiments may include a number of execution units dedicated to a particular function or set of functions. Other embodiments may include only one execution unit or one execution unit that can perform a particular function. The illustrated execution logic 250 performs the operations specified by code instructions.

[0051] After the completion of the operation specified by the code instruction, the backend logic 260 retires the instruction of code 213. In one embodiment, the processor core 200 allows unsequential execution but requires sequential instruction retirement. The retirement logic 265 can take various forms known to those skilled in the art (e.g., a reorder buffer). In this way, during the execution of code 213, the processor core 200 is converted with respect to at least the output generated by the decoder, hardware registers and tables utilized by the register renaming logic 225, and any registers (not shown) modified by the execution logic 250.

[0052] Although not shown in Figure 11, the processing element may include other elements on the chip having the processor core 200. For example, the processing element may include memory control logic together with the processor core 200. The processing element may include I / O control logic, and / or I / O control logic integrated with the memory control logic. The processing element may also include one or more caches.

[0053] Referring now to Figure 12, a block diagram of an embodiment of computing system 1000 according to one embodiment is shown. Figure 12 shows a multiprocessor system 1000 including a first processing element 1070 and a second processing element 1080. Although two processing elements 1070 and 1080 are shown, it should be understood that an embodiment of system 1000 may include only one such processing element.

[0054] System 1000 is illustrated as a point-to-point interconnection system, where the first processing element 1070 and the second processing element 1080 are connected via a point-to-point interconnection 1050. It should be understood that some or all of the interconnections shown in Figure 12 may be implemented as multidrop buses rather than point-to-point interconnections.

[0055] As shown in Figure 12, each of the processing elements 1070 and 1080 may be a multicore processor including first and second processor cores (i.e., processor cores 1074a and 1074b, and processor cores 1084a and 1084b). Such cores 1074a, 1074b, 1084a, and 1084b may be configured to execute instruction code in a manner similar to that described above in relation to Figure 11.

[0056] Each processing element 1070, 1080 may include at least one shared cache 1896a, 1896b. The shared caches 1896a, 1896b may store data (e.g., instructions) used by one or more components of the processor, such as cores 1074a, 1074b, and 1084a, 1084b, respectively. For example, the shared caches 1896a, 1896b may locally cache data stored in memory 1032, 1034 for faster access by components of the processor. In one or more embodiments, the shared caches 1896a, 1896b may include one or more intermediate level caches, last level caches (LLCs), and / or combinations thereof, such as level 2 (L2), level 3 (L3), level 4 (L4), or other level caches.

[0057] Although only two processing elements 1070 and 1080 are shown, it should be understood that the scope of this embodiment is not limited thereto. In other embodiments, one or more additional processing elements may be present within a given processor. Alternatively, one or more of the processing elements 1070 and 1080 may be elements other than processors, such as accelerators or field-programmable gate arrays. For example, the additional processing elements may include an additional processor identical to the first processor 1070, an additional processor that is non-uniform or asymmetric with respect to the first processor 1070, an accelerator (e.g., a graphics accelerator or a digital signal processing (DSP) unit), a field-programmable gate array, or any other processing element. There may be various differences between the processing elements 1070 and 1080 in terms of a spectrum of metrics including architecture, microarchitecture, thermal, power consumption characteristics, etc. These differences may effectively manifest as asymmetry and heterogeneity between the processing elements 1070 and 1080. In at least one embodiment, various processing elements 1070, 1080 may be located within the same die package.

[0058] The first processing element 1070 may further include a memory controller logic (MC) 1072 and point-to-point (PP) interfaces 1076 and 1078. Similarly, the second processing element 1080 may include an MC 1082 and PP interfaces 1086 and 1088. As shown in Figure 12, the MCs 1072 and 1082 connect the processors to their respective memories, namely memory 1032 and memory 1034, which may be portions of main memory locally attached to their respective processors. Although the MCs 1072 and 1082 are shown integrated into the processing elements 1070 and 1080, in alternative embodiments the MC logic may be discrete logic outside the processing elements 1070 and 1080 rather than being integrated within them.

[0059] The first processing element 1070 and the second processing element 1080 may be coupled to the I / O subsystem 1090 via PP interconnects 1076 and 1086, respectively. As shown in Figure 12, the I / O subsystem 1090 includes PP interfaces 1094 and 1098. Furthermore, the I / O subsystem 1090 includes an interface 1092 for coupling the I / O subsystem 1090 with the high-performance graphics engine 1038. In one embodiment, a bus 1049 may be used to couple the graphics engine 1038 with the I / O subsystem 1090. Alternatively, a point-to-point interconnect may be used to couple these components.

[0060] Next, the I / O subsystem 1090 may be coupled to the first bus 1016 via interface 1096. In one embodiment, the first bus 1016 may be a Peripheral Component Interconnection (PCI) bus, a PCI Express bus, or another third-generation I / O interconnection bus, but the scope of the embodiment is not limited thereto.

[0061] As shown in Figure 12, various I / O devices 1014 (e.g., biometric scanners, speakers, cameras, sensors) may be coupled to the first bus 1016 together with a bus bridge 1018 that can connect the first bus 1016 to the second bus 1020. In one embodiment, the second bus 1020 may be a low-pin count (LPC) bus. In one embodiment, various devices, including a keyboard / mouse 1012, a communication device 1026, and a data storage unit 1019 such as a disk drive or other mass storage device which may include code 1030, may be coupled to the second bus 1020. The illustrated code 1030 may implement one or more embodiments of the methods 110 (Figure 6), 120 (Figure 7), and / or method 130 (Figure 8) that have already been described. Furthermore, the audio I / O 1024 may be coupled to a second bus 1020, and the battery 1010 may supply power to the computing system 1000.

[0062] It should be noted that other embodiments are contemplated. For example, instead of the point-to-point architecture of Figure 12, the system may implement a multidrop bus or other such communication topology. Also, the elements of Figure 12 may be divided using more or fewer integrated chips than those shown in Figure 12.

[0063] Additional notes and examples:

[0064] Example 1 is a computing system comprising a network controller, a processor coupled to the network controller, and a memory module coupled to the processor, wherein the memory module includes a set of instructions, and when the set of instructions is executed by the processor, the processor causes the processor to enable a first rank set in the memory module during the boot sequence based on the battery state and user interface, to disable a second rank set in the memory module during the boot sequence based on the battery state and user interface, to generate a map between the system address space and a first bank set of the first rank set, and to exclude a second bank set of the first rank set from the map.

[0065] Example 2 further includes a memory controller, and the instruction, when executed by the memory controller, causes the memory controller to monitor write activity with respect to a first bank set and, based on the write activity, disable refresh in one or more banks of the first bank set, the computing system described in Example 1.

[0066] Example 3 includes the computing system described in Example 1, wherein the user interface includes a configuration object structure that defines one or more of the following: memory properties, memory configuration, performance configuration, user interface element configuration, storage configuration, or hot-swap configuration.

[0067] Example 4 includes the computing system described in Example 1, where the battery state indicates that the battery charge level is below the normal threshold and above the reduced memory startup threshold, and the map is associated with the low battery mapping scheme.

[0068] Embodiment 5 includes a computing system according to any one of Examples 1 to 4, wherein the instruction, when executed by the processor, causes the processor to collect telemetry data during a configurable minimum memory startup mode, the telemetry data being associated with a first rankset and a second rankset, to detect changes in battery state, to enable the second rankset in response to the changes, and to incorporate the second bankset into the map in response to the changes.

[0069] Example 6 includes the computing system described in Example 5, where the change indicates that the battery charge level is greater than a normal threshold.

[0070] Embodiment 7 is a semiconductor device comprising one or more substrates and logic coupled to one or more substrates, wherein the logic is at least partially implemented in one or more configurable logics or fixed-function hardware logics, and the logic coupled to one or more substrates includes a device that, during a boot sequence, enables a first rank set in a memory module based on the battery state and user interface, disables a second rank set in a memory module based on the battery state and user interface, generates a map between the system address space and a first bank set of the first rank set, and excludes a second bank set of the first rank set from the map.

[0071] Example 8 includes the apparatus described in Example 7, wherein logic coupled to one or more boards monitors write activity with respect to a first bank set and, based on the write activity, disables refresh in one or more banks of the first bank set.

[0072] Example 9 includes the device described in Example 7, wherein the user interface includes a configuration object structure that defines one or more of the following: memory properties, memory configuration, performance configuration, user interface element configuration, storage configuration, or hot-swap configuration.

[0073] Example 10 shows that the battery state indicates that the battery charge level is below the normal threshold and above the reduced memory startup threshold, and the map includes the device described in Example 7, associated with the low battery mapping scheme.

[0074] Example 11 includes the apparatus described in any one of Examples 7 to 10, wherein logic coupled to one or more boards collects telemetry data during a configurable minimum memory startup mode, the telemetry data being associated with a first rankset and a second rankset, and the apparatus also includes the apparatus described in any one of Examples 7 to 10, which includes collecting, detecting changes in battery state, enabling the second rankset in response to the changes, and incorporating the second bankset into the map in response to the changes.

[0075] Example 12 includes the apparatus described in Example 11, wherein the change indicates that the battery charge level is greater than the normal threshold.

[0076] Example 13 includes the apparatus described in any one of Examples 7 to 12, wherein the logic coupled to one or more substrates includes transistor channel regions located within one or more substrates.

[0077] Example 14 includes at least one computer-readable storage medium containing a set of instructions, the set of instructions, when executed by a computer system, causes the computer system to: enable a first rank set in a memory module during a boot sequence based on battery status and user interface; disable a second rank set in a memory module during a boot sequence based on battery status and user interface; generate a map between the system address space and a first bank set of the first rank set; and exclude a second bank set of the first rank set from the map.

[0078] Example 15 includes at least one computer-readable storage medium as described in Example 14, wherein the instruction, when executed, causes the computer system to further monitor write activity with respect to a first bank set and, based on the write activity, disable refresh in one or more banks of the first bank set.

[0079] Example 16 includes at least one computer-readable storage medium as described in Example 14, wherein the user interface includes a configuration object structure that defines one or more of the following: memory properties, memory configuration, performance configuration, user interface element configuration, storage configuration, or hot-swap configuration.

[0080] Example 17 shows that the battery state indicates that the battery charge level is below a normal threshold and above a reduced memory startup threshold, and the map includes at least one computer-readable storage medium as described in Example 14, associated with a low battery mapping scheme.

[0081] Example 18 includes at least one computer-readable storage medium as described in any one of Examples 14-17, wherein the instruction, when executed, collects telemetry data during a minimum memory startup mode configurable by the computer system, the telemetry data being associated with a first rankset and a second rankset, further including detecting a change in battery state, enabling the second rankset in response to the change, and incorporating the second bankset into the map in response to the change.

[0082] Example 19 includes at least one computer-readable storage medium as described in Example 18, wherein the change indicates that the battery charge level is greater than a normal threshold.

[0083] Example 20 includes a method that, during the boot sequence, enables a first rankset in a memory module based on the battery state and user interface; during the boot sequence, disables a second rankset in a memory module based on the battery state and user interface; generates a map between the system address space and a first bank set of the first rankset; and excludes a second bank set of the first rankset from the map.

[0084] Example 21 includes the method of Example 20, further comprising monitoring write activity on a first bank set and, based on the write activity, disabling refresh on one or more banks in the first bank set.

[0085] Example 22 includes the method described in Example 20, wherein the user interface includes a configuration object structure that defines one or more of the following: memory properties, memory configuration, performance configuration, user interface element configuration, storage configuration, or hot-swap configuration.

[0086] Example 23 shows that the battery state is such that the battery charge level is below the normal threshold and above the reduced memory startup threshold, and the map is associated with the low battery mapping scheme, including the method described in Example 20.

[0087] Example 24 is a method of any one of Examples 20-23, which further includes collecting telemetry data during a configurable minimum memory startup mode, the telemetry data being associated with a first rankset and a second rankset, detecting changes in battery state, enabling the second rankset in response to the changes, and incorporating the second bankset into the map in response to the changes.

[0088] Example 25 includes the method described in Example 24, which indicates that the battery charge level is greater than a normal threshold.

[0089] Example 26 includes means for carrying out any one of the methods in Examples 20-25.

[0090] The embodiments are applicable to use in all types of semiconductor integrated circuit (IC) chips. Examples of these IC chips include, but are not limited to, processors, controllers, chipset components, programmable logic arrays (PLAs), memory chips, network chips, system-on-a-chip (SoCs), SSD / NAND controller ASICs, etc. Additionally, in some drawings, signal conductor lines are represented as lines. Some may differ in that they have numerical labels to indicate more component signal paths, to indicate a large number of component signal paths, and / or have arrows at one or more ends to indicate the primary information flow direction. However, this should not be interpreted in an restrictive manner. Rather, such additional details may be used in relation to one or more exemplary embodiments to facilitate a more easily understandable circuit. Any represented signal line, whether or not it has additional information, may actually contain one or more signals that can travel in multiple directions, and may be implemented in any suitable type of signal scheme, e.g., digital or analog lines implemented in differential pairs, optical fibers, and / or single-ended lines.

[0091] Embodiments are not limited to the same, but illustrative sizes / models / values / ranges may be given. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that smaller size devices will be manufactured. Additionally, well-known power / ground connections to IC chips and other components may or may not be shown in the figures for the sake of simplicity of illustration and description and to avoid obscuring specific aspects of the embodiments. Furthermore, arrangements may be shown in block diagram form to avoid obscuring embodiments and considering the fact that details relating to the implementation of such block diagram arrangements depend heavily on the computing system in which the embodiments are implemented; i.e., details of such should be within the scope of those skilled in the art. Where specific details (e.g., circuits) are described to illustrate an exemplary embodiment, it should be obvious to those skilled in the art that the embodiment can be implemented without these specific details or with modifications thereof. Embodiments for carrying out the invention are therefore intended to be illustrative, not limiting.

[0092] The term “connection” may be used herein to refer to any type of direct or indirect relationship between the components in question, and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical, or other connections. Furthermore, terms such as “first,” “second,” etc., may be used solely for the purpose of facilitating discussion and, unless otherwise indicated, do not have any special temporal or chronological meaning.

[0093] As used in this application and claims, a list of items joined by the term “one or more” may mean any combination of the enumerated terms. For example, the term “one or more of A, B, or C” may mean A, B, C, A and B, A and C, B and C, or A, B and C.

[0094] Those skilled in the art will understand from the foregoing description that the broad technology of the embodiments can be implemented in various forms. Therefore, although the embodiments have been described in relation to specific examples, the true scope of the embodiments should not be so limited, as other modifications will become apparent to those skilled in the art through examination of the drawings, specification, and the scope of the claims below.

Claims

1. A computing system, Network controller and A processor coupled to the aforementioned network controller, The memory module is coupled to the processor, and the memory module includes a set of instructions, and when the set of instructions is executed by the processor, the processor is provided with During the boot sequence, a first rankset in the memory module is enabled based on the battery status and user interface, During the boot sequence, the second rankset in the memory module is disabled based on the battery state and the user interface, To generate a map between the system address space and the first bank set of the first rank set, A computing system that removes the second bank set from the first rank set from the map.

2. The system further includes a memory controller, and when the instruction is executed by the memory controller, the memory controller is instructed to: Monitoring write activity related to the first bank set, The computing system according to claim 1, which causes the system to disable refreshing in one or more banks of the first bank set based on the write activity.

3. The computing system according to claim 1, wherein the user interface includes a configuration object structure that defines one or more of the following: memory properties, memory configuration, performance configuration, user interface element configuration, storage configuration, or hot-swap configuration.

4. The computing system according to claim 1, wherein the battery state indicates that the battery charge level is below a normal threshold and above a reduced memory startup threshold, and the map is associated with a low battery mapping scheme.

5. When the aforementioned instruction is executed by the processor, the processor will be instructed to: The collection of telemetry data during a configurable minimum memory startup mode, wherein the telemetry data is associated with the first rank set and the second rank set. To detect the change in the aforementioned battery state, In response to the aforementioned change, the second rank set is enabled, The computing system according to any one of claims 1 to 4, further comprising incorporating the second bank set into the map in response to the aforementioned change.

6. The computing system according to claim 5, wherein the aforementioned change indicates that the battery charge level is greater than a normal threshold.

7. A semiconductor device, One or more circuit boards, The logic includes, which is coupled to one or more boards, and the logic is at least partially implemented in one or more of the configurable logic or fixed-function hardware logic, and the logic coupled to one or more boards is, During the boot sequence, a first rankset in the memory module is enabled based on the battery status and user interface, During the boot sequence, the second rankset in the memory module is disabled based on the battery state and the user interface, To generate a map between the system address space and the first bank set of the first rank set, A device that removes the second bank set from the first rank set from the map.

8. The logic coupled to one or more substrates is Monitoring write activity related to the first bank set, The apparatus according to claim 7, which disables refreshing in one or more banks of the first bank set based on the write activity.

9. The apparatus according to claim 7, wherein the user interface includes a configuration object structure that defines one or more of the following: memory properties, memory configuration, performance configuration, user interface element configuration, storage configuration, or hot-swap configuration.

10. The apparatus according to claim 7, wherein the battery state indicates that the battery charge level is below a normal threshold and greater than a reduced memory startup threshold, and the map is associated with a low battery mapping scheme.

11. The logic coupled to one or more substrates is The collection of telemetry data during a configurable minimum memory startup mode, wherein the telemetry data is associated with the first rank set and the second rank set. To detect the change in the aforementioned battery state, In response to the aforementioned change, the second rank set is enabled, The apparatus according to any one of claims 7 to 10, which performs the following: in response to the aforementioned change, incorporate the second bank set into the map.

12. The apparatus according to claim 11, wherein the aforementioned change indicates that the battery charge level is greater than a normal threshold.

13. The apparatus according to any one of claims 7 to 10, wherein the logic coupled to the one or more substrates includes a transistor channel region positioned within the one or more substrates.

14. A computer-readable storage medium containing a set of instructions, wherein the set of instructions, when executed by a computer system, is stored in the computer system. During the boot sequence, a first rankset in the memory module is enabled based on the battery status and user interface, During the boot sequence, the second rankset in the memory module is disabled based on the battery state and the user interface, To generate a map between the system address space and the first bank set of the first rank set, A computer-readable storage medium that performs the following: removing the second bank set from the first rank set from the map.

15. When the instruction is executed, the computer system will: Monitoring write activity related to the first bank set, The at least one computer-readable storage medium according to claim 14, further comprising: disabling refresh in one or more banks of the first bank set based on the write activity.

16. The user interface includes a configuration object structure that defines one or more of the following: memory properties, memory configuration, performance configuration, user interface element configuration, storage configuration, or hot-swap configuration, for at least one computer-readable storage medium according to claim 14.

17. The battery state indicates that the battery charge level is below a normal threshold and greater than a reduced memory startup threshold, and the map is associated with a low battery mapping scheme, the at least one computer-readable storage medium according to claim 14.

18. When the instruction is executed, the computer system will: The collection of telemetry data during a configurable minimum memory startup mode, wherein the telemetry data is associated with the first rank set and the second rank set. To detect the change in the aforementioned battery state, In response to the aforementioned change, the second rank set is enabled, A computer-readable storage medium according to any one of claims 14 to 17, further comprising incorporating the second bank set into the map in response to the aforementioned change.

19. The change indicates that the battery charge level is greater than a normal threshold, the at least one computer-readable storage medium according to claim 18.

20. A method performed by a processor, During the boot sequence, a first rankset in the memory module is enabled based on the battery status and user interface, During the boot sequence, the second rankset in the memory module is disabled based on the battery state and the user interface, To generate a map between the system address space and the first bank set of the first rank set, A method comprising excluding a second bank set from the first rank set from the map.

21. Monitoring write activity related to the first bank set, The method according to claim 20, further comprising disabling refreshing in one or more banks of the first bank set based on the write activity.

22. The method according to claim 20, wherein the user interface includes a configuration object structure that defines one or more of the following: memory properties, memory configuration, performance configuration, user interface element configuration, storage configuration, or hot-swap configuration.

23. The method according to claim 20, wherein the battery state indicates that the battery charge level is below a normal threshold and greater than a reduced memory startup threshold, and the map is associated with a low battery mapping scheme.

24. The collection of telemetry data during a configurable minimum memory startup mode, wherein the telemetry data is associated with the first rank set and the second rank set. To detect the change in the aforementioned battery state, In response to the aforementioned change, the second rank set is enabled, The method according to any one of claims 20 to 23, further comprising incorporating the second bank set into the map in response to the aforementioned change.

25. The method according to claim 24, wherein the change indicates that the battery charge level is greater than a normal threshold.

Images