Control circuits, semiconductor devices

Abstract

To provide a control circuit which can be used both with DC input and AC input without controlling the ON / OFF of a X-CAP discharge function.SOLUTION: A control circuit comprises: an activation circuit 21 that is connected to a power supply input, and charges a VCC terminal voltage upon activation and discharges a phase capacitor of the power supply input upon stop of driving; an activation control circuit 23 that detects the VCC terminal voltage; an input detection circuit 22 that detects a VSEN terminal voltage; and an input determination circuit 24 that charges a CD terminal voltage, discharges the CD terminal voltage in response to detection of an up edge of the VSEN terminal voltage, determines an AC input and makes setting to an AC input mode when an up edge is detected after charging of the CD terminal voltage is started, and determines that the power supply input is a DC input and makes setting to a DC input mode when the CD terminal voltage has reached a DC determination voltage VCDdc with no up edge of the VSEN terminal voltage being detected.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a control circuit for a switching power supply.

Background Art

[0002] There has been proposed a power supply IC that selects between an AC line connection and a DC line connection and turns off the X-CAP discharge function via the HV terminal when the HV terminal is connected to the rectifying and smoothing side (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Conventional power supply ICs use the X-CAP discharge function to detect the presence or absence of voltage fluctuations in the HV terminal voltage and set the on / off state of the X-CAP discharge function. Therefore, it is necessary to use the X-CAP discharge function every time the power is turned on to check the presence or absence of fluctuations in the HV terminal voltage during a half cycle of the commercial frequency.

[0005] The present invention has been made in view of such problems, and an object thereof is to provide a control circuit that can be used for both DC input and AC input without controlling the on / off of the X-CAP discharge function.

Means for Solving the Problems

[0006] The control circuit according to the present invention is configured as follows in order to achieve the above object. The control circuit according to the present invention is a control circuit for a switching power supply, comprising a startup circuit connected to the power input, which charges a control voltage during startup and discharges the interphase capacitor of the power input when the switching power supply is stopped, The control voltage The system comprises a startup control circuit that detects the input voltage of the power supply input, an input detection circuit that charges the CD terminal voltage to which a capacitor is connected, and discharges the CD terminal voltage by detecting fluctuations in the input voltage that are on or around the AC detection voltage, and after charging to the CD terminal voltage has started, if a fluctuation that is on or around the detection voltage is detected, the system determines that the power supply input is an AC input and sets it to AC input mode, and if no fluctuations that are on or around the AC detection voltage are detected in the input voltage and the CD terminal voltage reaches a preset DC determination voltage, the system determines that the power supply input is a DC input and sets it to DC input mode. In the DC input mode, the clamping function clamps the CD terminal voltage to a predetermined clamping voltage, and the switching power supply is stopped when the input voltage drops to the DC detection voltage. In the AC input mode, the clamping function is released, and the switching power supply is stopped when the CD terminal voltage reaches a preset drive stop voltage that is higher than the clamping voltage. It is characterized by the following: [Effects of the Invention]

[0007] The control circuit of the present invention can determine whether the input is AC or DC without using the X-CAP discharge function, thus providing the advantage of being usable with both DC and AC inputs without controlling the on / off state of the X-CAP discharge function. [Brief explanation of the drawing]

[0008] [Figure 1] This figure shows the configuration of a current-resonant power supply using the control circuit according to the present invention. [Figure 2] This diagram shows the configuration of the control circuit shown in Figure 1. [Figure 3] This figure shows the configuration of the startup circuit shown in Figure 2. [Figure 4] This figure shows the configuration of the input detection circuit shown in Figure 2. [Figure 5] Figure 2 shows the configuration of the startup control circuit. [Figure 6] This figure shows the configuration of the input detection circuit shown in Figure 2. [Figure 7] This figure shows the configuration of the input detection circuit shown in Figure 2. [Figure 8]Figure 1 is a flowchart showing the output determination operation by the control circuit. [Figure 9] Figure 1(a) shows the waveform when AC input is applied. [Figure 10] Figure 1(b) shows the waveform when a DC input is applied. [Modes for carrying out the invention]

[0009] Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

[0010] The control circuit 10 in this embodiment is a semiconductor device such as an IC formed by encapsulating it in a resin package, and is a control circuit that drives the LLC type current resonant power supplies 1a and 1b shown in Figures 1(a) and 1(b). The control circuit 10 has a function to detect whether the input is AC or DC before the start of oscillation and to automatically switch between AC input operation mode and DC input operation mode.

[0011] The current resonant power supply 1a shown in Figure 1(a) illustrates an example of use in the AC input operating mode of the control circuit 10. The current resonant power supply 1a comprises an X capacitor Cx connected between the phases of the AC input power line, a full-wave rectifier circuit 2 that full-wave rectifies the AC input, a smoothing capacitor C1 connected across the output of the full-wave rectifier circuit 2, and a PFC circuit 3 that improves the power factor of the DC voltage rectified by the full-wave rectifier circuit 2 and smoothed by the smoothing capacitor C1. The control circuit 10 uses the output of the PFC circuit 3 as the input voltage Vin to drive a high-side switching element QH and a low-side switching element QL connected in series between the input voltage Vin and ground.

[0012] Figure 1(b) shows an example of the current resonant power supply 1b used in the DC input operating mode of the control circuit 10. The current resonant power supply 1b includes an input smoothing capacitor Cin connected between the phases of the DC input power supply line. The control circuit 10 drives a high-side switching element QH and a low-side switching element QL, which are connected in series between the DC input voltage Vin and ground.

[0013] The control circuit 10 includes a VS (high-side ground) terminal, a VGH (high-side output) terminal, a GND (ground) terminal, and a VGL (low-side output) terminal. The switching element QH is connected between the input voltage Vin and the VS terminal and is driven by a drive signal output from the VGH terminal. The switching element QL is connected between the VS terminal and the GND terminal and is driven by a drive signal output from the VGL terminal. In the control circuit 10, the VB terminal is a terminal for inputting a high-side drive power supply, and the REG terminal is a terminal for outputting a power supply for the drive circuit.

[0014] Referring to FIG. 2, the control circuit 10 includes a floating high-side drive circuit 11 that drives the switching element QH and a low-side drive circuit 12 that drives the switching element QL. The control circuit 10 includes a main control circuit 13 that controls the high-side drive circuit 11 and the low-side drive circuit 12, and an oscillation frequency control circuit 14 that generates an oscillation frequency using a feedback signal input from a feedback signal input terminal FB. The main control circuit 13 controls the high-side drive circuit 11 and the low-side drive circuit 12 at the oscillation frequency generated by the oscillation frequency control circuit 14 and performs negative feedback control on the output voltage.

[0015] The control circuit 10 includes an overcurrent detection circuit 15 that detects overcurrent. A current detection signal detected by a detection resistor R OCP is input to the RC (current detection signal input) terminal, and the overcurrent detection circuit 15 detects overcurrent by comparing the current detection signal with an overcurrent voltage. When the overcurrent detection circuit 15 detects overcurrent, the main control circuit 13 limits the output power.

[0016] The control circuit 10 includes an overload detection circuit 16 that detects an overload. When an overcurrent is detected by the overcurrent detection circuit 15, the overload detection circuit 16 charges a capacitor Ccl connected to the CL (capacitor connection for overload protection detection) terminal with a predetermined current, and compares the CL terminal voltage with an overload voltage to detect an overload. When an overcurrent is detected by the overload detection circuit 16, the main control circuit 13 stops the operation.

[0017] The control circuit 10 includes a soft start circuit 17 that gradually raises the output voltage over a predetermined time at the start of operation. The soft start circuit 17 charges a capacitor Ccss connected to the CSS (capacitor connection for soft start) terminal with a predetermined current at the start of operation, and the oscillation frequency control circuit 14 gradually lowers the oscillation frequency according to the CSS terminal voltage.

[0018] The control circuit 10 includes a thermal shutdown (TSD) circuit 25 that stops the operation when detecting overheating of the internal temperature. The thermal shutdown (TSD) circuit 25 detects the internal temperature by comparing, for example, the resistance value of a thermistor or the change in the forward voltage of a diode with a reference voltage. When the change in the aforementioned element reaches a preset heating protection operation temperature, the thermal shutdown (TSD) circuit 25 outputs a heating protection signal TSD to stop the power supply operation and prevent damage due to overheating.

[0019] The control circuit 10 includes a standby control circuit 18 that controls the burst oscillation operation during light load. The control circuit 10 includes an SB (capacitor for standby control) terminal to which a capacitor Csb is connected and a MODE (standby switching signal input) terminal to which a capacitor Cmode is connected. The standby control circuit 18 executes a burst oscillation operation with an oscillation period and an oscillation stop period according to the SB terminal voltage and the MODE terminal voltage.

[0020] The control circuit 10 includes an ST (start current input) terminal to which the start current from the power input is input via resistor R1 at startup, and a VSEN (power signal input) terminal to which the divided voltage value obtained by dividing the power input by the voltage divider circuit 4 is input as an input voltage detection signal. When the power input is an AC input, the AC input is rectified by diodes D1 and D2 and then input to the ST terminal via resistor R1. If the voltage divider circuit 4 is built into the control circuit 10, it may be a single terminal common to both the ST terminal and the VSEN terminal.

[0021] The control circuit 10 includes a VCC (control power input) terminal to which the power generated for the control circuit 10 by the auxiliary winding of the transformer T1 is input, and a CD (input determination) terminal to which the capacitor Ccd is connected.

[0022] The control circuit 10 includes a startup circuit 21. Referring to Figure 3, the startup circuit 21 includes a constant current circuit consisting of a MOSFET Q11, an NPN bipolar transistor Q12, and resistors R11 and R12. A series circuit consisting of MOSFET Q11, resistor R11, and diode D11 is connected between the ST terminal and the VCC terminal. Resistor R12 is connected between the drain and gate of MOSFET Q11, and Zener diode ZD11 is connected between the gate of MOSFET Q11 and ground. Bipolar transistor Q12 is connected in parallel with resistor R11, and the base of bipolar transistor Q12 is connected to the connection point between the source of MOSFET Q11 and resistor R11. As a result, when the input voltage Vin is connected to the ST terminal via resistor R1, the capacitor CVCC connected between the ends of the auxiliary winding of transformer T1 is charged with a constant current via diode D11 and the VCC terminal.

[0023] The startup circuit 21 includes a MOSFETQ13 whose on / off state is controlled by a startup / shutdown signal ST_off. MOSFETQ13 is connected between the gate of MOSFETQ11 and ground.

[0024] The startup circuit 21 includes a MOSFET Q14 whose on / off state is controlled by the X discharge signal x_dis. The MOSFET Q14 is connected between the connection point of a resistor R11 (the emitter of the bipolar transistor Q12) and a diode D11 and the ground.

[0025] The control circuit 10 includes an input detection circuit 22. Referring to FIG. 4, the input detection circuit 22 includes a comparator CMP21 having a hysteresis function for comparing the VSEN terminal voltage with the DC detection voltages VSENon and Vsenoff1. The comparator CMP21 outputs the comparison result between the VSEN terminal voltage and the DC detection voltage VSENon as a DC detection signal dc_vsen_on_off. When the DC detection signal dc_vsen_on_off becomes a low level, the main control circuit 13 transitions the X discharge signal x_dis to a high level. The X discharge signal x_dis becomes a low level when a low-input operation prohibition signal uvlo, which will be described later, becomes a low level.

[0026] The input detection circuit 22 includes a hysteresis comparator CMP22 for comparing the VSEN terminal voltage with the AC detection voltages VSENac1 and 2. The AC detection voltages VSENac1 and 2 are higher than the DC detection voltage VSENon and are set in the relationship of VSENon < VSENac2 < VSENac1. When the VSEN terminal voltage exceeds the AC detection voltage VSENac1, the output of the hysteresis comparator CMP22 transitions to a high level. The output of the hysteresis comparator CMP22 is input to a one-shot pulse generation circuit 221. When the output of the hysteresis comparator CMP22 transitions to a high level, the one-shot pulse generation circuit 221 generates a one-shot pulse, and the generated one-shot pulse is output as an up-edge detection signal vsen_up via an OR circuit OR21.

[0027] The input detection circuit 22 includes a hysteresis comparator CMP23 that compares the VSEN terminal voltage with the AC detection voltages VSENoff1 and 2. The AC detection voltages VSENoff1 and 2 are lower than the DC detection voltage VSENon, and are set in the relationship of VSENoff2 < VSENoff1 < VSENon. When the VSEN terminal voltage exceeds the AC detection voltage VSENoff1, the output of the hysteresis comparator CMP23 transitions to the high level. The output of the hysteresis comparator CMP23 is input to the one-shot pulse generation circuit 222. When the output of the hysteresis comparator CMP23 transitions to the high level, the one-shot pulse generation circuit 222 generates a one-shot pulse, and the generated one-shot pulse is output as the rising edge detection signal vsen_up through the OR circuit OR21. The rising edge detection signal vsen_up sets the flip-flop FF21 whose output becomes the AC detection signal ac_vsen_on_off (the AC detection signal ac_vsen_on_off becomes the high level).

[0028] The output of the NAND circuit NAND21 is connected to the reset terminal R of the flip-flop FF21. The NAND circuit NAND21 receives the low-input operation prohibition signal uvlo and the AC stop signal vsen_ac_off, which will be described later. When either the low-input operation prohibition signal uvlo or the AC stop signal vsen_ac_off becomes the low level, the flip-flop FF21 is reset (the AC detection signal ac_vsen_on_off becomes the low level).

[0029] The control circuit 10 includes a startup control circuit 23. Referring to Figure 5, the startup control circuit 23 includes a hysteresis comparator CMP31 that compares the VCC terminal voltage with the oscillation start voltage VCCon (e.g., 17V) and the oscillation stop voltage VCCoff (e.g., 8.9V). The comparison result of the hysteresis comparator CMP31 is output as a low-input operation disable signal uvlo. When the VCC terminal voltage exceeds the oscillation start voltage VCCon, the low-input operation disable signal uvlo transitions to a high level, and when the VCC terminal voltage falls below the oscillation stop voltage VCCoff, the low-input operation disable signal uvlo transitions to a low level. When the low-input operation disable signal uvlo transitions to a low level, the main control circuit 13 stops the oscillation operation.

[0030] The low-input operation disable signal uvlo is input to the set terminal S of the flip-flop FF31 via the inverter INV31, and is also input to the NAND circuit NAND31, the reset terminal R of the flip-flop FF32 which is set by various protection signals, and the AND circuit AND31, and is inverted into the NOR circuit NOR31.

[0031] The startup control circuit 23 includes a comparator CMP32 that compares the VCC terminal voltage with a detection start voltage VCCbias (e.g., 9.8V). The detection start voltage VCCbias is set to a voltage lower than the oscillation start voltage VCCon and higher than the oscillation stop voltage VCCoff. The output of the comparator CMP32 is input to the reset terminal R of the flip-flop FF31, the OR circuit OR31, and the NOR circuit NOR32.

[0032] The output Q of the flip-flop FF31 is the reset signal mode_reset. When the low-input operation disable signal uvlo transitions to a low level, the output Q transitions to a high level. When the output of the comparator CMP32 transitions to a high level, the output Q transitions to a low level.

[0033] The NAND31 circuit receives the signal vsen_on_off and the inverted output Qb of the flip-flop FF32, along with the low input disable signal uvlo. It outputs a low-level signal EN when all inputs are at a high level.

[0034] The signal EN is output as the signal PoR via inverters INV32 and INV33. A MOSFET Q31, whose on / off state is controlled by the signal dc_start, is connected between the connection point of inverters INV32 and INV33 and ground. Therefore, the signal PoR is low when both the signal EN and the signal dc_start are low, and high in all other combinations.

[0035] The OR circuit OR31 receives the output Q of the flip-flop FF32 along with the output of the comparator CMP32. The AND circuit AND31 receives the output of the OR circuit OR31 along with the signal vsen_on_off and the low-input operation disable signal uvlo. The output of the AND circuit AND31 and the overheat protection signal TSD, which goes high when the overheat protection operating temperature is reached, are input to the OR circuit OR32. The OR circuit OR32 outputs the start / stop signal ST_off, which goes high when either the output of the AND circuit AND31 or the overheat protection signal TSD is high.

[0036] The NOR32 circuit receives the signal sw_on along with the output of the comparator CMP32, and its output is input to the NOR31 circuit along with the signal vsen_on_off and the inverted low-input operation disable signal uvlo. The output of the NOR31 circuit is input to the NOR33 circuit along with the inverted input of the signal cd_3V_b. The output of the NOR33 circuit and the overheat protection signal TSD are input to the NOR34 circuit, which outputs the X discharge signal x_dis, which is high level when both the output of the NOR33 circuit and the overheat protection signal TSD are low level.

[0037] The control circuit 10 includes an input determination circuit 24. Referring to Figure 6, the input determination circuit 24 includes a constant current source CC41 that charges the capacitor Ccd connected to the CD terminal with a constant current via a diode D41.

[0038] The input determination circuit 24 includes a comparator CMP41 that compares the CD terminal voltage with the oscillation stop voltage VCD1 (for example, 3.0V). The output of the comparator CMP41 is output as an oscillation stop signal cd_3V_b, which becomes low level when the CD terminal voltage exceeds the oscillation stop voltage VCD1.

[0039] The OR42 circuit outputs an AC stop signal vsen_ac_off, which is low level when both the oscillation stop signal cd_3V_b and the output Q of the flip-flop FF41 are low level.

[0040] The input determination circuit 24 includes a comparator CMP42 that compares the CD terminal voltage with a CD discharge stop voltage VCD2 (e.g., 0.3V) that is lower than the oscillation stop voltage VCD1. The output of the comparator CMP42 becomes high when the CD terminal voltage is less than or equal to the CD discharge stop voltage VCD2, resetting the flip-flop FF41 which is set by the AC up edge detection signal ac_vsen_up.

[0041] The output Q of the flip-flop FF41 controls the on / off state of MOSFET Q41, which is connected between the CD terminal and ground. When the flip-flop FF41 is set by the AC up-edge detection signal ac_vsen_up, MOSFET Q41 is controlled to be ON, and the CD terminal voltage is discharged. When the CD terminal voltage drops to the CD discharge stop voltage VCD2, the flip-flop FF41 is reset, and MOSFET Q41 is controlled to be OFF, stopping the discharge of the CD terminal voltage.

[0042] The input determination circuit 24 includes a comparator CMP43 that compares the CD terminal voltage with a DC determination voltage VCDdc (e.g., 2.0V) that is lower than the oscillation stop voltage VCD1 and higher than the CD discharge stop voltage VCD2. The output of the comparator CMP43 is output as a DC determination signal cd_2V, which becomes high level when the CD terminal voltage exceeds the DC determination voltage VCDdc. In DC input mode, the DC determination signal cd_2V becomes a clamp signal cd_2V_clamp, which controls the on / off state of MOSFETQ42, which is connected between the connection point between the constant current source CC41 and the anode of diode D41 and ground. In DC input mode, MOSFETQ42 is controlled to be on at a high level when the DC determination signal cd_2V (clamp signal cd_2V_clamp) is on, and clamps the CD terminal voltage with the DC determination voltage VCDdc.

[0043] MOSFETQ43 is connected between the CD terminal and ground. MOSFETQ43 is controlled on / off by the output of the OR41 circuit. The OR41 circuit receives the vsen_off signal and the mode_reset signal, and MOSFETQ43 is controlled to be ON when either the vsen_off signal or the mode_reset signal is at a high level.

[0044] The input determination circuit 24, as shown in Figure 7, includes a flip-flop FF51 that sets the input to AC input mode and a flip-flop FF52 that sets the input to DC input mode. Both flip-flops FF51 and FF52 are reset by the reset signal mode_reset. Flip-flop FF51 is set by the output of AND circuit AND51, which takes the up-edge detection signal vsen_up and the inverted output Qb of flip-flop FF52 as inputs. Flip-flop FF52 is set by the output of AND circuit AND52, which takes the DC determination signal cd_2V and the inverted output Qb of flip-flop FF51 as inputs.

[0045] Therefore, if the up-edge detection signal vsen_up is detected before the VCC terminal voltage reaches the detection start voltage VCCbias (high level before the DC judgment signal cd_2V), flip-flop FF51 is set and flip-flop FF52 remains in the reset state. If the DC judgment signal cd_2V is detected before the up-edge detection signal vsen_up (high level before the up-edge detection signal vsen_up), flip-flop FF52 is set and flip-flop FF51 remains in the reset state.

[0046] The output of the flip-flop FF51 is output as the AC input detection signal ac_mode. The AC input detection signal ac_mode is input to the select terminal sel of the select circuit SEL51 and to the NOR circuit NOR51. The select circuit SEL51 outputs the DC detection signal dc_vsen_on_off OUT when the AC input detection signal ac_mode is low level and input to terminal D1. The select circuit SEL51 outputs the AC detection signal ac_vsen_on_off OUT when the AC input detection signal ac_mode is high level and input to terminal D2. The output of the select circuit SEL51 is input to the AND circuit AND54 and also inverted and input to the AND circuit AND53.

[0047] The output Q of the flip-flop FF52 is output as the DC input detection signal dc_mode. The DC input detection signal dc_mode is output to the NOR51 circuit along with the AC input detection signal ac_mode. The input is received. The output of the NOR51 circuit is the signal dc_start.

[0048] The input determination circuit 24 includes a flip-flop FF53 which is set by a low-input operation disable signal uvlo, inverted by inverter INV51, and reset by a signal PoR, inverted by inverter INV52. The inverted output Qb of the flip-flop FF53 is output as the signal sw_on. The inverted output Qb of the flip-flop FF53 is input to the AND circuit AND53 along with the output OUT of the inverted select circuit SEL51.

[0049] The input determination circuit 24 includes a flip-flop FF54 which is set by the output of the AND circuit AND53 and reset by the reset signal mode_reset. The output Q of the flip-flop FF54 is output as the signal vsen_off. The inverted output Q of the flip-flop FF54 is input to the AND circuit AND54 along with the output OUT of the select circuit SEL51. The output of the AND circuit AND54 becomes the signal vsen_on_off.

[0050] Next, the input determination operation of the control circuit 10 will be described in detail with reference to Figures 8 to 10.

[0051] Referring to Figure 8, the startup circuit 21 turns ON during startup (when power is turned on) and begins charging the VCC terminal (capacitor Cvcc) (step S101). When the startup circuit 21 is ON, as shown in Figure 3, the MOSFET Q11 and bipolar transistor Q12 are ON. That is, a constant current circuit is formed by the MOSFET Q11, bipolar transistor Q12 and resistor R11, and the current flowing through resistor R11 is controlled to be constant.

[0052] When the startup control circuit 23 detects that the VCC terminal voltage has reached the detection start voltage VCCbias (step S102), the input determination circuit 24 starts charging the CD terminal (capacitor Ccd) (step S103). Also, when the VCC terminal voltage reaches the detection start voltage VCCbias, the flip-flop FF31 of the startup control circuit 23 is reset and the reset signal mode_reset transitions to a low level.

[0053] The input detection circuit 22 detects the up edge of the VSEN terminal voltage (step S104), and the input determination circuit 24 detects that the CD terminal voltage has reached the DC determination voltage VCDdc (step S105). When the input detection circuit 22 detects the up edge of the VSEN terminal voltage using hysteresis comparators CMP22 and CMP23, it outputs an up edge detection signal vsen_up (1-shot pulse). Also, the flip-flop FF21 is set by the up edge detection signal vsen_up, and the AC detection signal ac_vsen_on_off becomes high level. Alternatively, when the input determination circuit 24 detects that the CD terminal voltage has reached the DC determination voltage VCDdc using comparator CMP43, it transitions the DC determination signal cd_2V to a high level (step S121).

[0054] If the CD terminal voltage does not reach the DC determination voltage VCDdc in step S105, and the up edge of the VSEN terminal voltage is detected in step S104, the input determination circuit 24 determines it is an AC input and sets it to AC input mode (step S106). In the case of an AC input, referring to Figure 9, the VCC terminal voltage reaches the detection start voltage VCCbias at time t11, and then the up edge of the VSEN terminal voltage is detected at time t12. The input determination circuit 24 sets it to AC input mode by setting the flip-flop FF51 shown in Figure 7, and sets the AC input determination signal ac_mode to a high level.

[0055] Each time an up edge of the VSEN terminal voltage is detected, the input determination circuit 24 turns on MOSFET Q41 via the set of flip-flops FF41 shown in Figure 6, and discharges the CD terminal voltage to the CD discharge stop voltage VCD2. After an up edge is detected and until the next up edge is detected, the CD terminal voltage is charged by the charging current of the constant current source CC41, but the capacitance of capacitor Ccd and the charging current are set to a level where the peak value of the CD terminal voltage does not reach the DC determination voltage VCDdc.

[0056] When the startup control circuit 23 detects that the VCC terminal voltage has exceeded the oscillation start voltage VCCon (step S107), the main control circuit 13 starts the oscillation operation upon detection of the next up edge of the VSEN terminal voltage (step S108). Along with the start of the oscillation operation, the main control circuit 13 turns on the MOSFET Q13 and turns off the startup circuit 21 by transitioning the start / stop signal ST_off to a high level. Referring to Figure 9, after the VCC terminal voltage exceeds the oscillation start voltage VCCon at time t13, the oscillation operation starts when the up edge of the VSEN terminal voltage is detected at time t14.

[0057] When oscillation starts in step S108, the input determination circuit 24 switches to a mode that detects when the CD terminal voltage reaches the oscillation stop voltage VCD1 (step S109). Note that in AC input mode, the flip-flop FF51 of the input determination circuit 24 shown in Figure 7 is set, so the AND circuit AND52 is turned off, and the function of clamping the CD terminal voltage to the DC determination voltage VCDdc is released.

[0058] Referring to Figure 9, when the AC input is disconnected at time t15, the up edge of the VSEN terminal voltage is no longer detected, and the CD terminal voltage rises above the DC judgment voltage VCDdc as discharge due to up edge detection ceases. At time t16, when the CD terminal voltage reaches the oscillation stop voltage VCD1, the oscillation stop signal cd_3V_b becomes low, and the AC stop signal vsen_ac_off becomes low via the OR circuit OR42. When the AC stop signal vsen_ac_off becomes low, the output of the NAND circuit NAND21 shown in Figure 4 becomes high, the flip-flop FF21 is reset, the AC detection signal ac_vsen_on_off becomes low, and the main control circuit 13 stops the oscillation operation (step S110). The main control circuit 13 also transitions the start-stop signal ST_off to low and the X discharge signal x_dis to high. The flip-flop FF41 of the input judgment circuit 24 is set, and the X discharge signal x_dis becomes high. As a result, the startup circuit 21 turns on MOSFET Q11 and bipolar transistor Q14, and the X capacitor Cx is discharged via the startup circuit 21 (step S111).

[0059] When the startup control circuit 23 detects at time t17 that the VCC terminal voltage has dropped below the oscillation stop voltage VCCoff (step S112), the input determination circuit 24 cancels the AC input mode setting (step S113). As the VCC terminal voltage falls below the oscillation stop voltage VCCoff, the flip-flop FF31 of the startup control circuit 23 shown in Figure 5 is set, and the reset signal mode_reset becomes high level. This reset signal mode_reset resets the flip-flop FF51 of the input determination circuit 24 shown in Figure 7, canceling the AC input mode setting. The main control circuit 13 also transitions the X discharge signal x_dis to a low level, stopping the discharge of the X capacitor Cx (step S114). If there is no power restoration, the control circuit 10 terminates its operation; if there is power restoration, the control circuit 10 returns to step S101 and executes the process.

[0060] If the up edge of the VSEN terminal voltage is not detected in step S104, and the CD terminal voltage reaches the DC determination voltage VCDdc in step S105, the input determination circuit 24 determines it is a DC input and sets it to DC input mode (step S121). In the case of a DC input, referring to Figure 10, after the VCC terminal voltage reaches the detection start voltage VCCbias at time t21, the CD terminal voltage reaches the DC determination voltage VCDdc at time t22 without the up edge of the VSEN terminal voltage being detected. The input determination circuit 24 sets it to DC input mode by setting the flip-flop FF52, and the AC input determination signal ac_mode is kept at a low level.

[0061] The comparator CMP43 shown in Figure 6 of the input determination circuit 24 outputs a high-level DC determination signal cd_2V. In DC input mode, this DC determination signal cd_2V becomes a clamp signal cd_2V_clamp, which controls the on / off state of MOSFET Q42. Therefore, in DC input mode, the CD terminal voltage is clamped by the DC determination voltage VCDdc.

[0062] When the startup control circuit 23 detects that the VCC terminal voltage has exceeded the oscillation start voltage VCCon (step S122), the main control circuit 13 starts the oscillation operation (step S123). Along with the start of the oscillation operation, the main control circuit 13 turns on the MOSFET Q13 shown in Figure 3 and turns off the startup circuit 21 by transitioning the start / stop signal ST_off to a high level. Referring to Figure 10, when the VCC terminal voltage exceeds the oscillation start voltage VCCon at time t23, the oscillation operation starts.

[0063] When the oscillation operation starts in step S124, the input detection circuit 22 detects that the VSEN terminal voltage has dropped to below the DC detection voltage VSENoff1 (step S124).

[0064] Referring to Figure 10, when the DC input is disconnected at time t24, the VSEN terminal voltage drops, and when the VSEN terminal voltage reaches the DC detection voltage VSENoff1 at time t25, the DC detection signal dc_vsen_on_off becomes low level, and the main control circuit 13 stops the oscillation operation (step S125).

[0065] Furthermore, the main control circuit 13 transitions the start / stop signal ST_off to a low level and the X discharge signal x_dis to a high level. As a result, the start circuit 21 turns on MOSFET Q11, bipolar transistor Q12, and MOSFET Q14, and the input smoothing capacitor Cin is discharged via the start circuit 21 (step S126).

[0066] At time t26, the startup control circuit 23 detects that the VCC terminal voltage has dropped below the oscillation stop voltage VCCoff (step S127), and the input determination circuit 24 cancels the DC input mode setting (step S128). When the VCC terminal voltage falls below the oscillation stop voltage VCCoff, the flip-flop FF31 shown in Figure 5 of the startup control circuit 23 is set, and the reset signal mode_reset becomes high level. This reset signal mode_reset resets the flip-flop FF52 shown in Figure 7 of the input determination circuit 24, canceling the DC input mode setting. The main control circuit 13 also transitions the X discharge signal x_dis to a low level, stopping the discharge of the input smoothing capacitor Cin (step S129). If there is no power restoration, the control circuit 10 terminates its operation; if there is power restoration, the control circuit 10 returns to step S101 and executes the process.

[0067] As described above, this embodiment is a control circuit 10 for a switching power supply (current resonant power supply 1a, 1b), and includes a startup circuit 21 connected to the power input (AC input, DC input) that charges the VCC terminal voltage (control voltage) at startup and discharges the interphase capacitors (X capacitor Cx, input smoothing capacitor Cin) of the power input when the switching power supply is stopped, a startup control circuit 23 that detects the VCC terminal voltage, an input detection circuit 22 that detects the input voltage Vin of the power input as the VSEN terminal voltage, and a circuit that charges the CD terminal voltage to which capacitor Ccd is connected. The system includes an input determination circuit 24 that, upon charging, discharges the CD terminal voltage by detecting fluctuations (up edge) in the VSEN terminal voltage between the AC detection voltages VSENac and VSENoff, and after charging of the CD terminal voltage has started, determines that the power input is an AC input and sets it to AC input mode when fluctuations in the VSEN terminal voltage between the detection voltages VSENac and VSENoff are detected, and determines that the power input is a DC input and sets it to DC input mode when the CD terminal voltage reaches the DC determination voltage VCDdc without detecting an up edge in the VSEN terminal voltage. This configuration allows for the determination of whether the input is AC or DC without using the X-CAP discharge function. Therefore, it can be used with both DC and AC inputs without controlling the on / off state of the X-CAP discharge function, and the integrated circuit control circuit 10 can be shared. Even in DC input mode, the input smoothing capacitor Cin can be discharged when the drive stops, enhancing safety in anticipation of maintenance by service personnel.

[0068] Furthermore, in this embodiment, in DC input mode, the clamping function clamps the CD terminal voltage to the DC determination voltage VCDdc (clamp voltage), and the VSEN terminal voltage drops to the DC detection voltage VSENoff1, stopping the operation of the switching power supply (current resonant power supply 1b). In AC input mode, the clamping function is released, and the CD terminal voltage reaches a preset drive stop voltage (oscillation stop voltage VCD1) above the DC determination voltage VCDdc, stopping the operation of the switching power supply (current resonant power supply 1a). This configuration allows the power input to be disconnected based on the VSEN terminal voltage in DC input mode, and based on the CD terminal voltage in AC input mode.

[0069] It is clear that the present invention is not limited to the above embodiments, and that each embodiment can be modified as appropriate within the scope of the technical concept of the present invention. Furthermore, the number, position, shape, etc. of the above-mentioned components are not limited to the above embodiments, and can be set to a number, position, shape, etc. that is suitable for carrying out the present invention. In each figure, the same reference numeral is used for the same component. [Explanation of Symbols]

[0070] 1a, 1b current resonant power supply 2 Full wave rectifier circuit 3 PFC circuit 4. Voltage divider circuit 10 Control circuits 11. High-side drive circuit 12 Low-side drive circuit 13 Main control circuit 14. Oscillation frequency control circuit 15 Overcurrent detection circuit 16 Overload detection circuit 17. Soft-start circuit 18 Standby control circuit 21 Startup Circuit 22 Input detection circuit 23 Startup control circuit 24 Input detection circuit 25 Thermal Shutdown (TSD) Circuit Cin input smoothing capacitor Cx Xcapacitor

Claims

1. A control circuit for a switching power supply, A startup circuit connected to the power input, which charges the control voltage during startup and discharges the interphase capacitor of the power input when the switching power supply is stopped, A startup control circuit for detecting the control voltage, An input detection circuit for detecting the input voltage of the power supply input, The device comprises an input determination circuit that charges the CD terminal voltage connected to a capacitor, discharges the CD terminal voltage upon detection of fluctuations in the input voltage around an AC detection voltage, determines the power input to be an AC input and sets it to AC input mode when fluctuations around the detection voltage are detected after charging to the CD terminal voltage has started, and determines the power input to be a DC input and sets it to DC input mode when fluctuations around the AC detection voltage of the input voltage are not detected and the CD terminal voltage reaches a preset DC determination voltage, In the DC input mode, the clamping function clamps the CD terminal voltage to a predetermined clamping voltage, and when the input voltage drops to the DC detection voltage, the switching power supply is stopped. In the AC input mode, the control circuit is characterized by releasing the clamping function and stopping the operation of the switching power supply when the CD terminal voltage reaches a preset drive stop voltage that is higher than or equal to the clamping voltage.

2. A semiconductor device characterized in that the control circuit described in claim 1 is integrated on a substrate.

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