Bias scheme for single-device synaptic elements

Abstract

A neuromorphic synapse array includes a plurality of synaptic array cells connected by circuitry such that the synaptic array cells are assigned to rows and columns of the array, each having a single-polarity synaptic weight, with a row connected to each input terminal of the synaptic array cell and a column connected to each output terminal of the synaptic array cell, where the synaptic array cells aligned in the columns of the array are defined as an operational column array; and an array of current mirrors, each current mirror exhibiting a mirror ratio of N:1, where N is the number of columns of synaptic array cells, each connected to a respective row such that the weight corresponding to all of the current mirrors is set to the average weight of all of the synaptic array cells that are updated during the learning phase.

Description

Technical Field

[0001] The present invention generally relates to neuromorphic and synaptic computing, and more particularly, to a biasing scheme for a single device-synaptic element.

Background Art

[0002] Neuromorphic and synaptic computing, also called artificial neural networks, are computing systems that enable an electronic system to function in a way that is essentially similar to a biological brain. Neuromorphic and synaptic computing generally do not utilize conventional digital models that manipulate 0s and 1s. Instead, neuromorphic and synaptic computing create connections between processing elements that are functionally equivalent to the neurons of a biological brain. Neuromorphic and synaptic computing can include various electronic circuits modeled on biological neurons.

[0003] In a biological system, the point of contact between the axon of a neuron and the dendrites on another neuron is called a synapse, and based on the synapse, the two neurons are called presynaptic and postsynaptic, respectively. The essence of an individual experience is stored in the conductance of the synapse. Synaptic conductance changes over time as a function of the relative spike times of the presynaptic and postsynaptic neurons by spike-timing-dependent plasticity (STDP).

[0004] Deep neural networks (DNNs) are a family of neuromorphic computing architectures that have made significant advances in various machine learning problems such as image or object recognition, speech recognition, and machine language translation. Computation of DNNs involves both training, where the network's weights are optimized for the training dataset, and forward inference, where the trained network is used for classification, prediction, or other useful tasks on novel, previously unseen test data. These networks are well-suited to computations involving large dense matrix products, which can be highly parallelized.

[0005] Conventional von Neumann hardware is constrained by the time and energy spent on data traveling between memory and the processor ("von Neumann bottleneck"). In contrast, in non-von Neumann schemes, computation is performed at the data location using the strength (weights) of synaptic connections stored in memory and directly modulated. However, for efficient on-chip training, it is preferable to replace the digital synaptic weights stored in a static random-access memory array with high-density analog devices that directly encode the synaptic weights into their conductance. Such analog systems can achieve significant speed increases and power reductions for both forward inference and training. Desirable features of analog devices for training include high-speed, low-power programming at multiple analog levels, dimensionality, good retention, high durability, and, most importantly, stepwise and symmetric conductance update characteristics.

[0006] To date, experimental demonstrations of analog memory-based DNN training have suffered from reduced classification accuracy due to the substantial non-idealization exhibited by existing devices. These demonstrations have featured filament-type resistive RAM (RRAM), non-filament-type resistive RAM, phase-change memory (PCM), conductive bridge RAM (CBRAM), ferroelectric RAM, and hybrid digital non-volatile memory (NVM) architectures. Therefore, the novel approach needs to use synaptic weights as a single device. [Overview of the project]

[0007] According to the embodiment, a neuromorphic synapse array is provided. The neuromorphic synapse array includes a plurality of synapse array cells, each synapse array cell being connected by circuits so that synapse array cells are assigned to rows and columns of an array, wherein each synapse array cell has a single-polarity synapse weight, each row being connected to each input terminal of the synapse array cell, each column being connected to each output terminal of the synapse array cell, and the synapse array cells aligned in the columns of the array are defined as an operational column array; and an array of current mirrors, each current mirror being connected to each row such that each current mirror exhibits a mirror ratio of N:1, where N is the number of columns of the synapse array cell, and the weights corresponding to all of the current mirrors are set to the average weight of all the synapse array cells which are updated during the learning phase.

[0008] According to another embodiment, a computer implementation method is provided. The computer implementation method includes connecting a plurality of synaptic array cells by a circuit such that synaptic array cells are assigned to rows and columns of an array, wherein each synaptic array cell has a single-polarity synaptic weight, each row is connected to each input terminal of the synaptic array cell, each column is connected to each output terminal of the synaptic array cell, and the synaptic array cells aligned to the columns of the array are defined as an operational column array; and connecting an array of current mirrors to the array, each current mirror having a mirror ratio of N:1, where N is the number of columns of the synaptic array cell, and each current mirror is connected to each row such that the weights corresponding to all of the current mirrors are set to the average weight of all of the synaptic array cells which are updated during the learning phase.

[0009] In yet another embodiment, a neuromorphic synaptic array is provided. A neuromorphic synapse array comprises multiple synapse array cells, each synapse array cell being connected by a circuit so that synapse array cells are assigned to rows and columns of an array, wherein each synapse array cell has a single-polarity synapse weight, each row being connected to each input terminal of the synapse array cell, each column being connected to each output terminal of the synapse array cell, and the synapse array cells aligned in the columns of the array are defined as an operational column array; an array of current mirrors, each current mirror exhibiting a mirror ratio of N:1, where N is the number of columns of the synapse array cell, and each current mirror being connected to each row such that the weights corresponding to all current mirrors are set to the average weights of all synapse array cells to be updated during the learning phase; and an array of current integrators, each current integrator being connected to each column of the array, and each current integrator including an integrating capacitor for receiving, copying, and discharging the collected mirror current.

[0010] In yet another embodiment, a computer implementation method is provided. The computer implementation method involves connecting a plurality of synaptic array cells by a circuit such that synaptic array cells are assigned to rows and columns of an array, wherein each synaptic array cell has a single-polarity synaptic weight, each row is connected to each input terminal of the synaptic array cell, and each column is connected to each output terminal of the synaptic array cell, and the synaptic array cells aligned in the columns of the array are defined as an operational column array, and connecting an array of current mirrors to the array, wherein each current mirror is N: Connecting an array of current mirrors, each connected to each row, with a Miller ratio of 1, where N is the number of rows of synaptic array cells, and each corresponding weight of all current mirrors is set to the average weight of all synaptic array cells updated during the learning phase; and connecting an array of current integrators to the array, each current integrator connected to each row of the array, and each current integrator includes an integrating capacitor for receiving the collected mirror current, copying the collected mirror current, and discharging the collected mirror current.

[0011] In yet another embodiment, a neuromorphic synapse array is provided. The neuromorphic synapse array comprises a plurality of synapse array cells electrically connected so that synapse array cells are assigned to rows and columns of an array, each synapse array cell having a single-polarity synapse weight; an array of current mirrors, each current mirror connected to each row such that each current mirror exhibits a mirror ratio of N:1, where N is the number of columns of synapse array cells, and the weights corresponding to all current mirrors are set to the average weight of all synapse array cells to be updated during the learning phase; and an array of current integrators, each current integrator connected to each column of the array, each current integrator including an integrating capacitor to receive the collected mirror current, copy the collected mirror current, and discharge the collected mirror current to accelerate the sum-of-accumulate (MAC) operation in an artificial neural network accelerator chip.

[0012] In one preferred embodiment, at least a portion of a plurality of synaptic array cells include resistive memory.

[0013] In another preferred embodiment, at least some of the multiple synaptic array cells include a current integrator.

[0014] In yet another preferred embodiment, the array of current mirrors includes different current mirror configurations for one or more rows of the array.

[0015] In yet another preferred embodiment, one current mirror configuration includes two n-type field-effect transistors (NFETs).

[0016] In yet another preferred embodiment, one current mirror configuration includes two p-type field-effect transistors (PFETs) and a single NFET.

[0017] In yet another preferred embodiment, one current mirror configuration includes two NFETs and a single operational amplifier (op-amp).

[0018] In yet another preferred embodiment, one current mirror configuration includes two PFETs, a single NFET, and two operational amplifiers.

[0019] In yet another preferred embodiment, the current integrator includes different configurations for one or more rows of the array.

[0020] In yet another preferred embodiment, a current integrator configuration includes two PFETs, a single NFET, and an integrating capacitor.

[0021] In yet another preferred embodiment, a current integrator configuration includes two PFETs, a single NFET, an operational amplifier, and an integrating capacitor.

[0022] In yet another preferred embodiment, the integrating capacitor receives the collected Miller current, copies the collected Miller current, and discharges the collected Miller current.

[0023] In yet another preferred embodiment, a neuromorphic synapse array accelerates multiply-accumulate (MAC) operations in an artificial neural network accelerator chip.

[0024] The advantages of the present invention include eliminating the processing time overhead for programming synaptic cells, as "reading", "writing", and "averaging" operations are not required. Further advantages include reducing the circuit layout area per operation. Another advantage includes reducing the energy consumption per operation. Also, another advantage includes reducing or eliminating read quantization error, average calculation error, and write quantization error. This results in higher memory capacity, faster processing, and better data transfer speed. Further advantages include higher quality, cost reduction, clearer scope, faster performance, fewer application errors, and fewer data errors.

[0025] It should be noted that the exemplary embodiments are described in relation to different subject matters. In particular, there are embodiments described in relation to method type claims and there are also embodiments described in relation to apparatus type claims. However, those skilled in the art will infer from the above and the following description that, unless otherwise specified, any combination of features belonging to one type of subject matter, in addition to any combination between features related to different subject matters, particularly any combination between the features of method type claims and the features of apparatus type claims, is also considered to be described in this document.

[0026] These and other features and advantages will become apparent from the following detailed description of its exemplary embodiments, which should be read in conjunction with the accompanying drawings.

[0027] The present invention will be described in detail in the following description of preferred embodiments with reference to the following drawings.

Brief Description of the Drawings

[0028] [Figure 1] Exemplary neuron excitation through the product-sum (MAC) operation of inputs from multiple pre-neurons by the synapses of a neuron is shown. [Figure 2] It should be noted that in the above translation, for the Japanese text, the Chinese characters are directly translated into English as appropriate. And for the tags like , etc., they are kept unchanged as required. Also, the line breaks are maintained as in the original text.This is a synaptic array cell according to an embodiment of the present invention, in which each row includes a current mirror. [Figure 3] Another embodiment of the present invention is a synaptic array cell including current mirrors in each row, wherein the current mirrors include a combination of transistors. [Figure 4] Another embodiment of the present invention is a synaptic array cell including current mirrors in each row, wherein the current mirrors include a combination of transistors and operational amplifiers. [Figure 5] This is a block / flow diagram of a method employing a current mirror to accelerate a multiply-accumulate (MAC) operation according to an embodiment of the present invention. [Figure 6] An exemplary neuromorphic and synaptronic network according to an embodiment of the present invention, including a crossbar of electronic synapses interconnecting electronic neurons and axons. [Figure 7] This is a block diagram of the components of a computing system according to an embodiment of the present invention, which includes a computing device and a neuromorphic chip capable of employing a current mirror to accelerate MAC calculations. [Figure 8] This is a block / flow diagram of an exemplary cloud computing environment according to an embodiment of the present invention. [Figure 9] This is a schematic diagram of an exemplary abstract model layer according to an embodiment of the present invention. [Figure 10] This figure shows an actual application of employing a current mirror to accelerate MAC calculations according to an embodiment of the present invention. [Figure 11] This is a block / flow diagram of a method for employing current mirroring to accelerate MAC calculations in an Internet of Things (IoT) system / device / infrastructure, according to an embodiment of the present invention. [Figure 12] This is a block / flow diagram of an exemplary IoT sensor used to collect data / information related to current mirrors that accelerate MAC calculations, according to an embodiment of the present invention. [Modes for carrying out the invention]

[0029] Throughout the drawing, identical or similar reference numbers represent identical or similar elements.

[0030] Embodiments of the present invention provide a method and device for shifting the accumulated (sum-product) value in a neuron to a value close to zero, where the activation function has the most sensitive region, by employing a current mirror circuit instead of a physical reference cell. Thus, each single device advantageously represents one synaptic weight.

[0031] In recent years, deep learning has revolutionized the field of machine learning by providing near-human performance in areas such as computer vision, speech recognition, and complex strategy games. However, current hardware implementations of deep neural networks are still far from competing with biological neural systems in terms of real-time information processing capabilities, which involve considerable energy consumption. Most neural networks are implemented on computing systems based on the von Neumann architecture, using separate memory and processing units or devices. These devices store information in their resistance / conductance states and exhibit conductivity modulation based on their programming history. The central idea of ​​building cognitive hardware-based devices is to store synaptic weights as their conductance states and to perform the associated computational tasks in place. Two essential synaptic attributes that need to be emulated by such devices are synaptic transmission efficiency and synaptic plasticity. Synaptic transmission efficiency refers to the generation of synaptic output based on incoming neuronal activation. Synaptic plasticity, in contrast, is the ability of synapses to change their weights, usually during the execution of a learning algorithm. An increase in synaptic weights is called enhancement, and a decrease is called attenuation. In artificial neural networks (ANNs), weights are typically modified based on a backpropagation algorithm.

[0032] In computation, multiply-accumulate operations are tasks that calculate the product of two numbers and add that product to an accumulator. The hardware unit that performs the operation is called a multiply-accumulate unit (MAC or MAC unit). The operation itself is often called MAC or MAC operation. MAC technology using resistive devices such as resistive random-access memory (RRAM), phase-change memory (PCM), and magnetic random-access memory (MRAM) is attracting increasing interest in neural network accelerator chips. + ) and negative (G - Differential sensing schemes using pairs of resistive devices are a widely used technique for representing signed synaptic weights. However, G + and G - Synaptic weighting using a single device with a reference cell instead of a pair of resistive devices was previously employed. An exemplary embodiment of the present invention advantageously employs a current mirror instead of a reference cell to represent synaptic weights. Embodiments of the present invention provide methods and devices for advantageously facilitating complex programming (writing) procedures by minimizing or eliminating read quantization errors, averaging errors, and programming (writing) quantization errors. Performance overhead and energy consumption are advantageously minimized, and additional layout area for certain circuit blocks can be advantageously eliminated.

[0033] While the present invention is described in terms of a given exemplary architecture, it should be understood that other architectures, structures, substrate materials, and process features and steps / blocks may vary within the scope of the invention. For clarification, it should be noted that certain features cannot be shown in all drawings. This is not intended to be construed as any particular embodiment or example, or as a limitation of the claims.

[0034] Figure 1 shows an exemplary neuronal excitation via a multiply-accumulate (MAC) operation of inputs from multiple preneurons at a neuronal synapse. The multiply-accumulate operation (MAC) can also be called a "product-sum." Neuromorphic arrays utilize MAC operations in biological neuronal activation potential models. Neuronal membrane potentials, also known as "neuronal action potentials," are calculated by adding (summing) the results of multiplying input values ​​with the weights of the synapses connected between the input ports and neurons.

[0035] Figure 2 shows a synaptic array cell, according to an embodiment of the present invention, which includes current mirrors in each row.

[0036] The synaptic array cell 10 includes a bit line 12 and a plurality of word lines 14, as well as a plurality of return lines 11 that collect current from each cell element in the row. The first row includes a plurality of resistive memory elements. For illustrative purposes, a first resistive memory 30 and a second resistive memory 32 are shown. A current mirror 20 is provided advantageously in the first row. The current mirror 20 is connected in series with the first resistive memory 30 and the second resistive memory 32. An input pulse 16 is applied to the first row of resistive memory elements.

[0037] The second row also includes multiple resistive memory elements. For illustrative purposes, the first resistive memory 30' and the second resistive memory 32' are shown for the second row. A current mirror 22 is provided advantageously for the second row. The current mirror 22 is connected in series with the first resistive memory 30' and the second resistive memory 32'. An input pulse is applied to the second row of resistive memory elements. Element 23 is the leg of the current mirror for sensing current. Each current mirror 20, 22 has two legs, one for sensing a reference current and the other for copying the current by performing amplification such as 1 / N. In addition, several paired legs 24, 26 are shown in each column N of the array 10, each including an integrating capacitor 25, 27.

[0038] Current mirrors 20 and 22 are circuits designed to copy the current flowing through one active device by controlling the current in another active device in the circuit, by keeping the output current constant regardless of the load. The "copied" current may be, and sometimes is, a changing signal current. In other words, a current mirror is a circuit block that functions to produce a copy of the current flowing to or from the input terminal by duplicating the current at the output terminal. An advantageous feature of current mirrors is their relatively high output resistance, which helps to keep the output current constant regardless of the load conditions. Another advantageous feature of current mirrors is their relatively low input resistance, which helps to keep the input current constant regardless of the driving conditions.

[0039] Conceptually, an ideal current mirror is simply an ideal inverting current amplifier that reverses the direction of current, or it may include a current-controlled current source (CCCS). Current mirrors 20, 22 can be advantageously used to supply bias current and active load to a circuit. Current mirrors 20, 22 can also be advantageously used to model a more realistic current source. There are some main specifications that characterize a current mirror. One is the transfer rate (for current amplifiers) or the magnitude of the output current (for constant current source CCS). Another is the AC output resistance, which determines how much the output current changes with the voltage applied to the mirror. Yet another specification is the minimum voltage drop across the output of the mirror required for the mirror to function properly. This minimum voltage is determined by the need to keep the mirror's output transistor in active mode. The voltage range over which the mirror operates is called the compliance range, and the voltage that marks the boundary between good and bad behavior is called the compliance voltage.

[0040] Figure 3 shows another embodiment of a synaptic array cell, according to an embodiment of the present invention, in which the current mirrors include a combination of transistors, and the current mirrors include a combination of transistors in each row.

[0041] The synaptic array cell includes a bit line 12 and a plurality of word lines 14, as well as a plurality of return lines 11 that collect current from each cell element in the row. The first row includes a plurality of resistive memory elements. For illustrative purposes, a first resistive memory 30 and a second resistive memory 32 are shown. A current mirror 40 is provided advantageously in the first row. The current mirror 40 is connected in series with the first resistive memory 30 and the second resistive memory 32. An input pulse 16 is applied to the first row of resistive memory elements.

[0042] The current mirror 40 includes two n-type field-effect transistors (NFETs) 41 and 42.

[0043] The second row includes multiple current integrators. For illustrative purposes, a first current integrator 50 and a second current integrator 60 are shown. A current mirror 44 is provided in the second row. The current mirror 44 is connected in series with the first current integrator 50 and the second current integrator 60.

[0044] The current mirror 44 includes two p-type field-effect transistors (PFETs) 45, 47 and a single NFET 49.

[0045] When input pulse 16 enters the array, current flows from the left legs of elements 50 and 60 through resistive memories 30 and 32 to the right leg of element 40. The current is then amplified by 1 / N and mirrored to the left leg of element 40. These behaviors occur advantageously in each row and column. The mirrored current is collected at the leftmost line, and the collected current is supplied from the left leg of element 44. The collected current is then mirrored to the right leg of element 44, and then advantageously copied from the integrating capacitors 58 and 68 in each column N and discharged. As a result, current mirrors 40 and 44 with a mirror ratio of N:1 are provided in each row, where N is the number of columns for the computational synaptic cell. The mirrored currents are advantageously summed without requiring a reference synaptic cell and mirrored to the integrating capacitors 58 and 68 on each column to shift the MAC result.

[0046] Elements 50 and 60 are current integrators containing two current mirrors and one integrating capacitor. Current integrator 50 contains two PFETs 52 and 54 and a single NFET 56, as well as an integrating capacitor 58. Similarly, integrator 60 contains two PFETs 62 and 64 and a single NFET 66, as well as an integrating capacitor 68.

[0047] The NFET current mirror has only one leg. A pair of common sensing legs is located on the right leg of element 44. Elements 50 and 60 can also be called "neuron circuits." The voltages over integrating capacitors 58 and 68 are typically converted to digital bits by an analog-to-digital converter (ADC), so that the connected system can use the output data as digital data.

[0048] Figure 4 shows another embodiment of a synaptic array cell, according to an embodiment of the present invention, in which each row includes a current mirror, the current mirror comprising a combination of a transistor and an operational amplifier.

[0049] The synaptic array cell includes a bit line 12 and a plurality of word lines 14, as well as a plurality of return lines 11 that collect current from each cell element in the row. The first row includes a plurality of resistive memory elements. For illustrative purposes, a first resistive memory 30 and a second resistive memory 32 are shown. A current mirror 70 is provided advantageously in the first row. The current mirror 70 is connected in series with the first resistive memory 30 and the second resistive memory 32. An input pulse 16 is applied to the first row of resistive memory elements.

[0050] The current mirror 70 includes two n-type field-effect transistors (NFETs) 71, 72 and an operational amplifier, i.e., an op-amp 73.

[0051] The second row includes multiple current integrators. For illustrative purposes, a first current integrator 80 and a second integrator 86 are shown. A current mirror 74 is provided in the second row. The current mirror 74 is connected in series with the first current integrator 80 and the second current integrator 86.

[0052] The current mirror 74 includes two PFETs 75 and 76, a single NFET 78, and two operational amplifiers 77 and 79.

[0053] When input pulse 16 enters the array, current flows from the left legs of elements 80 and 86 through resistive memories 30 and 32 to the right leg of element 70. The current is then advantageously amplified by 1 / N and mirrored to the left leg of element 70. These behaviors advantageously occur in each row and column. The mirrored current is collected in the leftmost line, and the collected current is supplied from the left leg of element 74. The collected current is then mirrored to the right leg of element 74, and then advantageously copied from the integrating capacitors 85 and 92 in each column N and discharged.

[0054] Elements 80 and 86 are current integrators containing two current mirrors and one integrating capacitor. Current integrator 80 contains two PFETs 81 and 82 and a single NFET 84, as well as an integrating capacitor 85. Current integrator 80 further contains an operational amplifier 83. Similarly, integrator 86 contains two PFETs 87 and 88 and a single NFET 90, as well as an integrating capacitor 92. Current integrator 86 further contains an operational amplifier 89.

[0055] The NFET current mirror has only one leg. A pair of common sensing legs is located on the right leg of element 74. Elements 80 and 86 can also be called "neuron circuits." The voltages on integrating capacitors 85 and 92 are typically converted to digital bits by an analog-to-digital converter (ADC), so that the connected system can use the output data as digital data.

[0056] Each of the circuit diagrams in Figures 2 to 4 can be advantageously implemented by an artificial intelligence (AI) accelerator chip, as shown below with reference to Figure 10.

[0057] Figure 5 is a block / flow diagram of a method for advantageously employing a current mirror to accelerate multiply-accumulate (MAC) operations according to an embodiment of the present invention.

[0058] In block 96, multiple synaptic array cells are connected by a circuit so that each synaptic array cell is assigned to rows and columns of an array, each synaptic array cell having a single polar synaptic weight, each row being connected to each input terminal of the synaptic array cell, and each column being connected to each output terminal of the synaptic array cell, and the synaptic array cells aligned in columns of an array are defined as an operational column array.

[0059] In block 98, an array of current mirrors is employed, each current mirror exhibiting a mirror ratio of N:1, where N is the number of rows of synaptic cells, and connected to each row, configured such that the weights corresponding to all mirrored currents are set to the average weights of all synaptic cells that are favorably updated during the learning phase.

[0060] Figure 6 shows an exemplary neuromorphic and synaptronic network according to an embodiment of the present invention, including a crossbar of electronic synapses interconnecting electronic neurons and axons.

[0061] An example tile circuit 100 has a crossbar 112 according to an embodiment of the present invention. In one embodiment, the entire circuit may include an "ultra-high density crossbar array" having a pitch in the range of about 10 nm to 500 nm. However, those skilled in the art will also be able to consider smaller and larger pitches. The neuromorphic and synaptronic circuit 100 includes a crossbar 112 interconnecting a plurality of digital neurons 111, including neurons 114, 116, 118, and 120. These neurons 111 are also referred to herein as "electronic neurons". For illustrative purposes, the example circuit 100 provides a symmetrical connection between two pairs of neurons (e.g., N1 and N3). However, embodiments of the present invention are useful not only for symmetrical connections of neurons but also for asymmetric connections of neurons (neurons N1 and N3 do not need to be connected by the same connection). The crossbars in the tile adapt to an appropriate ratio of synapses to neurons and therefore do not need to be square.

[0062] In the example circuit 100, neuron 111 is connected to the crossbar 112 via dendritic paths / wires (dendritic processes) 113, such as dendrites 126 and 128. Neuron 111 is also connected to the crossbar 112 via axonal paths / wires (axons) 115, such as axons 134 and 136. Neurons 114 and 116 are dendritic neurons, and neurons 118 and 120 are axonal neurons connected to axon 113. Specifically, neurons 114 and 116 are shown with outputs 122 and 124 connected to dendrites (e.g., bit lines) 126 and 128, respectively. Axonal neurons 118 and 120 are shown with outputs 130 and 132 connected to axons (e.g., word lines or access lines) 134 and 136, respectively.

[0063] When any of neurons 114, 116, 118, and 120 fire, they send pulses to their axonal and dendritic connections. Each synapse provides a point of contact between the axon of one neuron and the dendrites of another neuron, and with respect to the synapse, the two neurons are called the presynaptic and postsynaptic, respectively.

[0064] Each connection between dendrites 126, 128 and axons 134, 136 is made through a digital synaptic device 131 (synapse). The junction where the synaptic device is located may be referred to herein as a “crosspoint junction.” Generally, according to embodiments of the present invention, neurons 114 and 116 “fire” (send a pulse) in response to the input they receive from an axonal input connection (not shown) exceeding a threshold.

[0065] Synapse 131 may include resistive memories 30, 32. Synapse 131 may include current integrators 50, 60 in Figure 3 or current integrators 80, 86 in Figure 4. Synapse 131 may further include any type of current mirror described herein. Thus, those skilled in the art can consider all of the circuit elements in Figures 2 to 4 that are advantageously incorporated into or embedded in synapse 131 of circuit 100.

[0066] Neurons 118 and 120 “fire” (send pulses) in response to input exceeding a threshold, typically received from other neurons, via an external input connection (not shown). In one embodiment, when neurons 114 and 116 fire, they maintain decaying postsynaptic spike timing-dependent plasticity (STDP) (post-STDP) variables. For example, in one embodiment, the decay period may be 50 μs (1000 times shorter than in actual biological systems, corresponding to a 1000 times faster operating speed). Post-STDP variables are employed to achieve STDP by encoding the time since the last firing of the associated neuron. Such STDP is used to control long-term potentiation or “enhancement,” which in this context is defined as increasing synaptic conductance. When neurons 118 and 120 fire, they maintain pre-STDP (pre-synaptic STDP) variables that decay in a similar manner to neurons 114 and 116.

[0067] Pre-STDP and post-STDP variables may decay according to, for example, an exponential, linear, polynomial, or quadratic function. In another embodiment of the invention, the variable may increase instead of decreasing over time. At any given event, this variable may be used to achieve STDP by encoding the time since the last firing of the associated neuron. STDP is used to control long-term decay or "decay," which in this context is defined as decreasing synaptic conductance. The roles of the pre-STDP and post-STDP variables are reversed, with pre-STDP performing enhancement and post-STDP performing decay.

[0068] An external bidirectional communication environment can supply sensory input and consume motor output. Digital neurons 111, implemented using complementary metal-oxide-semiconductor (CMOS) logic gates, receive and integrate spike inputs. In one embodiment, neuron 111 includes a comparator circuit that generates a spike when the integral input exceeds a threshold. In one embodiment, the synapse is implemented using flash memory cells, and each neuron 111 may be an excitatory or inhibitory neuron (or both). Each learning rule for each neuron axon and dendrite is reconfigurable as described below. This assumes transferable access to a crossbar memory array. A spiking neuron is selected one at a time to send a spike event to the corresponding axon, which may be on a core or somewhere in a larger system with many cores.

[0069] As used herein, the term "electron neuron" refers to an architecture configured to simulate a biological neuron. An electronic neuron generates connections between processing elements that are broadly functionally equivalent to neurons in a biological brain. Therefore, neuromorphic and synaptronic systems including electronic neurons according to embodiments of the present invention may include various electronic circuits modeling biological neurons, but which, in many useful embodiments, can operate on a faster timescale (e.g., 1000 times) than their biological counterparts. Furthermore, neuromorphic and synaptronic systems including electronic neurons according to embodiments of the present invention may include various processing elements (including computer simulations) modeling biological neurons. While one exemplary embodiment of the present invention is described herein using an electronic neuron including an electronic circuit, the present invention is not limited to electronic circuits. Neuromorphic and synaptronic systems according to embodiments of the present invention can be implemented as neuromorphic and synaptronic architectures including circuits, and in addition, as computer simulations. In fact, embodiments of the present invention may take the form of complete hardware embodiments, complete software embodiments, or embodiments including both hardware and software elements.

[0070] Figure 7 is a block diagram of the components of a computing system according to an embodiment of the present invention, which includes a computing device and a neuromorphic chip capable of employing unit cells, synaptic weights, or both.

[0071] Figure 7 shows a block diagram of the components of system 200, including computing device 205. Figure 7 should be understood to provide merely an example of one embodiment and not imply any limitation regarding the environment in which different embodiments may be implemented. Many modifications may be made to the illustrated environment.

[0072] The computing device 205 includes a communication fabric 202, which provides communication between the computer processor 204, memory 206, persistent storage 208, communication unit 210, and input / output (I / O) interface 212. The communication fabric 202 can be implemented in any architecture designed to pass data, control information, or both, between processors (such as microprocessors, communication and network processors), system memory, peripheral devices, and any other hardware components in the system. For example, the communication fabric 202 can be implemented on one or more buses.

[0073] Memory 206, cache memory 216, and persistent storage device 208 are computer-readable storage media. In this embodiment, memory 206 includes random-access memory (RAM) 214. In another embodiment, memory 206 may be flash memory. In general, memory 206 may include any suitable volatile or non-volatile computer-readable storage media.

[0074] In some embodiments of the present invention, the deep learning program 225 is included in and operated by the neuromorphic chip 222 as a component of the computing device 205. In other embodiments, the deep learning program 255 is stored in a persistent storage device 208 for execution by the neuromorphic chip 222 in combination with one or more of the respective computer processors 204 via one or more memories of memory 206. In this embodiment, the persistent storage device 208 includes a magnetic hard disk drive. As an alternative to, or in addition to, a magnetic hard disk drive, the persistent storage device 208 may include a solid-state hard drive, a semiconductor storage device, read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, or any other computer-readable storage medium capable of storing program instructions or digital information.

[0075] The medium used by the persistent storage device 208 may also be removable. For example, a removable hard drive may be used for the persistent storage device 208. Other embodiments include optical and magnetic disks, thumb drives, and smart cards inserted into a drive for transfer to another computer-readable storage medium which is also part of the persistent storage device 208.

[0076] In these embodiments, the communication unit 210 provides communication with other data processing systems or devices, including resources of a distributed data processing environment. In these embodiments, the communication unit 210 includes one or more network interface cards. The communication unit 210 may provide communication through the use of either or both physical communication links and wireless communication links. The deep learning program 225 may be downloaded to the persistent storage device 208 through the communication unit 210.

[0077] The I / O interface 212 enables data input and output with other devices that may be connected to the computing system 200. For example, the I / O interface 212 may provide connection to an external device 218 such as a keyboard, keypad, touchscreen, or any other suitable input device, or a combination thereof. The external device 218 may also include portable computer-readable storage media such as thumb drives, portable optical or magnetic disks, and memory cards.

[0078] The display 220 provides a mechanism for displaying data to the user and may be, for example, a computer monitor.

[0079] Figure 8 is a block / flow diagram of an exemplary cloud computing environment according to an embodiment of the present invention.

[0080] While this invention includes a detailed description of cloud computing, it should be understood that the embodiments of the teachings enumerated herein are not limited to cloud computing environments. Rather, embodiments of this invention can be implemented in conjunction with any other type of computing environment that is currently known or may be developed in the future.

[0081] Cloud computing is a service delivery model that enables convenient on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly supplied and released with minimal administrative effort or interaction with service providers. This cloud model may include at least five characteristics, at least three service models, and at least four deployment models.

[0082] The characteristics are as follows:

[0083] On-demand self-service: Cloud consumers can unilaterally access computing capabilities such as server time and network storage as needed, automatically and without requiring human interaction with service providers.

[0084] Broad network access: Capabilities are available over the network and accessed through standard mechanisms that facilitate use by heterogeneous thin-client or thick-client platforms (e.g., mobile phones, laptops, and PDAs).

[0085] Resource sharing: A provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, with different physical and virtual resources dynamically allocated and reallocated as needed. Location independence has implications in that consumers generally do not have control or knowledge of the exact location of the resources provided, but may be able to specify the location at a higher level of abstraction (e.g., country, state, or data center).

[0086] Rapid Scalability: Capabilities can be supplied quickly and flexibly to scale out instantly, sometimes automatically, and released quickly to scale in instantly. To consumers, the available capabilities for supply often appear unlimited and can be purchased at any quantity at any time.

[0087] Measurable Services: Cloud systems automatically control and optimize resource usage by leveraging measurable capabilities at a level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both service providers and consumers.

[0088] The service model is as follows:

[0089] Software as a Service (SaaS): The capability offered to consumers is the use of a provider's applications running on cloud infrastructure. These applications are accessible from various client devices through thin-client interfaces such as web browsers (e.g., web-based email). Consumers do not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, storage, or even individual application capabilities, with the exception of potentially limited user-specific application configuration settings.

[0090] Platform as a Service (PaaS): The capability offered to consumers is the deployment of consumer-created or acquired applications, written using programming languages ​​and tools supported by the provider, onto cloud infrastructure. Consumers do not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but they have control over the deployed applications and, where possible, the application hosting environment configuration.

[0091] Infrastructure as a Service (IaaS): The capabilities offered to consumers are the provision of processing, storage, networking, and other basic computing resources that enable consumers to deploy and run any software, including operating systems and applications. Consumers do not manage or control the underlying cloud infrastructure, but they do have control over the operating system, storage, and deployed applications, and, where possible, limited control over select networking components (e.g., host firewalls).

[0092] The deployment model is as follows:

[0093] Private Cloud: The cloud infrastructure operates solely for the organization. The cloud infrastructure is managed by the organization or a third party and may reside on-premises or off-premises.

[0094] Community Cloud: Cloud infrastructure is shared by multiple organizations to support a specific community with shared concerns (e.g., missions, security requirements, policies, and compliance considerations). The cloud infrastructure is managed by the organization or a third party and may reside on-premises or off-premises.

[0095] Public Cloud: Cloud infrastructure is made available to the general public or large industry groups and is owned by organizations that sell cloud services.

[0096] Hybrid Cloud: Cloud infrastructure remains a unique entity, but it is a composite of two or more clouds (private, community, or public) joined together by standardized or proprietary technologies (e.g., cloud bursting for load balancing between clouds) that enable data and application portability.

[0097] Cloud computing environments are service-oriented, centered on statelessness, low coupling, modularity, and semantic interoperability. At the heart of cloud computing is the infrastructure, including a network of interconnected nodes.

[0098] Referring here to Figure 8, an exemplary cloud computing environment 350 for enabling a use case of the present invention is shown. As illustrated, the cloud computing environment 350 includes one or more cloud computing nodes 310 to which local computing devices used by cloud consumers, such as a personal digital assistant (PDA) or mobile phone 354A, a desktop computer 354B, a laptop computer 354C, or an automotive computer system 354N, or a combination thereof, can communicate. The nodes 310 can communicate with each other. They can be grouped physically or virtually within one or more networks, such as a private cloud, community cloud, public cloud, or hybrid cloud, or a combination thereof, as described above (not shown). This makes it possible for the cloud computing environment 350 to offer infrastructure, platforms, or software, or a combination thereof, as a service that does not require cloud consumers to maintain resources on their local computing devices. The types of computing devices 354A-N shown in Figure 8 are intended to be illustrative only, and it should be understood that the computing node 310 and the cloud computing environment 350 may communicate with any type of computerized device via any type of network or network-addressable connection or both (for example, using a web browser).

[0099] Figure 9 is a schematic diagram of an exemplary abstract model layer according to an embodiment of the present invention. The components, layers, and functions shown in Figure 9 are intended to be illustrative only, and embodiments of the present invention are not limited thereto. As illustrated, the following layers and corresponding functions are provided:

[0100] The hardware and software layer 460 includes hardware and software components. Examples of hardware components include a mainframe 461, a RISC (Reduced Instruction Set Computer) architecture-based server 462, a server 463, a blade server 464, a storage device 465, and network and networking components 466. In some embodiments, the software components include network application server software 467 and database software 468.

[0101] The virtualization layer 470 provides an abstraction layer from which the following examples of virtual entities may be provided: virtual servers 471, virtual storage 472, virtual networks 473 including virtual private networks, virtual applications and operating systems 474, and virtual clients 475.

[0102] In one embodiment, the management layer 480 may provide the functions described below. Resource supply 481 provides dynamic procurement of computing resources and other resources used to perform tasks within the cloud computing environment. Measurement and pricing 482 provides cost tracking when resources are used within the cloud computing environment and charges or invoices are issued for the consumption of these resources. In one embodiment, these resources may include application software licenses. Security provides identity verification for cloud consumers and tasks, as well as protection for data and other resources. User portal 483 provides consumers and system administrators with access to the cloud computing environment. Service level management 484 provides cloud computing resource allocation and management to ensure that the required service levels are met. Service level agreement (SLA) planning and execution 485 provides pre-positioning and procurement of cloud computing resources where future requirements are anticipated in accordance with the SLA.

[0103] The workload layer 490 provides embodiments of functionality that can be utilized in a cloud computing environment. Examples of workloads and functions that can be provided from this layer include mapping and navigation 441, software development and lifecycle management 492, virtual classroom education delivery 493, data analysis processing 494, transaction processing 495, and a single device 496 for synaptic weights.

[0104] Figure 10 shows a practical application of employing a current mirror to accelerate MAC calculations according to an embodiment of the present invention.

[0105] The artificial intelligence (AI) accelerator chip 501 may be used in a wide range of real-world applications, including, but not limited to, robotics 510, industrial applications 512, mobile or Internet of Things (IoT) 514, personal computing 516, consumer electronics 518, servers and data centers 520, physical and chemical applications 522, healthcare applications 524, and financial applications 526. The AI ​​accelerator chip 501 may employ the circuits shown in Figures 2–4, including the current mirror and current integrator described.

[0106] For example, Robotic Process Automation, or RPA510, enables organizations to automate tasks, streamline processes, improve employee productivity, and ultimately deliver a satisfying customer experience. Through the use of RPA510, robots can perform a large volume of repetitive tasks, freeing up company resources to focus on higher-value activities. The RPA robot 510 emulates a person performing manual, repetitive tasks, making decisions based on a set of predefined rules and integrating with existing applications. It does all of this while maintaining compliance, reducing errors, and improving customer experience and employee engagement. The AI ​​accelerator chip 510, employing the circuits shown in Figures 2-4, can extend the RPA510.

[0107] Figure 11 is a block / flow diagram of a method for advantageously employing current mirroring to accelerate MAC computation in an Internet of Things (IoT) system / device / infrastructure, according to an embodiment of the present invention.

[0108] According to some embodiments of the present invention, the network is implemented using IoT methodologies. For example, the AI ​​accelerator chip 501 may be incorporated into, for example, wearable, implantable, or ingestible electronic devices and Internet of Things (IoT) sensors. Wearable, implantable, or ingestible devices may include at least health and wellness monitoring devices, as well as fitness devices. Wearable, implantable, or ingestible devices may further include at least implantable devices, smartwatches, head-mounted devices, security and prevention devices, as well as gaming and lifestyle devices. IoT sensors may be incorporated into at least home automation applications, automotive applications, user interface applications, lifestyle or entertainment applications or both, urban or infrastructure applications or both, toys, healthcare, fitness, retail, tags or trackers or both, platforms and components, etc. The AI ​​accelerator chip 501 described herein may be incorporated into any type of electronic device for any type of use or application or operation.

[0109] IoT systems enable users to achieve deeper automation, analysis, and integration within the system. IoT improves these areas and the range of their precision. IoT leverages existing and advanced technologies for sensing, networking, and robotics. Features of IoT include artificial intelligence, connectivity, sensors, active engagement, and the use of small devices. In various embodiments, the AI ​​accelerator chip 501 of the present invention may be incorporated into a variety of different devices or systems, or both. For example, the AI ​​accelerator chip 501 may be incorporated into a wearable or portable electronic device 904. The wearable / portable electronic device 904 may include an embeddable device 940 such as smart clothing 943. The wearable / portable device 904 may include a smart watch 942 and smart jewelry 945. Wearable / portable devices 904 may further include fitness monitoring devices 944, health and wellness monitoring devices 946, head-mounted devices 948 (e.g., smart glasses 949), security and prevention systems 950, gaming and lifestyle devices 952, smartphones / tablets 954, media players 956, or computer / computing devices 958, or combinations thereof.

[0110] The AI ​​accelerator chip 501 of the present invention may be further incorporated into Internet of Things (IoT) sensors 906 for a variety of applications, such as home automation 920, automobiles 922, user interfaces 924, lifestyle or entertainment or both 926, cities or infrastructure or both 928, retail 910, tags or trackers or both 912, platforms and components 914, toys 930, or healthcare 932, or a combination thereof, as well as fitness 934. The IoT sensor 906 may employ the AI ​​accelerator chip 501. Naturally, those skilled in the art may consider incorporating such an AI accelerator chip 501 into any type of electronic device for any type of application, not limited to those described herein.

[0111] Figure 12 is a block / flow diagram of an exemplary IoT sensor used to advantageously collect data / information related to current mirrors that accelerate MAC calculations, according to an embodiment of the present invention.

[0112] Without sensors, the IoT loses its defining characteristics. IoT sensors act as defining instruments that transform the IoT from a standard passive network of devices into an integrated, active system in the real world.

[0113] The IoT sensor 906 employs an AI accelerator chip 501 to transmit information or data to any type of distributed system continuously and in real time via the network 908. Exemplary IoT sensors 906 may include, but are not limited to, a position / presence / proximity sensor 1002, a motion / velocity sensor 1004, a displacement sensor 1006 such as an acceleration / tilt sensor 1007, a temperature sensor 1008, a humidity / moisture sensor 1010, and a flow sensor 1011, an acoustic / sound / vibration sensor 1012, a chemical / gas sensor 1014, a force / load / torque / strain / pressure sensor 1016, or an electrical / magnetic sensor 1018, or a combination thereof. Those skilled in the art may consider using any combination of such sensors to collect data / information from a distributed system for further processing. Those skilled in the art may also consider using other types of IoT sensors, such as, but are not limited to, a magnetometer, gyroscope, image sensor, optical sensor, radio frequency identification (RFID) sensor, or micro-flow sensor, or a combination thereof. IoT sensors may also include energy modules, power management modules, RF modules, and sensing modules. RF modules manage their signal processing and communication through WiFi, ZigBee(R), Bluetooth(R), wireless transceivers, duplexers, etc.

[0114] The present invention may be a system, method, or computer program product, or a combination thereof. The computer program product may include a computer-readable storage medium having computer-readable program instructions thereon for causing a processor to perform an aspect of the present invention.

[0115] A computer-readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction-executing device. A computer-readable storage medium may, but is not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of those described above. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random-access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), static random-access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disks (DVDs), memory sticks, floppy(R) disks, mechanically encoded devices such as punch cards or grooved raised structures on which instructions are recorded, and any suitable combination of those described above. The computer-readable storage media used herein should not be interpreted as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmitting media (e.g., light pulses passing through optical fiber cables), or electrical signals transmitted through wires.

[0116] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device, or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface within each computing / processing device receives computer-readable program instructions from the network and transfers them for storage on the computer-readable storage medium within each computing / processing device.

[0117] The computer-readable program instructions for performing the operation of the present invention may be either source code or object code written in any combination of one or more programming languages, including assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or object-oriented programming languages ​​such as Smalltalk(R) and C++, and conventional procedural programming languages ​​such as the C programming language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (for example, via the Internet using an Internet service provider). In some embodiments, for example, an electronic circuit including a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer-readable program instructions by individualizing the electronic circuit using state information of computer-readable program instructions in order to carry out aspects of the present invention.

[0118] Aspects of the present invention are described herein with reference to flowcharts or block diagrams, or both, of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block in a flowchart or block diagram, or both, and any combination of blocks in a flowchart or block diagram, or both, can be implemented by computer-readable program instructions.

[0119] These computer-readable program instructions may be provided to at least one processor of a general-purpose computer, a dedicated computer, or other programmable data processing device for manufacturing machines, such that instructions executed by the processor of a computer or other programmable data processing device generate means for performing functions / operations specified in one or more blocks or modules of a flowchart or block diagram or both. These computer-readable program instructions may also be stored in a computer-readable storage medium that can instruct a computer, a programmable data processing device, or other device, or a combination thereof, to function in a particular way.

[0120] Computer-readable program instructions can also be loaded onto a computer, other programmable data processing device, or other device to execute a series of action blocks / steps on the computer, other programmable device, or other device to create a computer-executed process, so that the instructions executed on the computer, other programmable device, or other device perform functions / actions specified in one or more blocks or modules of a flowchart or block diagram, or both.

[0121] The flowcharts and block diagrams in the drawings illustrate the architecture, functionality, and operation of possible embodiments of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or part of an instruction containing one or more executable instructions for performing a specified logical function. In some alternative embodiments, the functions described within a block may occur in an order other than that shown in the drawings. For example, two consecutively shown blocks may actually be executed substantially simultaneously, or blocks may be executed in reverse order depending on the functionality involved. It should also be noted that each block in a block diagram or flowchart, or both, and any combination of blocks in a block diagram or flowchart, or both, may be implemented by a dedicated hardware-based system that performs a specified function or operation, or executes a combination of dedicated hardware and computer instructions.

[0122] Any reference in the specification to “one embodiment” or “embodiment” of the Principle, and any other variations thereof, means that certain features, structures, properties, etc., described in relation to the embodiment are included in at least one embodiment of the Principle. Therefore, the appearance of the phrase “in one embodiment” or “in an embodiment” and any other variations, appearing in various places throughout the specification, does not necessarily all refer to the same embodiment.

[0123] The use of any of the following " / ", "and / or", and "at least one of" should be understood as being intended to include, for example, "A / B", "A and / or B", and "at least one of A and B", the selection of only the first listed option (A), or only the second listed option (B), or the selection of both options (A and B). As further examples, in the case of "A, B, and / or C" and "at least one of A, B, and C", such expressions are intended to include the selection of only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or the selection of all three options (A, B, and C). This can also be extended to cases where many items are listed, as will be readily apparent to those skilled in the art in this and related fields.

[0124] While preferred embodiments of a scalable and immediate biasing scheme for a single-device synaptic element have been described (intended to be illustrative and not limiting), it should be noted that modifications and variations may be made in light of the above teachings by those skilled in the art. Therefore, it should be understood that modifications may be made in the specific embodiments described, within the scope of the invention outlined by the attached claims. Thus, while aspects of the invention have been described with the details and specificities required by patent law, what is claimed and desired and protected by patent certificate is stated in the attached claims.

Claims

1. It is a neuromorphic synaptic array, A plurality of synaptic array cells, each synaptic array cell being connected by a circuit to be assigned to rows and columns of an array, wherein each synaptic array cell has a single-polarity synaptic weight, each row is connected to each input terminal of the synaptic array cell, each column is connected to each output terminal of the synaptic array cell, and the synaptic array cells aligned in the columns of the array are defined as an arithmetic column array, An array of current mirrors connected to the array, wherein each current mirror exhibits a mirror ratio of N:1, where N is the number of rows of the synaptic array cell, and each current mirror is connected to the array of current mirrors connected to each of the rows. Equipped with, A weight corresponding to the sum of the mirror currents collected by the current mirror is set as the average weight for the entire synaptic array cell, and the average weight is configured to be updated during the learning phase to shift the MAC result. Neuromorphic synaptic array.

2. The neuromorphic synaptic array according to claim 1, wherein at least a portion of the plurality of synaptic array cells include resistive memory.

3. The neuromorphic synaptic array according to claim 1 or 2, further comprising current integrators connected to each of the aforementioned rows.

4. The neuromorphic synaptic array according to claim 1, wherein the configuration of at least one of the current mirrors includes two n-type field-effect transistors (NFETs).

5. The neuromorphic synaptic array according to claim 1, wherein the configuration of at least one of the current mirrors comprises two p-type field-effect transistors (PFETs) and a single NFET.

6. The neuromorphic synaptic array according to claim 1, wherein the configuration of at least one of the current mirrors includes two NFETs and a single operational amplifier (op-amp).

7. The neuromorphic synaptic array according to claim 1, wherein the configuration of at least one of the current mirrors includes two PFETs, a single NFET, and two operational amplifiers.

8. The neuromorphic synaptic array according to claim 3, wherein the configuration of at least one of the current integrators comprises two PFETs, a single NFET, and an integrating capacitor.

9. The neuromorphic synaptic array according to claim 3, wherein the configuration of at least one of the current integrators includes two PFETs, a single NFET, an operational amplifier, and an integrating capacitor.

10. The neuromorphic synaptic array according to claim 8 or 9, wherein the integrating capacitor receives the collected Miller current, copies the collected Miller current, and discharges the collected Miller current.

11. It is a neuromorphic synaptic array, A plurality of synaptic array cells, each synaptic array cell being connected by a circuit to be assigned to rows and columns of an array, wherein each synaptic array cell has a single-polarity synaptic weight, each row is connected to each input terminal of the synaptic array cell, each column is connected to each output terminal of the synaptic array cell, and the synaptic array cells aligned in the columns of the array are defined as an arithmetic column array, An array of current mirrors connected to the array, wherein each current mirror exhibits a mirror ratio of N:1, where N is the number of rows of the synaptic array cell, and each current mirror is connected to the array of current mirrors connected to each of the rows. An array of current integrators connected to the array, wherein each current integrator is connected to each of the rows, and each current integrator includes an integrating capacitor connected to the array of current mirrors, Equipped with, The mirror currents collected by the current mirrors are mirrored to each current integrator, and a weight corresponding to the sum of the mirror currents is set as the average weight for the entire synaptic array cell, and the average weight is configured to be updated during the learning phase to shift the MAC results in each of the operation sequences. Neuromorphic synaptic array.

12. A computer implementation method, The circuit connects a plurality of synaptic array cells such that the synaptic array cells are assigned to rows and columns of an array, wherein each synaptic array cell has a single-polarity synaptic weight, each row is connected to each input terminal of the synaptic array cell, each column is connected to each output terminal of the synaptic array cell, and the synaptic array cells aligned in the columns of the array are defined as an arithmetic column array. Connecting an array of current mirrors to the aforementioned array, wherein each current mirror exhibits a mirror ratio of N:1, where N is the number of rows of the synaptic array cells, and each current mirror is connected to each of the rows, The array of current mirrors is configured such that the weight corresponding to the sum of the mirror currents collected by the current mirrors is set as the average weight of the entire synaptic array cell, wherein the average weight is updated during the learning phase to shift the MAC result. Computer implementation methods, including those mentioned above.

13. The computer implementation method according to claim 12, further comprising connecting a current integrator to each of the aforementioned rows.

14. A computer implementation method, The circuit connects a plurality of synaptic array cells such that the synaptic array cells are assigned to rows and columns of an array, wherein each synaptic array cell has a single-polarity synaptic weight, each row is connected to each input terminal of the synaptic array cell, each column is connected to each output terminal of the synaptic array cell, and the synaptic array cells aligned in the columns of the array are defined as an arithmetic column array. Connecting an array of current mirrors to the aforementioned array, wherein each current mirror exhibits a mirror ratio of N:1, where N is the number of rows of the synaptic array cells, and each current mirror is connected to each of the rows, Connecting an array of current integrators to the array, wherein each current integrator is connected to each column of the array, and each current integrator includes an integrating capacitor connected to the array of current mirrors, The array of current mirrors is configured such that the mirror currents collected by the current mirrors are mirrored to each of the current integrators, and the weights corresponding to the sum of the mirror currents are set as the average weights for the entire synaptic array cell, wherein the average weights are updated during the learning phase to shift the MAC results in each of the operation sequences. Computer implementation methods, including those mentioned above.

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