Nano-tipped filament confinement

Abstract

Methods for forming a configurable resistive device, a configurable resistive device, and a neuromorphic computing device include isotropically etching a layer stack, the layer stack having an insulator layer in contact with a conductor layer, and selectively forming a divot in an exposed sidewall of the conductor layer. The layer stack is isotropically etched to selectively form a divot in an exposed sidewall of the insulator layer, thereby forming a peak at an interface between the insulator layer and the conductor layer. A dielectric layer is formed over the layer stack to cover the peak. An electrode is formed over the dielectric layer such that the dielectric layer is between the electrode and the peak.

Description

Technical Field

[0001] The present invention relates generally to semiconductor device manufacturing, and more particularly to the manufacture of resistive random access memory (RRAM) cells.

Background Art

[0002] RRAM is a type of memory that encodes information in the resistance state of RRAM cells. For example, an RRAM cell can have various different physical states that it can take, and each cell can have a different resistance. The value stored in an RRAM cell can be read by applying a voltage to the RRAM cell and measuring the resulting current. The resistance of the RRAM cell can then be determined from the measured current.

Summary of the Invention

[0003] A method of forming a programmable resistive device includes isotropically etching a stack of layers having an insulator layer contacting a conductor layer, and selectively forming divots on exposed sidewalls of the conductor layer. The stack of layers is isotropically etched to selectively form divots on exposed sidewalls of the insulator layer, thereby forming pointed ends at an interface between the insulator layer and the conductor layer. A dielectric layer is formed over the stack of layers to cover the pointed ends. An electrode is formed over the dielectric layer such that the dielectric layer is between the electrode and the pointed ends.

[0004] A programmable resistive cell includes a stack of layers including an insulator layer contacting a conductor layer, each having a concave sidewall surface intersecting at an interface between the insulator layer and the conductor layer to form pointed ends that concentrate electric field strength. A dielectric layer is formed over the stack of layers to cover the pointed ends. An electrode is formed over the dielectric layer such that the dielectric layer is positioned between the electrode and the pointed ends.

[0005] The neuromorphic computing device includes an array of configurable resistor cells. Each configurable resistor cell includes a laminate of layers, each having a concave sidewall surface that intersects at the interface between the insulating layer and the conductive layer to form a tip that concentrates the electric field strength; a dielectric layer formed on the laminate of layers covering the tip; and an electrode formed on the dielectric layer such that the dielectric layer is located between the electrode and the tip.

[0006] These features and other features and advantages will become apparent from the following detailed description of exemplary embodiments of the invention, which should be read in conjunction with the accompanying drawings.

[0007] The following description will provide details of a preferred embodiment with reference to the following diagram. [Brief explanation of the drawing]

[0008] [Figure 1] This is a cross-sectional view of a step in forming a device having a configurable resistance, showing a laminate of alternating insulating and conductive layers according to an embodiment of the present invention. [Figure 2] This is a cross-sectional view of a step in forming a device having configurable resistance, in which a laminate of alternating insulating and conductive layers is patterned to form a device laminate, according to an embodiment of the present invention. [Figure 3] This is a cross-sectional view of a step in forming a device having configurable resistance, showing an etch that creates a divot on the sidewall of a conductor layer, according to an embodiment of the present invention. [Figure 4] This is a cross-sectional view of a step in forming a device having configurable resistance, showing an etch according to an embodiment of the present invention, which creates a concave divot on the sidewall of the insulator layer to form a tip at the interface of the insulator layer with the conductor layer. [Figure 5] This is a cross-sectional view of a step in forming a device having configurable resistance, showing the formation of a dielectric layer on a device stack according to an embodiment of the present invention. [Figure 6] This is a cross-sectional view of a step in forming a device having a configurable resistance, showing the formation of an upper electrode on a device stack according to an embodiment of the present invention. [Figure 7] This is a top-down diagram of the steps in forming a device having configurable resistance, showing the positions of the device stack and upper electrode according to an embodiment of the present invention. [Figure 8] This is a cross-sectional view of a step in forming a device having configurable resistance, showing the formation of a word line electrode through a device stack according to an embodiment of the present invention. [Figure 9] This is a cross-sectional view of a step in forming a device having configurable resistance, showing the formation of a number of word wire electrodes that contact each conductor layer within a device stack, according to an embodiment of the present invention. [Figure 10] This is a cross-sectional view of a step in forming a device having a configurable resistance, showing the formation of a plurality of word line electrodes and a plurality of bit line electrodes according to an embodiment of the present invention. [Figure 11] This is a block / flow diagram of a method for forming a device having a configurable resistance according to an embodiment of the present invention. [Figure 12] This is a diagram of an artificial neural network that can be implemented using a device having a configurable resistor, according to an embodiment of the present invention. [Figure 13] This is a diagram of a neuromorphic computing device capable of implementing an artificial neural network using configurable resistance cells, according to an embodiment of the present invention. [Modes for carrying out the invention]

[0009] Resistive random-access memory (RRAM) cells can be formed using memristor elements, for example, made from hafnium oxide. During operation, defects can form within the dielectric material, which can be programmed to correspond to different resistive states. For example, a low-resistance state can be considered equivalent to logic "1," while a high-resistance state corresponds to logic "0." Thus, an RRAM cell can have a configurable resistance. Changes between these states can be electrically triggered, for example, by changing the polarity of the electric field across the memristor element. Such RRAM cells can be used for classical memory applications, as well as in neuromorphic computing applications where resistive memory cells are used to perform calculations in neural network models.

[0010] One method for implementing memristor elements is to use a hafnium oxide dielectric layer. Conductive filaments may form within the hafnium oxide under a suitable electric field, providing conductive paths through the dielectric layer. However, the formation of such filaments is random and, as the cell size scales down, is accompanied by significant edge effects due to etching damage. To localize the formation of such filaments, structures with pointed tips that are useful for concentrating the electric field may be formed. This allows for a lower control voltage, and the likelihood of filament formation increases compared to the likelihood of filament formation in less useful locations. Thus, filaments may preferentially form on structures with pointed tips. In terms of voltage, RRAM cells without pointed tips to increase electric field strength operate at voltages between approximately 1V and 3V, while RRAM cells with such pointed structures can operate at significantly lower voltages. In one specific example, an RRAM cell with a pointed structure can operate at approximately 0.5V or less.

[0011] During operation, filaments can form within the dielectric layer through oxidation-reduction reactions. Mechanisms involved include electrochemical metallization (ECM) and valence-change memory (VCM). In ECM, conductive paths in the switching layer may be formed by metal cations of electrochemically active electrodes under an electric field. In VCM, anion migration (e.g., oxygen vacancies) contributes to the formation of conductive paths within the oxide layer. VCM may utilize an oxygen-trapping layer to facilitate anion movement between electrodes.

[0012] Referring to Figure 1, a cross-sectional view of one step in the formation of an RRAM cell is shown. A stack of layers 110 is formed on a substrate 102. The stack 110 alternates between dielectric layers 104 and conductive layers 106, with the bottom layer of dielectric layer 104 positioned below the bottom layer of conductive layer 106 to prevent leakage current between the conductive layer 106 and the substrate 102. For simplicity of explanation, seven layers are shown in the stack 110, but it should be understood that any appropriate number of layers may be used. For example, a structure formed in a process designed around NAND memory may have hundreds of layers.

[0013] The substrate 102 may be a bulk semiconductor substrate. In one example, the bulk semiconductor substrate may be a silicon-containing material. Specific examples of silicon-containing materials suitable for bulk semiconductor substrates include, but are not limited to, silicon, silicon-germanium, silicon-germanium carbide, silicon carbide, polysilicon, epitaxial silicon, amorphous silicon, and multilayers thereof. Although silicon is the primary semiconductor material used in wafer manufacturing, alternative semiconductor materials such as germanium, gallium arsenide, gallium nitride, cadmium telluride, and zinc selenide may also be used, though not limited to these. Although not shown in this figure, the substrate 102 may also be a semiconductor-on-insulator (SOI) substrate.

[0014] In addition, the substrate 102 may be a device layer including a variety of different components, including active devices such as transistors, passive electrical devices such as resistors, capacitors, or inductors, conductive wirings, vias, and interconnects such as contacts, and insulating structures such as interlayer dielectrics and shallow trench isolation regions.

[0015] The conductor layer 106 can be specifically considered to be formed from titanium nitride or other titanium-based materials, tantalum-based materials (e.g., TaN), or tungsten-based materials (e.g., W x N y ), but it should be understood that any suitable conductive material can be used instead. Other exemplary conductive materials can include, for example, titanium, tantalum, tungsten, nickel, molybdenum, copper, platinum, silver, gold, ruthenium, iridium, rhenium, rhodium, cobalt, and alloys thereof.

[0016] The insulator layer 104 can be specifically considered to be formed from materials such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or silicon oxide (SiOx), but it should be understood that any suitable dielectric material can be used instead.

[0017] Referring now to FIG. 2, a cross-sectional view of a certain step in the formation of the RRAM cell is shown. The original layer stack 110 is patterned to form the device stack 202. The device stack 202 includes the exposed sidewalls of the dielectric layer 104 and the conductor layer 106.

[0018] Forming the device stack 202 from the laminate 110 may be performed using any suitable patterning process such as photolithography to form the mask 204, followed by one or more anisotropic etches. For example, reactive ion etching (RIE), which is a form of plasma etching, places the surface to be etched on an electrode supplied with radio frequency power during the etching. Further, during RIE, the surface to be etched is biased to accelerate etching species drawn from the plasma toward the surface, and the chemical etching reaction occurs in a direction perpendicular to the surface. Other examples of anisotropic etching that may be used at this point in the present invention include ion beam etching, plasma etching, or laser ablation.

[0019] Referring now to FIG. 3, a cross-sectional view of a step in the formation of an RRAM cell is shown. Selective isotropic etching, such as wet chemical etching or dry chemical etching, of the material of the conductor layer 106 is performed, leaving the dielectric layer 104 and the substrate 102 relatively undamaged. The etching forms a concave divot 302 in the sidewalls of the conductor layer 106. As used herein, the term "selective" with respect to a material removal process means that the rate of material removal for the first material is greater than the rate of removal for at least one other material of the structure to which the material removal process is applied.

[0020] Referring now to FIG. 4, a cross-sectional view of a step in the formation of an RRAM cell is shown. Selective isotropic etching, such as wet chemical etching or dry chemical etching, of the material of the insulator layer 104 is performed, leaving the conductor layer 106 relatively undamaged. The etching creates a concave divot 402 in the sidewalls of the insulator layer 104. It should be understood that the etching of the insulator layer 104 and the conductor layer 106 shown in FIGS. 3 and 4 may be performed in any suitable order.

[0021] Each of these isotropic etchings has a greater rate of material removal near the center of each layer, such that the concave divots 302 and 402 have curved profiles. At the boundary between each pair of dielectric layer 104 and conductive layer 106, these curved profiles intersect to create the pointed 404.

[0022] Referring here to Figure 5, a cross-sectional view of a step in the formation of an RRAM cell is shown. For example, a deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD) is used to conformally deposit a layer of dielectric material 502 so as to cover the tip 404 and the entire device stack 202. The dielectric material 502 can have a thickness of about 1 nm to about 15 nm (nanometers). Specific exemplary embodiments may have a thickness ranging from about 3 nm to about 9 nm. Specific exemplary embodiments may have a thickness ranging from about 4 nm to about 7 nm. In some embodiments, the RRAM dielectric material 502 is a high-k dielectric material. In some embodiments, the dielectric material 502 is a transition metal oxide. Examples of materials that may be suitable for RRAM cell dielectrics include nickel oxide, tantalum oxide, titanium oxide, hafnium oxide, tungsten oxide, zircon oxide, aluminum oxide, and strontium titanium oxide.

[0023] CVD is a deposition process in which the species to be deposited is formed as a result of chemical reactions between gaseous reactants at temperatures above room temperature (e.g., from about 25°C to about 900°C). The solid reaction products are deposited on the surface, forming a film, coating, or layer of solid products. Various CVD processes include, but are not limited to, atmospheric pressure CVD (APCVD), reduced pressure CVD (LPCVD), plasma CVD (PECVD), and organometallic CVD (MOCVD), and combinations thereof may also be used. In an alternative embodiment using ALD, the chemical precursors react with the material surface one at a time to deposit a thin film on the surface.

[0024] Referring here to Figure 6, a cross-sectional view of a step in the formation of an RRAM cell is shown. The upper electrode 602 is formed, for example, by conformally depositing a conductive material so as to cover the entire dielectric material 502. The upper electrode 602 may include a laminated structure of aluminum-containing alloys (e.g., TiAl, TiAlC, TaAl, or TaAlC), titanium, tantalum, a combination of at least one of the above, or a metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride). An exemplary laminated structure may include titanium nitride and TiAlC. The upper electrode 602 may further include a combination of tungsten, molybdenum, platinum, hafnium, copper, aluminum, gold, nickel, iridium, or at least one of the above.

[0025] During operation, the conductive layer 106 acts as the first electrode, and the upper electrode 602 acts as the second electrode. The current can pass across the dielectric material 502 and through the electrodes, determining the resistance of the dielectric material.

[0026] Referring now to Figure 7, a top-down view of the RRAM cell in Figure 6 is shown. This figure shows two cross-sections: cross-section A identifies the location of the cross-section shown in Figure 6, while cross-section B identifies the location of the cross-section, which will be referenced in the discussion below to illustrate a different interconnect location.

[0027] Referring now to Figure 8, a cross-sectional view of a step in the formation of an RRAM cell is shown. This figure is shown along cross-section B in Figure 7. This figure shows the upper electrode 602 on the device stack 202. A word line electrode 804 is formed in a via penetrating the device stack 202 and in contact with the conductor layer 106. The interlayer dielectric 802 is formed on the device stack 202 between the upper electrode 602 and the word line electrode 804. In this example, all of the conductor layers 106 are connected to one word line electrode 804.

[0028] Referring now to Figure 9, a cross-sectional view of a step in the formation of an alternative RRAM cell is shown. This figure is also shown along cross-section B in Figure 7. In this example, the device laminate 202 is etched into a stepped laminate 906 by etching each conductive layer 106 to different lengths. This is done by repeating masking and etching, so that each conductive layer 106 and the corresponding dielectric layer 104 are selectively etched according to their respective masks. Before etching the next layer, a new mask can be formed to protect a larger surface area of ​​the next layer.

[0029] Multiple different word line electrodes 904 are formed to contact different conductor layers 106. An interlayer dielectric 902 is formed around the upper electrode 602 and the numerous word line electrodes 904. In this way, the different conductor layers 106 can be addressed individually.

[0030] Referring now to Figure 10, a cross-sectional view of a step in the formation of an alternative RRAM cell is shown. This figure is also shown along cross-section B of Figure 7. In this example, a number of word line electrodes 904 may be formed, as in the example of Figure 9. In addition, this example shows multiple bit line electrodes 1002 instead of a single upper electrode 602. Any appropriate number of such bit line electrodes 1002 each contact the sidewall of the conductor layer 106 via the dielectric material 502.

[0031] Referring here to Figure 11, a method for forming an RRAM cell is shown. Block 1102 is formed by alternating deposition processes, for example, to create a laminate 110 of alternating dielectric layers 104 and conductive layers 106. Block 1104 is then patterned using, for example, a photolithography mask 204 and anisotropic etching to form a device laminate 202.

[0032] Block 1106 performs isotropic etching selectively on the conductive layer 106 to form divots 302 on the sidewalls of the conductive layer 106. Block 1108 performs isotropic etching selectively on the dielectric layer 104 to form divots 402 on the sidewalls of the dielectric layer 104. Blocks 1106 and 1108 may be performed in any order; for example, etching of the dielectric layer 104 may be performed before etching of the conductive layer 106.

[0033] Block 1110 deposits high-k dielectric material on tip 404 formed by the formation of divots 302 and 402, for example, using a conformal deposition process, to form a dielectric layer 502 on the device laminate 202. An upper electrode 602 is formed on the device laminate 202, providing an electrical connection to the conductor layer 106 via the dielectric layer 502. Block 1114 can form a word line electrode 804 that provides direct electrical contact to one or more conductor layers 106 by forming vias that penetrate the device laminate 202 and forming conductive material therein.

[0034] The present invention will be discussed with respect to a given illustrative architecture; however, it should be understood that other architectures, structures, substrate materials, and process features and steps may be modified within the scope of the invention.

[0035] When an element such as a layer, region, or substrate is said to be "on top of" or "covering" another element, it will also be understood that the aforementioned element may be directly on top of the other element or that there may be further intervening elements. In contrast, when an element is said to be "directly on top of" or "directly covering" another element, there are no intervening elements. When an element is said to be "connected to" or "joined" another element, it will also be understood that it may be directly connected to or joined to the other element, or that there may be intervening elements. In contrast, when an element is said to be "directly connected to" or "directly joined" another element, there are no intervening elements.

[0036] This embodiment may include a design for an integrated circuit chip, which may be created in a graphical computer programming language and stored on a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive, such as within a storage access network). If the designer does not manufacture the chip or the photolithography mask used to manufacture the chip, the designer may transmit the obtained design to such an entity directly or indirectly by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., via the Internet). The stored design is then converted to a format suitable for the manufacture of a photolithography mask (e.g., GDSII), which typically includes multiple copies of the chip design to be formed on a wafer. The photolithography mask is used to define areas of the wafer (or layers thereon, or both) to be etched or otherwise processed.

[0037] Methods such as those described herein may be used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw material wafer form (i.e., as a single wafer with a number of unpackaged chips), as bare dies, or in packaged form. In the latter case, the chips are mounted in single-chip packages (such as plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (such as ceramic carriers with single-sided or double-sided interconnections or embedded interconnections). In either case, the chips are then integrated with other chips or discrete circuit elements or other signal processing devices, or combinations thereof, as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product may be any product containing an integrated circuit chip, ranging from toys and other low-end applications to displays, keyboards or other input devices, and advanced computer products with central processors.

[0038] It should also be understood that the material compounds will be described with respect to the listed elements, for example, SiGe. These compounds contain different proportions of elements in the compound, for example, SiGe is Si x Ge 1-x This includes elements such as x being less than or equal to 1, etc. In addition, other elements may be included in the compound, and it will function as before according to this principle. Compounds containing additional elements will be called alloys here.

[0039] Any reference in the specification to “one embodiment” or “a embodiment” of the principle, as well as to other variations thereof, means that certain features, structures, properties, etc., described in relation to the embodiments are included in at least one embodiment of the principle. Thus, the phrases “in one embodiment” or “in a certain embodiment,” which appear in various places throughout the specification, as well as the appearance of any other variations, do not necessarily all refer to the same embodiment.

[0040] Please be aware that the use of any of the following " / ", "~ or... or both", and "~ at least one of" includes, for example, in the cases of "A / B", "A or B or both", and "at least one of A and B", the selection of only the first listed option (A), or only the second listed option (B), or the selection of both options (A and B). As further examples, in the cases of "A or B or C or a combination thereof" and "at least one of A, B, and C", such phrasing includes the selection of only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or the selection of all three options (A, B, and C). This may be extended to the extent that the many items listed are readily recognizable to those skilled in the art of this and related technologies.

[0041] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the embodiments described herein. As used herein, the singular forms “a,” “an,” and “the” also include the plural forms unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” or “including,” when used herein, identify the presence of the described feature or integer or step or operation or element or component or combination thereof, but do not exclude the presence or addition of one or more other features or integers or steps or operations or elements or components or groups thereof or combination thereof.

[0042] Terms indicating spatial relationships, such as "beneath," "below," "lower," "above," and "upper," may be used herein for ease of description to describe the relationship of one element or feature to another, as illustrated in the diagram. It will be understood that terms indicating spatial relationships encompass different orientations of the device in use or operation, in addition to the orientation depicted in the diagram. For example, if the device in the diagram is turned upside down, the element described as "below" or "below" the other element or feature should then be oriented "above" the other element or feature. Thus, the term "below" can encompass both upward and downward orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and descriptions of spatial relationships used herein may be interpreted accordingly. Furthermore, when a layer is said to be "between" two layers, it should be understood that there may be only that layer between the two layers, or there may be one or more intervening layers.

[0043] Although terms such as "first," "second," etc. may be used in this specification to describe various elements, it will be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, the first element discussed below may be named the second element without deviating from the scope of this concept.

[0044] In some embodiments, RRAM cells may be used for neuromorphic computing in neural networks. An artificial neural network (ANN) is an information processing system generated by a biological nervous system, such as the brain. One element of an ANN is the structure of the information processing system, which includes a large number of highly interconnected processing elements (called "neurons") that work in parallel to solve a particular problem. An ANN is further trained using a set of training data, with learning that includes adjustments to the weights that exist between the neurons. Through such a learning process, an ANN is configured for a specific application, such as pattern recognition or data classification.

[0045] Referring here to Figure 12, a generalized diagram of a neural network is shown. Although a specific structure of an ANN with three layers and a set number of fully connected neurons is shown, it should be understood that this is for illustrative purposes only. In fact, this embodiment can take any suitable form, including any number of layers and any one or more patterns of connections between them.

[0046] ANNs demonstrate the ability to derive meaning from complex or inaccurate data and can be used to extract patterns and detect trends that are too complex to be detected by humans or other computer-based systems. The structure of a neural network is generally known to have input neurons 1202 that provide information to one or more "hidden" neurons 1204. The connections 1208 between the input neurons 1202 and the hidden neurons 1204 are weighted, and these weighted inputs are then processed by the hidden neurons 1204 according to several functions within the hidden neurons 1204. These weights 1208 may be implemented using the configurable resistor devices described above.

[0047] There can be any number of layers of hidden neurons 1204, as well as neurons that perform different functions. Different neural network structures such as convolutional neural networks, max-out networks, etc., also exist, and the above may vary depending on the structure and function of the hidden layers, as well as the weight patterns between the layers. Individual layers can perform specific functions and may include convolutional layers, pooling layers, fully connected layers, softmax layers, or any other appropriate type of neural network layer. Finally, a set of output neurons 1206 receives and processes weighted input from the last set of hidden neurons 1204.

[0048] This represents a "feed-forward" computation in which information propagates from input neuron 1202 to output neuron 1206. Upon completion of the feed-forward computation, the output is compared to the desired output available from the training data. Errors related to the training data are then handled in a "back-propagation" computation, where hidden neuron 1204 and input neuron 1202 receive information about errors propagating backward from output neuron 1206. Once the back-error propagation is complete, a weight update is performed, updating the weighted connection 1208 to explain the received errors. Note that the three modes of operation: feed-forward, back-propagation, and weight update, do not overlap with each other. This represents just one variation of the ANN computation, and any other appropriate form of the computation may be used instead.

[0049] To train an ANN, the training data may be split into a training set and a test set. The training data contains pairs of inputs and known outputs. During training, the inputs of the training set are fed into the ANN using feedforward propagation. After each input, the output of the ANN is compared to its corresponding known output. The difference between the output of the ANN and the known output related to the particular input above is used to generate an error value, which may be backpropagated through the ANN, after which the ANN's weight values ​​may be updated. This process continues until all pairs in the training set have been used up.

[0050] After training is complete, the ANN may be tested against a test set to ensure that the training has not become overfitted. If the ANN can generalize to new inputs beyond what it has already been trained on, then it can be used. If the ANN cannot accurately reproduce the known outputs of the test set, then additional training data will be needed, or the ANN's hyperparameters will probably need to be tuned.

[0051] ANNs can be implemented in hardware. For example, each weight 1208 may be characterized as a weight value stored as the resistance value of a Resistive Processing Unit (RPU), which generates a predictable current output when an input voltage is applied according to a configurable resistance.

[0052] Referring here to Figure 13, a hardware architecture 1300 for an ANN is shown. It should be understood that this architecture is purely illustrative, and other architectures or types of neural networks may be used instead. The hardware embodiments described herein are included for the purpose of illustrating the general principles of neural network computation with a high degree of generality and should not be construed as limiting.

[0053] Furthermore, the layers of neurons and the weights connecting them, as described below, are described in a general manner and can be replaced by any type of neural network layer having any appropriate degree or type of interconnectivity. For example, the layers may include convolutional layers, pooling layers, fully connected layers, softmax layers, or any other appropriate type of neural network layer. Moreover, layers may be added or removed as needed, and the weights described herein may be replaced by more complex forms of interconnectivity.

[0054] During feedforward operation, the input neuron 1302 supplies an input voltage in parallel to each row of the weights 1304. As noted above, the weights 1304 can be implemented in hardware, for example, using the configurable resistor cells described above. In the hardware embodiments described herein, each weight 1304 has a configurable resistance value such that a current output flows from the weight 1304 to each hidden neuron 1306. The current output from the weights 1304 thus represents a weighted input to the hidden neurons 1306.

[0055] Following the hardware embodiment, the current output with the given weight 1304 is,

number

[0056] A set of reference weights 1307 has a fixed resistance and integrates the outputs of the reference weights into a reference current supplied to each of the hidden neurons 1306. Some reference conductances need to be encoded in the matrix as both positive and negative values ​​because conductance values ​​can only be positive numbers. The current generated by weights 1304 is positive in continuous values, and therefore reference weights 1307 are used to give the reference current, and above the reference current, the current is thought to have a positive value, and below the reference current, the current is thought to have a negative value. As an alternative to using reference weights 1307, another embodiment may use a separate array of weights 1304 to take in negative values.

[0057] Hidden neuron 1306 uses currents from an array of weights 1304 and reference weight 1307 to perform a certain calculation. This calculation may be, for example, any suitable activation function and may be implemented in hardware or software using a suitable circuit.

[0058] The hidden neuron 1306 then outputs its own voltage to another array of weights 1304 based on its activation function. This array performs the same weighting calculation on the array above, using a column of weights 1304 that receive voltages from each hidden neuron 1306 to generate a weighted current output that is added row by row and supplied to output neuron 1308.

[0059] It should be understood that any number of these stages can be implemented by inserting additional layers of the array and hidden neurons 1306. It should also be noted that some neurons may be constant neurons 1309 that provide a constant output to the array. Constant neurons 1309 can reside among input neurons 1302 or hidden neurons 1306 or both and are used only during feedforward operation.

[0060] During backpropagation, the output neuron 1308 supplies a voltage return across the entire array of weights 1304. The output layer compares the generated network response to the training data and calculates an error. The error is applied to the array as a voltage pulse, where the height, duration, or both of the pulses are modulated proportionally to the error value. In this example, the rows of weights 1304 receive voltages from each output neuron 1308 in parallel and convert the above voltages into currents that are added column-wise to provide input to the hidden neuron 1306. The hidden neuron 1306 integrates the weighted feedback signal with the derivatives of the feedforward calculation and stores the error value before outputting the feedback signal voltage to each column of weights 1304. This backpropagation proceeds through the entire network 1300 until all hidden neurons 1306 and input neurons 1302 have stored the error value.

[0061] The weight update process will depend on how the weights 1304 are implemented. With respect to a configurable resistor containing a phase-change material, input neurons 1302 and hidden neurons 1306 can apply a first weight update voltage forward, and output neurons 1308 and hidden neurons 1306 can apply a second weight update voltage backward via the network 1300. The combination of these voltages can create a state change within each weight 1304, for example, by raising the temperature of the weight 1304 above a threshold, and thus causing the weight 1304 to take on a new resistance value by changing the resistance of the weight. In this way, the weights 1304 can be trained to adapt the neural network 1300 to errors during processing.

[0062] If we describe preferred embodiments of nanotip filament confinement (exemplary and not limiting), it should be noted that modifications and variations may be made by those skilled in the art in consideration of the above teachings. Therefore, it should be understood that changes within the scope of the invention, as outlined in the claims below, may be made to the specific embodiments disclosed. With the aspects of the invention thus described, along with the details and originality required by patent law, what is desired to be patented and protected by the patent certificate is described in the claims below.

Claims

1. A method for forming a configurable resistor device, The process involves isotropically etching a laminate of layers, wherein the laminate of layers has an insulating layer in contact with a conductor layer, and selectively forming divots on the exposed side walls of the conductor layer, and the isotropic etching process is performed in such a way. The isotropic etching of the laminate of the insulator layer is performed to selectively form divots on the exposed side walls of the insulator layer, thereby causing the curved profiles to intersect and form a tip at the interface between the insulator layer and the conductor layer. A dielectric layer is formed on the laminate of the layers so as to cover the tip, The dielectric layer is located between the electrode and the tip, and the electrode is formed on the dielectric layer. Methods that include...

2. The method according to claim 1, wherein forming the dielectric layer includes conformally depositing hafnium oxide.

3. The method according to claim 1, wherein forming the electrode includes conformally depositing a conductive material to fill the divot.

4. The method according to claim 1, wherein the laminate of the layers comprises alternating conductive layers and insulating layers.

5. The method according to claim 4, further comprising forming the alternating layers of the conductor layer into a stepped pattern.

6. The method according to claim 5, further comprising forming a plurality of word line contacts, each of which word line contacts is in contact with a respective conductor layer within the laminate of the layers.

7. The method according to claim 4, further comprising forming a word line contact in a via that penetrates the laminate of the aforementioned layers and contacts each of the conductor layers.

8. The method according to claim 1, wherein the laminate of the layers includes an etch mask on the conductive layer and the insulating layer such that the dielectric layer is formed on the etch mask.

9. A configurable resistor cell, A laminate of layers including an insulating layer in contact with a conductive layer, each having concave, curved profile sidewall surfaces that intersect at the interface between the insulating layer and the conductive layer such that they form a pointed end that concentrates the electric field strength, A dielectric layer formed on the laminate of the layers so as to cover the tip, The dielectric layer is positioned between the electrode and the tip, and the electrode is formed on the dielectric layer. A configurable resistor cell equipped with the following features.

10. The configurable resistor cell according to claim 9, wherein the laminate of the layers comprises a plurality of conductive layers and insulating layers alternately.

11. The configurable resistor cell according to claim 10, wherein the alternating layers of the plurality of conductor layers and insulating layers have a stepped pattern.

12. The configurable resistor cell according to claim 11, further comprising a plurality of word line contacts, each of which contacts contacts a respective conductor layer within the laminate of the layers.

13. The configurable resistor cell according to claim 10, further comprising a word wire contact in a via that penetrates the laminate of the aforementioned layers and contacts each of the conductor layers.

14. The configurable resistor cell according to claim 9, further comprising an etch mask layer located between the laminate of the layers and the dielectric layer on the laminate of the layers.

15. The configurable resistor cell according to claim 9, wherein the dielectric layer is formed from hafnium oxide.

16. A neuromorphic computing device comprising an array of configurable resistor cells according to any one of claims 9 to 15.

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