Semiconductor-type qubit device

Abstract

[Problem] The present invention addresses the problem of providing a semiconductor-type quantum bit device having reduced variations in characteristics of quantum bit operations when multiple units thereof are integrated. [Solution] A semiconductor-type quantum bit device 10 is characterized by comprising at least: a support substrate 1 including a first conductivity type semiconductor layer; a fringe electric field formation layer 2 that is formed on the support substrate 1, and that includes a second conductivity type semiconductor layer which has a conductivity type different from that of the first conductivity type semiconductor layer or a metal layer which, together with the support substrate, forms a Schottky barrier wall; an embedded oxide layer 3 that is formed on the fringe electric field formation layer 2; and a quantum dot semiconductor layer 4 that is formed on the embedded oxide layer 3 and in which quantum dots are formed.

Description

[Technical Field]

[0001] This invention relates to a semiconductor-type qubit device in which variations in qubit operation characteristics are suppressed by a fringe field. [Background technology]

[0002] Quantum computers are being developed in various forms, including superconducting, ion trap, photon quantum, and semiconductor types. Among these, semiconductor qubit devices have compatibility with existing semiconductor equipment manufacturing facilities for classical computers, and research into large-scale integration is progressing, leveraging the integration technology cultivated for classical computers.

[0003] For example, with respect to semiconductor-type qubit devices, a technique has been proposed to reduce the formation area per qubit and enable high integration by embedding tiny magnets necessary for spin manipulation by electron dipole spin resonance (EDSR) within the semiconductor layer (see Non-Patent Document 1). According to this proposal, by arranging the aforementioned minute magnets, it is possible to realize a single-qubit gate with excellent qubit manipulation characteristics and an integrated circuit that highly integrates it.

[0004] Incidentally, in large-scale integration of the aforementioned semiconductor-type qubit devices, in order to perform meaningful quantum operations with fewer errors, it is essential to suppress variations in the characteristics of each integrated semiconductor-type qubit device, in addition to high integration. In this respect, the semiconductor-type qubit device, like classical transistors, will experience variations in qubit operation between individual devices if there are variations in device dimensions during the manufacturing process. In particular, with the semiconductor-type qubit device, even very small dimensional variations on the order of a few nanometers can cause significant variations in qubit operation. Since even with state-of-the-art manufacturing equipment, it is difficult to avoid very slight dimensional variations, there is a need to develop new technologies that can suppress individual characteristic variations when multiple units are assembled, even if dimensional variations are present. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] S. Iizuka et al., VLSI Tech. Dig. 2021, JFS5-5. [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] The present invention aims to solve the aforementioned problems of the conventional approach and achieve the following objective: to provide a semiconductor-type qubit device in which variations in qubit operation characteristics are suppressed when multiple qubits are integrated. [Means for solving the problem]

[0007] The present invention is based on the above findings, and the means for solving the above problems are as follows: <1> A semiconductor-type qubit device comprising at least a support substrate composed of a first conductivity type semiconductor layer; a fringe field forming layer formed on the support substrate and composed of either a second conductivity type semiconductor layer having a different conductivity type than the first conductivity type semiconductor layer or a metal layer forming a Schottky barrier with the support substrate; an embedded oxide layer formed on the fringe field forming layer; and a quantum dot semiconductor layer formed on the embedded oxide layer on which quantum dots are formed. <2> The support substrate has a back gate electrode that allows voltage to be applied to it. <1> A semiconductor-type qubit device as described above. <3> The embedded oxide layer has a thickness of 10 nm to 100 nm. <1> or <2> A semiconductor-type qubit device as described above. <4> The quantum dot semiconductor layer is formed in the shape of a long strip when viewed from above, and the width of the long strip in the short direction is at most 100 nm. <1> from <3> A semiconductor-type qubit device as described in any of the following. <5> The quantum dot semiconductor layer has a thickness of 2.5 nm to 50 nm. <1> from <4> Semiconductor qubit device as described in any of the following 。 <6> The concentration of the first conductive impurity in the support substrate is 1 × 10 19 cm -3 The above describes a configuration in which the fringe field forming layer is composed of a second conductivity type semiconductor layer, and the second conductivity type impurity concentration is 1 × 10⁻⁶. 19 cm -3 The above <1> from <5> A semiconductor-type qubit device as described in any of the following. <7> The support substrate is formed of Si, and the second conductivity type semiconductor layer is formed of Si. <6> A semiconductor-type qubit device as described above. <8> The quantum dot semiconductor layer is formed of one of Si, SiGe, and Ge. <1> from <7> A semiconductor-type qubit device as described in any of the following. <9> The embedded oxide layer is formed of either SiO2 or GeO2. <1> from <8> A semiconductor-type qubit device as described in any of the following. <10> The structure comprises at least three barrier gate electrodes and two plunger gate electrodes formed on a quantum dot semiconductor layer via a gate insulating layer, with the two plunger gate electrodes each spaced apart from the barrier gate electrodes between two adjacent barrier gate electrodes, and quantum dots formed at two positions on the quantum dot semiconductor layer facing the plunger gate electrodes, and a static magnetic field application section that allows a static magnetic field to be applied to the quantum dots. <1> from <9> A semiconductor-type qubit device as described in any of the following. [Effects of the Invention]

[0008] According to the present invention, the aforementioned problems in the prior art can be solved, and a semiconductor-type qubit device can be provided in which variations in qubit operation characteristics are suppressed when multiple devices are integrated. [Brief explanation of the drawing]

[0009] [Figure 1(a)]This is a perspective view showing the basic configuration of the semiconductor-type qubit device of the present invention. [Figure 1(b)] This is a cross-sectional view in the yz plane in Figure 1(a). [Figure 2(a)] This is a perspective view showing an example configuration of a semiconductor-type spin qubit device. [Figure 2(b)] This is a cross-sectional view in the yz plane in Figure 2(a). [Figure 3] This is an explanatory diagram illustrating the problem of dimensional deviation during SWAP gate operation. [Figure 4(a)] This is a perspective view showing an example configuration of a semiconductor-type charge qubit device. [Figure 4(b)] This is an explanatory diagram (1) for illustrating a single-qubit gate operation in a semiconductor-type charge qubit device. [Figure 4(c)] This is an explanatory diagram (2) for illustrating a single-qubit gate operation in a semiconductor-type charge qubit device. [Figure 5(a)] This is a perspective view showing an overview of a semiconductor-type spin qubit device related to the setup of a simulation test. [Figure 5(b)] This is an explanatory diagram for illustrating the configuration of the yz plane in Figure 5(a). [Figure 5(c)] This is a top view illustrating the configuration of the xy-plane in Figure 5(a). [Figure 6] This figure shows the calculation results of exchange interaction (Jex) for the "P substrate" condition in the comparative test device, as well as for the "N / P substrate" condition and the "N / P substrate & Vsub = 0.3V" condition in the test device. [Figure 7] This figure shows the calculation results for SWAP operation fidelity. [Figure 8] This is an explanatory diagram showing the relationship between the exchange interaction between two qubits and the potential barrier area. [Figure 9] This figure shows the potential distribution of the yz plane in the test device and the comparative test device. [Figure 10]This figure shows the electron density distribution in bit 1 and bit 2, based on the wave functions of electrons in bit 1 and bit 2. [Figure 11] This figure shows the relationship between ΔdB, ΔhB, ΔSB (normalized by dB, hB, and SB) and ΔW. [Modes for carrying out the invention]

[0010] (Semiconductor-type qubit device) First, the basic configuration of the semiconductor-type qubit device of the present invention will be explained with reference to the drawings. Figure 1(a) is a perspective view showing the basic configuration of the semiconductor-type qubit device of the present invention, and Figure 1(b) is a cross-sectional view in the yz plane of Figure 1(a). As shown in Figures 1(a) and 1(b), the semiconductor qubit device 10 includes at least a support substrate 1, a fringe field formation layer 2, an embedded oxide layer 3, a quantum dot semiconductor layer 4, and a back gate electrode 5.

[0011] The support substrate 1 is composed of a first conductivity type semiconductor layer. There are no particular restrictions on the material used to form the support substrate 1, and known semiconductor substrates can be used, but among them, Si (silicon) is preferred from the viewpoint of processability and availability. Examples of impurities that impart the first conductivity type include known impurities such as boron (B) in the case of P-type and known dopant materials such as phosphorus (P) in the case of N-type. The first conductivity type semiconductor layer can be obtained, for example, by adding these dopant materials to the melt of a semiconductor material such as Si during the production of an ingot by the Czochralski method, and the support substrate 1 can be obtained by cutting this ingot to the desired size. There are no particular restrictions on the concentration of the first conductive type impurity in the support substrate 1, but it is 1 × 10 19 cm -3 The above is preferable, 1 × 10 20 cm -3The above is more preferable. If the impurity concentration is too low, the strength of the fringe electric field obtained by disposing the fringe electric field forming layer 2 may be insufficient. The upper limit of the impurity concentration of the first conductive type is 1×10 21 cm -3 or so.

[0012] The fringe electric field forming layer 2 is a layer formed on the support substrate 1. By forming the fringe electric field forming layer 2 on the support substrate 1, a fringe electric field is generated that curves and wraps from the outer edge corner extending in the longitudinal direction (in the x direction in the figure) on the upper surface of the fringe electric field forming layer 2 toward the embedded oxide layer 3 in the inner direction (in the y direction in the figure) on the upper surface of the fringe electric field forming layer 2.

[0013] One configuration for generating such a fringe electric field is a configuration in which the fringe electric field forming layer 2 is a second conductive type semiconductor layer having a conductive type different from that of the first conductive type semiconductor layer. The material for forming the second conductive type semiconductor layer is not particularly limited, and known semiconductor substrates can be mentioned. Among them, Si is preferable from the viewpoints of processability and availability. The impurity for imparting the second conductive type is an impurity having a polarity opposite to that of the impurity for imparting the first conductive type. In the case of the P type, known impurities such as B can be mentioned, and in the case of the N type, known dopant materials such as P can be mentioned. The second conductive type semiconductor layer can be obtained by known forming methods such as ion implantation of these dopant materials or forming an epitaxial growth layer doped with a dopant material. The impurity concentration of the second conductive type in the second conductive type semiconductor layer is not particularly limited, but 1×10 19 cm -3 or more is preferable, and 1×10 20 cm -3 or more is more preferable. If the impurity concentration is too low, the strength of the fringe electric field obtained by disposing the fringe electric field forming layer 2 may be insufficient. The upper limit of the impurity concentration of the second conductive type is 1×10 21 cm -3 or so. When the fringe field forming layer 2 is made of the second conductivity type semiconductor layer, the support substrate 1 and the fringe field forming layer 2 can be made using known N / P substrates and P / N substrates, thereby simplifying the manufacturing process. In particular, when the support substrate 1 is made of Si and the fringe field forming layer 2 is made of Si, the second conductivity type semiconductor layer can be constructed using a general-purpose Si N / P substrate or Si P / N substrate. When the semiconductor-type qubit device 10 is configured as an electron-type qubit device using electrons as semiconductor carriers, the conductivity type of the first conductivity type semiconductor layer (support substrate 1) is set to P-type, and the conductivity type of the second conductivity type semiconductor layer (fringe field forming layer 2) is set to N-type. Conversely, when the device is configured as a hole-type qubit device using holes as semiconductor carriers, the conductivity type of the first conductivity type semiconductor layer (support substrate 1) is set to N-type, and the conductivity type of the second conductivity type semiconductor layer (fringe field forming layer 2) is set to P-type.

[0014] Another configuration for generating a fringe field is one in which the fringe field forming layer 2 is a metal layer that forms a Schottky barrier between it and the support substrate 1. In order to form a Schottky barrier between the metal layer and the support substrate 1, the metal layer should be configured to have a work function equivalent to that of the second conductivity type semiconductor layer. In other words, the metal layer is required to play a role in replacing the second conductivity semiconductor layer in an N / P substrate configuration or a P / N substrate configuration consisting of the support substrate 1 and the second conductivity semiconductor layer, in order to obtain a fringe electric field. For example, using the Fermi level that governs the work function, when the second conductivity type semiconductor layer is formed of silicon, the Fermi level when the conductivity type is N-type is approximately 4.0 eV to 4.3 eV, and when the conductivity type is P-type, the Fermi level is approximately 4.8 eV to 5.1 eV. The Fermi level is similar when the support substrate 1 (the first conductivity type semiconductor layer) is formed of silicon. Based on these relationships, when the support substrate 1 is composed of an N-type silicon semiconductor layer, the material used to form the metal layer (which replaces the P-type semiconductor layer) can be any metallic material with a Fermi level of approximately 4.6 eV to 6.0 eV, such as Au (gold) or Pt (platinum). Furthermore, when the support substrate 1 is composed of a P-type silicon semiconductor layer, the material used to form the metal layer (which replaces the N-type semiconductor layer) can be any metallic material with a Fermi level of approximately 3.0 eV to 4.4 eV, such as Al (aluminum) or W (tungsten). There are no particular restrictions on the method for forming the metal layer, and known methods such as vapor deposition and CVD can be used.

[0015] The embedded oxide layer 3 is a layer formed on the fringe field forming layer 2. There are no particular restrictions on the embedded oxide layer 3, but it is preferable to form it with either SiO2 or GeO2, as it can be easily formed using existing manufacturing equipment. There are no particular restrictions on the method for forming the embedded oxide layer 3, and known methods for forming a box layer on an SOI substrate can be applied. The thickness of the embedded oxide layer 3 (thickness in the vertical direction (z direction in the figure)) is preferably 10 nm to 100 nm. If the thickness is less than 10 nm, it becomes difficult for fringe electric fields to penetrate into the embedded oxide layer 3, and if it exceeds 100 nm, the penetrated fringe electric fields may become uniform, reducing their influence on the quantum dot semiconductor layer 4.

[0016] The quantum dot semiconductor layer 4 is formed on the embedded oxide layer 3 and is the layer on which quantum dots are formed. While there are no particular restrictions on the material used to form the quantum dot semiconductor layer 4, it is preferable to use Si, Ge (germanium), or SiGe (a mixed crystal of these materials) because it can be easily formed using existing manufacturing equipment. There are no particular restrictions on the method for forming the quantum dot semiconductor layer 4, and known methods for forming SOI layers on SOI substrates and similar methods can be applied. The quantum dot semiconductor layer 4 may be of either the first conductivity type or the second conductivity type, and the methods described for the first conductivity type semiconductor layer and the second conductivity type semiconductor layer can be applied to imparting these conductivity types. Furthermore, there are no particular restrictions on the impurity concentration in the quantum dot semiconductor layer 4, and 1 × 10⁻⁶ 11 cm -3 ~1 × 10 18 cm -3 It is to that extent.

[0017] The quantum dot semiconductor layer 4 is formed in the shape of a long strip when viewed from above (xy top surface in the figure) in order to form a dot row of multiple quantum dots along the longitudinal direction of the strip (x direction in the figure). There are no particular restrictions on the width (W) of the long strip in the short direction (y direction in the figure), but it is preferably 100 nm or less. If the width (W) exceeds 100 nm, it may be difficult to form the quantum dots. The lower limit of the width (W) is approximately 2 nm. There are no particular restrictions on the thickness of the quantum dot semiconductor layer 4 (thickness in the vertical direction (z direction in the figure)), but it is preferably between 2.5 nm and 50 nm. If the thickness is less than 2.5 nm, it may be difficult to obtain the device characteristics as designed, and if it exceeds 50 nm, the thick quantum dot semiconductor layer 4 body may shield the quantum dots, making it difficult to exert a fringe electric field.

[0018] The quantum dots and the qubits composed of the quantum dots are formed by arranging electrodes and controlling the voltage, which are formed on the quantum dot semiconductor layer 4 via a gate insulating layer. The configuration of the semiconductor-type qubit device 10 can be applied to either the spin qubit device or the charge qubit device described later by adding these electrode configurations. Furthermore, the electric field formed by the gate insulating layer and the electrode creates a fringe electric field around the fringe electric field forming layer 2.

[0019] In the semiconductor-type qubit device 10, a trench structure is provided, which is cut in the x-direction from the quantum dot semiconductor layer 4 to an intermediate position on the support substrate 1. The trench structure regulates the width in the short direction of the embedded oxide layer 3 and the fringe field formation layer 2 to match the width (W) in the short direction of the quantum dot semiconductor layer 4. There are no particular limitations on the method for forming the trench structure, and known lithography methods can be used. In the illustrated example of the semiconductor-type qubit device 10, multiple quantum dots can be formed along the longitudinal direction (x direction) of the quantum dot semiconductor layer 4, which is formed in the shape of a long strip when viewed from above, and a one-dimensional qubit array can be formed. However, by forming the long strip-shaped quantum dot semiconductor layer 4, the embedded oxide layer 3 of the same shape, and the fringe field formation layer 2 in the y direction as well as the x direction, and crossing these long strips, a two-dimensional qubit array can also be easily formed. The configuration of these qubit sequences can be realized in any structure according to known integration techniques, and the technical concept of the present invention is not limited to the illustrated examples. Furthermore, although the illustrated examples show a single-element structure of a 2-qubit gate, large-scale integration is possible by applying multiple 2-qubit gate structures to the qubit sequence.

[0020] The back gate electrode 5 is an electrode to which a voltage can be applied to the support substrate 1. The arrangement of the back gate electrode 5 is not limited to the example shown, but if it is configured as an electrode layer formed on the surface of the support substrate 1 opposite to the surface on which the fringe field forming layer 2 is formed, the wiring structure of the semiconductor qubit device 10 can be simplified. The back gate electrode 5 is an optional structure in the semiconductor qubit device 10, but as will be verified in the Examples section below, it has the effect of significantly reducing variations in qubit operation characteristics. There are no particular restrictions on the method for forming the back gate electrode 5; it can be formed by appropriately selecting from known electrode materials and electrode layer formation methods.

[0021] [First Embodiment: Semiconductor-type Spin Qubit Device] Referring to Figures 2(a) and 2(b), an example in which the semiconductor-type qubit device of the present invention is configured as a spin qubit device capable of 2-qubit gate operations will be described as the first embodiment. Figure 2(a) is a perspective view showing an example configuration of a semiconductor-type spin qubit device, and Figure 2(b) is a cross-sectional view of Figure 2(a) in the yz plane.

[0022] As shown in Figures 2(a) and (b), the semiconductor spin qubit device 20 has a support substrate 21, fringe field formation layer 22, embedded oxide layer 23, quantum dot semiconductor layer 24, and back gate electrode 25, which are configured similarly to the support substrate 1, fringe field formation layer 2, embedded oxide layer 3, quantum dot semiconductor layer 4, and back gate electrode 5 in the semiconductor qubit device 10. In addition, three barrier gate electrodes 27a, 27b, and 27c and two plunger gate electrodes 28a and 28b are formed on the quantum dot semiconductor layer 24 via a gate insulating layer 26. Furthermore, the semiconductor-type spin qubit device 20 includes a static magnetic field application section (not shown) and an embedded magnet layer 29.

[0023] The plunger gate electrode 28a (28b) is positioned between two adjacent barrier gate electrodes 27a, 27b (27b, 27c), spaced apart from the barrier gate electrodes 27a, 27b (27b, 27c). The barrier gate electrodes 27a, 27b, 27c and plunger gate electrodes 28a, 28b act on the behavior of semiconductor carriers (electrons or holes; hereafter, electrons will be used as the model) in two quantum dot regions of the quantum dot semiconductor layer 24, and quantum dots Q1 and Q2 are formed at two positions opposite to the plunger gate electrodes 28a, 28b of the quantum dot semiconductor layer 24. Furthermore, in a two-qubit gate operation, the plunger gate electrodes 28a and 28b change the potential of the quantum dots Q1 and Q2, controlling the electron number state within the dots, while the barrier gate electrodes 27a, 27b, and 27c change the tunnel barrier (potential barrier) between the quantum dots Q1 and Q2, controlling the exchange interaction between the two qubits. In the semiconductor-type spin qubit device 20, since the two-qubit gate operation is performed using the exchange interaction between these two qubits, if the distance between quantum dots Q1 and Q2 is too large, malfunctions may occur in the execution of the two-qubit gate operation. Therefore, it is preferable to appropriately set the element that governs the distance between quantum dots Q1 and Q2. Specifically, it is preferable that the length of the plunger gate electrodes 28a and 28b in the direction along the longitudinal direction of the quantum dot semiconductor layer 24 (in the x-direction in the figure) be 2 nm to 100 nm, the length of the barrier gate electrodes 27a, 27b, and 27c in the direction along the longitudinal direction of the quantum dot semiconductor layer 24 be 2 nm to 100 nm, and the separation distance between the plunger gate electrode 28a (28b) and the two adjacent barrier gate electrodes 27a, 27b (27b, 27c) be 2 nm to 50 nm.

[0024] There are no particular restrictions on the method for forming the gate insulating layer 26, the barrier gate electrodes 27a, 27b, 27c, and the plunger gate electrodes 28a, 28b. They can be formed by applying known gate electrode materials and gate electrode formation methods used in classical CMOS transistors and the like.

[0025] The static magnetic field application unit is a unit that can apply a static magnetic field to the quantum dots Q1 and Q2 and the embedded magnet layer 29. The static magnetic field is uniform throughout the entire device. When a static magnetic field B0 is applied from the static magnetic field application unit to the localized energy levels of electrons confined in quantum dots Q1 and Q2, the energy levels become gμ B B0(μ B Zeeman splitting occurs due to the energy difference of the Bohr magneton (g: g factor of electron spin), and a quantum two-level system is generated in the quantum dots Q1 and Q2, which is represented by two quantum states: the |0> state and the |1> state. The static magnetic field application unit is not particularly limited and can be appropriately selected from known components consisting of magnets and coils.

[0026] In the semiconductor-type spin qubit device 20 configured in this way, the tunnel barrier between quantum dots Q1 and Q2 is changed by controlling the voltage of the barrier gate electrodes 27a, 27b, and 27c, thereby providing an exchange interaction between the two qubits, and enabling a SWAP gate operation, which is a two-qubit gate operation. Here, exchange interaction refers to the effect where two electrons, one each present in quantum dots Q1 and Q2, overlap in their electron orbitals, influencing each other's electron spins, and the energy J is such that this interaction occurs. ex This is given as the energy difference between the case where the spins are aligned and the case where they are staggered.

[0027] The specific SWAP gate operation is performed by applying an exchange interaction of appropriate magnitude to the two initial quantum states |0>|1> (or |1>|0>) in quantum dots Q1 and Q2, thereby swapping (SWAP) the two quantum states, resulting in the two quantum states |1>|0> (or |0>|1>). In other words, as shown in Figure 3, the execution of a SWAP gate operation requires an exchange interaction (J ex The magnitude of this exchange interaction (J ex Using the magnitude of (J0) as the reference, a constant voltage (V) is applied to the barrier gate electrodes 27a, 27b, and 27c. BG ) Control is performed. In this case, if there is a dimensional misalignment (ΔW) in the width (W) of the quantum dot semiconductor layer 24 in the short direction, in a configuration that does not consider the dimensional misalignment, the exchange interaction (J) ex The magnitude of ) changes from the reference (from J0 to J0'), and as a result, the initial two quantum states |0>|1> (or |1>|0>) do not invert to the two quantum states |1>|0> (or |0>|1>), and the SWAP gate operation results in an Error. However, in the semiconductor spin qubit device 20, the fringe field generated by the fringe field formation layer 22 interacts with the exchange interaction (J) with respect to the dimensional displacement (ΔW). ex ) compensates to bring it closer to the reference J0 from J0'. Therefore, when multiple 2-qubit gate structures using semiconductor-type spin qubit devices 20 are integrated, even if there is a dimensional misalignment (ΔW) between them, the characteristic variation is suppressed by the compensation effect of the fringe field formation layer 22, and a constant voltage (V) is maintained. BG This allows for SWAP gate operations with fewer errors through ) control. Figure 3 is an explanatory diagram illustrating the dimensional deviation problem that occurs during SWAP gate operation.

[0028] Let's continue the explanation by referring again to Figures 2(a) and (b). The embedded magnet layer 29 is a layer embedded in a recess drilled in the bottom (trench groove) of the trench structure of the support substrate 21. There are no particular restrictions on the material used to form the embedded magnet layer 29. Examples include known magnetic materials that are magnetized by an external magnetic field applied from the static magnetic field application unit. In particular, magnetic materials containing at least one of the elements iron, cobalt, nickel, and manganese are preferred. Furthermore, there are no particular restrictions on the method for forming the embedded magnet layer 29. For example, a method combining a known lithography method for forming a recess and a known CVD method, ALD method, CMP method, etc., for forming the embedded magnet layer 29 in the recess can be used.

[0029] The embedded magnet layer 29 is magnetized by the static magnetic field B0 applied from the static magnetic field application section, forming a magnetization M. The magnetization M locally generated in this magnetized portion is affected by a gradient magnetic field B, where the magnetic field strength changes spatially at the positions of the quantum dots Q1 and Q2. SL It forms. In this state, when an AC voltage is applied to the plunger gate electrode 28a (or 28b), the center of mass of the electrons in quantum dot Q1 (or Q2) is moved to the gradient magnetic field B. SL By vibrating within the device, electrons effectively sense vibrations of a transverse magnetic field component perpendicular to B0, enabling quantum mechanical transitions between two levels: up-spin and down-spin. In other words, electron spin manipulation can be controlled by an electrical signal via the plunger gate electrode 28a (or 28b) to perform a one-qubit gate (X-gate) operation. The embedded magnet layer 29 is an optional component for performing these single-qubit gate operations, and by including it, the semiconductor-type spin qubit device 20 can simultaneously realize both two-qubit gate operations and single-qubit gate operations. Any quantum operation can be performed by combining universal gate sets, which are a combination of one-qubit gates and two-qubit gates, as a single element. In this sense, the configuration of the semiconductor-type spin qubit device 20, which can construct universal gate sets that take characteristic variations into account, has extremely important technical significance in realizing any quantum operation. Furthermore, the magnets constituting the embedded magnet layer 29 have gradient magnetic fields B at the positions of quantum dots Q1 and Q2. SL Anything that forms part of the structure is acceptable, and it may be placed in a different position. Furthermore, in addition to the spin manipulation method using electron dipole spin resonance (EDSR) with a gradient magnetic field from the magnet, the 1-qubit gate operation on quantum dots Q1 and Q2 can also be performed using an electron spin resonance (ESR) method, which involves transmitting microwaves to quantum dot Q1 (or Q2) via wiring to vibrate electrons within quantum dot Q1 (or Q2). This provides further examples of modifications based on the electron spin resonance method for the semiconductor-type spin qubit device 20.

[0030] [Second Embodiment: Semiconductor-type Charge Qubit Device] Next, with reference to Figures 4(a) to 4(c), a second embodiment will be described in which the semiconductor-type qubit device of the present invention is configured as a charge qubit device. Figure 4(a) is a perspective view showing an example configuration of a semiconductor-type charge qubit device, and Figures 4(b) and 4(c) are explanatory diagrams for explaining a single-qubit gate operation in a semiconductor-type charge qubit device.

[0031] As shown in Figure 4(a), the semiconductor-type charge qubit device 30 has a basic structure consisting of a support substrate 31, a fringe field formation layer 32, a fringe field formation layer 34, and a back gate electrode 35, which are configured similarly to the support substrate 1, fringe field formation layer 2, embedded oxide layer 3, quantum dot semiconductor layer 4, and back gate electrode 5 in the semiconductor-type qubit device 10. Furthermore, the semiconductor-type charge qubit device 30 has a gate insulating layer 36, barrier gate electrodes 37a, 37b, 37c, and plunger gate electrodes 38a, 38b, which are configured in the same way as the gate insulating layer 26, barrier gate electrodes 27a, 27b, 27c, and plunger gate electrodes 28a, 28b in the semiconductor-type spin qubit device 20. In short, the semiconductor-type charge qubit device 30 is configured by removing the static magnetic field application section and the embedded magnet layer 29, which are unnecessary for the operation of the charge qubit device, from the semiconductor-type spin qubit device 20.

[0032] The semiconductor-type charge qubit device 30 and the semiconductor-type spin qubit device 20 are fundamentally similar in that they both include a structural component comprising at least two quantum dots (Q1, Q2) formed on a common quantum dot semiconductor layer (24, 34), and the aforementioned various electrodes corresponding to quantum computation operations performed by these two quantum dots, and that multiple such structural components can be integrated within a single device. However, in the semiconductor-type spin qubit device 20, the quantum information of the quantum two-level system is defined by the spin state (up spin, down spin) of the electrons within the quantum dots (Q1, Q2), whereas in the semiconductor-type charge qubit device 30, the quantum information of the quantum two-level system is defined by the existence state of the electrons present in one of the two quantum dots (Q1, Q2). In other words, in the semiconductor-type charge qubit device 30, two quantum dot (Q1, Q2) structures are created by voltage control of the barrier gate electrodes 37a, 37b, and 37c, and the probability that one electron exists in either of the quantum dots (Q1, Q2) is controlled by voltage control of the plunger gate electrodes 38a and 38b.

[0033] Specifically, first, the voltages of the barrier gate electrodes 27a, 27b, and 27c are adjusted to form quantum dots, and then the voltages of the plunger gate electrodes 38a and 38b are adjusted to control the presence of one electron in either of the quantum dots (see Figure 4(b)). Next, a pulse voltage is applied to the plunger gate electrodes 38a and 38b for a certain period of time to align the energy levels of the two quantum dots (Q1 and Q2), and during that time, electrons are controlled to be able to move between the energy levels by tunnel transitions (see Figure 4(c)). As a result, in the semiconductor spin qubit device 20, electrons transition between two levels in a quantum two-level system (left and right quantum dots Q1 and Q2), and quantum information can be defined by adding these two levels and their superposition state. In other words, a one-qubit gate (X gate) operation is performed by controlling the existence state of electrons in the two quantum dots (Q1 and Q2) via electrical signals mediated by plunger gate electrodes 38a and 38b.

[0034] Here, the operation time for the X-gate operation (see Figure 4(c)) is determined by the magnitude of the potential barrier between the two quantum dots (Q1, Q2) indicated by "b" in the figure, and is determined based on the case where there is no dimensional deviation (ΔW) in the width (W) in the short direction of the quantum dot semiconductor layer 34. In reality, when integrating a single-qubit gate (X gate) using multiple quantum dot semiconductor layers 34 (X gate arrays) with a common electrode structure, there will be some degree of dimensional misalignment (ΔW) in each X gate structure. As a result, in configurations that do not consider this dimensional deviation (ΔW), the size of the potential barrier changes from the reference, leading to variations in characteristics between different X gates and resulting in errors in the calculation results. However, in the semiconductor-type charge qubit device 30, the fringe field generated by the fringe field formation layer 32 compensates for the deviation in the size of the potential barrier due to the dimensional deviation (ΔW) so as to bring it closer to the reference. In other words, the starting point for considering the characteristic variations in the semiconductor-type charge qubit device 30 is the deviation of the potential barrier size between the two quantum dots (Q1, Q2) from a reference, and since this is the same origin as the starting point for considering the characteristic variations in the semiconductor-type spin qubit device 20, the deviation of the potential barrier size from the reference is compensated by the fringe field for the same reasons explained for the semiconductor-type spin qubit device 20. Therefore, even when the semiconductor-type charge qubit device 30 is composed of multiple X-gate structures with dimensional misalignment (ΔW), the compensation effect of the fringe field formation layer 32 suppresses characteristic variations, enabling X-gate operations with fewer errors. [Examples]

[0035] To investigate the effectiveness and preferred conditions of the present invention, simulation tests were conducted on the fidelity of quantum mechanical interactions (exchange interactions) between two qubits and two-qubit gate (SWAP gate) operations.

[0036] <Test Conditions> The aforementioned simulation tests were conducted using the MOS-type Si spin qubit device (test device) shown in Figures 5(a) to 5(c) as the basic assumption. Figure 5(a) is a perspective view showing an overview of the semiconductor-type spin qubit device related to the setup of the simulation tests, Figure 5(b) is an explanatory diagram for explaining the configuration of the yz plane in Figure 5(a), and Figure 5(c) is a top view for explaining the configuration of the xy plane in Figure 5(a).

[0037] The test apparatus is configured in accordance with the semiconductor qubit device shown in Figure 1, and includes a support substrate (N / P substrate) in which a P-type support layer (P substrate) and an N-type support layer (N dope) are laminated on a back gate electrode, and a BOX layer and an SOI layer are laminated on the support substrate, with a PG (plunger gate) electrode and a BG (barrier gate) electrode formed at predetermined positions on the SOI layer via a gate oxide layer. The aforementioned back gate electrode is composed of an Al (aluminum) electrode and receives a voltage (V) from an external power supply. sub ) is set to be applicable. The P-type support layer has an acceptor density of 1 × 10 20 cm -3 It is set as a Si layer. The aforementioned N-type support layer has a donor density of 2 × 10 20 cm -3 Therefore, it is set as a Si layer with a thickness of 5 nm in the z direction. These P-type and N-type support layers are provided with a trench structure, and the trench groove formed from the upper surface of the N-type support layer along the z-direction toward the bottom surface of the P-type support layer is set to a depth of 100 nm. Furthermore, the width (W) in the y-direction of the P-type support layer and the N-type support layer remaining after the formation of the trench groove is set to 48 nm. Consequently, the width (W) in the y-direction of the BOX layer, SOI layer, gate oxide layer, PG electrode, and BG electrode formed on the N-type support layer is also set to 48 nm. In this simulation test, several numerical changes (ΔW) are applied to this y-direction width (W=48 nm) as a base, and their effects are confirmed. The aforementioned BOX layer is an SiO2 layer formed as a buried oxide layer, with a thickness of 40 nm in the z direction. The SOI layer is a Si layer formed as a Si layer (Silicon on ISulator) on an insulating layer, with a thickness of 12 nm in the z direction. By controlling the voltage applied to the PG electrode and the BG electrode, quantum dots constituting two qubits, Bit 1 and Bit 2, are formed in this SOI layer at a position directly below the PG electrode in the z direction. The gate oxide layer is made of SiO2, and its thickness in the z direction is set to 10 nm. The BG electrode is composed of an Al (aluminum) electrode, and as shown in Figure 5(c), three BG electrodes are arranged spaced apart from each other in the x direction, with one BG electrode positioned in the center of the two BG electrodes at both ends. The length of the BG electrode in the x direction (L BG ) will all be set to 36nm. Furthermore, the PG electrode is composed of an Al (aluminum) electrode, and as shown in Figure 5(c), two are arranged in the x direction, with one positioned in the center of two adjacent BG electrodes. The length of the PG electrode in the x direction (L PG ) will all be set to 48nm. Furthermore, these PG electrodes and BG electrodes are arranged spaced apart from each other with a gap of 6 nm in the x-direction (see Figure 5(c)). Furthermore, each part of the P-type support layer located above the trench groove is covered with an appropriate insulating material. Furthermore, in this simulation test, the static magnetic field applied to the qubit is assumed to be up to approximately 0.1T.

[0038] In the test apparatus configured in this way, a SWAP operation can be performed to reverse the quantum state of the two qubits, bit 1 and bit 2, formed in the SOI layer, due to quantum mechanical exchange interaction (for example, reversing from the |0>|1> state to the |1>|0> state).

[0039] <Simulator> The aforementioned simulation test was conducted using a simulator (see Reference 1 for details) that was independently developed by the applicant and equipped with a function to analyze the quantum state of semiconductor-type qubits. Reference 1: H. Asai et al., EDTM Tech. Dig. 2021, p. 238.

[0040] <Verification of variability in exchange interactions> For both the test target apparatus and the comparative test target apparatus, which is set such that the N-type support layer (N dope) is not formed in the test target apparatus and the region where the N-type support layer is formed is part of the P-type support layer (P substrate), bit 1 and bit 2 are formed in the SOI layer by voltage control between the PG electrode and the BG electrode, and the exchange interaction (J) between these two qubits is controlled. ex The above was calculated using the simulator. Here, the test apparatus is subjected to two conditions: an "N / P substrate" condition in which no voltage is applied to the back gate electrode, and an "N / P substrate & V" condition in which a voltage of 0.3V is applied to the back gate electrode. sub Calculations were performed under two conditions: the "=0.3V" condition and the "P substrate" condition. For the comparative test device, calculations were performed under the "P substrate" condition, in which no voltage was applied to the back gate electrode. Furthermore, for each condition, calculations were performed under three conditions: the basic condition where the width W shown in Figure 5(b) is 48 nm (ΔW=0), and the size-change conditions where the width W is changed by ±3 nm in two ways (ΔW=-3 nm, ΔW=+3 nm).

[0041] As a specific method for calculating the exchange interaction, first, following the aforementioned reference 1, the wave functions of electrons in bit 1 and bit 2 were determined such that the electron distribution within the quantum dot region of the SOI layer and the carrier distribution outside the quantum dot region were self-consistent. Next, using the obtained wavefunction, the exchange interaction between bit 1 and bit 2 was calculated using a method similar to the Heitler-London method for molecular orbitals. This calculation method was performed by calculating the exchange interaction between bit 1 and bit 2 in the following steps (a) and (b), in accordance with Reference 2 below. In (b), the energy difference between the spin singlet state and the triplet state corresponds to the exchange interaction. (a) Extract the wave functions of the orbits in which the electrons occupy for bit 1 and bit 2, respectively. (b) Construct a Hamiltonian of the two-electron state considering spin, and calculate the energy difference between the spin singlet state and the triplet state from its diagonalization. Reference 2: Physical Review B, 59 2070 (1999).

[0042] The "P substrate" conditions in the aforementioned comparative test device, and the "N / P substrate" conditions and "N / P substrate & V" conditions in the aforementioned test device. sub Exchange interaction under the condition =0.3V (J ex The results of each calculation are shown in Figure 6. As shown in the lower part of Figure 6, under the "P substrate" condition in the comparative test apparatus, the exchange interaction under the two size change conditions (ΔW=-3nm, ΔW=+3nm) shows a variation of ±35% compared to the exchange interaction under the basic condition (ΔW=0). On the other hand, as shown in the center of Figure 6, under the “N / P substrate” condition in the test apparatus, the range of variation was kept to ±20%, and as shown in the upper part of Figure 6, under the “N / P substrate & V” condition in the test apparatus, the range of variation was kept to ±20%, and as shown in the upper part of Figure 6, sub Under the condition of =0.3V, the range of variation is kept within ±1%. Thus, in Figure 6, the range of variation in the exchange interaction due to the influence of the two size change conditions (ΔW=-3nm, ΔW=+3nm) changes in the order of left, center, and right, and in this order the exchange interaction obtained under the size change conditions is equal to the J of the basic condition (ΔW=0). ex This indicates that it is approaching. In other words, this result indicates that in the test device, the exchange interaction (J) due to the variation in width W is ex This shows that the change in ) can be suppressed by introducing an "N / P substrate," and further, that this suppression effect becomes more pronounced when a voltage is applied to the back gate electrode.

[0043] <Verification of fidelity> As explained with reference to Figure 6, a dimensional error of just 3 nm can result in significant fluctuations in the exchange interaction. Therefore, the impact of these fluctuations on the device is of great interest. In this simulation test, the degree to which quantum computation operations performed on a device with dimensional errors become inaccurate compared to quantum computation operations performed on a standard device with correct dimensions is expressed by the “gate operation fidelity F” in equation (1) below. G It was evaluated using the following indicator.

[0044]

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[0045] Fidelity F G The calculation method will be explained. First, the test device and the comparative test device to be calculated are 2-qubit spin qubit devices, and the Hamiltonian of the 2-qubit state in a 2-qubit spin qubit device can be described by the following equations (2) to (4).

[0046]

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[0047] Next, the SWAP operation in a two-qubit spin qubit device is ideally realized when, in the Hamiltonian, a voltage pulse is applied to the BG (barrier gate) electrode for a constant time τ (=h / 2J0) to set J(t) = J0. In other words, in this case, the quantum state of the two qubits changes such that |0>|1>, where bit 1 is 0 and bit 2 is 1, is swapped (SWAP) to |1>|0>, where bit 1 is 1 and bit 2 is 0.

[0048] From this relationship, the SWAP operation of a standard device with correct dimensions can be defined by applying an ideal rectangular wave pulse voltage to the BG (barrier gate) electrode for a time τ = h / 2J0, assuming the initial quantum states of the two qubits are |0>|1>. In this case, the quantum operation K in a device with dimensional errors can be expressed using J0 of a reference device with correct dimensions and J0' of a device with dimensional errors, with fidelity F G The aforementioned equation (1) for ultimately reduces to the simple equations expressed in the following equations (5) and (6).

[0049]

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[0050] Therefore, for the test target device and the comparative test target device, (1) when the dimensions are correct (W=0), the exchange interaction J0 obtained by applying a pulse voltage to the BG (barrier gate) electrode for a time τ=h / 2J0 is calculated using the simulator; (2) when there is a dimensional error, the exchange interaction J0' obtained by applying a pulse voltage to the BG (barrier gate) electrode for a time τ=h / 2J0 is calculated using the simulator; and (3) using the obtained exchange interactions J0 and J0', the gate operation fidelity F is calculated by performing the calculations according to equations (5) and (6). G We obtained this F. G This can be called SWAP operation fidelity because the operation performed is a SWAP operation.

[0051] The calculation of SWAP operation fidelity is performed using the "P substrate" condition and "P substrate & V" conditions in the comparative test device. sub =0.3V condition, and the “N / P substrate” condition and “N / P substrate & V” in the test device. sub The experiment was conducted under four conditions with the "=0.3V" condition. sub The "=0.3V" condition is the condition in which a voltage of 0.3V is applied to the back gate electrode in the comparative test device. Figure 7 shows the calculation results for SWAP operation fidelity. Generally, a fidelity of 99% or higher is required as the standard for quantum error correction (see Reference 3). However, as shown in Figure 7, under the “N / P substrate” conditions in the test device, the “P substrate” conditions and “P substrate & V” conditions in the comparative test device are different. sub Compared to the =0.3V condition, it is possible to achieve SWAP operation fidelity of 99% or more with a wider range of dimensional variations (ΔW). Furthermore, in the aforementioned test device, the “N / P substrate & V sub Under the =0.3V condition, a SWAP operation fidelity of 99% or higher can be achieved with a significantly wider range of dimensional variations (ΔW) compared to other conditions, dramatically improving SWAP operation fidelity. In the aforementioned test device, “N / P substrate & V sub Under the 0.3V condition, dimensional variation (ΔW) with fidelity of 99% or higher is tolerated within a range of ±5nm, significantly exceeding the 0.9nm gate dimension variation of 3σ in state-of-the-art semiconductor manufacturing technology (the 2022 target value for IRDS (International Roadmap for Devices and Systems) by the IEEE), enabling large-scale qubit integration of more than 1 million qubits. Since this dramatic improvement in SWAP operation fidelity due to voltage application to the back gate electrode is not observed in the comparative test device, it is clear that it is influenced by the "N / P substrate" condition in the test device. Reference 3: AG Fowler et al., Phys. Rev. A, 86, 032324 (2012).

[0052] <Consideration of the principle for suppressing characteristic variations> Based on these simulation results, the “N / P substrate” conditions and “N / P substrate & V” for the test device are determined. sub We further investigated why the "=0.3V" condition suppresses characteristic variations caused by dimensional variations.

[0053] First, let's consider the cause of characteristic variations due to the influence of dimensional variations (ΔW). In a semiconductor-type two-qubit device, the exchange interaction between two qubits is affected by the potential barrier area between the two qubits, as shown in Figure 8. Figure 8 is an explanatory diagram showing the relationship between the exchange interaction between two qubits and the potential barrier area. If there is a dimensional variation (ΔW) in the width of the SOI layer, the energy levels of the two qubits change. This change simultaneously affects the potential barrier height (h) between the two qubits. B ) and the distance (d) between the bottom of the potential of one qubit and the bottom of the potential of the other qubits. B By changing both ) and the potential barrier (h B ) and distance (d B The potential barrier area (S) is determined primarily by ) B This brings about a change in the potential barrier area (S B The change in ) gives an exponential change to the exchange interaction between the two qubits. In other words, dimensional variation (ΔW) is equal to variation in potential barrier area (ΔS B This gives an exponential change to the exchange interaction between the two qubits. In other words, this finding suggests that even with dimensional variations (ΔW), variations in potential barrier area (ΔS) are not a problem. B If we can suppress this, it means we can suppress the change in the exchange interaction between the two qubits. In order to obtain the calculation results shown in Figure 8, the effective potential distribution between the two qubits was extracted. The potential Ψ was weighted by the electron density ρ in the quantum dot, and the effective one-dimensional potential distribution Ψ in the direction along the bit sequence of the qubit (x-direction) was obtained. 1D We found (x). The calculation results shown in Figure 8 are the two-dimensional electron density normalized by the following equation (7) (ρ 2D Effective one-dimensional potential distribution Ψ weighted by (y,z) 1D (x) is obtained using the following equation (8), and then the effective one-dimensional potential distribution Ψ is obtained. 1D (x) The potential barrier between the two qubits (h B ) and the distance (d) between the bottom of the potential of one qubit and the bottom of the potential of the other qubits. B ) and the potential barrier area (S B This was obtained by calculating ( ).

[0054]

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[0055] Next, even if there is dimensional variation (ΔW), the variation in potential barrier area (ΔS) B We will now verify, with reference to Figure 9, that if the above can be suppressed, the change in the exchange interaction between the two qubits can be suppressed. Figure 9 shows the potential distribution of the yz plane in the test device and the comparative test device obtained by the above calculation. In the comparative test apparatus, as shown on the left side of Figure 9, it was confirmed that the qubit region of the SOI layer receives potential control in a straight line from the P-type support layer. On the other hand, in the test apparatus, as shown on the right side of Figure 9, it was confirmed that the qubit region of the SOI layer receives potential control in a manner that wraps around from the corner of the outer edge of the upper surface of the N-type support layer towards the interior of the upper surface. This is thought to be because the fringe field generated by the N / P substrate imparts potential modulation to the qubit region. In other words, the fringe electric field, similar to the potential distribution shown in Figure 9, is generated in the same way as the controlled fringe electric field, wrapping around from the corners of the outer edge of the upper surface of the N-type support layer towards the interior of the upper surface. Therefore, it can be considered that potential modulation is applied to the qubit region in this manner. Furthermore, the fringe electric field is affected by the variation in the potential barrier area (ΔS B This is thought to contribute to suppressing the potential barrier area variation (ΔS) due to the variation in width W. B ) is the reference potential barrier area (S B The fringe field compensates for potential barrier modulation so that it approaches ).

[0056] Next, “N / P board & V sub We will examine the reason why the SWAP operation fidelity dramatically improved under the condition of =0.3V. Figure 10 shows the electron density distribution in bit 1 and bit 2, based on the electron wave functions in bit 1 and bit 2 obtained during the calculation of the exchange interaction mentioned above. As shown in the upper part of Figure 10, in the “N / P substrate” where no voltage is applied to the back gate electrode, the electrons in bit 1 and bit 2 are attracted to the plunger gate electrode side, resulting in an angular electron density distribution biased toward the interface with the gate oxide layer. On the other hand, in the “N / P substrate & V sub Under the condition of =0.3V, the electrons in bit 1 and bit 2 are attracted to the back gate electrode side, resulting in an electron density distribution in which electrons move from the upper surface side of the SOI layer towards the center. As a result, the effect of compensating for potential barrier modulation by the "N / P substrate" in the direction of wrapping around to the inside of the N-type support layer, and the effect of eliminating the bias in the electron density distribution in the thickness direction (z direction) of the N-type support layer, work in conjunction, and it is thought that the influence of dimensional variation in width W (ΔW) on the potential of bit 1 and bit 2 is further minimized.

[0057] Finally, d B h B SB Δd normalized in B , Δh B , ΔS B and the relationship with ΔW are shown in Fig. 11. As shown in Fig. 11, in the "P substrate" condition (P sub.) in the comparison test target device, as the variation of ΔW increases, Δh B / h B and ΔS B / S B change significantly, while in the "N / P substrate" condition (N / P sub.) in the test target device, the changes in Δh B / h B and ΔS B / S B can be suppressed. In particular, in the "N / P substrate & V sub = 0.3V" condition (N / P sub. & V sub = 0.3V), the changes in Δh B / h B and ΔS B / S B can be significantly suppressed. This result is consistent with the previous verification results and serves as conclusive evidence to support the effectiveness of the present invention.

Explanation of Reference Signs

[0058] 1, 21, 31 Support substrate 2, 22, 32 Fringe electric field formation layer 3, 23, 33 Buried oxide layer 4, 24, 34 Quantum dot semiconductor layer 5, 25, 35 Back gate electrode 10 Semiconductor type quantum bit device 20 Semiconductor type spin quantum bit device 27a, 27b, 27c, 37a, 37b, 37c Barrier gate electrode 28a, 28b, 38a, 38b Plunger gate electrode 29 Buried magnet layer 30 Semiconductor type charge quantum bit device

Claims

1. At least a support substrate composed of a first conductivity type semiconductor layer, A fringe field forming layer is formed on the support substrate and is composed of either a second conductivity type semiconductor layer having a different conductivity type from the first conductivity type semiconductor layer, or a metal layer that forms a Schottky barrier with the support substrate. A buried oxide layer formed on the fringe field forming layer, A quantum dot semiconductor layer formed on the aforementioned embedded oxide layer, on which quantum dots are formed, A semiconductor-type qubit device characterized by having the following features.

2. A semiconductor-type qubit device according to claim 1, having a back gate electrode that allows a voltage to be applied to a support substrate.

3. The semiconductor-type qubit device according to claim 1 or 2, wherein the thickness of the embedded oxide layer is 10 nm to 100 nm.

4. The semiconductor-type qubit device according to claim 1 or 2, wherein the quantum dot semiconductor layer is formed in the shape of a long strip when viewed from above, and the width of the long strip in the short direction is at most 100 nm.

5. The semiconductor-type qubit device according to claim 1 or 2, wherein the thickness of the quantum dot semiconductor layer is 2.5 nm to 50 nm.

6. The concentration of the first conductive type impurity in the support substrate is 1 × 10 １９ cm －３ The above describes a configuration in which the fringe field forming layer is composed of a second conductivity type semiconductor layer, and the second conductivity type impurity concentration is 1 × 10⁻⁶. １９ cm －３ The semiconductor-type qubit device according to claim 1 or 2, wherein the above conditions apply.

7. The semiconductor-type qubit device according to claim 6, wherein the support substrate is formed of Si and the second conductivity type semiconductor layer is formed of Si.

8. The semiconductor-type qubit device according to claim 1 or 2, wherein the quantum dot semiconductor layer is formed of any one of Si, SiGe, and Ge.

9. The embedded oxide layer is SiO ２ and GeO ２ A semiconductor-type qubit device according to claim 1 or 2, formed from either of the following.

10. At a minimum, a structure comprising: three barrier gate electrodes and two plunger gate electrodes formed on a quantum dot semiconductor layer via a gate insulating layer, with two of the plunger gate electrodes positioned one at a time between two adjacent barrier gate electrodes and spaced apart from the barrier gate electrodes, and quantum dots formed at two positions on the quantum dot semiconductor layer facing the plunger gate electrodes, A semiconductor-type qubit device according to claim 1 or 2, comprising a static magnetic field application unit capable of applying a static magnetic field to the quantum dot.

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