Switching element drive circuit

Abstract

To provide a driver circuit for a switching element including a protection circuit capable of distinctively determining short circuit of an output load and short circuit between a gate and an emitter.SOLUTION: A driver circuit drives a switching element which can be driven by switching a conduction state between a first terminal and a second terminal according to a control signal inputted to a control terminal. The circuit compares a first voltage which is a voltage at a terminal connected to the first terminal through a diode with a first reference voltage, compares a second voltage corresponding to the control terminal with a second reference voltage, and based on the comparison results, generates, as an error signal indicating abnormality of the switching element, a first error signal corresponding to short circuit of the load or a second error signal corresponding to short circuit of the second terminal of the control terminal and different from the first error signal.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a drive circuit for a switching element.

Background Art

[0002] There is known a switching element that can be driven by switching the conduction state between a first terminal and a second terminal according to a control signal input to a control terminal. As this type of switching element, there is an insulated gate bipolar transistor (IGBT: Insulated Gate Bipolar Transistor). The insulated gate bipolar transistor (hereinafter, appropriately referred to as "IGBT") includes a collector terminal, an emitter terminal, and a gate terminal as the first terminal, the second terminal, and the control terminal, respectively, and can switch the conduction state between the collector terminal and the emitter terminal according to a control signal applied to the gate terminal.

[0003] A switching element such as an IGBT is used in a power conversion device such as an inverter. In such a power conversion device, when a fault such as an open circuit occurs at the collector terminal (output terminal) to which the output load is connected while the IGBT is in the conduction state (on state), an excessive current flows between the collector terminal and the emitter terminal, and in some cases, there is a risk of causing problems such as damage to the switching element.

[0004] Some drive circuits for switching elements include a protection circuit for preventing such problems. For example, Patent Document 1 discloses an example of a drive circuit for a switching element including a circuit for protecting the switching element from faults such as an open circuit or a short circuit at the output terminal. In this document, when the IGBT is in the conduction state (on state), a drive circuit including a so-called DESAT circuit that detects the potential difference between the collector and the emitter and detects the overcurrent state of the IGBT based on whether the potential difference is greater than or equal to a certain value is proposed.

Prior Art Documents

Patent Documents

[0005] [Patent Document 1] Japanese Patent Publication No. 2002-208847 [Overview of the project] [Problems that the invention aims to solve]

[0006] Incidentally, in switching elements such as IGBTs, in addition to the aforementioned failures such as output terminal short circuits, short circuits can occur between the gate and emitter. Such gate-emitter short circuits also cause an increase in the collector-emitter potential difference in IGBTs. Therefore, the aforementioned DESAT circuit, which determines abnormalities based on the collector-emitter potential difference, cannot distinguish between an output terminal short circuit caused by a short circuit in the output load and a gate-emitter short circuit.

[0007] At least one embodiment of this present invention has been made in view of the above circumstances, and aims to provide a driving circuit for a switching element that includes a protection circuit capable of distinguishing and determining between a short circuit of the output load and a short circuit between the gate and emitter. [Means for solving the problem]

[0008] (1) The driving circuit of the switching element according to at least one embodiment of this embodiment is the same as the above In order to solve the problem, The conductivity between the first and second terminals is switched according to the control signal input to the control terminal. A drive circuit for a switching element that can be driven by, The cathode of the diode is connected to the first terminal, and the anode of the diode is connected to the first terminal. The first voltage, which is the voltage at the terminal, is the first voltage due to a short circuit of the load connected to the first terminal. A first comparator compares the voltage with a first reference voltage to determine the change in pressure, A second voltage corresponding to the voltage of the control terminal is short-circuited by the control terminal to the second terminal. A second comparator compares the change in the second voltage with a second reference voltage to determine the change in the second voltage. and, Based on the comparison results of the first comparator and the second comparator, the switch As an error signal indicating an abnormality of the element, a first error signal corresponding to a short circuit of the load, This corresponds to a short circuit of the control terminal to the second terminal and is a second error signal different from the first error signal. An error signal generation unit that generates an error signal, Equipped with 、 The error signal generation unit, If the first comparator determines that the first voltage exceeds the first reference voltage, and the second comparator determines that the second voltage exceeds the second reference voltage, the first error signal is generated as the error signal. If the first comparator determines that the first voltage exceeds the first reference voltage, and the second comparator determines that the second voltage is less than or equal to the second reference voltage, the second error signal is generated as the error signal. ru.

[0009] According to the embodiment of (1) above, in the first comparator, a first voltage, which is the voltage of a terminal connected via a diode to a first terminal to which a load is connected, is compared with a first reference voltage, and in the second comparator, a second voltage corresponding to the voltage of a control terminal is compared with a second reference voltage. Based on the comparison results of the first and second comparators, the error signal generation unit generates either a first error signal corresponding to a short circuit of the load, or a second error signal corresponding to a short circuit of the control terminal to the second terminal, as an error signal indicating an abnormality of the switching element. Since the first and second error signals are generated in different ways, the generated error signals can distinguish whether the abnormality in the switching element is a short circuit of the load or a short circuit of the control terminal to the second terminal, based on either the first or second error signal.

[0010] (2) In other embodiments, in the embodiment of (1) above, The error signal generation unit, If the first comparator determines that the first voltage exceeds the first reference voltage, and the second comparator determines that the second voltage exceeds the second reference voltage, the first error signal is generated as the error signal. If the first comparator determines that the first voltage exceeds the first reference voltage, and the second comparator determines that the second voltage is less than or equal to the second reference voltage, the second error signal is generated as the error signal.

[0011] According to the embodiment of (2) above, if the first comparator determines that the first voltage exceeds the first reference voltage, and the second comparator determines that the second voltage exceeds the second reference voltage, a first error signal is generated as an error signal. Furthermore, if the first comparator determines that the first voltage exceeds the first reference voltage, and the second comparator determines that the second voltage is less than or equal to the second reference voltage, a second error signal is generated as an error signal. By generating error signals according to the comparison results of the first and second comparators in this way, it is possible to distinguish whether the abnormality occurring in the switching element is a short circuit in the load or a short circuit to the second terminal of the control terminal.

[0012] (3) In other embodiments, in the embodiment of (1) or (2) above, The system includes a terminal for detecting the first voltage, a capacitive element connected between the terminal and the second terminal, and a current source for supplying a charging current to the capacitive element.

[0013] According to the embodiment of (3) above, the delay time until the first voltage rises to reach the first reference voltage due to a short circuit of the load or a short circuit to the second terminal of the control terminal in the switching element can be adjusted by the size of the capacitive element. Such adjustment of the size of the capacitive element can be performed, for example, to prevent false detection when the first voltage reaches the first reference voltage when switching the switching element from the off state to the on state, and by externally arranging the capacitive element relative to the package of the switching element drive circuit, the delay time can be easily adjusted by changing the capacitive element.

[0014] (4) In other embodiments, in any one embodiment of (1) to (3) above, The first error signal and the second error signal are pulse signals having different time widths from each other.

[0015] According to the aspect (4) above, by generating the first error signal and the second error signal as pulse signals having different time widths from each other, the receiving side of the error signal can preferably distinguish the first error signal and the second error signal based on the time width of the pulse signal.

[0016] (5) In another aspect, in any one of the aspects (1) to (4) above, When the voltage difference between the first voltage and the power supply voltage of the drive circuit of the switching element becomes not more than a predetermined value, the error signal generation unit generates the error signal based on the comparison result of the second comparator regardless of the comparison result of the first comparator.

[0017] According to the aspect (5) above, since the error signal is generated based on the voltage difference between the first voltage and the power supply voltage, even when the power supply voltage drops due to some factor, by detecting the rise of the first voltage, an accurate abnormality determination can be made when a short circuit of the load or the like occurs.

[0018] (6) In another aspect, in any one of the aspects (3) to (5) above, When the voltage difference between the second voltage and the power supply voltage of the drive circuit of the switching element becomes not more than a predetermined value, the current supply amount to the capacitor element is configured to increase.

[0019] According to the aspect (6) above, after it is determined that the switching operation to the on state of the switching element is completed depending on whether the voltage difference between the second voltage and the power supply voltage of the switching element becomes not more than a predetermined value, by increasing the current supply amount to the capacitor element via the terminal for detecting the first voltage, the delay time until the first voltage reaches the first reference voltage when a short circuit of the load or the like occurs can be shortened. Thereby, by shortening the period during which an excessive current flows through the switching element during the delay period, malfunctions such as breakage of the switching element can be preferably suppressed.

Advantages of the Invention

[0020] According to at least one embodiment of this present invention, a driving circuit for a switching element can be provided that includes a protection circuit capable of distinguishing and determining between a short circuit between the gate and emitter and a short circuit between the output terminals, such as a ceiling fault or a ground fault. [Brief explanation of the drawing]

[0021] [Figure 1] This is a circuit diagram showing the drive circuit for the switching element according to the first embodiment. [Figure 2] Figure 1 shows an example of the configuration of the error pulse generation circuit. [Figure 3A] This is a time chart showing the time changes of voltage and current at each part of the drive circuit in Figure 1 when the IGBT switches from the off state to the on state and when the DESAT circuit is operating. [Figure 3B] This is a time chart showing the time changes of voltage and current at each part of the drive circuit in Figure 1 when the IGBT switches from the off state to the on state and when the DESAT circuit is operating. [Figure 4] This is a circuit diagram showing the drive circuit for the switching element according to the second embodiment. [Figure 5] This is a circuit diagram showing the drive circuit for the switching element according to the third embodiment. [Figure 6] Figure 5 is a time chart showing the time changes of voltage and current at each part of the drive circuit when the IGBT switches from the off state to the on state and when the DESAT circuit is operating. [Figure 7] This is a circuit diagram of a driving circuit for a switching element related to the reference technology. [Figure 8] Figure 7 is a time chart showing the time changes of voltage and current at each part of the drive circuit when the IGBT switches from the off state to the on state and when the DESAT circuit is operating. [Figure 9] This is a circuit diagram of the switching element drive circuit 1'' related to other reference technologies. [Modes for carrying out the invention]

[0022] Hereinafter, several embodiments of this disclosure will be described with reference to the attached drawings. However, the dimensions, materials, shapes, relative arrangements, etc., of the components described or shown in the drawings as embodiments are not intended to limit the scope of this disclosure, but are merely illustrative examples.

[0023] (Reference technology) First, we will describe some reference technologies that serve as the basis for several embodiments of the present invention. Figure 7 is a circuit diagram of a switching element drive circuit 1' according to the reference technology, and Figure 8 is a time chart showing the time changes of voltage and current in each part of the drive circuit 1' in Figure 7 when the IGBT is switched from the off state to the on state (turn-on) and when the DESAT circuit is operating.

[0024] The drive circuit 1' has a switching element that can be driven by switching the conduction state between the first terminal and the second terminal in accordance with a control signal input to the control terminal. In this example, the switching element is an IGBT, and the first terminal, second terminal, and control terminal are provided as a collector terminal, emitter terminal, and gate terminal, respectively, and the conduction state between the collector terminal and the emitter terminal can be switched in accordance with a control signal applied to the gate terminal.

[0025] A load L, which can be driven by the load power supply VLOAD, is connected to the collector terminal of the IGBT. An external gate drive signal is input to the drive circuit 1', and the IGBT is driven according to the gate drive signal. Specifically, when transistor MP1 turns on in response to the gate drive signal, the output voltage of power supply VSUP is applied from the PG terminal to the gate terminal of the IGBT via resistor R1, thereby switching the IGBT to the ON state.

[0026] If the IGBT is in the ON state and a short circuit occurs across the load L (fault), the collector-emitter voltage Vce of the IGBT will rise, potentially causing an excessive current to flow between the collector and emitter of the IGBT. Therefore, the drive circuit 1' includes a DESAT circuit as a protection circuit to detect this event and resolve the overcurrent condition by switching the IGBT to the OFF state.

[0027] The drive circuit 1' has a DESAT terminal connected to the collector terminal of the IGBT via a diode D1. Typically, the load power supply VLOAD is configured to supply a voltage greater than the power supply VSUP. Therefore, diode D1 is provided to prevent excessive voltage from being applied to the DESAT terminal. The voltage at the DESAT terminal (first voltage V1) is compared with a first reference voltage VREF1 by the first comparator COMP1. The first comparator COMP1 inputs an output signal corresponding to the comparison result between the first voltage V1 at the DESAT terminal and the first reference voltage VREF1 to the error pulse generation circuit 2'. Specifically, the output signal of the first comparator COMP1 is at an H level if the first voltage V1 is greater than the first reference voltage VREF1, and at an L level if the first voltage V1 is less than or equal to the first reference voltage VREF1.

[0028] Furthermore, the capacitive element C1 provided between the DESAT terminal and the emitter terminal is an element for setting a delay time when the first voltage V1 at the DESAT terminal rises. As shown in Figure 8, at time t0, the gate drive signal VIN is input to the IN terminal, and at time t1, the gate-emitter voltage Vge of the IGBT reaches the threshold voltage of the IGBT. During the period ton from time t1 to t3, when the IGBT is switched from the off state to the on state (turn-on), setting a delay time with the capacitive element C1 prevents the DESAT circuit from operating before the IGBT is completely switched on. In the example in Figure 7, the capacitive element C1 is charged by the current source I1, generating a delay time until the first voltage V1 at the DESAT terminal reaches the first reference voltage VREF1.

[0029] In the DESAT circuit, under normal operation, when the IGBT is turned on at time t1, the collector-emitter voltage Vce decreases, causing diode D1 to turn on. As a result, at time t2, the first voltage V1 at the DESAT terminal is maintained at a constant value (clamped) and becomes below the first reference voltage VREF (at this time, the output signal of the first comparator COMP1 is at the L level). On the other hand, if a short circuit occurs across the load L at time ts after time t3, the collector-emitter voltage Vce of the IGBT rises, and consequently, the first voltage V1 at the DESAT terminal also rises. Here, the first voltage V1 at the DESAT terminal exhibits a gradually increasing behavior, having a delay time corresponding to the capacitance value of the capacitive element C1 connected between the DESAT terminal and the emitter terminal. In the first comparator COMP1, when the first voltage V1 at the DESAT terminal reaches the first reference voltage VREF1, the output signal switches from L level to H level, which detects that a short circuit occurred across the load L at time t4.

[0030] The output signal of the first comparator COMP1 is input to the error pulse generation circuit 2'. The error pulse generation circuit 2' generates a pulse (voltage signal) with a predetermined H level time width corresponding to the input level from the first comparator COMP1. The pulse signal output from the error pulse generation circuit 2' is input to the S terminal of the RS-FF circuit 4, causing the output of the Q terminal of the RS-FF circuit 4 to latch to an H level. As a result, the output of the inverting circuit INV1 switches to an H level, turning off transistor MP1 and turning on transistor MN1, thereby lowering the gate voltage Vge of the IGBT and turning off the IGBT, thus resolving the IGBT overcurrent condition.

[0031] On the other hand, the pulse signal output from the error pulse generation circuit turns transistor MN2 ON for a certain period of time (the duration of the H level pulse), switching the FLT terminal voltage to the L level. The FLT terminal voltage is input as an error signal to an external control microcontroller or similar device (not shown). The control side can determine that the DESAT circuit has operated by receiving this error signal.

[0032] The drive circuit 1' having the above configuration has advantages in that it does not require a terminal for detecting current on the IGBT side or a resistor for current detection on the emitter terminal side. However, since it does not directly detect the current flowing through the IGBT, even if a short circuit occurs between the gate-emitter terminals of the IGBT, causing the IGBT to turn off, the first voltage V1 at the DESAT terminal will exceed the first reference voltage VREF1, similar to the case where a short circuit occurs in the load L as described above. In other words, the DESAT circuit described above, which performs abnormality determination based on the comparison result of the first voltage V1 and the first reference voltage VREF1 in the first comparator COMP1, cannot distinguish between abnormalities due to a short circuit at the output terminal and abnormalities related to a short circuit between the gate and emitter. Such problems can be suitably resolved by the embodiments described below.

[0033] (First Embodiment) Figure 1 is a circuit diagram showing the drive circuit 1A of the switching element according to the first embodiment, and Figure 2 is an example of the configuration of the error pulse generation circuit 2 in Figure 1. In subsequent embodiments, common reference numerals will be used to denote configurations corresponding to the aforementioned reference technologies, and redundant explanations will be omitted unless otherwise specified.

[0034] The drive circuit 1A shown in Figure 1 has an NG terminal connected to the gate terminal via a resistor R2 in order to pull down the voltage at the gate terminal of the IGBT. The voltage at the NG terminal (second voltage V2) is compared with the second reference voltage VREF2 by the second comparator COMP2. Specifically, the output signal of the second comparator COMP2 is at an H level when the second voltage V2 is less than or equal to the second reference voltage VREF2, and at an L level when the second voltage V2 is greater than the second reference voltage VREF2.

[0035] The output signal of the second comparator COMP2 is input to the error pulse generation circuit 2. As shown in Figure 2, the error pulse generation circuit 2 includes a first input terminal OUT_COMP1 to which the output signal of the first comparator COMP1 is input, and a second input terminal OUT_COMP2 to which the output signal of the second comparator COMP2 is input. The error pulse generation circuit 2 also includes a first pulse generator 6A and a second pulse generator 6B that detect the rising edges of the output signals of logic circuits AND1 and AND2, respectively, and generate pulse signals. The first pulse signal P1 generated by the first pulse generator 6A and the second pulse signal P2 generated by the second pulse generator 6B are different from each other. In this embodiment, the first pulse signal P1 and the second pulse signal P2 have different time widths T1 and T2, but other parameters such as frequency and amplitude may also be different. The first pulse signal P1 and the second pulse signal P2 generated by the first pulse generator 6A and the second pulse generator 6B are input to the OR logic circuit, respectively, and their logical OR is output as the output signal POUT of the error pulse generation circuit 2.

[0036] Next, the specific operation of the drive circuit 1A having the above configuration will be explained. Figures 3A and 3B are time charts showing the time changes of voltage and current at each part of the drive circuit 1A in Figure 1 when the IGBT switches from the off state to the on state (turn-on) and when the DESAT circuit is operating. Note that in Figures 3A and 3B, the NG terminal voltage V2 and the IGBT gate voltage VNG are shown as the same waveform. Strictly speaking, when the voltage at the IGBT gate terminal is pulled down, a difference will occur due to the potential difference generated across resistor R2.

[0037] In Figures 3A and 3B, at time t0, the gate drive signal VIN, which is input externally to the IN terminal of drive circuit 1A, switches from L level to H level, initiating the switching of the IGBT from the off state to the on state. When the gate drive signal input to the IN terminal of drive circuit 1A switches from L level to H level, transistor MP1 turns on, and transistors MN1 and MN3 turn off. As a result, the gate voltage VNG of the IGBT rises, and the first voltage V1 at the DESAT terminal also rises. Then, at time t1, when the gate voltage VNG reaches the threshold voltage of the IGBT (second reference voltage VREF2), the IGBT turns on, and the collector-emitter voltage Vce decreases (the diode D1 turns on, and at time t2, the first voltage V1 at the DESAT terminal is maintained at a constant value (clamped)). Subsequently, at time t3, the charging of the gate capacitance of the IGBT is completed, and the IGBT is fully on.

[0038] In Figure 3A, after the IGBT is turned on, at time ts, a short circuit occurs across the load L, causing the collector-emitter voltage Vce to rise sharply. As a result, the first voltage V1 at the DESAT terminal reaches the first reference voltage VREF1 at time t4 after a delay time corresponding to the capacitive element C1. At this time, the second voltage V2 at the NG terminal is greater than the second reference voltage V2, so the output signal of the second comparator COMP2 becomes L level. Therefore, in the error pulse generation circuit 2, as shown in Figure 2, the input to the pulse generator P1 is switched to H level, and the first pulse signal P1 with a time width T1 is output from the POUT terminal. The first pulse signal P1 output from the error pulse generation circuit 2 is input to the S terminal of the RS-FF circuit 4, and by switching the output of the Q terminal of the RS-FF circuit 4 to H level, transistor MP1 is turned off, transistors MN1 and MN3 are turned on, the IGBT is turned off to eliminate the overcurrent condition, and the first voltage V1 at the DESAT terminal is lowered to ground level.

[0039] Furthermore, the first pulse signal P1 output from the error pulse generation circuit 2 turns transistor MN2 ON for a time width T1, causing an error signal with a time width T1 to be output from the FLT terminal. As a result, the external controller can determine, based on the time width T1 of the received error signal, that a short circuit occurred across both ends of the load L at time ts.

[0040] In Figure 3B, after the IGBT is turned on, at time ts, a short circuit occurs between the gate and emitter of the IGBT, causing it to turn off and the collector-emitter voltage Vce to rise. As a result, the first voltage V1 at the DESAT terminal reaches the first reference voltage VREF1 at time t4 after a delay time corresponding to the capacitive element C1. At this time, the gate voltage VNG is lowered to near ground voltage due to the short circuit between the gate and emitter of the IGBT, and the second voltage V2 at the NG terminal is below the second reference voltage VREF2, so the output signal of the second comparator COMP2 is at a high level. Therefore, in the error pulse generation circuit 2, as shown in Figure 2, the input of the pulse generator P2 is switched to a high level, and a second pulse signal with a time width T2 (>T1) is output from the POUT terminal. At this time, the IGBT is in the off state, as shown in Figure 3A, and the second pulse signal P2 output from the error pulse generation circuit 2 turns transistor MN2 ON for a time width T2, causing an error signal with a time width T2 to be output from the FLT terminal. As a result, the external controller can determine, based on the time width T2 of the received error signal, that a short circuit occurred between the gate and emitter of the IGBT at time ts.

[0041] As the error signal output from the FLT terminal has a time width corresponding to the type of event that occurred in the IGBT, an external controller can accurately determine what kind of event occurred in the IGBT based on the type of error signal received (in this embodiment, the time width).

[0042] Here, Figure 9 is a circuit diagram of a switching element drive circuit 1'' relating to another reference technology. In this drive circuit 1'', a resistor RS is provided to measure the source current of transistor MP1, which is connected to the PG terminal that supplies current to the gate terminal, in order to detect a short circuit between the gate and emitter of the IGBT. By comparing the potential difference across the ends of resistor RS with a reference voltage VREF using a comparator COMP, it is possible to determine whether or not an excessive current is flowing through transistor MP1.

[0043] In such a drive circuit 1'', when the IGBT gate voltage rises, the current IPG at the PG terminal becomes temporarily excessive, as shown in Figure 3B at times t0 to t1. Therefore, a delay circuit 8 is provided on the output side of the comparator COMP to set a delay period to disable the signal from the comparator COMP while the gate voltage is rising. Since this delay period depends on the gate capacitance of the IGBT, it must be adjusted according to the gate capacitance (if the delay period is not adjusted appropriately, the output of the comparator COMP may switch during the normal operation of the IGBT, potentially leading to a false detection of a short circuit between the gate and emitter of the IGBT). Accordingly, if the drive circuit 1'' is integrated as an integrated circuit, as shown in the configuration of Figure 9, additional terminals for connecting capacitances, etc., must be added so that the capacitances, etc., can be replaced in order to adjust the delay period.

[0044] In contrast, in the drive circuit 1A shown in this embodiment (see Figures 1 to 3), as described above, when the first voltage V1 at the DESAT terminal rises to the first reference voltage VREF1, the gate voltage of the IGBT is detected by the second voltage V2 at the NG terminal and compared with the second reference voltage VREF2 to determine whether or not a short circuit has occurred between the gate and emitter of the IGBT. Normally, the capacitive element C1 connected to the DESAT terminal is set to match the gate rise time of the IGBT (the size of the capacitive element C1 is adjusted so that false detection does not occur when the first voltage V1 exceeds the first reference voltage VREF1 during switching from the off state to the on state, as described above). Therefore, if the gate capacitance is large and the gate rise time is long, this can be addressed by increasing the size of the capacitive element C1 connected to the DESAT terminal. In this way, it is possible to address this using the existing configuration of the capacitive element C1, and thus it is not necessary to add terminals as in the reference technology shown in Figure 9.

[0045] Furthermore, in the reference technology shown in Figure 9, the short-circuit state between the gate and emitter of the IGBT is determined based on the current IPG flowing through the PG terminal. However, the current IPG continues to flow until the PG terminal voltage rises to near the output voltage of the power supply VSUP, and its value depends on the resistance value of resistor R1 installed between the PG terminal and the gate terminal of the IGBT. Therefore, depending on the delay time of the delay circuit and the resistance value of resistor R1, it may be possible to determine that the gate and emitter of the IGBT is short-circuited even though the IGBT is normally in the ON state.

[0046] In contrast, in the drive circuit 1A shown in this embodiment (see Figures 1 to 3), if the IGBT is in the normally ON state, the first voltage V1 at the DESAT terminal does not rise to the first reference voltage VREF1, so such false detection does not occur. Also, since the transistor MN1 is in the OFF state when the gate voltage rises, no potential difference is generated across the resistor R2, and the gate voltage of the IGBT can be measured accurately.

[0047] (Second Embodiment) Figure 4 is a circuit diagram showing the drive circuit 1B of the switching element according to the second embodiment.

[0048] In the aforementioned drive circuit 1A, the first reference voltage VREF1, which is used for comparison with the first voltage V1 at the DESAT terminal in the first comparator COMP1, is set according to the output voltage of the power supply VSUP. For example, if the output voltage of the power supply VSUP is 15V, it is often set to around 6V. In this situation, if for some reason the output voltage of the power supply VSUP connected to the VDD terminal drops to 6V or less, even if the IGBT load L is short-circuited, the first voltage V1 at the DESAT terminal may not rise to the first reference voltage VREF1, and the fault may not be detected.

[0049] Typically, this type of drive circuit includes a UVLO (Voltage Reduction Lockout) circuit to monitor the output voltage of the power supply VSUP, and controls the IGBT to switch off when a drop in the VSUP output voltage is detected. However, such a UVLO circuit has a delay time of several microseconds to prevent it from being activated by temporary fluctuations in the output voltage of the VSUP during gate driving. If this delay time is longer than the detection time of the DESAT circuit (the time from time ts to time t4 when the first voltage V1 reaches the first reference voltage VREF1 in Figures 3A and 3B), an excessive current will continue to flow through the IGBT during this time.

[0050] In contrast, in the drive circuit 1B, the error pulse generation circuit 2 is configured such that when the voltage difference between the first voltage V1 at the DESAT terminal and the output voltage of the power supply VSUP falls below a predetermined value (third reference voltage VREF3), an error signal is generated based on the comparison result of the second comparator COMP2, regardless of the comparison result of the first comparator COMP1. Figure 4 shows an example of such a drive circuit 1B configuration, which includes a third comparator COMP3 that compares the first voltage V1 at the DESAT terminal with the third reference voltage VREF3. Since the third reference voltage VREF3 is connected to the power supply VSUP via the VDD terminal, the voltage input to the inverting input terminal of the third comparator COMP3 depends on the output voltage of the power supply VSUP.

[0051] If the output voltage of the power supply VSUP drops due to some factor, the voltage input to the inverting input terminal of the third comparator COMP3 will be lower than the first reference voltage VREF1. Therefore, even if the first voltage V1 in the first comparator COMP1 cannot reach the first reference voltage VREF1 when the ends of the load L are short-circuited, the third comparator COMP3 can monitor the voltage difference between the first voltage V1 and the output voltage of the power supply VSUP, thereby supplying a high-level output signal to the error pulse generation circuit 2 via the OR gate.

[0052] Thus, in the drive circuit 1B, even when the output voltage of the power supply VSUP drops, fault detection is possible based on the rise in the first voltage V1 at the DESAT terminal caused by the abnormality. Therefore, compared to control that switches the IGBT to the off state by the UVLO circuit, the time during which excessive current flows through the IGBT is significantly reduced, and damage to the IGBT can be effectively prevented.

[0053] (Third embodiment) Figure 5 is a circuit diagram showing the drive circuit 1C of the switching element according to the third embodiment, and Figure 6 is a time chart showing the time changes of voltage and current in each part of the drive circuit 1C of Figure 5 when the IGBT is switched from the off state to the on state (turn-on) and when the DESAT circuit is operating.

[0054] When a short circuit occurs across the load L or between the gate and emitter, the delay time until the first voltage V1 at the DESAT terminal rises to reach the first reference voltage VREF1 is set, as described above, so that the first voltage V1 at turn-on, when the IGBT switches from the off state to the on state, does not reach the first reference voltage VREF1. On the other hand, as described above with reference to Figure 3, once the IGBT is fully turned on by the second voltage V2 at the NG terminal rising to the IGBT on voltage, the constraints at turn-on are removed, and by setting a shorter delay time, faster anomaly detection becomes possible.

[0055] To solve these problems, the drive circuit 1C is configured to increase the amount of current supplied to the DESAT terminal that detects the first voltage V1 (source current IDESAT) when the voltage difference between the second voltage V2 at the NG terminal and the output voltage of the power supply VSUP falls below a predetermined value, that is, to increase the amount of current supplied to the capacitive element C1. Figure 5 shows an example of such a drive circuit 1C configuration, which includes a fourth comparator COMP4 that compares the second voltage V2 at the NG terminal with the output voltage of the power supply VSUP. When the fourth comparator COMP4 detects that the voltage difference between the second voltage V2 and the output voltage of the power supply VSUP has fallen below the fourth reference voltage VREF4, the RS-FF circuit 12 switches the switch SW connected to the current source I2 to ON, thereby increasing the amount of current supplied to the DESAT terminal to I1 + I2. As a result, as shown in Figure 6, when the IGBT is fully ON at time t3', and then at time ts a short circuit occurs across the load L or a gate-emitter short circuit occurs (a fallout), the delay time (time ts~t4') until the first reference voltage VREF1 at the DESAT terminal rises can be shortened. Consequently, the time during which excessive current flows through the IGBT is further reduced, effectively preventing damage to the IGBT.

[0056] Furthermore, in the drive circuit 1C having such a configuration, the IGBT being fully turned on is determined by the condition that the voltage difference between the second voltage V2 at the NG terminal and the output voltage of the power supply VSUP rises to the fourth reference voltage VREF4. When the capacitance of the IGBT is large, the rise time until the IGBT is fully turned on increases, and the delay time until the output of the fourth comparator COMP4 switches becomes longer. This increases the source current to the DESAT terminal before the IGBT is fully turned on, preventing the delay time until the first voltage V1 reaches the first reference voltage VREF1 from becoming shorter than the set value. [Explanation of symbols]

[0057] 1A-1C drive circuit 2. Error pulse generation circuit 4 RS-FF circuit 8. Delay Circuit 12 RS-FF circuit C1 Capacitive element COMP1 First comparator COMP2 Second Comparator COMP3 Third Comparator COMP4 Fourth Comparator D1 diode I1 current source I2 current source IGBT switching element L load SW Switch VREF1 First Reference Voltage VREF2 Second Reference Voltage VREF3 Third Reference Voltage VREF4 4th Reference Voltage V1 First Voltage V2 Second voltage VSUP power supply

Claims

1. A drive circuit for a switching element that can be driven by switching the conductivity state between a first terminal and a second terminal in accordance with a control signal input to a control terminal, A first comparator is provided, to which the cathode of a diode is connected to the first terminal, and which compares a first voltage, which is the voltage at the terminal to which the anode of the diode is connected, with a first reference voltage for determining the change in the first voltage due to a short circuit of a load connected to the first terminal. A second comparator compares a second voltage corresponding to the voltage of the control terminal with a second reference voltage for determining a change in the second voltage due to the control terminal being short-circuited to the second terminal, An error signal generation unit generates, based on the comparison results of the first comparator and the second comparator, an error signal indicating an abnormality of the switching element, which is either a first error signal corresponding to a short circuit of the load, or a second error signal different from the first error signal corresponding to a short circuit of the control terminal to the second terminal. Equipped with, The error signal generation unit, If the first comparator determines that the first voltage exceeds the first reference voltage, and the second comparator determines that the second voltage exceeds the second reference voltage, the first error signal is generated as the error signal. A switching element drive circuit that generates the second error signal as the error signal when the first comparator determines that the first voltage exceeds the first reference voltage, and the second comparator determines that the second voltage is less than or equal to the second reference voltage.

2. A driving circuit for a switching element according to claim 1, comprising a terminal for detecting the first voltage, a capacitive element connected between the terminal and the second terminal, and a current source for supplying a charging current to the capacitive element.

3. The switching element drive circuit according to claim 1 or 2, wherein the first error signal and the second error signal are pulse signals having different time widths.

4. The switching element drive circuit according to claim 1 or 2, wherein the error signal generation unit generates the error signal based on the comparison result of the second comparator, regardless of the comparison result of the first comparator, when the voltage difference between the first voltage and the power supply voltage of the switching element drive circuit falls below a predetermined value.

5. The switching element drive circuit according to claim 2, wherein the second voltage is configured to increase the amount of current supplied to the capacitive element when the voltage difference between the second voltage and the power supply voltage of the switching element drive circuit falls below a predetermined value.

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