Integrated antenna array with beamformer IC chip having multiple surface boundaries

Abstract

To provide a compact antenna device that integrates an RFIC chip and an antenna array, and a method for manufacturing the antenna device.SOLUTION: An antenna device 100 includes an antenna substrate 110 having opposing first and second surfaces and at least one antenna element 125_i arranged on the first surface, at least one RFIC chip 150_j having a bottom surface attached to the second surface of the antenna substrate and having an RF contact 157 coupled to the at least one antenna element through the antenna substrate, the RFIC chip includes an RF signal conductor 151_s on its top surface and beam forming circuits 130_i, 153 coupled between the RF contact and the RF signal conductor, and a transmission line section 180 having a bottom surface attached to the second surface of the antenna substrate and a top surface on which a transmission line conductor 181_s is arranged and electrically connected to the RF signal conductor of the RFIC chip through a top surface wiring 141.SELECTED DRAWING: Figure 3-1

Description

Technical Field

[0001] The present disclosure generally relates to a distributed beamformer integrated circuit (IC) chip-integrated antenna array.

Background Art

[0002] Today, antenna arrays are widely used in various applications at microwave and millimeter-wave frequencies in aircraft, satellites, vehicles, ships, and general-purpose ground-based communication base stations, etc. Such antenna arrays typically include microstrip radiating elements driven by a phase shift beamforming circuit to generate a phased array for beam steering. Typically, the entire antenna system including the antenna array and the beamforming circuit is desired to be thin and occupy minimal space.

[0003] An integrated antenna array may be defined as an antenna array composed of antenna elements integrated with a radio frequency (RF) integrated circuit (RFIC) chip (also referred to as a "beamformer IC" (BFIC)) in a compact structure. The integrated antenna array may have a sandwich-type configuration in which the antenna elements are disposed in an exterior component layer and the RFIC is distributed over the entire effective antenna aperture in a proximity parallel component layer behind the antenna element layer. The RFIC may include a transmitting RF power amplifier (PA), a receiving low noise amplifier (LNA), and / or a phase shifter for beam steering. By dispersing the PA / LNA in this way, higher efficiency in transmission and / or improved noise performance in reception can be achieved, as well as higher reliability compared to non-distributed IC designs.

Summary of the Invention

[0004] In one aspect of the present disclosure, the antenna device comprises an antenna substrate having opposing first and second surfaces. At least one antenna element is disposed on the first surface of the antenna substrate. At least one radio frequency integrated circuit (RFIC) chip has a lower surface attached to the second surface of the antenna substrate and has an RF contact coupled to at least one antenna element through the antenna substrate. At least one RFIC chip has an RF signal conductor on its upper surface and a beamforming circuit coupled between the RF contact and the RF signal conductor. The transmission line section has a lower surface attached to the second surface of the antenna substrate and an upper surface through which the transmission line conductor is disposed and connected to the RF signal conductor of the RFIC chip via upper surface wiring such as wire bonds, ribbon bonds, or edge contact pairs.

[0005] This means that at least one RFIC chip within the integrated antenna structure has multiple surface boundaries, which can provide performance and manufacturing advantages for the antenna device.

[0006] Embodiments of a phased array antenna include a plurality of antenna elements arranged on a first surface of an antenna substrate, and a plurality of RFIC chips mounted on a second surface of the antenna substrate, each having a lower surface and an RF contact, each coupled to at least one of the antenna elements. Each RFIC chip has an RF signal conductor on its upper surface and a beamforming circuit for beam manipulation coupled between each RF contact and the RF signal conductor. At least one transmission line is arranged between the RFIC chips and has a plurality of branch arm conductors of a beamforming network (BFN) on its upper surface, with each branch arm conductor connected to the RF signal conductor of each RFIC chip through upper surface wiring. [Brief explanation of the drawing]

[0007] The above and other aspects and features of the disclosed technology will become more apparent from the following detailed description, in conjunction with the accompanying drawings in which similar reference letters indicate similar elements or features. Different elements of the same or similar kind may be distinguished by adding a reference label with an underline / dash and a second label that distinguishes them within the same / similar elements (e.g., _1, _2), or by directly adding a reference label with a second label. However, where given the description uses only a first reference label, this label is applicable to any one of the same / similar elements having the same first reference label, regardless of the second label. Elements and features may not be drawn to scale in the drawings.

[0008] [Figure 1] Figure 1 is a plan view of an exemplary antenna device according to one embodiment. [Figure 2] Figure 2 is a front and side view of the antenna device shown in Figure 1. [Figure 3] Figure 3A is a partial cross-sectional view of the antenna device taken along the line 3A-3A in Figure 1, showing an exemplary wiring structure suitable between the CPW RFIC chip and the CPW transmission line. Figure 3B is a cross-sectional view of the exemplary wiring structure within the antenna device, taken along a plane perpendicular to the plane shown in Figure 3A. [Figure 4] Figure 4A is a partial cross-sectional view of an antenna device taken along the line 3A-3A in Figure 1, in one embodiment using a microstrip chip and a microstrip transmission line. Figure 4B is a cross-sectional view of an exemplary wiring structure within the antenna device of Figure 4A, taken along a plane perpendicular to the plane shown in Figure 4A. [Figure 5] Figure 5A is a plan view of another embodiment of an antenna device using a microstrip RFIC chip and a CPW transmission line. Figure 5B is a plan view showing a portion of the RFIC chip in the antenna device of Figure 5A. Figure 5C is a cross-sectional view of an exemplary wiring structure taken along the 5C-5C line in Figure 5A. [Figure 6]Figure 6A is a plan view showing a portion of a microstrip RFIC chip in another embodiment of the antenna device, with the active die side of the RFIC chip facing the antenna substrate. Figure 6B is a plan view showing a portion of a CPW chip in another embodiment of the antenna device, with the active die side of the RFIC chip facing the antenna substrate. [Figure 7] Figures 7A-7C are schematic diagrams of each active circuit unit (ACU) in an exemplary antenna device. [Figure 8] Figure 8 is a schematic diagram showing an exemplary beamforming circuit with multiple ACUs within an RFIC chip. [Figure 9] Figure 9 is a schematic diagram showing the beamforming network within the antenna device. [Figure 10] Figure 10 is a flowchart illustrating an exemplary method for manufacturing an antenna device. [Modes for carrying out the invention]

[0009] For explanatory purposes, the following description is provided with reference to the accompanying drawings to assist in a comprehensive understanding of certain exemplary embodiments of the technology disclosed herein. The description includes various specific details to help those skilled in the art understand the technology, but these details should be considered merely illustrative. For the purposes of simplification and clarification, descriptions of well-known functions and structures may be omitted where their inclusion would obscure the understanding of the technology by those skilled in the art.

[0010] Figure 1 is a plan view of an exemplary antenna device 100 according to one embodiment, and Figure 2 is a front side view of the antenna device 100. Referring together to Figures 1 and 2, the antenna device 100 (hereinafter referred to as "antenna 100") includes an antenna substrate 110 having a top surface 111 on which a plurality of radio frequency integrated circuit (RFIC) chips 150_1 to 150_K are mounted. (Note that the RFIC chip 150 is also called a beamformer IC (BFIC) chip.) N antenna elements 125_1 to 125_N that form a planar array 122 may be arranged on the bottom surface 113 of the antenna substrate 110. Each antenna element 125_i is coupled to the RFIC chip 150_j (i,j = any integer) through vias 155 (forming probe feeds) and RF contacts 157 located on the bottom surface of the RFIC chip 150_j. Next, each RF contact 157 is coupled to an RF signal conductor 151_s on the upper surface of the RFIC chip 150_j through a beamforming circuit that includes one or more active circuit units (ACUs) such as 130_1, 130_2, etc. The integer values ​​of K and N may vary from embodiment to embodiment depending on the application. In the following discussion (and as shown in Figures 1 and 2), for ease of understanding, we will discuss an example of a “small array” where K=4 and N=8.

[0011] The antenna substrate 110 may include a dielectric layer 190, a grounding surface 210 for reflecting signal energy from the antenna element 125, and a layer region 220 ("Redistribution Layer (RDL)") containing conductive lines for DC and / or control signals supplied to the RFIC chip 150. At least one transmission line ("TL") section 180 has a lower surface attached to the upper surface 111 of the antenna substrate 110. The TL section 180 has an upper surface on which the signal conductors 181_s of the transmission line are arranged and coupled at K positions through each upper surface wiring (USIN) 141 to the RF signal conductors 151_s. (Each K position of the signal conductors 181_s may be called a branch arm of the combiner / divider.) The USIN 141 is wiring directly created between the conductors on the upper surface of the RFIC chip 150 and the TL section 180. Therefore, the USIN141 does not include vias on either the RFIC chip 150 or the TL section 180 for interconnecting conductors 151 and 181 through conductive elements in the antenna substrate 110 on the upper surface. Some examples of the USIN141 include wire bonds, ribbon bonds, and edge contact pairs (edge ​​contacts on the TL section 180 and edge contacts on the RFIC chip 150 welded to them).

[0012] The TL section 180 may include 2:1 RF couplers 118_1, 118_2, and 118_3, such as Wilkinson or hybrid couplers, which form the overall K:1 combiner / divider. In the illustrated embodiment, the transmission line medium for both the TL section 180 and the RFIC chip 150 is a coplanar waveguide (CPW). In the CPW medium, a pair of ground conductors 181_g1 and 181_g2 are located on the opposite side of the signal conductor 181_s, and a pair of ground conductors 151_g1 and 151_g2 are located on the opposite side of the signal conductor 151_s. Each ground conductor 151_g1 and 151_g2 is interconnected with its adjacent portion via USIN 141. Alternatively, the transmission line medium for the RFIC chip 150 and the TL section 180 may be a microstrip, in which case the ground conductors 151 and 181 are omitted. Here, an RFIC chip 150 having a CPW beamforming circuit is referred to as a CPW chip, and an RFIC chip 150 having a microstrip beamforming circuit is referred to as a microstrip chip 150. Similar terminology may be used for the TL section 180. In other embodiments illustrated in Figure 1, the microstrip chip 150 may be interconnected with the CPW TL section 180 through hybrid transitions within the microstrip chip 150. This embodiment will be described later in relation to Figures 5A to 6. In all cases, an example of the material for the dielectric substrate 185 of the TL section 180 is alumina. In medium or large element arrays, the antenna 100 may include multiple TL sections 180 to facilitate manufacturing, particularly handling of brittle alumina substrates. Multiple TL sections 180 may be interconnected by wire bonds or the like if necessary.

[0013] Along with the wiring structure and the layout of the antenna 100, the top of the RFIC chip 150 is on the active die side (active region) of the chip, where the beamforming circuit, including the amplifier and / or phase shifter, is located. For example, the doping region and the metal wiring of the beamforming circuit transistors, as well as the combiner / divider 153 conductors, are located in the active region. By interconnecting the top surface conductors using the top surface wiring 141 between the RFIC 150 and the transmission line section 180, an extra transmission line layer in the antenna substrate 110 for forming the RF connection between the RFIC 150 and the TL section 180 can be avoided. Therefore, the manufacturing of the antenna substrate 110 can be simplified by omitting the step of forming another transmission line layer. Thus, the antenna substrate 110 may have a single layer of dielectric 190 formed on it, which is referred to here as a “single RF layer” substrate. On the other hand, the polymer layer of the layer region 220 may form the outermost surface 111 of the antenna substrate 110. In another embodiment illustrated in Figure 2, the RFIC 150 may be flipped over so that the active die side faces the antenna substrate. As a result, the polymer layers are in close proximity, creating an interface with high losses, and an underfill may be applied around the connection joint. As shown in Figure 2, when the active die side is facing upwards, it is relatively far from the antenna ground surface 210. This reduces the likelihood of vibrations caused by reflections between the ground surface 210 and the active die side.

[0014] Each ACU 130 includes an amplifier and / or a phase shifter to adjust the transmit and / or receive signals to and from the antenna elements 125. The RFIC chip 150 is distributed across the effective aperture of the antenna 100, each coupled to one or more antenna elements 125, and the antenna 100 may be considered an active antenna array. In embodiments where the ACU 130 includes a phase shifter for dynamic phase shifting of the signal, the antenna 100 functions as a phased array. In such a phased array embodiment, the beam formed by the antenna 10 is manipulated to a desired beam directivity angle set primarily according to the phase shift of the phase shifter. Additional amplitude adjustment capabilities may also be included within the RFIC 150 to adjust the antenna pattern. In any case, the antenna 100 may be configured as a transmit antenna system, a receive antenna system, or a system that transmits and receives both.

[0015] The connector 170 may be side-mounted or surface-mounted and connected to the signal conductor 181_s. In the transmission direction, the input RF transmission signal is applied to the connector 170 and divided into K segmented transmission signals by the coupler 118, and each of the K segmented transmission signals is applied to RFIC chips 150_1 to 150_K. (A schematic diagram of the signal flow is shown in Figure 9 and will be described later.) If the RFIC 150_j contains multiple M ACU 130s, the RFIC 150_j further includes an M:1 combiner / divider 153 that divides the segmented transmission signal into M further segmented signals, and each of the further segmented signals is applied to one of the ACU 130s. Once adjusted by the ACU 130, the adjusted signal becomes an "element signal" and is applied to one of the antenna elements 125.

[0016] In the receiving direction, a reverse signal flow occurs, and the element signal is received by the ACU 130 from antenna element 125 and adjusted (and typically filtered) by a receiving amplifier and / or phase shifter. The adjusted received signal is sent through combiners / dividers 153 and 118 to generate a composite received signal at connector 170. Here, the beamforming network (BFN) may be considered to include all signal paths between signal connector 170 and antenna elements 125_1 to 125_N. In the BFN, a single input transmit signal is divided into N element signals, and / or the N element signals received from antenna element 125 are combined into a single composite received signal.

[0017] Figure 2 also illustrates that the antenna 100 may include a cover 107 (not shown in Figure 1) that protects at least the upper side from external elements. Since the USIN 141 can be fragile, it should be protected from dust, moisture, etc., and the cover 107 is appropriately mounted to the rest of the assembly to provide such protection. In other examples, instead of the cover 107, a printed wiring assembly (PWA) is mounted on the upper side of the antenna 100 to provide the desired protection from external elements. A radome may also be provided on the lower side to protect the antenna element 125.

[0018] In Figures 1 and 2, two antenna elements 125 are shown as an example, each coupled to an RFIC 150. In other examples, each RFIC chip 150 is coupled to a single antenna element 125 or three or more antenna elements 125. The antenna 100 is also shown to include additional chips 160_1 and 160_2, such as a serial peripheral interface (SPI) chip. Chip 160 may function to provide DC signals and / or control signals to the RFIC 150 through signal lines such as 304_1, 308_1, formed within a layer region 220 of the antenna substrate 110. The DC signals may bias the amplifier and / or control the switching state of a switch in the ACU 130. The control signals may control the phase shift of a phase shifter in the ACU 130.

[0019] Each antenna element 125 may be a microstrip patch antenna element printed on an antenna substrate 190. Other types of antenna elements, such as dipoles or monopoles, may be substituted. When embodied as a microstrip patch, the antenna elements 125 may have any preferred shape, such as circular (illustrated in Figure 1), square, rectangular, or elliptical, and may be fed and configured in a manner sufficient to achieve the desired polarization, e.g., circular, linear, or elliptical. The number, type, size, shape, spacing between elements, and feeding mechanism of the antenna elements 125 may vary from embodiment to embodiment depending on the performance objectives of the application. While an example of antenna 100 with eight antenna elements 125 is shown, a typical embodiment for achieving a narrow antenna beam may include hundreds or thousands of antenna elements 125. In the embodiments described below, each antenna element 125 is a microstrip patch fed with single probe feeding. Probe feeding may be implemented as vias 155 electrically connected to RF contacts 157 of the RFIC 150, also known as input / output (I / O) pads. The I / O pads are interfaces that allow signals to enter or exit the RFIC 150. In another example, each antenna element 125 is fed by two offset vias 155 using different circular polarization feeding methods. In yet another example, an electromagnetic feeding mechanism is used instead of vias 155, and each antenna element 125 is excited from its respective feeding point with near-field field energy.

[0020] In one example, the antenna 100 is configured to operate over a millimeter (mm) wave frequency band, generally defined as a band within the range of 30 GHz to 300 GHz. In other examples, the antenna 100 operates in the microwave range of about 1 GHz to 30 GHz, or in the sub-microwave range below 1 GHz. Here, a radio frequency (RF) signal refers to a signal having a frequency in the range of less than 1 GHz to up to 300 GHz. Note that an RFIC configured to operate at microwave or millimeter wave frequencies is often referred to as a monolithic microwave integrated circuit (MMIC) and is typically composed of III-V semiconductor materials such as indium phosphate (InP) or gallium arsenide (GaAs), or other materials such as silicon-germanium (SiGe).

[0021] FIG. 3A is a partial cross-sectional view of the antenna device taken along the line 3A-3A of FIG. 1, showing an exemplary wiring structure suitable for one embodiment having a CPW chip 150 and a CPW transmission line portion 180. The antenna element 125_i is coupled to the beamforming circuit of the ACU 130_i formed within the active die side 340 of the RFIC chip 150_j (i, j = any integer). Such coupling may be made through a first via 155, a catch pad 369, a conductive joint 363, an RF contact 157, a second via 355, and a conductor 342. (As shown in FIG. 3B and discussed below, one or more ground vias forming a GS or GSG connection set together with the second via 355 may be included for noise reduction.) The first via 155 may form at least a part of the probe feed for the antenna element 125_i. The first via 155 is formed within the dielectric 190 and electrically connects the antenna element 125_i to the catch pad 369 formed on the upper surface 111 of the antenna substrate 110. The first via 155 passes through an opening 371 formed in the ground plane 210 to prevent a short to the ground plane. The opening 371 may be annularly surrounded by an insulating material 373 such as a polymer at the depth level of the ground plane 210. The insulating material 373 may be composed of the same material as the material within the insulating layer of the layer region 220.

[0022] The layer region 220 may include, in order from the upper surface 111, the ground plane 210, the first insulating layer 302, the first conductive layer 304, the second insulating layer 306, the second conductive layer 308, and the third insulating layer 310. The first and second conductive layers 304 and 308 may be patterned to form signal lines such as 304_1 and 308_1 used to send DC and / or control signals from the SPI chips 160_1 and 160_2 to the RFIC chip 150, for example. The conductive layers 304 and 308 are composed of metal or other conductive materials. The openings may be formed in the conductive layers 304 and 308, for example, by not depositing the conductive material in the region of the openings during the formation of each layer. The openings may be annularly surrounded by an insulating material so that the first via 155 crosses the openings and does not short-circuit to the conductive layers 304 and 308. Each layer 302, 304, etc. within the layer region 220 may be at least one order of magnitude thinner than the dielectric 190. For example, each of these layers may have a thickness (in the z direction) on the order of 2 to 10 μm, while the dielectric 190 may have a thickness on the order of 250 μm. The first and second conductive layers 304 and 308 may each form signal / ground lines in the x-y plane having a width on the order of 12 μm and spaced apart from each other at an interval on the order of 12 μm. Each of the layers 304 and 308 may be etched or patterned to form dozens, hundreds, or thousands of signal lines and ground lines in a typical embodiment of the antenna 100. However, in other embodiments, the layer region 220 may be omitted, and in such cases, the bias voltage and signals are sent to the RFIC 150 through other means.

[0023] The contact pad 369 is electrically connected to the RF contact 157 through a conductive joint 363 such as a solder ball, gold bump, or copper pillar, along with a solder cap, thermocompression adhesive, or conductive epoxy. The RF contact 157 is then connected to the conductor 342 through a second via 355 formed within the RFIC chip 150_j via a chip material 345, such as InP or GaAs. The conductor 342 may be directly connected to or form part of the metal wiring of a transistor terminal or other circuit element of the beamforming circuit. The conductor 342 may be metal wiring printed on the top surface 341 of the RFIC chip 150_j, in which case the second via 355 may be formed as a through-substrate via (TSV) extending completely through the chip material 345. Alternatively, the conductor 342 may be located below the outermost surface 341, and the second via 355 may be formed as a blind via connecting to the conductor 342 within the chip material 345 at its upper end. Conductor 342 coincides with circuit point p of the beamforming circuit, which may be the input node of ACU130. The output of ACU130 coincides with circuit point w, but may be connected to the branch arm port (output port) (if any) of combiner / divider 153.

[0024] The input port of the combiner / divider 153 is electrically connected to the conductor 151_s at circuit point "q". USIN 141 connects the conductor 151_s to the conductor 181_s of the TL section 180. If USIN 141 is a wire bond, its cross-section may be cylindrical or circular. If USIN 141 is a ribbon bond, its cross-section may be elliptical or rectangular. The conductor 181_s may be a metal wiring printed on the upper surface of the dielectric 185 of the TL section 180. If the TL section 180 is a coplanar waveguide, the lower surface of the dielectric 185 may be bonded to the outermost surface 111 (upper surface of the polymer layer 302) of the antenna substrate 110 using non-conductive or conductive epoxy 333.

[0025] In a typical embodiment, the RFIC chip 150_j may have dozens or more than 100 electrical contacts such as 357, 367, etc., on its underside. These contacts may receive bias voltage and / or control signals from signal lines formed in the first and second conductive layers 304 and 308 through wiring having conductive joints 363. For example, to connect a signal line formed in the first conductive layer 304 to an electrical contact 357 of the RFIC chip 150_j, an opening may be created in the first insulating layer 302 to expose the signal line in the first conductive layer 304, and a conductive well 387 may be formed in the opening. The opening in the first insulating layer 302 may be created by placing a resist material on layer 304 at the location of the next opening, and then depositing the insulating material of the insulating layer 302 in the area that does not contain the resist material. A contact pad 379 may be formed on the well 387, and a conductive joint 363 formed by a heating / cooling process may connect the contact pad 379 to the contact 357. Furthermore, the contact pad 379 is omitted, and the conductive joint 363 is electrically bonded to the well 387.

[0026] Similarly, openings may be formed in the first insulating layer 302, the first conductive layer 304, and the second insulating layer 306 to connect the signal lines formed in the second conductive layer 308 to the electrical contacts 367 of the RFIC chip 150_j. The process of forming the openings may similarly involve placing one layer of resist material at a time at the location of the next opening while the corresponding layer material is being deposited. Additional insulating material 391 (e.g., the same material as insulating layers 302 and 306) may be deposited in an annular region around the openings in the first conductive layer 304. This material prevents short circuits to the next conductive well 377 formed by deposition, etc., within the cavity created by the series of openings. Contact pads 379 may be formed on the conductive well 377. Conductive joints 363 connect the electrical contacts 367 to contact pads 359, or, if contact pads 359 are omitted, connect the electrical contacts 367 directly to the conductive well 377.

[0027] It may be desirable to form a direct electrical connection between the electrical contacts of the RFIC 150 and the antenna grounding surface 210. For example, the electrical contact 347 is electrically connected to the grounding surface 210 through a connecting joint 363, a contact pad 399, and a conductive well 372 (if the contact pad 399 is omitted, the connecting joint 363 may be directly connected to the conductive well 372). The grounding surface 338 may be located on the underside of the RFIC chip 150 and may be conductively bonded to the contact 347. The grounding surface 338 may be a DC ground and / or a transmission line ground (e.g., a microstrip, CPW, or stripline grounding conductor). Note that different types of transmission line media may be present on a single RFIC chip 150. The conductive well 372 may be formed in a similar manner to the conductive well 377, having the step of passing through a second conductive layer 308 and a third insulating layer 310 to form an additional opening that exposes the surface of the grounding surface 210. The additional insulating material 392 may be deposited in an annular region surrounding the opening of the second conductive layer 308 to prevent short circuits to the conductive wells 372 that are subsequently formed.

[0028] The underfill material 364 surrounds at least some of the connecting joints 363, and can improve their reliability by mechanically supporting the connecting joints. Typically, the underfill material 364 may be a mixed material composed mainly of amorphous fused silica.

[0029] Figure 3B is a cross-sectional view of an exemplary wiring structure within antenna 100, taken along a plane perpendicular to the plane shown in Figure 3A. Figure 3B (yz-plane view) shows a ground-signal-ground (GSG) transition from the ground plane 210 to the coplanar waveguide on the upper surface of the RFIC chip 150_j, crossing the first via 155 and the second via 355 (both shown in the xz-plane of Figure 3A). The GSG transition can prevent radiation from the second via 355 from affecting the performance of the beamforming circuit.

[0030] The coplanar waveguide on the upper surface of the RFIC chip 150_j includes a signal conductor 342 and, on its opposite side, first and second ground conductors 344_1 and 344_2. The first ground via 356_1 has an upper end connected to the first ground conductor 344_1 and defines a first ground point g1 (discussed graphically below). The first ground via 356_1 may have its lower end connected to a catch pad 327_1 on the lower surface of the RFIC chip 150_j. The wiring between the catch pad 327_1 and the connection point on the ground surface 210 on one side of the first via 155 may include a conductive joint 363, a catch pad 369_1, and a conductive well 374_1. Similarly, the second ground via 356_2 has an upper end connected to the second ground conductor 344_2 and defines a second ground point g2. The second ground via 356_2 may be connected at its lower end to a catch pad 327_2. The wiring between the catch pad 327_2 and the connection point on the ground surface 210 opposite the first via 155 may include a conductive joint 363, a catch pad 369_2, and a conductive well 374_2.

[0031] The insulating material 373 encloses the region between the first via 155 and the first and second conductive wells 374_1 and 374_2 in an annular shape, preventing the first via 155 from shorting to ground. This configuration allows probe feeding to begin from the height (in the z direction) of the ground surface 210, minimizing unwanted radiation between the ground surface 210 and the upper surface of the RFIC tip 150_j. Note that in other configurations, only one ground via 356 may be used to form a ground-signal (GS) transition, or three or more ground vias 356 may be used surrounding the second via 355 (which can also be considered a GSG transition). Yet another configuration uses a slot line transition instead of the second via 355 and the first and second ground vias 356_1 and 356_2.

[0032] Figure 4A is a partial cross-sectional view of antenna 100 taken along line 3A-3A in Figure 1, in one embodiment using a microstrip chip and a microstrip transmission line. In this example, the ground conductors 151_g1, 151_g2, 181_g1, and 181_2 are omitted, and the signal conductors 151_s and 181_s are assumed to be microstrip signal conductors. The microstrip ground surface 438 may be located on the underside of the RFIC chip 150_j. The microstrip ground surface 438 may be a ground surface for the microstrip medium having signal conductors such as 151_s and other signal conductors of the beamforming circuit of ACU 130, and for the combiner / divider 153 in the active region 340. The microstrip ground surface 438 may be electrically connected to the antenna ground surface 210 through the contact pad 347, conductive joint 363, contact pad 399, and conductive well 373 described above. The transmission line section 180 in Figure 4A includes a microstrip internal conductor 181_s on its upper surface and a grounding surface 433 on its lower surface. The grounding surface 433 may similarly be connected to the antenna grounding surface 210 through a conductive joint 363, a contact pad 397, and a conductive well 473 similar to the conductive well 373.

[0033] Figure 4B is a cross-sectional view of an exemplary wiring structure within the antenna 100, configured with the microstrip of Figure 4A, taken along a plane perpendicular to the plane shown in Figure 4A. Figure 4B shows a GSG transition from the ground surface 210 across the first via 155 and the second via 355 to the microstrip medium formed of a microstrip ground surface 438, signal conductors such as beamforming circuits 342 in the active die side 340, and chip material 345 separating the signal conductors from the microstrip ground surface 438. The wiring between the microstrip ground surface 438 and the connection point of the ground surface 210 on one side of the first via 155 may include a catch pad 327_1, a conductive joint 363, a catch pad 369_1, and a conductive well 374_1. Wiring of the same configuration connecting the two ground surfaces 438 and 210 may be created on the opposite side of the first via 155, which has a catch pad 327_2, another connecting joint 363, a catch pad 369_2, and a conductive well 374_2. Similar to the CPW in Figure 3B, the GSG transition in Figure 4B can prevent radiation from the second via 355 from affecting the performance of the beamforming circuit. Other aspects and operations of the antenna structures in Figures 4A and 4B may be the same as those described above in Figures 1 to 3B.

[0034] Figure 5A is a plan view of an antenna device 100' according to another embodiment. Figure 5B is a plan view showing a portion of the RFIC chip of the antenna device 100', and Figure 6 is a cross-sectional view of an exemplary wiring structure taken along line 6-6 in Figure 5A. Referring together to Figures 5A, 5B, and 6, the antenna 100' differs from the antenna 100 shown in Figure 1 by configuring the RFIC chips 150_1 to 150_K as microstrip chips instead of CPW chips. The microstrip RFIC chip 150 may include a microstrip combiner / divider 553, a microstrip ACU 130, and a transition from microstrip to CPW (hereinafter referred to as "hybrid transition"). The combiner / divider 533 may include microstrip signal conductors 551_s at the input port and output branches connected to each ACU 130. The hybrid transition may be formed by the input portion of the signal conductor 551_s at the end of the RFIC chip 150, the first and second grounding pads 551_g1 and 551_g2 on the opposite side of the signal conductor 551_s, and the first and second grounding vias 655_1 and 655_2.

[0035] The first and second vias 655_1 and 655_2 connect the grounding pads 551_g1 and 551_g2, respectively, to the microstrip grounding surface 438. Figure 6 is a cross-sectional view of the RFIC chip 150_j partially passing through the first grounding pad 551_g1 (the tip structure is omitted for clarity), showing the grounding via 655_1 that electrically connects the first grounding pad 551_g1 to the microstrip grounding surface 438. The second grounding via 655_2 may have the same or a similar structure. In addition, the same or a similar wiring may be formed between the grounding surface 438 and the antenna grounding surface 210 as described above. This wiring may include contact / catch pads 347 and 399, a conductive joint 363 between them, and a conductive well 373. The top wiring 141 may be provided to connect signal conductor 551_s to signal conductor 181_s, first grounding pad 551_g1 to grounding conductor 181_g1, and second grounding pad 551_g2 to second grounding conductor 181_g2. Other embodiments of antenna 100' may be the same as those described above for antenna 100.

[0036] Figure 6A is a plan view showing a portion of the microstrip RFIC chip 150_j of another embodiment of the antenna 100, where the active die side of the RFIC chip 150 faces the antenna substrate 110. That is, the RFIC 150 may be inverted compared to the embodiment described above, such that the outer surface of the active die side 340 is considered to be the bottom surface of the RFIC 150. In this case, the top wiring (USIN) 141 is further used to connect the beamforming circuit within the active die side (through vias within the RFIC 150) to the top conductor of the TL section 180. The microstrip ground surface 438 may be located on the top surface of the RFIC chip 150_j, and the signal conductors 651_s may be in the shape of isolated "islands" within an annular opening of the ground surface 438 that exposes the chip material 345. Vias 655 may be formed between the bottom active region 340 and the top signal conductors 651_s. USIN141 may be a wire bond or ribbon bond. When TL section 180 is a CPW, the first USIN141 connects conductor 651_s to conductor 181_s, and the second and third USIN141 connect points on the grounding surface 438 opposite to conductor 651_s to their respective grounding conductors 181_g1 and 181_g2. When TL section 180 is a microstrip, the second and third USIN141 connected to the grounding surface 438 may be omitted.

[0037] Figure 6B is a plan view showing a portion of the CPW RFIC chip 150_j of another embodiment of the antenna 100, where the active die side of the RFIC chip 150 faces the antenna substrate 110. As shown in the embodiment of Figure 6A, the RFIC 150 may be inverted compared to the previously described embodiment such that the outer surface of the active die side 340 is considered to be the bottom surface of the RFIC 150. The top surface of the RFIC chip 150_j has grounding pads 551_g1 and 551_g2, similar to that shown in Figure 5B, but may also have pad-shaped signal conductors 651_s. In this case, the first via 655_s may be provided to connect the CPW signal conductor in the active region 340 to the signal conductor 651_s, and the second and third vias 655_g1 and 655_g2 are provided to connect the first and second grounding conductors in the active region 340 to the grounding pads 551_g1 and 551_g2, respectively. Firstly, the second and third USINs 141 may be provided to connect to the TL section 180 in the same manner as discussed in Figure 5B if the TL section 180 is a CPW. If the TL section 180 is a microstrip, the grounding pads 551_g1, 551_g2 and vias 655_g1, 655_g2 may be omitted.

[0038] Figure 7A shows an exemplary beamforming circuit of an active circuit unit (ACU) 130_i configured for the receiving path (antenna receiving direction) of the RFIC chip 150. The ACU 130_i may include a front-end receiving circuit between an input point p (shown in Figures 3A to 6) and an output point w, which may include a series-connected low-noise amplifier (LNA) 502, a receiving path phase shifter 504, and a bandpass filter 506. In the case of the CPW chip in Figures 3A to 3B, the first and second grounding points g1 and g2 may be coplanar waveguide grounding points of the LNA 502, and circuit point p may be the input point of the signal conductor of the LNA 502. The phase shifter 504 and filter 506 may also be designed as components of the CPW. In embodiments having a microstrip chip, the microstrip grounding surface 438 (see Figures 4A and 6) may be the grounding surface for all components of the ACU 130_i. The LNALNA502 and the phase shifter 504 may receive bias / control voltages from vias / signal lines (not shown) within the RFIC chip 150 extending from electrical contacts such as 357 and 367 (see Figures 3A, 4A, and 6).

[0039] Figure 7B shows an exemplary beamforming circuit of an active circuit unit (ACU) 130_i configured for the transmit path (antenna transmit direction) of the RFIC chip 150. Here, the front-end circuit within the ACU 130_i may include a power amplifier (PA) 512, a transmit path phase shifter 514, and a bandpass filter 516 connected in series. In the case of the CPW chip in Figures 3A and 3B, the first and second grounding points g1 and g2 may be coplanar grounding points of the PA 512, and circuit point p may be the output point of the signal conductor of the PA 512. The phase shifter 514 and filter 516 may also be designed as components of the CPW. In the microstrip chip embodiment, the microstrip grounding surface 438 may be the grounding surface for all components of the ACU 130_i. The PA 512 and phase shifter 514 may receive bias / control voltages from vias / signal lines (not shown) within the RFIC chip 150 extending from electrical contacts such as 357, 367.

[0040] Figure 7C shows an exemplary beamforming circuit of an active circuit unit (ACU) 130_i configured for both the receive and transmit paths of the RFIC chip 150. In this case, the (ACU) 130_i includes a first transmit / receive (T / R) circuit 532 having an input port connected to an input point p, and a second T / R circuit 534 having an input port connected to an output point w. The receive path, including an LNA 502 and a phase shifter 504, may be connected between the first output ports of the T / R circuits 532 and 534. The transmit path, including a phase shifter 514 and a PA 512, may be connected between the second output ports of the T / R circuits 532 and 534. The T / R circuits 532 and 534 may each include a bandpass filter and / or switches to enable both transmission and reception of the path signal from the input port through each output port. In some examples, different frequency bands are used for transmitting and receiving signals, and bandpass filtering can adequately provide isolation between paths. Time-division multiplexing can provide further or alternative isolation between paths. In embodiments of CPW, the first and second grounding points g1 and g2 may be grounding points of the T / R circuit 532.

[0041] Figure 8 is a schematic diagram showing an exemplary beamforming circuit with multiple ACUs within an RFIC chip. The RFIC 150_j may include multiple ACUs 130_1 to 130_M, each having an input port at circuit points p_1 to _M and an output port at circuit points w_1 to w_M. The integer M can vary from embodiment to embodiment, from a minimum of 2 (see the example shown in Figure 1) to any suitable number of ACUs 130 that can be implemented within a single RFIC chip 150_j. Circuit points p_1 to P_M may be coupled to antenna elements 125_1 to 125_M through feeds 601_1 to 601_M, each feed 601 including a second via 355, a first via 155, and a wiring structure between them, as described above for Figures 3A to 6 in relation to circuit point p. For example, in an embodiment of the CPW chip, each ACU130_i may include first and second ground conductors fixed to first and second ground points g1_i and g2_i. The M:1 combiner 540 combines the received signal output from the ADC130 at points w_1 to w_M into a combined received signal at point q during the receive path operation, and / or divides the transmitted signal applied at point q into M divided transmitted signals applied to ACU130_1 to 130_M at points w_1 to w_M.

[0042] Figure 9 is a schematic diagram showing an exemplary beamforming network (BFN) 700 within antenna 100. The BFN 700 may include a K:1 combiner / divider 780 formed within the transmission line section 180 and K RFIC chips 150_1 to 150_K, each having the configuration of RFIC 150_j shown in Figure 8. The K:1 combiner / divider 780 has an input port connected to the connector 170 at circuit point t, and K output ports connected to RFIC chips 150_1 to 150_K at circuit points q_1 to q_K. Each RFIC chip 150 may be coupled to M antenna elements such as 125_1 to 125_M through M RF contacts 157. Thus, there are N antenna elements 125_1 to 125_N, where N = M × K. As mentioned above, in the case of a typical antenna 100 forming a narrow antenna beam, the number N will be in the hundreds or thousands. In the example shown in Figure 1, K=4, M=2, and N=8.

[0043] Figure 10 is a flowchart of an exemplary method 800 for manufacturing an antenna 100. The sequence of operations shown may be changed as necessary. In method 800, the antenna substrate 110 may be formed from a wafer, and first vias 155 may be formed by drilling holes therein and filling the holes with conductive material by electroplating or a similar process (S802). The antenna elements 125 and the ground surface 210 may then be printed on the lower and upper surfaces of the antenna substrate, respectively (S804). Subsequently, the RDL region 220 may be formed on the antenna substrate 110 above the ground surface (S806).

[0044] The RFIC chip 150 has beamforming circuits 130, 153, a second via 355, a ground via 356 (in the CPW embodiment), an RF contact 157, and other electrical contacts such as 357, 367, etc., which are fabricated separately (S808). A BFN combiner / divider 780 may be separately formed on the transmission line (TL) section 180 (S810). The conductive joint 363 may first be bonded to the RF contact 157 and other electrical contacts of the RFIC chip 150, and / or to the catch pad 369 / other contacts on the upper surface of the antenna substrate 110 (S812). The RFIC chip 150, other IC chips 160, and the TL section 180 may be arranged on the antenna substrate 110 (S814). A heating / cooling cycle may be performed to melt and cool the solder or other conductive material of the conductive joint 363, thereby conductively bonding the RFIC chip, other IC chips, and TL section to the antenna substrate (S816). The top wiring 141, such as wire bond or ribbon bond, may then be attached to the RFIC chip conductor 151 or 551 and the TL section 180 conductor (branch arm) on the opposite end to interconnect them (S818). The connector 170 may be attached to the TL section 180, and the cover 107 or PWA may be attached to the resulting assembly (S820).

[0045] The embodiments described above have been explained in the context of an antenna device 100. Other implementations of the technology disclosed herein may be applied to non-antenna applications or to wiring structures of other parts of an antenna system. For example, in other exemplary configurations, the antenna element 125 may be replaced by at least one other type of circuit component, such as a second IC chip, like a modem. The RFIC chip 150 may be coupled to the second IC chip using the same or similar wiring structures as described above (e.g., using a first via 155, a second via 355, etc.). In such embodiments, the transmission line section 180 may support circuits other than combiners / dividers of a beamforming network, but the RFIC chip 150 may be interconnected from the active die side to the transmission line section 180 in the same manner as disclosed herein. In other examples, the transmission line section may be replaced by another RF circuit component, such as another RFIC chip configured to perform functions different from those of the RFIC chip 150. The resulting configuration / electronic device is formed in a compact three-dimensional stacked structure, which has advantages similar to those described for antenna 100, such as reduced loss, reduced vibration, and / or ease of manufacture.

[0046] While the technologies described herein are shown and explained in particular with reference to their exemplary embodiments, those skilled in the art will understand that various modifications of form and detail may be made therein without departing from the spirit and scope of the subject matter of the claims as defined by the following claims and their equivalents.

Claims

1. Antenna device (100, 100'): An antenna substrate (110) having opposing first (113) and second (111) surfaces, At least one antenna element (125) is disposed on the first surface (113) of the antenna substrate, At least one radio frequency integrated circuit (RFIC) chip (150_j) having a lower surface attached to the second surface of the antenna substrate and having an RF contact (157) coupled to at least one antenna element through the antenna substrate, having an RF signal conductor (151_s, 551_s) on its upper surface (341) and having a beamforming circuit (130_i, 153) coupled between the RF contact and the RF signal conductor, An antenna device (100, 100') comprising: a transmission line section (180) having a lower surface attached to the second surface of the antenna substrate, and an upper surface through upper wiring (141) on which a transmission line conductor (181_s) is disposed and electrically connected to the RF signal conductor of the RFIC chip.

2. A method for manufacturing an antenna device: The steps include forming an antenna substrate having opposing first and second surfaces, The steps include printing at least one antenna element on the first surface of the antenna substrate, The steps include manufacturing a radio frequency integrated circuit (RFIC) chip having a lower surface attached to the second surface of the antenna substrate, The steps of forming a transmission line section, having a lower surface attached to the second surface of the antenna substrate, an upper surface through which transmission line conductors are arranged and electrically connected to the RF signal conductors of the RFIC chip, and a dielectric substrate located between the lower surface and the upper surface of the transmission line section, A method for providing this.

3. The antenna substrate is formed to include an antenna grounding surface adjacent to or forming at least a portion of the second surface, and the antenna grounding surface is electrically connected to the grounding contact of the RFIC chip. The method according to claim 2, wherein the RFIC chip RF contact is coupled to the at least one antenna element through an opening in the antenna ground surface.

4. The method according to claim 3, wherein the antenna substrate is further formed to include a redistribution layer between the antenna ground surface and the second surface in order to provide a DC voltage and / or control signal to the RFIC chip.

5. The method according to claim 2, wherein the upper surface of the RFIC chip is manufactured as the active die side of the RFIC chip.

6. The method according to claim 5, wherein the RFIC chip is manufactured to include vias connecting RF contacts to the active die side.

7. The method according to claim 2, wherein the antenna substrate is formed to include vias formed within the antenna substrate, the vias electrically or electromagnetically coupling RF contacts to at least one antenna element.

8. The method according to claim 7, wherein the lower surface of the RFIC chip is manufactured to be attached to the second surface of the antenna substrate through a plurality of electrical connection joints, and one of the electrical connection joints connects the RF contact to the via.

9. The method according to claim 8, wherein the plurality of electrical connection joints include solder bumps, copper pillars, gold bumps, conductive epoxy joints, or thermocompression joints.

10. The method according to claim 8, further comprising the step of placing an underfill material in the space surrounding the electrical connection joint between the second surface of the antenna substrate and the lower surface of the RFIC chip.

11. The method according to claim 2, wherein the top wiring is wire bond, ribbon bond, or edge terminal pair.

12. The method according to claim 2, wherein the RFIC chip is manufactured to include a beamforming circuit comprising at least one of a transmitting amplifier, a receiving amplifier, and a phase shifter for adjusting a signal communicated between the RFIC chip and the at least one antenna element.

13. The method according to claim 2, wherein the transmission line section is formed to include at least a portion of a beamforming network (BFN) that divides an input transmission signal into a plurality of divided transmission signals provided to one of a plurality of RFIC chips mounted on the antenna substrate, and / or receives a plurality of received signals from the plurality of RFIC chips, and combines the received signals to form an output signal, the plurality of RFIC chips including manufactured RFIC chips.

14. The method according to claim 2, wherein the dielectric substrate is formed to include an alumina substrate attached to the second surface of the antenna substrate.

15. The transmission line conductor of the transmission line section is formed as a signal conductor of a coplanar transmission line, and the coplanar transmission line has first and second ground conductors on the opposite side of the signal conductor. The method according to claim 12, wherein the third and fourth ground conductors of the RFIC chip located on the upper surface of the RFIC chip are manufactured to interconnect with the first and second ground conductors of the coplanar transmission line through their respective upper surface wirings.

16. The beamforming circuit of the RFIC chip is configured on the lower surface of the RFIC chip in a microstrip medium including a microstrip contact surface, The method according to claim 15, wherein the RFIC chip is manufactured to further include first and second ground vias connecting the third and fourth ground conductors to the microstrip ground surface, respectively.

17. The method according to claim 2, wherein the transmission line portion is formed as a microstrip transmission line including the dielectric substrate, the transmission line conductor on the upper surface of the dielectric substrate, and the microstrip grounding surface on the lower surface of the dielectric substrate.

18. The method according to claim 2, wherein the at least one antenna element is formed as a microstrip patch element.

19. The at least one antenna element is formed to include a plurality of N antenna elements, The method according to claim 2, wherein the RFIC chip is manufactured to include N beamforming circuits, each including at least one of an amplifier and a phase shifter, and each of the N beamforming circuits is coupled to the N antenna elements through N vias formed in the antenna substrate.

20. A method for manufacturing a phased array antenna, The steps include forming an antenna substrate having opposing first and second surfaces, The steps include printing a plurality of antenna elements on the first surface of the antenna substrate, A step of manufacturing a plurality of radio frequency integrated circuit (RFIC) chips, each having a lower surface attached to the second surface of the antenna substrate, and each of the lower surfaces having an RF contact coupled to at least one of the plurality of antenna elements through the antenna substrate, each having an RF signal conductor on its upper surface, and each having a beam shaping circuit for beam manipulation coupled between each RF contact and the RF signal conductor, A method comprising the step of forming at least one transmission line section, which includes a lower surface disposed between the RFIC chips and attached to the second surface of the antenna substrate, and an upper surface on which a portion of a beamforming network (BFN) including a plurality of branch arm conductors is disposed, wherein each branch arm conductor is interconnected to one of the RF signal conductors of the RFIC chips through upper surface wiring.

21. The BFN further comprises a plurality of amplifiers and a plurality of phase shifters, and the beamforming circuit of each of the RFIC chip comprises at least one of the amplifiers and at least one of the phase shifters, The antenna substrate further includes the antenna ground surface and the layer region between the antenna ground surface and the second surface, the antenna ground surface and the layer region, which include a plurality of conductive lines that send a DC voltage to the amplifier and a control signal to the phase shifter in order to control each phase and perform beam manipulation. The method according to claim 20, wherein the phased array antenna further comprises a plurality of integrated circuit chips mounted on the second surface of the antenna substrate and coupled to the layer region in order to provide at least one of the control signals.

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