Low aspect ratio varistor

Abstract

To provide a compact varistor and a varistor array having a low clamping electric power.SOLUTION: A low aspect ratio varistor 10 has a rectangular configuration defining a first side surface 28 and a second side surface 29 that face each other and are offset in a widthwise direction 30 and a first end surface 26 and a second end surface 27 that face each other and offset in a lengthwise direction 34. The varistor includes a first electrode layer including a first electrode 16 having an electrode length in the lengthwise direction and an electrode width in the widthwise direction. The varistor may also include a second electrode layer including a second electrode having an electrode length in the lengthwise direction and an electrode width in the widthwise direction. The varistor may also include a first terminal 17 and a second terminal 19 adjacent to and connected with the first and second opposing end surfaces, respectively. At least one of the first and second electrodes may have an electrode aspect ratio less than about 1.SELECTED DRAWING: Figure 1C

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the benefit of the filing of U.S. Provisional Patent Application No. 62 / 593,340, filed Dec. 1, 2017, which is hereby incorporated by reference in its entirety.

[0002] The present subject matter generally relates to electronic components configured to be mounted on a circuit board, and more particularly, to varistors and varistor arrays.

Background Art

[0003] Multilayer ceramic devices, such as multilayer ceramic capacitors or multilayer ceramic varistors, are typically constructed having a plurality of stacked dielectric electrode layers. During manufacture, the layers can often be pressed into a vertically stacked structure. Multilayer ceramic devices can include a single electrode or can include multiple electrodes in an array.

[0004] A varistor is a voltage - dependent non - linear resistor and has been used as a surge - absorbing electrode, an arrester, and a voltage - stabilizing device. A varistor can be connected, for example, in parallel with delicate electronic components. The non - linear resistance response of a varistor is often characterized by a parameter known as the limiting voltage. For an applied voltage below the limiting voltage of the varistor, the varistor generally has a very high resistance and thus acts similar to an open circuit. However, when the varistor is exposed to a voltage that exceeds the limiting voltage of the varistor, the resistance of the varistor decreases and thus the varistor acts more similar to a short circuit, allowing a greater flow of current through the varistor. This non - linear response can be used to divert current surges away from delicate electronic circuits to protect the delicate electronic components.

Summary of the Invention

Problems to be Solved by the Invention

[0005] For some time, the design of various electronic circuits has been driven by the general industry trend toward miniaturization. Miniaturization of electronic circuits results in lower operating currents and lower tolerance to current surges. Therefore, small varistor arrays with low power limits are desirable. [Means for solving the problem]

[0006] According to one embodiment of the present invention, a varistor is disclosed having a rectangular structure that defines opposing first and second sides offset in the width direction, and opposing first and second end faces offset in the length direction. The varistor comprises a first terminal adjacent to the opposing first end face, and a first electrode layer including a first electrode having an electrode length in the length direction and an electrode width in the width direction. The first electrode is connected to the first terminal along the electrode width of the first electrode. The varistor also comprises a second terminal adjacent to the opposing second end face, and a second electrode layer including a second electrode having an electrode length in the length direction and an electrode width in the width direction. The second electrode is connected to the second terminal along the electrode width of the second electrode. At least one of the first electrode or the second electrode may have an electrode aspect ratio of less than about 1.

[0007] According to another embodiment of the present invention, a first side and a second side are offset in the width direction. A varistor is provided having a rectangular structure that defines the sides and opposing first and second end faces offset in the longitudinal direction. The varistor comprises a first terminal adjacent to the opposing first end face and a first electrode layer including a first electrode. The first electrode is connected to the first terminal. The varistor comprises a second terminal adjacent to the opposing second end face and a second electrode layer including a second electrode. The second electrode is connected to the second terminal. The second electrode overlaps with the first electrode along an overlapping region. The overlapping region has an overlapping aspect ratio of less than about 1.

[0008] According to another embodiment of the present invention, a varistor array is provided having a rectangular structure defining opposing first and second sides offset in the width direction, and opposing first and second end faces offset in the length direction. The varistor array comprises a first terminal associated with the opposing first end faces and a first electrode layer comprising a first set of electrodes. Each of the first set of electrodes is connected to the first terminal and each has an electrode length in the length direction and an electrode width in the width direction. The varistor array comprises a second terminal associated with the opposing second end faces and a second electrode layer comprising a second set of electrodes. Each of the second set of electrodes is connected to the second terminal and has an electrode length in the length direction and an electrode width in the width direction. At least one of the electrodes from the second set of electrodes or the first set of electrodes has an electrode aspect ratio of less than about 1.

[0009] A complete and feasible disclosure of the subject matter, including the best mode, directed to those skilled in the art, is presented herein with reference to the accompanying drawings. [Brief explanation of the drawing]

[0010] [Figure 1A] This is a cross-sectional view of one embodiment of a varistor according to an aspect of the present disclosure. [Figure 1B] Figure 1A is a top view of the varistor layer. [Figure 1C] This is a perspective view of the varistor shown in Figure 1A without terminals. [Figure 1D] This is a perspective view of the varistor shown in Figure 1A, which has terminals. [Figure 2A] This is a cross-sectional view of a T-electrode embodiment of a varistor according to an aspect of the present disclosure. [Figure 2B] Figure 2A is a top view of the varistor layer. [Figure 2C] This is a perspective view of the varistor shown in Figure 2A without terminals. [Figure 2D] This is a perspective view of the varistor shown in Figure 2A, which has terminals. [Figure 3A]Figures 1A to 1D show the overlapping regions between pairs of dielectric layers according to the embodiments shown. [Figure 3B] Figures 2A to 2D show the overlapping regions between pairs of dielectric layers according to the embodiments shown. [Figure 4] This figure shows a panel layout relating to the manufacturing of multiple dielectric electrode layers according to the embodiments shown in Figures 1A to 1D. [Figure 5] Figures 2A to 2D show panel layouts for the manufacturing of multiple dielectric electrode layers according to the embodiments shown. [Figure 6] This figure shows a varistor array according to an aspect of the present disclosure. [Figure 7] This figure shows an exemplary current wave used to test the limiting voltage of a varistor according to an aspect of the present disclosure. [Figure 8] This figure shows the current and voltage during an exemplary test of the limiting voltage of a varistor according to an aspect of the present disclosure. [Modes for carrying out the invention]

[0011] The repetition of reference numerals throughout this specification and the accompanying drawings is intended to represent identical or similar features, electrodes, or steps of the subject matter. Those skilled in the art will understand that this disclosure is merely a description of exemplary embodiments and is not intended to limit broader aspects of the subject matter as implemented in the exemplary configurations.

[0012] Generally, this disclosure pertains to varistors and varistor arrays having lower limiting voltages. Generally, reducing the active resistance of a varistor can result in a lower limiting voltage. For example, many factors can contribute to the active resistance of a varistor, including the properties of the material used to form the varistor, as well as the dimensions of the varistor and its electrodes.

[0013] A varistor may comprise multiple alternating dielectric layers, each of which may comprise an electrode. The dielectric layers may be press-formed together and sintered to form a single unit. The dielectric layers may comprise any suitable dielectric material, such as barium titanate, zinc oxide, or any other suitable dielectric material. Various additives may be included in the dielectric material to provide or enhance the voltage-dependent resistance of the dielectric material. For example, in some embodiments, the additives may comprise cobalt oxide, bismuth oxide, manganese oxide, or a combination thereof. In some embodiments, the additives may comprise gallium oxide, aluminum oxide, antimony oxide, chromium oxide, titanium oxide, lead oxide, barium oxide, nickel oxide, vanadium oxide, tin oxide, or a combination thereof. The dielectric material may be doped with additives ranging from about 0.5 mol percent to about 3 mol percent, and in some embodiments, with additives ranging from about 1 mol percent to about 2 mol percent. The average grain size of the dielectric material can contribute to its nonlinear properties. In some embodiments, the average grain size can range from approximately 10 to 100 microns, and in some embodiments, it can range from approximately 20 to 80 microns. The varistor may also include two terminals, with each electrode connected to its respective terminal. The electrodes may provide resistance along their length and / or in the connection between the electrodes and terminals.

[0014] Regardless of the specific configuration used, the inventors have found that it is possible to achieve varistors that exhibit lower limiting voltages through selective control of the aspect ratio of the electrodes and / or the overall dimensions. For example, in some embodiments, at least one electrode may have an aspect ratio defined as the length of the electrode divided by the width of the electrode. In some embodiments, the electrode aspect ratio of at least one electrode is less than 1. For example, in some embodiments, the electrode aspect ratio may be greater than about 0.05 and less than 1, in some embodiments, greater than about 0.1 and less than about 0.9, in some embodiments, greater than about 0.2 and less than about 0.8, and in some embodiments, greater than about 0.3 and less than about 0.7.

[0015] In some embodiments, the electrodes may overlap or interleave in the length and width directions. Also, the size and shape of the overlapping region between the electrodes may affect the active resistance of the varistor and, therefore, may affect the limiting voltage. The overlapping region may have an overlap aspect ratio defined as the length of the overlapping region divided by the width of the overlapping region. In some embodiments, the overlap aspect ratio may be less than 1. For example, in some embodiments, the overlap aspect ratio may be greater than about 0.05 and less than 1, in some embodiments, greater than about 0.1 and less than about 0.9, in some embodiments, greater than about 0.2 and less than about 0.8, and in some embodiments, greater than about 0.3 and less than about 0.7.

[0016] According to aspects of the present disclosure, in some embodiments, a varistor or varistor array is defined as the length of the varistor or varistor array divided by the width of the varistor or varistor array It may have an overall aspect ratio as defined. In some embodiments, the overall aspect ratio may be less than 1. For example, in some embodiments, the overall aspect ratio may be greater than about 0.05 and less than 1, in some embodiments, greater than about 0.1 and less than about 0.9, in some embodiments, greater than about 0.2 and less than about 0.8, and in some embodiments, greater than about 0.3 and less than about 0.7.

[0017] In some embodiments, a varistor or varistor array according to aspects of the present disclosure may have a breakdown voltage of less than 40 volts. For example, in some embodiments, varistor 10 may have a breakdown voltage ranging from about 1 volt to about 24 volts, in some embodiments, a breakdown voltage ranging from about 2 volts to about 12 volts, in some embodiments, a breakdown voltage ranging from about 3 volts to about 8 volts, and in some embodiments, a breakdown voltage ranging from about 4 volts to about 6 volts.

[0018] Next, referring to the figures, exemplary embodiments of the present disclosure will be described in detail below. FIGS. 1A - 1D show one embodiment of varistor 10 according to aspects of the present disclosure. FIG. 1A is a schematic cross - sectional view showing various layers of one embodiment of varistor 10. In one embodiment, varistor 10 may include, for example, as described above, a plurality of generally planar dielectric layers made of a ceramic dielectric material.

[0019] Referring to FIG. 1A, varistor 10 may include alternating first layers 12 and second layers 14. Each first layer 12 may include a first electrode 16 connected to a first terminal 17, and each second layer 14 may include a second electrode 18 connected to a second terminal 19. Electrodes 16, 18 may be formed from a conductor such as palladium, silver, platinum, copper, or may be formed from another suitable conductor that can be printed on the dielectric layer.

[0020] Furthermore, the varistor 10 may include an upper derivative layer 20 and a lower derivative layer 22. In some embodiments, one or more of the upper derivative layer 20 and the lower derivative layer 22 may include a dummy electrode 24. Although the varistor 10 is shown having a single upper derivative layer 20 and a single lower derivative layer 22, it should be understood that any suitable number of upper derivative layers 20 or lower derivative layers 22 can be used without departing the scope of this disclosure. Moreover, in some embodiments, the upper derivative layer 20 and the lower derivative layer 22 may not include a dummy electrode 24 at all, or may not include any electrodes at all.

[0021] Furthermore, it should be understood that this disclosure is not limited to any particular number of dielectric electrode layers. For example, in some embodiments, the varistor 10 may include two or more dielectric electrode layers, four or more dielectric electrode layers, eight or more dielectric electrode layers, ten or more dielectric electrode layers, twenty or more dielectric electrode layers, thirty or more dielectric electrode layers, or any suitable number of dielectric electrode layers.

[0022] Referring to Figures 1C and 1D, the varistor 10 may have a first end face 26. Not shown in view of Figures 1C and 1D, the varistor 10 may include a second end face 27 opposite the first end face 26 and offset in the longitudinal direction 34. The varistor 10 may also have a first side surface 28, and not shown in view of Figures 1C and 1D, the varistor may include a second side surface 29 opposite the first side surface 28 and offset in the width direction 30.

[0023] Figure 1B shows the first layer 12 of the varistor 10. In some embodiments, layers 12, 14 and electrodes 16, 18 may each have an overall rectangular shape. , 18 may have a length 36 in the longitudinal direction 34 and a width 38 in the width direction 30.

[0024] Figure 1C shows a varistor 10 without any terminals. As described above, in some embodiments, the upper layer 22 of the varistor 10 may include a dummy electrode 24. The edge of the first electrode 16 may extend to the first end face 26. Referring to Figure 1D, the varistor 10 may include a terminal structure for coupling the internal electrodes 16, 18 of the varistor 10 to a printed circuit board. The terminal structure may include a first terminal 17 and a second terminal 19. The first terminal 17 and the second terminal 19 may include a metallized layer of platinum, copper, palladium-silver, or other suitable conductive material. A chromium / nickel layer followed by a silver / lead layer, applied by a typical processing technique such as sputtering, can be used as the outer conductive layer for the terminal structure.

[0025] As shown in Figure 1D, the first terminal 17 may be positioned on the first end face 26 of the varistor 10 such that the first terminal 17 is electrically connected to the first electrode 16. The first electrode 16 may extend to the first end face 26 of the varistor 10 and be connected to the first terminal 17. Furthermore, the second terminal 19 may be positioned on the second end face 27 of the varistor, and the second electrode 18 may extend to the second end face 27 of the varistor 10 and be connected to the second terminal 19.

[0026] As described above, the upper dielectric layer 20 and / or the lower dielectric layer 22 may include dummy electrodes 24. In some embodiments, the dummy electrodes 24 can improve electrical connectivity to terminals 17, 19. For example, the terminal material may be deposited along the first end face 26 and the second end face 27 such that the dummy electrodes 24 form part of terminals 17, 19, and each terminal 17, 19 wraps around the respective end of the varistor 10. In some embodiments, terminals 17, 19 may be deposited on or otherwise formed on the dummy electrodes 24 such that terminals 17, 19 wrap around the respective end of the varistor 10. However, in other embodiments, the varistor 10 may not include dummy electrodes 24 at all, and terminals 17, 19 may not be arranged along the upper and lower surfaces of the varistor 10. For example, in some embodiments, terminals may be arranged only on the first end face 26 and the second end face 27.

[0027] Referring to Figure 1D, the varistor 10 may have an overall length 40 in the length direction 34 and an overall width 42 in the width direction 30. The overall length 40 and / or overall width 42 may include terminals 17, 19.

[0028] Referring to Figures 2A to 2D, in another embodiment, at least one of the electrodes 16, 18 may be configured as a T-electrode. This embodiment may otherwise be configured similarly overall to the embodiments shown in Figures 1A to 1D. The T-electrode may have a protruding portion 54 having two opposing side edges and a terminal edge. The T-electrode may also have one or more shoulder portions 56. Referring to Figures 2A to 2D, the first terminal 17 may be connected to the first electrode 16 along at least one of the first side 28 or second side 29 of the varistor 10.

[0029] According to aspects of the present disclosure, the T-electrode configuration can result in improved electrical connection between electrodes 16, 18 and terminals 17, 19, which can result in lower active resistance and therefore lower limiting voltage. As shown in Figures 2B and 2C, in this embodiment, electrode 16 may extend to at least one of the first side 28 or the second side 29. For example, one shoulder portion 56 may intersect the first side 28, and the other shoulder portion 56 may intersect the second side 29. Each shoulder portion 56 has a side length 58 that extends the shoulder portion 56 to one of the first side 28 and the second side 29. The following may be specified. As shown in Figure 2D, in some embodiments, terminals 17, 19 may be formed along a portion of the first side 28 and / or the second side 29 such that terminals 17, 19 are electrically connected to the respective electrodes 16, 18 along the sides 28, 29. In some embodiments, the side length ratio obtained by dividing the total length 40 of the varistor 10 by the side length 58 of the varistor 10 may be in the range of about 2.5 to about 10, in some embodiments it may be in the range of about 3 to about 10, in some embodiments it may be in the range of about 4 to about 10, and in some embodiments it may be in the range of about 5 to about 10.

[0030] The electrodes 16 and 18 may overlap or be interleaved, as shown in Figures 1A and 2A. To better illustrate this, Figures 3A and 3B show a first dielectric layer 12 stacked on a second dielectric layer 14. Figure 3A shows the rectangular electrode configuration shown in Figures 1A to 1D. In Figures 3A and 3B, the first layer 12 is shown as partially transparent so that the overlapping region 60 is shown as a combination of the cross-hatching pattern of the first electrode 16 and the cross-hatching pattern of the second electrode 18. The overlapping region may have a width 62 in the width direction 30 and a length 64 in the length direction 34.

[0031] Generally, a varistor with low resistance results in a low limiting voltage. Many factors, such as the geometric configuration and material properties of the various components of the varistor 10, can contribute to the active resistance of the varistor. For example, electrodes 16 and 18 may contribute resistance along their lengths. Similarly, the connections between electrodes 16 and 18 and terminals 17 and 19 may contribute resistance. In some embodiments, at least one electrode 12 may have an electrode aspect ratio defined as length 36 divided by width 38. As mentioned above, in some embodiments, the electrode aspect ratio may be less than about 1.

[0032] Furthermore, the shape of the overlapping region 60 between electrodes 16 and 18 may affect the active resistance of the varistor 10, and therefore may affect the limiting voltage of the varistor 10. In some embodiments, the overlapping region 60 may have an overlapping aspect ratio defined as the overlapping length 64 divided by the overlapping width 62. As mentioned above, in some embodiments, the overlapping aspect ratio may be less than about 1.

[0033] Furthermore, the overall shape of the varistor 10 may affect its active resistance, and therefore may affect its limiting voltage. The varistor 10 may have an overall aspect ratio defined as the total length 40 of the varistor 10 divided by its total width 42. As mentioned above, in some embodiments, the overall aspect ratio may be less than approximately 1.

[0034] Figure 4 shows a panel layout 66 relating to the fabrication of multiple dielectric electrode layers 12 according to embodiments of the varistor 10 shown in Figures 1 and 2. The electrodes 16, 18 may be printed onto a sheet of dielectric material using any suitable printing technique. For example, silkscreen printing with electrode ink may be used. The individual dielectric electrode layers 12, 14 may be stacked, diced, press-formed, and / or sintered to form the varistor 10. For example, a guillotine may be configured to dice the stacked sheets along one or more longitudinal cutting lines 68 and one or more transverse cutting lines 70.

[0035] Figure 5 shows a panel layout 66 relating to the fabrication of multiple dielectric electrode layers 12 according to the embodiment of the varistor 10 shown in Figures 2A to 2D. The printing and cutting techniques described above may be used. As described above, the laminated thin sheets are formed by one or more vertical cutting lines 68, It may be cut along one or more horizontal cutting lines 68.

[0036] Figures 4 and 5 show a panel layout 66 having six electrodes 16, 17 in a 3x2 electrode arrangement; however, in other embodiments, the panel layout 66 may include other numbers and arrangements of electrodes. For example, in some embodiments, the panel layout 66 may include 2 to 1000 electrodes; in some embodiments, 10 to 100 electrodes; and in some embodiments, 20 to 50 electrodes. However, any suitable number of electrodes may be printed on the panel layout 66.

[0037] Referring to Figure 6, in some embodiments, a varistor array 100 containing multiple varistors may be formed. In some embodiments, the varistor array 100 may contain three varistors. The varistor array 100 may contain four pairs of alternating layers 12, 14, each of which layers 12, 14 may provide three electrodes 16, 18 for each varistor. The varistor array 10 shown in Figure 6 may contain rectangular electrodes 16, 18 shown in Figures 1A to 1D and / or T electrodes shown in Figures 2A to 2D. The varistor array 100 may be manufactured in a manner similar to that described with respect to the single varistor embodiment shown in Figures 1 to 4. For example, electrode ink may be printed on laminated sheets (e.g., using a silkscreen). In some embodiments, the panel layout 66 shown in Figure 4 and / or Figure 5 may be used. As described above, the individual dielectric electrode layers 12 and 14 may be stacked, diced, pressed, and / or sintered to form a varistor array 100.

[0038] The varistor array 100 may have a total length 102 in the length direction 34 and a total width 104 in the width direction 30. The varistor array 100 may have an overall aspect ratio defined as the total width 104 divided by the total length 102. As described above, in some embodiments, the overall aspect ratio may be less than about 1.

[0039] When a voltage transient or voltage surge occurs, current can flow between two or more electrodes 16, 18. This can prevent current from flowing to one or more other components of the circuit board, thereby protecting other components on the circuit board from damage. The varistor 10 and / or varistor array 100 described herein may be particularly suitable for automotive applications. Other applications may include providing surge protection for both differential-mode and common-mode transient voltage surges.

[0040] The present invention can be better understood by referring to the following examples.

[0041] Examples As is known in the art, the case size of an electronic device may be expressed as a four-digit code (e.g., XXYY), where the first two digits (XX) are the length of the device in millimeters (or in units of 1 / 1000 of an inch), and the last two digits (YY) are the width of the device in millimeters (or in units of 1 / 1000 of an inch). For example, common metric case sizes may include 2012, 1608, and 0603. According to aspects of this disclosure, “reverse geometry” varistors may be provided. For example, a reverse geometry 1220 metric case size varistor may be provided (having a length of 12 millimeters and a width of 20 millimeters). The reverse geometry 1220 metric case size varistor may be “reverse” compared to a conventional 2012 metric case size varistor (having a length of 20 millimeters and a width of 12 millimeters). An inverse geometric 1220 metric case-size varistor may, for example, have an overall rectangular electrode. Such an inverse geometric varistor is The electrode aspect ratio may be about 0.78. In some embodiments, the inverse geometry 1220 metric case-size varistor may include a T electrode. Such an inverse geometry varistor may have an electrode aspect ratio of about 0.49. Each of the aforementioned inverse geometry 1220 varistors may have an overlap aspect ratio of about 0.48 and an overall aspect ratio of about 0.67.

[0042] Other embodiments of the inverse geometry varistor according to aspects of this disclosure may include the inverse geometry 0816 varistor and the inverse geometry 0603 varistor. Each of these varistors may be configured to have a rectangular electrode and / or a T electrode.

[0043] Test method The following sections provide exemplary methods for testing varistors to measure various varistor characteristics.

[0044] The limiting voltage of the varistor may be measured using a Keithley 2400(R) series source measure unit (SMU), for example, a Keithley 2410-C(R) SMU. The varistor may receive a current wave of 8 / 20 microseconds, for example, according to ANSI standard C62.1. The current wave may have a peak current value of 1 mA. The peak current value may be selected so that it causes the varistor to "clamp" the voltage, as will be described in more detail later. An exemplary current wave is shown in Figure 7. The current (vertical axis 202) is plotted against time (horizontal axis 204). The current can increase to a peak current value 206 and then decay. The "rise" time period (shown by the vertical dashed line 206) can be from the start of the current pulse (at t=0) until the current reaches 90% of the peak current value 206 (shown by the horizontal dashed line 208). The "rise" time can be 8 microseconds. The "decay time" (shown by the vertical dashed line 210) can be from the start of the current pulse (at t=0) to 50% of the peak current value 206 (shown by the horizontal dashed line 212). The "decay time" can be 20 microseconds. The limiting voltage is measured as the maximum voltage across the varistor during the current wave.

[0045] Referring to Figure 8, the voltage across the varistor (horizontal axis 302) is plotted against the current flowing through the varistor (vertical axis 304). As shown in Figure 8, once the voltage exceeds the breakdown voltage 306, the additional current flowing through the varistor does not significantly increase the voltage across it. In other words, the varistor "clamps" the voltage at approximately the limiting voltage 308. Therefore, the limiting voltage 308 can be accurately measured as the maximum voltage measured across the varistor during a current wave. This remains true as long as the peak current value 310 is not large enough to damage the varistor.

[0046] These and other variations and modifications of the present invention can be implemented by those skilled in the art without departing from the spirit and scope of the invention. Furthermore, various implementations It should be understood that the morphological aspects may be replaced, either as a whole or in part. Furthermore, it will be recognized by those skilled in the art that the above description is merely illustrative and is not intended to limit the invention to what may be further described in such appended claims. (1) According to a first aspect of the present invention, a varistor has a rectangular structure defining opposing first and second sides offset in the width direction and opposing first and second end faces offset in the length direction, comprising a first terminal adjacent to the opposing first end face and a first electrode having an electrode length in the length direction and an electrode width in the width direction, wherein the first electrode comprises a first electrode layer connected to the first terminal along the electrode width of the first electrode, and a second terminal adjacent to the opposing second end face and a second electrode having an electrode length in the length direction and an electrode width in the width direction, wherein the second electrode comprises a second electrode layer connected to the second terminal along the electrode width of the second electrode, wherein at least one of the first electrode or the second electrode has an electrode aspect ratio of less than about 1. (2) According to a second aspect of the present invention, in the first aspect, the limiting voltage of the varistor is less than about 12 volts. (3) According to a third aspect of the present invention, in the first aspect, the first electrode overlaps with the second electrode in both the width direction and the length direction such that it defines an overlapping region having an overlapping width in the width direction and an overlapping length in the length direction, the overlapping region having an overlapping aspect ratio of less than 1. (4) According to a fourth aspect of the present invention, the first aspect further comprises the total length in the longitudinal direction between the opposing first end face and the second end face, the total width in the width direction between the opposing first side face and the second side face, and an overall aspect ratio of less than 1. (5) According to a fifth aspect of the present invention, in the first aspect, at least one of the first electrode or the second electrode is a T electrode. (6) According to a sixth aspect of the present invention, in the first aspect, the first terminal is connected to the first electrode along at least one of the opposing first side or the opposing second side of the varistor. (7) According to a seventh aspect of the present invention, in the first aspect, at least one of the first electrode or the second electrode intersects with at least one of the opposing first side surface or the opposing second side surface. (8) According to an eighth aspect of the present invention, a varistor has a rectangular structure defining opposing first and second side surfaces offset in the width direction, and opposing first and second end surfaces offset in the length direction, comprising a first terminal adjacent to the opposing first end surface and a first electrode layer including a first electrode connected to the first terminal, and a second terminal adjacent to the opposing second end surface and a second electrode layer including a second electrode connected to the second terminal, wherein the second electrode overlaps with the first electrode along an overlapping region having an overlapping width in the width direction and an overlapping length in the length direction, and the overlapping region has an overlapping aspect ratio of less than about 1. (9) According to the ninth aspect of the present invention, the eighth aspect further comprises the total length in the longitudinal direction between the opposing first end face and the second end face, the total width in the width direction between the opposing first side face and the second side face, and an overall aspect ratio of less than 1. (10) According to the tenth aspect of the present invention, in the eighth aspect, the limiting voltage of the varistor is less than about 12 volts. (11) According to the eleventh aspect of the present invention, in the eighth aspect, at least one of the first electrode or the second electrode is a T electrode. (12) According to a twelfth aspect of the present invention, in the eighth aspect, the first terminal is connected to the first electrode along at least one of the opposing first side or the opposing second side of the varistor. (13) According to a thirteenth aspect of the present invention, in the eighth aspect, at least one of the first electrode or the second electrode intersects with at least one of the opposing first side surface or the opposing second side surface. (14) According to a fourteenth aspect of the present invention, a varistor array is a varistor array having a rectangular structure defining opposing first and second sides offset in the width direction and opposing first and second end faces offset in the length direction, comprising a first terminal associated with the opposing first end faces and a first set of electrodes, each of which is connected to the first terminal and has a first electrode layer having an electrode length in the length direction and an electrode width in the width direction, comprising a second terminal associated with the opposing second end faces and a second set of electrodes, each of which is connected to the second terminal and has a second electrode layer having an electrode length in the length direction and an electrode width in the width direction, wherein at least one electrode of the first set of electrodes or the second set of electrodes has an electrode aspect ratio of less than about 1. (15) According to a 15th aspect of the present invention, in a 14th aspect, at least one of the electrodes of the first set of electrodes overlaps with at least one of the electrodes of the second set of electrodes in the length direction and the width direction such that it defines an overlap region having an overlap width in the width direction and an overlap length in the length direction, the overlap region having an overlap aspect ratio of less than about 1. (16) According to the sixteenth aspect of the present invention, in the fourteenth aspect, the overall length in the longitudinal direction between the opposing first end face and the second end face, the overall width in the width direction between the opposing first side surface and the second side surface, and an overall aspect ratio of less than 1. (17) According to the 17th aspect of the present invention, in the 14th aspect, at least one of the electrodes of the first set or the electrodes of the second set is a T electrode. (18) According to the eighteenth aspect of the present invention, in the fourteenth aspect, the first terminal is connected to the first electrode along at least one of the opposing first side or the opposing second side of the varistor. (19) According to a 19th aspect of the present invention, in a 14th aspect, at least one of the electrodes of the first set or the electrodes of the second set intersects with at least one of the opposing first side surface or the opposing second side surface. (20) According to a 20th aspect of the present invention, in a 14th aspect, the limiting voltage between the first terminal and the second terminal of the varistor array is less than about 12 volts.

Claims

1. A varistor having a rectangular structure that defines opposing first and second side surfaces offset in the width direction, and opposing first and second end surfaces offset in the length direction, A first terminal adjacent to the opposing first end face, A first electrode layer comprising a first electrode having an electrode length in the longitudinal direction and an electrode width in the width direction, wherein the first electrode is connected to a first terminal along the electrode width of the first electrode, and the first electrode further comprises a protruding portion, a first shoulder portion that curves from the protruding portion and intersects the opposing first side surface, and a second shoulder portion that curves from the protruding portion and intersects the opposing second side surface, A second terminal adjacent to the opposing second end face, The second electrode includes an electrode having an electrode length in the longitudinal direction and an electrode width in the width direction, and the second electrode is connected to the second terminal along the electrode width of the second electrode, and Equipped with, The aforementioned barista, The total length in the longitudinal direction between the opposing first end face and the second end face, and the total width in the width direction between the opposing first side face and the second side face, The overall aspect ratio is less than 1 and It has, At least one of the first electrode or the second electrode has an electrode aspect ratio of less than 1. A varistor in which the first terminal is connected to the first electrode along at least one of the opposing first side or the opposing second side of the varistor.

2. The varistor according to claim 1, wherein the limiting voltage of the varistor is less than 12 volts.

3. The first electrode overlaps with the second electrode in both the width direction and the length direction so as to define an overlapping region having an overlapping width in the width direction and an overlapping length in the length direction. The varistor according to claim 1, wherein the overlapping region has an overlapping aspect ratio of less than 1.

4. A varistor having a rectangular structure that defines opposing first and second side surfaces offset in the width direction, and opposing first and second end surfaces offset in the length direction, A first terminal adjacent to the opposing first end face, A first electrode layer including a first electrode connected to the first terminal, A second terminal adjacent to the opposing second end face, A second electrode layer including a second electrode connected to the second terminal and Equipped with, The aforementioned barista, The total length in the longitudinal direction between the opposing first end face and the second end face, and the total width in the width direction between the opposing first side face and the second side face, The overall aspect ratio is less than 1 and It has, The second electrode overlaps with the first electrode along an overlapping region having an overlapping width in the width direction and an overlapping length in the length direction. The overlapping region has an overlapping aspect ratio of less than 1. Each of the first electrode and the second electrode is a T-electrode having a first side length extending along the opposing first side and a second side length extending along the opposing second side, A varistor in which each of the first and second terminals has a first portion extending along an opposing first side surface and a second portion extending along an opposing second side surface, the first portion having the same length as the first side and the second portion having the same length as the second side.

5. The varistor according to claim 4, wherein the limiting voltage of the varistor is less than 12 volts.

6. A varistor array having a rectangular structure that defines opposing first and second side surfaces offset in the width direction, and opposing first and second end surfaces offset in the length direction, A first terminal associated with the opposing first end face, A first set of electrodes is included, each of which is connected to the first terminal and has a first electrode layer having an electrode length in the longitudinal direction and an electrode width in the width direction, A second terminal associated with the opposing second end face, The second set of electrodes includes a second electrode layer having an electrode length in the longitudinal direction and an electrode width in the width direction, each of the electrodes in the second set being connected to the second terminal and having an electrode layer having an electrode length in the longitudinal direction and an electrode width in the width direction. Equipped with, The aforementioned varistor array is The total length in the longitudinal direction between the opposing first end face and the second end face, and the total width in the width direction between the opposing first side face and the second side face, The overall aspect ratio is less than 1 and It has, At least one electrode from the first set of electrodes or the second set of electrodes has an electrode aspect ratio of less than 1. A varistor array in which at least one electrode from the first set of electrodes or the second set of electrodes is a T electrode, the T electrode having a shoulder portion that curves from a protruding portion of the T electrode to the side length of the T electrode.

7. At least one of the electrodes of the first set overlaps with at least one of the electrodes of the second set in the length direction and width direction such that it defines an overlapping region having an overlapping width in the width direction and an overlapping length in the length direction. The varistor array according to claim 6, wherein the overlapping region has an overlapping aspect ratio of less than 1.

8. The varistor array according to claim 6, wherein at least one of the electrodes of the first set and at least one of the electrodes of the second set reach at least one of the opposing first side or the opposing second side.

9. The varistor array according to claim 6, wherein the limiting voltage between the first terminal and the second terminal of the varistor array is less than 12 volts.

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