Signal processing device, photon counting circuit, medical diagnostic device, and signal processing method

Abstract

A signal processing device, a photon counting circuit, a medical diagnostic device, and a signal processing method. A signal processing device for an electromagnetic radiation sensor comprises a common input (S_out) and a number of auto-zero (AZ) comparators (comp1, comp2, ..., compn+1), each AZ comparator comprising a reference potential terminal for receiving a reference voltage (vrefn), a signal input for receiving a voltage to be compared, and a signal output coupled to said processing block (PROC). The processing block (PROC) is configured to evaluate the comparison results provided by said number of AZ comparators. An AZ digital-to-analog converter (DAC) (AZ-DAC) is configured to provide an AZ reference voltage at an AZ reference output (DAC_out) based on a predefined AZ word (AW). A switching circuit (SW) switchably and individually couples said common input (S_out) and said AZ reference output (DAC_out) to said signal input of the respective AZ comparator. The control block (CTRL) is configured to, for each AZ comparator, disconnect the common input (S_out) from the signal input of the respective AZ comparator during a respective disconnection time (T_discon) and connect the AZ reference output (DAC_out) to the signal input of the respective AZ comparator during the respective disconnection time for the respective AZ time by controlling the switching circuit (SW).

Description

Technical Field

[0001] The present disclosure relates to a signal processing device for electromagnetic radiation sensors such as multi - energy spectrum CT (Computed Tomography). The present disclosure also relates to a photon counting circuit, a medical diagnostic device, and a signal processing method.

[0002] Related Applications This patent application claims the priority of German Patent Application No. 10 2022 109 535.5, the disclosure of which is incorporated herein by reference.

Background Art

[0003] In electromagnetic radiation sensors such as multi - energy spectrum CT, usually, a photon counting system is used for each pixel (each channel) of the generated image. Each pixel (each channel) includes a plurality of comparators for evaluating a pulsed signal supplied from a front - end circuit that evaluates the signal of a radiation - sensitive device such as a photodiode. Due to the very strict specifications for offset error and gain error, it is necessary to eliminate the offset of each comparator and, optionally, the gain error of the front - end. In the conventional approach, this is achieved by local digital - to - analog converters (DACs) for each comparator. These DACs each occupy a significant chip area and consume power.

Summary of the Invention

[0004] Particularly in electromagnetic radiation sensors, it is an object to provide an improved processing concept that enables more efficient processing of input signals.

[0005] This object is achieved by the subject matter of the independent claims. Embodiments and variants are based on the dependent claims.

[0006] The improved processing concept is based on the idea of ​​using only a single DAC for multiple comparators, instead of providing a separate DAC for each comparator. For example, switching circuits and control logic are provided to supply the output voltage of the single DAC individually to each comparator during a period when the signal inputs to each comparator are disconnected from the common input, such as when a pulsed signal is supplied from the front end.

[0007] For example, multiple comparators are auto-zero (AZ) DACs, and the voltage supplied by the DACs is an AZ voltage generated based on a predetermined AZ word that can be set individually for each AZ comparator.

[0008] Because only a single DAC is used, chip area and power consumption can be reduced compared to conventional methods. In an example implementation of a signal processing device for an electromagnetic radiation sensor relating to the improved processing concept, the signal processing device has a common input that can be coupled to the output of the front-end circuit of the electromagnetic radiation sensor and provide a voltage pulse signal. The signal processing device further comprises multiple AZ comparators, each AZ comparator having a reference potential terminal that receives a reference voltage, a signal input that receives a voltage to be compared, and a signal output coupled to the processing block.

[0009] The signal processing device further comprises a processing block that evaluates the comparison results supplied by multiple AZ comparators, an AZ digital-to-analog converter that supplies an AZ reference voltage to the AZ reference output based on a predetermined AZ word, and a switching circuit that individually and switchably connects the common input and the AZ reference output to the signal input of each AZ comparator. This allows the signal input to be connected to the common input and / or the AZ reference output for each AZ comparator, regardless of the connection status of other AZ comparators.

[0010] The signal processing device further includes a control block. The control block controls switching circuits to disconnect the common input from the signal input of each AZ comparator for each AZ comparator during their respective disconnection times, for example, in a non-overlapping manner, and also controls switching circuits to connect the AZ reference output to the signal input of each AZ comparator for their respective AZ times during their respective disconnection times.

[0011] This allows the AZ operation in each AZ comparator to be triggered. The AZ operation itself may take several hundred nanoseconds to complete, and it may be necessary to refresh it every few microseconds to avoid compromising drift performance. However, in that case, the amount of radiation such as X-rays during the AZ time is essentially wasted, and the dead time may become long.

[0012] Therefore, if the signal processing device consists of N+1 AZ comparators, at least N AZ comparators are connected to the common input at each time interval. Furthermore, while at least N of these AZ comparators are operational to produce comparison results, only one or none of the AZ comparators become inoperable at a time when the common input is disconnected. This configuration significantly reduces dead time.

[0013] During each AZ time within each disconnection time, an AZ reference voltage for each comparator is supplied to its signal input, enabling AZ operation to remove offset and / or low-frequency noise.

[0014] For example, the control block is configured to sequentially disconnect each AZ comparator. This allows a ping-pong approach to be applied, automatically zeroing out the offset and / or low-frequency noise of one comparator while keeping the rest operational. This minimizes dead time and achieves good low-frequency noise / drift performance. Sequential disconnection may also include disconnecting two or more AZ comparators at once, provided that a sufficient number of AZ comparators are operational and capable of providing comparison results.

[0015] For example, sequential disconnection is performed repeatedly at predetermined repetition times. The shorter the repetition time, the more likely it is that one comparator will be inactive at any given time. If the repetition time is too long, the effectiveness of automatic zeroing may decrease. For this reason, the repetition time may be selected considering both of the aforementioned conditions.

[0016] In various implementations, the processing block is configured to count events based on comparison results supplied by multiple AZ comparators. This can be particularly useful in photon counting.

[0017] For example, the number of AZ comparators is in the range of 4 to 10, for instance, 5 to 8.

[0018] During the operation of the signal processing unit at the end of each disconnection time, i.e., when the signal input of the AZ comparator is reconnected to the common input, a voltage jump or voltage step may occur depending on the voltage level at the common input. This may, in some cases, cause glitches in the signal input of the reconnected AZ comparator, the common input, or even the signal inputs of all comparators. In large-scale multi-pixel CT systems, thousands of comparators may be switching per IC, making it crucial to reduce glitches and crosstalk from the power supply and reference path. The improved processing concept provides a method for handling glitches when such glitches need to be considered.

[0019] For example, the operation of the processing blocks that evaluate each comparison result may be stopped at the end of each disconnection time. This ensures that comparison results based on potential glitches are not considered by the processing blocks.

[0020] For example, for the above purpose, the control block is configured to supply a stop indicator to the processing block at the end of each disconnection time, and the processing block is configured to stop evaluating the comparison results while the stop indicator is being supplied.

[0021] Another example of how to handle glitches related to the improved processing concept is to supply the voltage at the common input to the signal input of the AZ comparator via a decoupling element after the AZ comparator's automatic zero adjustment, i.e., after each AZ time and within the disconnection time. This ensures that when reconnected at the end of the disconnection time, the same or at least similar voltage as the common input is present at the disconnected AZ comparator's signal input. The decoupling element is, for example, a buffer element. Upon reconnection, the same or similar voltage can avoid or at least reduce the glitch.

[0022] For example, for the above purpose, the switching circuit further connects the common input to the signal input of each AZ comparator, switchable and individually via a decoupling element. Furthermore, the control block connects the common input to the signal input of each AZ comparator via the decoupling element by controlling the switching circuit during each disconnection time and after each AZ time. In particular, both conditions are satisfied.

[0023] An example implementation for handling glitches may be a combination of stopping the operation of the processing block and connecting the common input to the signal input via a decoupling element.

[0024] As mentioned above, the stop indicator is set at the end of each disconnection period. This means, for example, that the stop indicator is set from a little before the end of the disconnection period to a little after the end of the disconnection period, i.e., the end of the disconnection period falls within the duration of the stop indicator.

[0025] For example, if only an approach using a stop indicator is used, i.e., without using a decoupling element, the duration of the stop indicator may be in the range of 500 ps to 5000 ps, ​​for example, in the range of 1 ns to 2 ns.

[0026] When both approaches to handling glitches are combined, i.e., when a decoupling element is employed, the duration of the stop indicator may be in the range of 50 ps to 500 ps, ​​for example, in the range of 100 ps to 200 ps.

[0027] Each AZ comparator includes an AZ capacitor connected between its reference input and its reference potential terminal. The AZ comparator also includes a switchable feedback connection between its reference input and its signal output, and the control block enables each feedback connection for each AZ time.

[0028] Therefore, during the operation of the AZ comparator, while the AZ voltage is supplied to the signal input and the reference input and the signal output are connected during each AZ time, the AZ reference voltage supplied to the signal input is established at the reference input, and the AZ capacitor is charged to this AZ reference voltage. For this reason, when the connection between the signal output and the reference input of the comparator is released, the AZ capacitor determines the voltage of the reference input and affects the threshold voltage of the comparator.

[0029] For example, the AZ word is different for each AZ comparator. For this reason, each AZ reference voltage is also different for each AZ comparator. This makes it possible to individually adjust and / or compensate the threshold voltage of each comparator.

[0030] The photon counting circuit according to the improved processing concept includes a signal processing device according to any one of the above-described embodiments. Further, the photon counting circuit includes a photon detector that generates a current pulse when receiving a photon, and a signal shaper that is coupled to the photon detector and generates a voltage pulse at a common input based on the received current pulse. For example, the photon detector has a photon-sensitive region and is configured to generate a current pulse in response to the incidence of a photon on the photon-sensitive region.

[0031] As described above, the medical diagnostic device according to the improved processing concept includes at least one photon counting circuit. The device is configured, for example, as an X-ray device or a computed tomography scanner.

[0032] The improved processing concept is not limited to the implementation mode as a device, and can also be implemented as a corresponding signal processing method.

[0033] For example, a signal processing method relating to the concept of improved processing is provided for an electromagnetic radiation sensor having a common input and multiple AZ comparators, each AZ comparator being switchably coupled to the common input and having a signal input to receive voltages to be compared and a signal output for supplying the comparison results. This method includes, for example, disconnecting the common input from the signal input of each AZ comparator for their respective disconnection times so as not to overlap for each AZ comparator, supplying an AZ reference voltage based on each AZ word to the signal input of each AZ comparator for their respective AZ times for their respective disconnection times, and evaluating the comparison results supplied by the multiple AZ comparators.

[0034] In various implementations of the signal processing device described above, when the signal input of the comparator is reconnected to the common input, glitch effects may occur at the end, after each disconnection time. Taking such glitch effects into consideration, the method may further include supplying a stop indicator at the end of each disconnection time and stopping the evaluation of the comparison results while the stop indicator is supplied.

[0035] In addition, or instead, the method may further include connecting the common input to the signal input of each AZ comparator via a decoupling element during each disconnection time and after each AZ time.

[0036] Further implementations of the signal processing method will be readily apparent to those skilled in the art from the above-described various implementations of the signal processing device. For example, the method can be implemented in the signal processing device described above. Specifically, the method may be implemented in a photon counting system in which one or more comparators are arranged in addition to the minimum number of comparators required for the application. Thus, there is always, i.e., always, the minimum number of comparators capable of comparison operation. However, other implementations are not limited to these examples. [Brief explanation of the drawing]

[0037] The improved processing concept will be explained in detail below with reference to the drawings. In each drawing, elements and functional blocks with the same or similar functions are denoted by the same reference numeral. Therefore, redundant explanations may be omitted in the following drawings. [Figure 1] Figure 1 shows an example of a photon counting circuit implementation that includes a signal processing device. [Figure 2] Figure 2 shows an example of an implementation of an automatic zero comparator. [Figure 3] Figure 3 shows an example of a timing diagram for the signal processing device shown in Figure 1. [Figure 4] Figure 4 shows an example of a signal processing device implementation. [Figure 5] Figure 5 shows an example of a timing diagram for the signal processing device shown in Figure 4. [Figure 6] Figure 6 shows other implementation examples of the signal processing device. [Figure 7] Figure 7 shows an example of a timing diagram for the signal processing device shown in Figure 6. [Figure 8] Figure 8 shows other implementation examples of the signal processing device. [Figure 9] Figure 9 shows an example of a timing diagram for the signal processing device shown in Figure 8. [Figure 10] Figure 10 shows an example of a medical diagnostic device equipped with a photon counting circuit. [Modes for carrying out the invention]

[0038] Figure 1 shows an example implementation of a photon counting circuit equipped with a signal processing device relating to an improved processing concept. Generally, the signal processing device is suitably used in electromagnetic radiation sensors. The signal processing device comprises a plurality of automatic zero (AZ) comparators, comparator 1, comp2, compn, and compn+1, with 4 to 10, for example, 5 to 8 AZ comparators. Each AZ comparator has a signal output coupled to the processing block PROC and its respective input coupled to the switching circuit SW. The common input S_out of the signal processing device is coupled to the switching circuit SW and is also coupled to an input for receiving a reference voltage vrefn. The signal processing device further comprises an AZ digital-to-analog converter DAC, which is configured to supply an AZ reference voltage at the AZ reference output based on a predetermined AZ word AW. The AZ reference output DAC_out is coupled to the input side of the switching circuit SW.

[0039] The processing block is configured to evaluate the comparison results supplied by multiple AZ comparators, comp1, comp2, compn, and compn+1, for example, by counting the comparison events supplied by the AZ comparators.

[0040] The photon counting circuit comprises a radiation-sensitive element, symbolically shown as a photodiode in Figure 1, for example. The radiation-sensitive element supplies a current pulse in response to the reception of photons. In other implementation embodiments, the radiation-sensitive element includes, for example, a CdZnTe material that absorbs X-rays and directly converts them into an electrical signal.

[0041] The output of the radiation-sensitive element is coupled, for example, to a signal shaper SH, and an optional baseline extraction circuit BE is connected in antiparallel to the signal shaper SH. The signal shaper SH generates a voltage pulse from the received current pulse and supplies the resulting signal to a common input S_out. The optional baseline extraction circuit BE evaluates the signal obtained at the common input S_out and supplies feedback to the inputs of the signal shaper SH.

[0042] The configuration in which a radiation-sensitive element is implemented together with a corresponding front end to supply a signal having a voltage pulse to a photon counting circuit is well known in the art and will not be described in further detail herein. In the common S_out, for example, as long as a signal having a voltage pulse is supplied by the radiation-sensitive element and the corresponding front end, this signal can be processed by a signal processing device downstream of the common input S_out.

[0043] According to the improved processing concept, the signal processing unit uses a switching circuit to "take out" one comparator at a time in a ping-pong manner, automatically zeroing out its offset and / or low-frequency noise while allowing the rest to operate and perform the comparison. The switching circuit SW switches individually to connect the common input S_out and the AZ reference output DAC_out to the signal inputs of each AZ comparator in a switchable manner. For example, a switch is provided for each AZ comparator to connect the signal input for the signal to be compared to the common input S_out. Furthermore, each AZ comparator has a switch to connect its signal input to the AZ reference output DAC_out.

[0044] Figure 2 shows an example implementation of the AZ comparator. The comparator's signal input is formed by a non-inverting input with a plus sign. Both the common input S_out and the AZ reference output DAC_out are coupled to the signal input by their respective switches. An AZ capacitor CAZ is connected between the comparator's reference input, corresponding to the inverting input with a minus sign, and each reference potential terminal to which the reference voltage vrefn is supplied. The comparator's signal output is coupled to the reference input via a further switch. This establishes a switchable feedback connection.

[0045] During normal operation, the signal input is connected to a common input S_out, controlled by its respective disconnect signal discon, while the feedback connection and the AZ reference output DAC_out are opened based on their respective auto-zero signals az. This allows for a comparison between the signal at the common input S_out and the threshold voltage of a comparator, which is influenced by the voltage stored in the AZ capacitor CAZ.

[0046] In automatic zero-phase mode, the signal input is disconnected from the common input S_out by the corresponding disconnect signal discon. Furthermore, within the time frame in which the common input S_out is disconnected, the signal input can be connected to the AZ reference output DAC_out, and the feedback connection can be closed based on the automatic zero signal az. In this way, while each AZ voltage is supplied to the signal input, the feedback connection stores the corresponding voltage in the AZ capacitor CAZ. This allows for correction of offset noise and low-frequency noise such as flicker noise and popcorn noise. In addition, the drift performance of the comparator can also be improved.

[0047] Other embodiments of the AZ comparator are not limited by this example. For example, other comparator structures can be used as long as they can perform automatic zeroing based on the AZ reference voltage during the period in which the common input S_out is disconnected from the comparison input and the signal inputs of each comparator.

[0048] Referring again to Figure 1, the control block relating to the improved processing concept is configured to control the switching circuit SW so that the common input S_out is disconnected from the signal input of each AZ comparator for its respective disconnection time, without overlap for each AZ comparator comp1, comp2, compn, and compn+1, and the AZ reference output DAC_out is connected to the signal input of each AZ comparator for its respective AZ time, for its respective disconnection time. As a result, at most one comparator is disconnected from the common input S_out at any given time, and at least n AZ comparators remain operational at all times. For example, this is established using the respective control signals compx_discon and compx_az, where x is in the range of 1 to n+1, and the extended discontinue and az correspond to the signals discontinue and az, respectively, as described in relation to Figure 2.

[0049] Note that the switch connecting the common input S_out to the signal input of the AZ comparator is shown as an opener, and that a high level of each control signal opens or closes the switch.

[0050] Next, Figure 3 shows an example of a switching method for selecting the corresponding control signal for a switching circuit SW. For example, for the first AZ comparator comp1, the corresponding disconnection signal comp1_discon disconnects the AZ comparator's signal input from the common input S_out for a disconnection time T_discon. During this disconnection time T_discon, the auto-zero signal comp1_az goes high, controlling the connection of the AZ reference output DAC_out to the signal input of each AZ comparator for their respective AZ times. Each AZ time is, for example, shorter than the disconnection time T_discon. For other comparators, such as comparator 2 with signals comp2_discon and comp2_az, and AZ comparator compn+1 with signals compnn+1_discon and compn+1_az, similar control signals are generated using the same method as described for the first comparator comp1.

[0051] As can be seen from the timing diagram in Figure 3, the disconnection times of the AZ comparator do not overlap. Also, the disconnection for automatic zeroing is repeated for each repetition time T_rep. The repetition time T_rep is selected to be as long as possible, for example, taking into account the discharge of the AZ capacitor CAZ during the repetition time T_rep.

[0052] Because pulses at the common input S_out can arrive at random timings, the potential of the common input S_out may differ from the baseline of the auto-zeroed comparator. Therefore, connecting or disconnecting the AZ comparator to the common input S_out may cause glitches.

[0053] Figure 4 shows an implementation example of a signal processing device based on the embodiment of the signal processing device in Figure 1, but with an improved concept that takes into account the effects of potential glitches. Similar to Figure 1, in the implementation embodiment of Figure 4, the reference voltage vrefn is supplied to the AZ comparators Comp1, Comp2, Comp, and Comp+1, respectively. Furthermore, the common input S_out and the AZ reference output DAC_out are coupled to the comparator via the switching circuit SW.

[0054] In this example, the AZ-DAC consists of a coarse DAC and a fine DAC, which receive different parts of the AZ word AW, namely the coarse word CW and the fine word FW, respectively. Both the coarse and fine DACs receive a reference voltage vrefn as a negative supply voltage. The coarse DAC receives a supply voltage vrefp as its positive supply voltage, and the fine DAC receives the output of the coarse DAC as its positive supply voltage. Other implementations of the AZ-DAC are not limited to this embodiment.

[0055] To account for potential glitches that may occur when the AZ comparator switches between input and output, the control block CTRL is configured to supply a stop indicator halt_count to the processing block PROC at the end of each disconnection time T_discon. The stop indicator halt_count may extend until the start of the disconnection time when the subsequent comparator disconnects from the common input S_out. Such a configuration is shown, for example, in the signal diagram of Figure 5, with the stop indicator halt_count added to the signal diagram of Figure 3. Referring again to Figure 4, the processing block PROC is configured to stop evaluating the comparison result, e.g., counting the comparison result, when the stop indicator halt_count is supplied, especially when each signal is at a high level.

[0056] Figure 6 shows another example of an implementation of a signal processing device relating to an improved processing concept that takes glitch effects into account. The implementation in Figure 6 is based on the implementation of the signal processing device shown in Figure 1 and further includes a specific implementation of the AZ-DAC described with reference to Figure 4. The switching circuit SW in the implementation in Figure 6 further comprises switches that individually couple the signal inputs of the AZ comparators, comp1, comp2, compn, and compn+1, to the outputs of decoupling elements BUF, which are implemented, for example, as buffer elements. The decoupling elements BUF are coupled to a common input S_out on their input side. As a result, any fluctuations at the output of the decoupling elements do not directly affect the potential at their inputs, the common inputs S_out, but are absorbed by the decoupling elements BUF. Thus, the signal inputs of each AZ comparator are switchedly coupled to the common input S_out via the decoupling elements BUF.

[0057] For example, a decoupling element BUF is a fast buffer that exhibits rapid response between its input and output. Here, the term "fast" refers to the relationship between the rise and fall times of a typical pulsed signal at the common input S_out. For example, there is little to no delay between the input and output signals.

[0058] Figure 7 is based on the signal diagram of Figure 3, and furthermore, a control signal with an extended _bufcon exists for each comparator. For example, in the case of comparator comp1, each control signal comp1_bufcon connects the common input S_out to the signal input of AZ comparator comp1 via the decoupling element BUF during their respective disconnection time T_discon and after their respective AZ time intervals, i.e., when the control signal comp1_az is at a high level. As a result, the potential of the signal input of comparator comp1 becomes the level of the potential of the common input S_out, or at least close to it. Therefore, even if the signal input of comparator comp1 is directly reconnected to the common input S_out, no glitch will occur, or at least the effect of such a glitch will be minimal.

[0059] As shown in the rest of the signal diagram in Figure 7, the same method can be applied to other AZ comparators. Similar to the implementation described above, this procedure may be repeated for a repeating time T_rep.

[0060] Figure 8 shows an implementation of a signal processing device relating to an improved processing concept, based on a combination of the methods described with reference to Figures 4 and 6. Therefore, both a stop indicator and a decoupling element are used. Figure 9 shows the respective switching schemes for the control signals supplied by the control block CTRL. Figure 9 is based on the switching scheme shown in Figure 7, with the addition of a corresponding stop indicator.

[0061] In the implementation shown in Figure 4, where only the stop indicator is used, the duration of the stop indicator, i.e., the high state of the corresponding signal, is, for example, in the range of 500 picoseconds to 5000 picoseconds, and may also be in the range of 1 ns to 2 ns.

[0062] In the implementation shown in Figure 8, which reduces potential glitches using a decoupling element BUF, the duration of the stop indicator can be reduced to, for example, one-tenth compared to the implementation shown in Figure 4. Therefore, the duration of the stop indicator can be in the range of 500 ps to 5000 ps, ​​for example, in the range of 100 ps to 200 ps.

[0063] The AZ word AW may be supplied from the control block CTRL. For example, the AZ word for each comparator may be stored in memory or supplied from a specially programmed FPGA. For example, the AZ word may be predetermined during the calibration phase.

[0064] Figure 10 shows an example of an application where a photon counting circuit 2 equipped with a signal processing device according to any one of the above-described implementation embodiments is provided in a medical diagnostic device 1. The medical diagnostic device 1 may be configured, for example, as an X-ray device or a computed tomography scanner.

[0065] Embodiments of the improved processing concept disclosed herein are described for the purpose of familiarizing the reader with novel forms of implementation of the improved processing concept. While preferred embodiments have been shown and described, many changes, modifications, equivalents, and substitutions of the disclosed concept can be made by those skilled in the art without unnecessarily departing from the claims.

[0066] In particular, the implementations relating to the improved processing concept are not limited to the disclosed embodiments, and as many alternative examples as possible are provided for the features included in the above embodiments. However, any modifications, equivalents, and substitutes of the disclosed concept are intended to be included within the claims appended herein.

[0067] Features described in separate dependent claims can be advantageously combined. Furthermore, reference numerals used in the claims should not be construed as limiting the scope of the claims.

[0068] Furthermore, as used herein, the terms “have,” “include,” and “equip” do not exclude other elements. In addition, as used herein, the article “a” is intended to include one or more constituent elements or components, and is not limited to being interpreted as meaning only one. [Explanation of symbols]

[0069] SH signal shaper BE Baseline Extraction S_out Common input comp1, comp2 AZ comparators compn, compn+1 AZ comparator SW switching circuit Block Processing Block CTRL control block vrefn Reference voltage DAC_out AZ reference output AW AZ word CW rough words FW detailed words CAZ AZ Capacitor T_discon Disconnection time T_rep repetition time compx_discon disconnect signal compx_az AZ signal compx_bufcon control signal halt_count Stop indicator BUF Decoupling Element 1. Medical diagnostic equipment 2-Photon Counting Circuit

Claims

1. A signal processing device for an electromagnetic radiation sensor, wherein the signal processing device is Common input (S_out) and, Multiple automatic zero (AZ) comparators (comp1, comp2, ..., compn+1), where each AZ comparator is: A reference potential terminal that receives a reference voltage (vrefn), The signal input that receives the voltage to be compared, A signal output coupled to a processing block (PROC) is provided, The aforementioned plurality of automatic zero (AZ) comparators (comp1, comp2, ..., compn+1) The processing block (PROC) is configured to evaluate the comparison results supplied by the plurality of AZ comparators, An AZ digital-to-analog converter (DAC) (AZ-DAC) is configured to supply an AZ reference voltage to an AZ reference output (DAC_out) based on a predetermined AZ word (AW), A switching circuit (SW) that switchesly connects the common input (S_out) and the AZ reference output (DAC_out) to the signal input of each AZ comparator, A control block (CTRL) that controls a switching circuit (SW), For each AZ comparator, the common input (S_out) is disconnected from the signal input of each AZ comparator during its respective disconnection time (T_discon). The AZ reference output (DAC_out) is configured to be connected to the signal input of each AZ comparator for each respective AZ time during each disconnection time. The control block (CTRL) is provided, Signal processing device.

2. The control block (CTRL) is configured to sequentially disconnect each AZ comparator. The signal processing apparatus according to claim 1.

3. The control block (CTRL) is configured to repeatedly perform the sequential disconnection at a predetermined repetition time (T_rep). The signal processing apparatus according to claim 2.

4. The control block (CTRL) is configured to supply a stop indicator (halt_count) to the processing block (PROC) at the end of each disconnection time (T_discon). The processing block (PROC) is configured to stop evaluating the comparison results when the stop indicator (halt_count) is supplied. The signal processing apparatus according to claim 1.

5. The duration of the aforementioned stop indicator (halt_count) is within the range of 500 ps to 5000 ps. The signal processing apparatus according to claim 4.

6. The switching circuit (SW) further switches the common input (S_out) to the signal input of each AZ comparator via a decoupling element (BUF), The control block (CTRL) controls the switching circuit (SW) to directly disconnect the signal input of the AZ comparator from the common input (S_out) during each disconnection time, and during the AZ time within the disconnection time, it supplies the AZ reference output (DAC_out) of the AZ digital-to-analog converter (AZ-DAC) to the signal input, and after the AZ time and within the disconnection time, it connects the common input (S_out) to the signal input of each AZ comparator via the decoupling element (BUF). The signal processing apparatus according to claim 1.

7. The switching circuit (SW) further connects the common input (S_out) to the signal input of each AZ comparator individually and switchably via a decoupling element (BUF), The control block (CTRL) is further configured to control the switching circuit (SW) to directly disconnect the signal input of the AZ comparator from the common input (S_out) during each disconnection time, and to supply the AZ reference output (DAC_out) of the AZ digital-to-analog converter (AZ-DAC) to the signal input during the AZ time within the disconnection time, and to connect to the signal input of each AZ comparator via a decoupling element (BUF) after the AZ time and within the disconnection time. The duration of the aforementioned stop indicator (halt_count) is within the range of 50 ps to 500 ps. The signal processing apparatus according to claim 4.

8. Each AZ comparator is: An AZ capacitor (CAZ) is connected between the reference input of each AZ comparator and the reference potential terminal of each AZ comparator, Each of the aforementioned reference inputs and each of the aforementioned signal outputs is provided with a switchable feedback connection, The control block (CTRL) is configured to enable each feedback connection during each AZ time. The signal processing apparatus according to claim 1.

9. The aforementioned AZ word (AW) is different for each AZ comparator. The signal processing apparatus according to claim 1.

10. The processing block (PROC) is configured to count events based on the comparison results supplied by the plurality of AZ comparators. The signal processing apparatus according to claim 1.

11. The number of AZ comparators is in the range of 4 to 10. The signal processing apparatus according to claim 1.

12. A signal processing apparatus according to any one of claims 1 to 11, A photon detector configured to generate a current pulse upon receiving a photon, The system includes a signal shaper (SH) coupled to the photon detector and configured to generate a voltage pulse at the common input (S_out) based on the received current pulse, Photon counting circuit (2).

13. The device comprises at least one photon counting circuit (2) according to claim 12, It is configured as an X-ray device or computed tomography scanner. Medical diagnostic device (1).

14. A signal processing method for an electromagnetic radiation sensor comprising a common input (S_out) and a plurality of automatic zero (AZ) comparators (comp1, comp2, ..., compn+1), wherein each AZ comparator is A signal input for receiving voltages to be compared, which is switchably coupled to the aforementioned common input (S_out), It includes a signal output for supplying comparison results, The aforementioned method, For each AZ comparator, the common input (S_out) is disconnected from the signal input of each AZ comparator during its respective disconnection time (T_discon). The AZ reference output (DAC_out) based on a predetermined AZ word (AW), output from a single AZ digital-to-analog converter (DAC), is supplied to the signal input of each AZ comparator for each AZ time during each of the aforementioned disconnection times. This includes evaluating the comparison results supplied by the plurality of AZ comparators, method.

15. A stop indicator (halt_count) is supplied at the end of each of the aforementioned disconnection times (T_discon), The evaluation of the comparison result is further stopped while the stop indicator (halt_count) is being supplied, The method according to claim 14.

16. The further includes, during the AZ time within each of the disconnection times, supplying the AZ reference output (DAC_out) of the AZ digital-to-analog converter (AZ-DAC) to the signal input of each of the AZ comparators, and connecting the common input (S_out) to the signal input of each of the AZ comparators via a decoupling element (BUF) after the AZ time and within the disconnection time, The method according to claim 14 or 15.

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