A / D converter, semiconductor device

Abstract

Provided is an A / D converter that exhibits a high speed and a smaller layout area even when the analog input range (dynamic range) is so designed as to be wider.　A CDAC 2 and a comparator 3 constitute a circuit that operates with a first signal amplitude that is an amplitude equivalent to the input potential range of an analog input potential Vin. A control circuit 4 is a circuit that operates with a second signal amplitude that is an amplitude smaller than the first signal amplitude. The signal connection between the circuit operating with the first signal amplitude and the circuit operating with the second signal amplitude is implemented via a level shift circuit 5 that performs a signal amplitude conversion. The transition of an operation instruction signal B [M:0] is implemented such that the Hamming distance is one.

Description

[Technical Field]

[0001] This invention relates to a successive approximation type A / D converter using a CDA (capacitive DAC). [Background technology]

[0002] Successive approximation A / D converters have a resolution of n bits, and 2 n The system comprises a CDA consisting of one capacitive element, one comparator, and a control circuit for the CDA, and uses a binary search method to obtain a digital value through n comparison operations (see, for example, Patent Document 1). [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2002-374169 [Overview of the project] [Problems that the invention aims to solve]

[0004] When an A / D converter requires a large analog input range (dynamic range), it needs to be constructed with high-voltage components capable of withstanding the voltage of the signal amplitude within that range. However, using high-voltage components results in a larger layout area for the A / D converter. For example, if the high-voltage component is a MOSFET (transistor), the gate interlayer film needs to be thicker and the gate width larger compared to when low-voltage components are sufficient. Therefore, to achieve performance equivalent to that of a low-voltage component (for example, the source-drain current when the MOSFET is ON), a larger layout area is required for a high-voltage component. Furthermore, the use of high-voltage components increases the parasitic capacitance and resistance of the circuit, preventing the A / D converter from operating at high speeds and resulting in a slower conversion speed relative to power consumption.

[0005] A / D converters can have a smaller layout area if they are constructed using only low-voltage components, for example, the smallest-sized low-voltage components used in the process. In recent years, MOSFETs have become miniaturized, and A / D converters can also benefit from this miniaturization. Furthermore, using low-voltage components reduces the parasitic capacitance and resistance of the circuit, resulting in a high conversion speed relative to power consumption. However, the analog input range cannot exceed the voltage rating of the low-voltage components, resulting in an A / D converter with a small analog input range (dynamic range).

[0006] This invention was made in view of the aforementioned problems, and its objective is to provide a high-speed A / D converter with a small layout area, even when the analog input range (dynamic range) is wide. [Means for solving the problem]

[0007] To achieve the above objective, the A / D converter according to the present invention is configured as follows. The A / D converter according to the present invention is a successive approximation type A / D converter comprising: a capacitive DAC that performs a sampling operation to sample an analog input potential and a target voltage generation operation to sequentially generate a comparison target potential bit by bit based on the sampled analog input potential; a comparator that compares the comparison target potential with a comparison potential; and a control circuit that outputs the operation steps of the capacitive DAC and the comparator as an operation instruction signal consisting of a plurality of bit sequences and controls the operation of the capacitive DAC and the comparator, wherein the capacitive DAC and the comparator are circuits that operate with a first signal amplitude whose amplitude is the input potential range of the analog input potential, the control circuit is a circuit that operates with a second signal amplitude which is smaller than the first signal amplitude, the signal connection between the circuit that operates with the first signal amplitude and the circuit that operates with the second signal amplitude is performed via a level shift circuit that converts the signal amplitude, and the transition of the operation instruction signal is characterized in that the transition is such that the Hamming distance is 1. [Effects of the Invention]

[0008] The A / D converter of the present invention can utilize low-voltage elements for its control circuit, which have a lower voltage rating than the elements constituting the capacitive DAC and comparator. This allows for a wide analog input range (dynamic range) while still benefiting from the miniaturization advancements of recent years and reducing the layout area. Furthermore, the control signals output from the control circuit, which control the capacitive DAC and comparator, travel with a Hamming distance of 1. This enables high-speed operation without malfunction even when there are large variations in the elements constituting the control circuit and the elements constituting the capacitive DAC and comparator. Overall, this invention provides an A / D converter with a wide analog input range (dynamic range), a small layout area, and high speed. [Brief explanation of the drawing]

[0009] [Figure 1] This is a block diagram showing the configuration of an embodiment of the A / D converter according to the present invention. [Figure 2] Figure 1 is a flowchart showing the operation of CDA. [Figure 3] This figure shows the operation instruction signals output from the control circuit shown in Figure 1. [Figure 4] This diagram shows the configuration of the level shifter shown in Figure 1. [Figure 5] Figure 3 shows the characteristics of the level shifter. [Figure 6] Figure 1 illustrates the problems caused by the circuit delay time difference of the level shifter shown. [Modes for carrying out the invention]

[0010] Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

[0011] As shown in Fig. 1, the A / D converter 1 of this embodiment is a successive approximation type A / D converter including a CDAC (capacitive DAC) 2, a comparator 3, a control circuit 4, and a level shift circuit 5. The A / D converter 1 is configured as a semiconductor device incorporated in a digital switching power supply IC (semiconductor integrated circuit) or the like. The A / D converter 1 successively repeats a comparison operation between a comparison target potential generated based on an analog input potential Vin and a comparison potential V ref to convert the analog input potential Vin into a digital conversion value D[(N - 1):0] of N bits (for example, N = 12).

[0012] The CDAC 2 includes a capacitance element C A and a plurality of capacitance elements C0 to C (N-1) whose capacitance values are weighted at a binary ratio (a ratio of powers of 2). A The capacitance elements C (N-1) are connected at one end to the non-inverting input terminal of the comparator 3. The capacitance elements C A and C0 are set to the same capacitance value. When the capacitance values of the capacitance elements C A and C0 are C, the capacitance values of the capacitance elements C0 to C (N-1) are set to 2C to 2 (N―1) C, respectively.

[0013] The CDAC 2 includes a plurality of sample switches X B , X0 to X (N-1) . The sample switch X B connects the comparison potential V ref to the non-inverting input terminal of the comparator 3. The sample switches X0 to X (N-1) are provided corresponding to the capacitance elements C0 to C (N-1) respectively, and connect the analog input potential Vin to the other ends of the capacitance elements C0 to C (N-1) .

[0014] The CDAC 2 includes main switches Y0 to Y (N-1) . The main switches Y0 to Y (N-1) are provided corresponding to the capacitance elements C0 to C (N-1) respectively, and (N-1)The other end has a reference potential V High Or reference potential V Low Connect it. Reference potential V High The reference potential V Low It is set to a higher potential.

[0015] The CDAC2 includes an input signal conversion circuit 21. The input signal conversion circuit 21 converts the operation instruction signal B[M:0] input from the control circuit 4 into an input signal for the CDAC2 consisting of a sample switch control signal SANPLE and main switch control signals SW[(N-1)]~SW[0]. The input signal conversion circuit 21 converts the sample switch X by the sample switch control signal SANPLE. B , X0~X (N-1) By controlling them collectively, a sampling operation is performed to sample the analog input potential Vin. In addition, the input signal conversion circuit 21 controls the main switch Y0 to Y using the main switch control signals SW[(N-1)]~SW[0]. (N-1) By individually controlling each of these, the bitwise comparison target potential V is determined based on the sampled analog input potential Vin. (N-1) The system performs a target voltage generation operation that sequentially generates ~V0.

[0016] The sampling operation and comparison potential generation operation using CDAC2 will be explained with reference to Figure 2. (Sampling operation) The input signal conversion circuit 21 is in a standby state, and sample switch X B , X0~X (N-1) and main switch Y0~Y (N-1) Turn off all of them (Step A1).

[0017] The input signal conversion circuit 21 is in a standby state, and all of the sample switches X, i.e., sample switches X B , X0~X (N-1) The switch is turned ON, and the analog input potential Vin is connected to the capacitive element C A , C0~C (N-1) Import into (Step A2).

[0018] The input signal conversion circuit 21 converts all of the sample switches X, i.e., sample switches X B , X0~X (N-1) This causes the capacitor element C to switch to the OFF state (step A3). A , C0~C (N-1) (Analog input potential Vin - comparison potential V) ref This results in a state where a charge corresponding to ) is accumulated.

[0019] Steps A1 to A3 described above constitute the sampling operation. The sampling operation consists of "3" steps.

[0020] (Operation to generate comparison potential) The input signal conversion circuit 21 sets the main switch control signal SW[(N-1)] to 1 and the main switch Y (N-1) Reference potential V High Connect it and set the main switch control signals SW[(N-2)]~SW[0] to 0 and switch the main switch Y (N-2) ~Y0 is the reference potential V Low Connect to (step B1). This connects to the capacitive element C (N-1) V is the reference potential. High In addition, capacitive elements C0~C (N-2) V is the reference potential. Low Each is connected to a comparison potential V, which is used to determine the digital conversion value D[(N-1)] of the most significant bit (the Nth bit). (N-1) This is generated.

[0021] The input signal conversion circuit 21 compares the target potential V (N-1) Comparison potential V ref The main switch control signal SW[(N-1)] is fixed based on the comparison result Q (step B2).

[0022] Comparison potential V (N-1) The comparison potential is V ref If the comparison result Q is lower than or equal to 0, the digital conversion value D[(N-1)] and the main switch control signal SW[(N-1)] are determined to be 1. Thereafter, the main switch control signal SW[(N-1)] is fixed to 1, and the capacitive element C (N-1)V is the reference potential. High It will be connected to [the device].

[0023] Comparison potential V (N-1) The comparison potential is V ref If the comparison result Q is higher than 1, the digital conversion value D[(N-1)] and the main switch control signal SW[(N-1)] are determined to be 0. Thereafter, the main switch control signal SW[(N-1)] is fixed to 0, and the capacitive element C (N-1) V is the reference potential. Low It will be connected to [the device].

[0024] Subsequently, the same process as in steps B1 and B2 is performed, starting from the most significant bit, and the comparison target potential V of bits (N-1) to the 2nd bit is calculated. (N-2) ~V2 is generated for each, and the digital conversion values ​​D[(N-2)]~D[2] and the main switch control signals SW[(N-2)]~SW[2] are determined (Step B3)~(Step B(2N-2)).

[0025] At the least significant bit (1st bit), the input signal conversion circuit 21 sets the main switch control signal SW[0] to 1, and the main switch Y0 to the reference potential V High Connect it (Step B(2N-1)). This brings the capacitive element C0 to the reference potential V. High It is connected to generate a comparison potential V0 for determining the digital conversion value D[0] of the least significant bit (1st bit).

[0026] The input signal conversion circuit 21 compares the target potential V0 with the comparison potential V ref The main switch control signal SW[0] is fixed based on the comparison result Q (step B2N).

[0027] The comparison potential V0 is the comparison potential V ref If the comparison result Q is lower than or equal to 0, the digital conversion value D[0] and the main switch control signal SW[0] are determined to be 1. Thereafter, the main switch control signal SW[0] is fixed to 1, and the capacitive element C0 is at the reference potential V High It will be connected to [the device].

[0028] The comparison potential V0 is the comparison potential V ref If the comparison result Q is higher than 1, the digital conversion value D[0] and the main switch control signal SW[0] are determined to be 0. Thereafter, the main switch control signal SW[0] is fixed at 0, and the capacitive element C0 is at the reference potential V Low It will be connected to [the device].

[0029] Steps B1 to B2N described above constitute the comparison potential generation operation. The number of steps in the comparison potential generation operation is "2N".

[0030] Comparator 3 compares the output voltage from the capacitive DAC2 input to the non-inverting input terminal with the comparison potential V input to the inverting input terminal. ref It compares the two and outputs the comparison result Q. The comparison target potential V0 is the comparison potential V ref If it is lower than, comparator 3 outputs the comparison result Q=0. ref If it is higher than the given value, comparator 3 outputs the comparison result Q=1.

[0031] When the control circuit 4 receives a start signal START from the higher-level device, it outputs an operation instruction signal B[M:0] to the input signal conversion circuit 21 of the CDAC2, instructing the execution of the sampling operation and the comparison target potential generation operation. Based on the comparison result Q of the comparator 3, which is repeated sequentially from the most significant bit to the least significant bit, the control circuit 4 outputs an N-bit (for example, N=12) digital conversion value D"(N-1):0", and outputs an end signal END to the higher-level device.

[0032] The control circuit 4 controls the operation of the CDAC2 and comparator 3 by outputting the operation steps of the CDAC2 and comparator 3 as an operation instruction signal B[M:0] consisting of multiple bit sequences. The operation instruction signal B[M:0] is, for example, a (M+1) bit code and is a parallel signal with a number of bits that can uniquely indicate the number of steps for the sampling operation and the comparison target potential generation operation. For example, if N=12 and the number of steps for the sampling operation and the comparison target potential generation operation is 2N+3=27, the operation instruction signal B[M:0] will consist of a bit code of 5 bits or more, with M=4 or more.

[0033] The control circuit 4 advances the operation instruction signal B[M:0] using a "Gray code" with a Hamming distance of 1. Figure 3 is a progression table of the operation instruction signal B[M:0] when N=12 and M=4. In this case, the number of steps in CDAC2 is 27, consisting of steps A1~A3 + B1~B24. The operation instruction signal B[M:0] progresses from the 1st "00000" to the 27th "00111" with a Hamming distance of 1. Figure 3 shows an example where the "Gray code" progresses in ascending order from "00000", but it may also progress in descending order, or switch between ascending and descending order midway through. The operation instruction signal B[M:0] only needs to progress with a Hamming distance of 1, and codes other than the "Gray code" may be used.

[0034] CDAC2 and comparator 3 are configured as circuits with a large first signal amplitude (e.g., 5V) using components with a high power supply voltage VCC, in order to increase the dynamic range of the analog input potential Vin to be converted. CDAC2 and comparator 3 are circuits that operate with a first signal amplitude whose amplitude is within the input potential range of the analog input potential Vin. Control circuit 4 is configured as a circuit with a smaller second signal amplitude (e.g., 1V) using components with a low power supply voltage VDD, in order to reduce the layout. Control circuit 4 is a circuit that operates with a second signal amplitude smaller than the first signal amplitude. As a result, the components constituting control circuit 4 can be low-voltage components with a lower voltage rating than the components constituting CDAC2 and comparator 3.

[0035] The level shift circuit 5 converts the signal amplitude for signal connection between the CDA2 and comparator 3 and the control circuit 4. The level shift circuit 5 converts the signal amplitude of the comparison result Q of comparator 3 from the first voltage to the second voltage using a level shifter L. Q The level shift circuit 5 includes a level shifter L that converts the signal amplitude of the operation instruction signal B[M:0] from the second voltage to the first voltage. M Equipped with ~L0. Level shifter L M ~L0 is provided in parallel for each bit of the operation instruction signal B[M:0].

[0036] Level Shifter L M ~L0 is composed of multiple transistors, for example, as shown in Figure 4, but as shown in Figure 5, variations in the elements tend to cause differences in the delay time for each circuit (hereinafter referred to as circuit delay time difference). The A / D converter 1 is provided with an input signal conversion circuit 21 in the CDAC2 and the operation instruction signal B[M:0] is advanced with a Hamming distance of 1, thereby controlling the level shifter L M This resolves the problems caused by the circuit delay time difference of ~L0.

[0037] Below, Level Shifter L M This section explains the problems that arise due to the circuit delay time difference of ~L0. First, we consider a case in which the CDAC2 is directly controlled by the sample switch control signal SANPLE and the main switch control signals SW[(N-1)]~SW[0] output from the control circuit 4, without providing an input signal conversion circuit 21 to the CDAC2. In this case, the main switch control signals SW[(N-1)]~SW[0] are controlled by a level shifter L N-1 The signal is input to CDAC2 via L0.

[0038] If SW

[11] =1, SW

[10] =0 transitions to SW

[11] =0, SW

[10] =1, the comparison potential generated by CDAC2 changes as shown in Figure 6. Figure 6(a) shows the case where the transitions of SW

[11] and SW

[10] occur simultaneously. Figure 6(b) shows the case where the transitions of SW

[11] and SW

[10] occur simultaneously with the level shifter L 11 , L10 This shows the case where the circuit is shifted due to the time difference in the delay time.

[0039] As shown in Figure 6(b), if the transition of SW

[10] is input to CDAC2 earlier than the transition of SW

[11] , then when SW

[10] transitions from 0 to 1, SW

[11] is still in the 1 state. As a result, the main switch Y 11、 Y 10 In all cases, the reference potential V High As the connection is established, the reference potential rises. Subsequently, SW

[11] transitions to 0, causing the reference potential to drop to the potential where SW

[11] =0 and SW

[10] =1. However, the potential guidance distance becomes longer, causing a delay in the output of CDAC2.

[0040] Level Shifter L N-1 It is also conceivable to install a flip-flop after L0 and synchronize the transition of the main switch control signal SW[(N-1)]~SW[0] using a timing signal. However, level shifter L N-1 The circuit delay time difference of ~L0 is not constant, as shown in Figure 6(c). Therefore, the timing signal needs to have a large time margin that takes into account the setup time and hold time, which cover all the variations in signal delay time that may occur due to component variations. Furthermore, the timing signal itself must also be considered as passing through the level shifter, which is a major obstacle to increasing the speed of A / D conversion.

[0041] By providing the input signal conversion circuit 21 in the CDAC2, the main switch control signals SW[(N-1)] to SW[0] can be synchronized, thus solving the above problem. However, if the operation instruction signal B[M:0] uses a code (for example, binary) that progresses with a Hamming distance of 2 or more, the level shifter L M The circuit delay time difference of ~L0 creates a new problem.

[0042] Consider the case where the Hamming distance, in which the operation instruction signal B[4:0] = "00111" transitions to "01000", progresses by 4. In this case, the input signal conversion circuit 21 executes the process corresponding to the operation instruction signal B[4:0] = "01000".

[0043] However, due to the circuit delay time differences between level shifters L N-1 ~L0, the input signal conversion circuit 21 may recognize "01111", "01011", and "01010" before and after "01000". In this case, the DAC2 will perform an unintended operation. Thus, when the operation instruction signal B[M:0] is a code that progresses with a Hamming distance of 2 or more, the input signal conversion circuit 21 may misrecognize an unintended code.

[0044] As in this embodiment, when the operation instruction signal B[M:0] progresses with a Hamming distance of 1, only one bit of the signal in the operation instruction signal B[M:0] switches. Therefore, even if there are circuit delay time differences between level shifters L N-1 ~L0, the input signal conversion circuit 21 will not misrecognize the operation instruction signal B[M:0].

[0045] As described above, this embodiment includes a sampling operation for sampling the analog input potential Vin, and a target voltage generation operation for sequentially generating comparison target potentials V (N-1) ~V0 for each bit based on the sampled analog input potential Vin. The CDAC (capacitive DAC) 2 that performs these operations, and the comparison target potentials V (N-1) ~V0 and the comparison potential V refA successive approximation A / D converter 1 comprises a comparator 3 that compares with the CDA2 and a comparator 3, and a control circuit 4 that outputs the operation steps of the CDA2 and comparator 3 as an operation instruction signal B[M:0] consisting of a plurality of bit sequences and controls the operation of the CDA2 and comparator 3. The CDA2 and comparator 3 are circuits that operate with a first signal amplitude whose amplitude is the input potential range of the analog input potential Vin, and the control circuit 4 is a circuit that operates with a second signal amplitude which is smaller than the first signal amplitude. The signal connection between the circuit that operates with the first signal amplitude and the circuit that operates with the second signal amplitude is performed via a level shift circuit 5 that converts the signal amplitude, and the transition of the operation instruction signal B[M:0] is such that the Hamming distance is 1. This configuration allows the elements constituting the control circuit 4 to be low-voltage elements with lower voltage ratings than the elements constituting the CDA2 and comparator 3. Therefore, even with a large analog input range (dynamic range), the benefits of recent miniaturization can be enjoyed, and the layout area can be reduced. In addition, since the operation instruction signal B[M:0] travels with a Hamming distance of 1, the input signal conversion circuit 21 can prevent misrecognition of the operation instruction signal B[M:0] caused by the circuit delay time difference of the level shift circuit 5, thereby enabling faster A / D conversion.

[0046] Furthermore, in this embodiment, the transition of the operation instruction signal B[M:0] is Gray code. This configuration allows the operation instruction signal B[M:0] to proceed with a Hamming distance of 1.

[0047] It is clear that the present invention is not limited to the above embodiments, and that each embodiment can be modified as appropriate within the scope of the technical concept of the present invention. For example, in this application, the target voltage generation circuit that sequentially generates the comparison target potential for each bit is a capacitive DAC circuit, but it is clear that the same problem shown in this application can be solved by using a resistive DAC circuit with resistors as the target voltage generation circuit. Also, the number, position, shape, etc. of the above components are not limited to the above embodiments, and can be set to a number, position, shape, etc. that is suitable for carrying out the present invention. The same reference numerals are used for the same components in each figure.

Explanation of Symbols

[0048] 1 A / D converter 2 CDAC (capacitive DAC) 3 Comparator 4 Control circuit 5 Level shift circuit 21 Input signal conversion circuit C, C A , C0~C (n-1) Capacitive element L Q , L M ~L0 level shifter X B , X(N-1)~X0 sample switch Y (N-1) ~Y0 main switch

Claims

1. A successive approximation A / D converter comprising: a capacitive DAC that performs a sampling operation to sample an analog input potential and a target voltage generation operation to sequentially generate a comparison target potential bit by bit based on the sampled analog input potential; a comparator that compares the comparison target potential with a comparison potential; and a control circuit that outputs the operation steps of the capacitive DAC and the comparator as an operation instruction signal consisting of a plurality of bit sequences and controls the operation of the capacitive DAC and the comparator, The aforementioned capacitive DAC and comparator are circuits that operate with a first signal amplitude whose amplitude is the input potential range of the analog input potential. The control circuit is a circuit that operates with a second signal amplitude that is smaller than the first signal amplitude. The signal connection between the circuit operating with the first signal amplitude and the circuit operating with the second signal amplitude is made via a level shift circuit that converts the signal amplitude. The A / D converter is characterized in that the transition of the operation instruction signal is such that the Hamming distance is 1.

2. The A / D converter according to claim 1, characterized in that the transition of the operation instruction signal is a Gray code.

3. A semiconductor device characterized in that the A / D converter described in claim 1 or 2 is integrated on a substrate.

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