Method for forming a void spacer in a semiconductor device and semiconductor device

Abstract

A semiconductor device having an air gap spacer formed as part of a BEOL layer or MOL layer of the semiconductor device, and a method for making such an air gap spacer, are provided. For example, a method includes forming a first metal structure and a second metal structure on a substrate, the first metal structure and the second metal structure being disposed adjacent to each other with an insulating material therebetween. The insulating material is etched to form a space between the first metal structure and the second metal structure. A pinch-off deposition process is used to deposit a layer of dielectric material over the first metal structure and the second metal structure to form a void in the space between the first metal structure and the second metal structure. A portion of the void extends above a top surface of at least one of the first metal structure and the second metal structure.

Description

Technical Field

[0001] This field generally relates to semiconductor fabrication, and more particularly to techniques for fabricating air gap spacers for semiconductor devices.

Background Art

[0002] In semiconductor manufacturing technology, the miniaturization of design rules and the increase in integration density are progressing, and the separation between adjacent structures in an integrated circuit is becoming increasingly fine. Therefore, undesirable capacitive coupling may occur between adjacent metal wirings in a BEOL (back-end-of-line) interconnect structure, or between adjacent contacts of FEOL (front-end-of-line) devices (e.g., MOL (middle-of-the-line) device contacts) in an integrated circuit. The parasitic capacitances associated with these structures may lead to a degradation in the performance of semiconductor devices. For example, capacitive coupling between the contacts of a transistor may lead to an increase in parasitic capacitance between the gate and source or between the gate and drain, which may adversely affect the operating speed of the transistor or increase the energy consumption of the integrated circuit. Furthermore, undesirable capacitive coupling between adjacent metal wirings in a BEOL structure may also lead to an increase in resistance-capacitance delay (or latency), crosstalk, and an increase in dynamic power dissipation in the interconnect stack.

[0003] To reduce parasitic coupling between adjacent conductive structures, the semiconductor industry is adopting the use of low-dielectric-constant (low-k) and ultra-low-k (ULK) dielectrics (instead of conventional SiO2 (k=4.0)) as insulating materials for the MOL and BEOL layers of ultra-large-scale integrated circuits (ULSI). However, the emergence of low-k dielectrics associated with rapid miniaturization has created significant challenges in terms of the long-term reliability of these low-k materials. For example, since low-k materials generally have lower intrinsic dielectric breakdown strength than conventional SiO2 dielectrics, low-k TDDB (infrared dielectric degradation over time) is generally considered a significant problem. Generally, TDDB refers to the loss of dielectric insulation over time when a dielectric is subjected to voltage / current bias and temperature stress. TDDB causes an increase in leakage current, thereby degrading the performance of nanoscale integrated circuits. [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] The present invention provides a semiconductor device having a void spacer formed as part of the BEOL layer or MOL layer of the semiconductor device, and a method for fabricating such a void spacer. [Means for solving the problem]

[0005] Embodiments of the present invention include a semiconductor device having a void spacer formed as part of the BEOL layer or MOL layer of the semiconductor device, and a method for fabricating a void spacer as part of the BEOL layer and MOL layer of the semiconductor device.

[0006] For example, a method for fabricating a semiconductor device includes forming a first metal structure and a second metal structure on a substrate, wherein the first and second metal structures are arranged adjacent to each other with an insulating material in between. The insulating material is etched to form a space between the first and second metal structures. Layers of dielectric material are deposited on the first and second metal structures to form a void within the space between the first and second metal structures. A portion of this void extends above the upper surface of at least one of the first and second metal structures.

[0007] In one embodiment, the first metallic structure includes a first metallic wire formed within the interlevel dielectric layer of the BEOL interconnect structure, and the second metallic structure includes a second metallic wire formed within the ILD layer of the BEOL interconnect structure.

[0008] In another embodiment, the first metal structure includes device contacts, and the second metal structure includes the gate structure of the transistor. In one embodiment, the device contacts are higher than the gate structure, and the portion of the gap extends above the gate structure and below the upper surface of the device contacts.

[0009] Other embodiments of the invention will also be described in the following embodiments, which should be read in conjunction with the attached drawings. [Brief explanation of the drawing]

[0010] [Figure 1] This is a schematic diagram showing a semiconductor device comprising a gap spacer integrally formed within the BEOL structure of a semiconductor device according to an embodiment of the present invention. [Figure 2] This is a schematic diagram showing a semiconductor device comprising a gap spacer integrally formed within the BEOL structure of a semiconductor device according to an embodiment of the present invention. [Figure 3]This figure schematically illustrates the improvement in TDDB reliability and the reduction in capacitive coupling between metal wires in a BEOL structure achieved by using a void structure formed using the pinch-off deposition method according to an embodiment of the present invention, compared to a void structure formed using a conventional method. [Figure 4] This figure schematically illustrates the improved TDDB reliability and reduced capacitive coupling between metal wires in the BEOL structure achieved by using a void structure formed using the pinch-off deposition method according to an embodiment of the present invention, compared to a void structure formed using a conventional method. [Figure 5] This is a schematic cross-sectional view showing a semiconductor device comprising a gap spacer integrally formed within the BEOL structure of a semiconductor device, according to another embodiment of the present invention. [Figure 6] This figure schematically illustrates a method for fabricating the semiconductor device shown in Figure 1 according to an embodiment of the present invention, and is a schematic cross-sectional view showing a semiconductor device in an intermediate fabrication stage in which an aperture pattern is formed within an ILD (interlayer dielectric) layer. [Figure 7] This diagram schematically illustrates a method for fabricating the semiconductor device shown in Figure 1 according to an embodiment of the present invention, and is a schematic cross-sectional view showing the semiconductor device shown in Figure 6 after a conformal layer of liner material has been deposited and a layer of metal material has been deposited to fill the openings in the ILD layer. [Figure 8] This figure schematically illustrates a method for fabricating the semiconductor device shown in Figure 1 according to an embodiment of the present invention, and is a schematic cross-sectional view showing the semiconductor device shown in Figure 7 after the surface of the semiconductor structure has been planarized to the ILD layer to form a metal wiring layer. [Figure 9] This figure schematically illustrates a method for fabricating the semiconductor device shown in Figure 1 according to an embodiment of the present invention, and is a schematic cross-sectional view showing the semiconductor device shown in Figure 8 after protective caps have been formed on the metal wires of the metal wiring layer. [Figure 10]This figure schematically illustrates a method for fabricating the semiconductor device shown in Figure 1 according to an embodiment of the present invention, and is a schematic cross-sectional view showing the semiconductor device shown in Figure 9 after etching the ILD layer to form spaces between the metal wires of the metal wiring layer. [Figure 11] This figure schematically illustrates a method for fabricating the semiconductor device shown in Figure 1 according to an embodiment of the present invention, and is a schematic cross-sectional view showing the semiconductor device shown in Figure 10 after a conformal layer of insulating material has been deposited to form an insulating liner that covers the exposed surfaces of the metal wiring layer and the ILD layer. [Figure 12] This figure schematically illustrates a method for fabricating the semiconductor device shown in Figure 1 according to an embodiment of the present invention, and is a schematic cross-sectional view showing the semiconductor device shown in Figure 11, illustrating a process in which a dielectric material is deposited using a non-conformal deposition process to initiate the formation of a pinch-off region within the deposited dielectric material above the space between metal wires in a metal wiring layer. [Figure 13] This is a schematic cross-sectional view showing a semiconductor device comprising a void spacer integrally formed within the FEOL / MOL structure of a semiconductor device, according to another embodiment of the present invention. [Figure 14] This figure schematically illustrates a method for fabricating the semiconductor device shown in Figure 13 according to an embodiment of the present invention, and is a schematic cross-sectional view showing a semiconductor device in an intermediate fabrication stage where a vertical transistor structure is formed on a semiconductor substrate. [Figure 15] This figure schematically illustrates a method for fabricating the semiconductor device shown in Figure 13 according to an embodiment of the present invention, and is a schematic cross-sectional view showing the semiconductor device shown in Figure 14 after a premetal dielectric layer has been patterned and contact openings have been formed between the gate structures of the vertical transistor structure. [Figure 16] This figure schematically illustrates a method for fabricating the semiconductor device shown in Figure 13 according to an embodiment of the present invention, and is a schematic cross-sectional view of the semiconductor device shown in Figure 15 after a conformal liner layer has been formed on the surface of the semiconductor device and the contact openings have been backed with the liner material. [Figure 17]This figure schematically illustrates a method for fabricating the semiconductor device shown in Figure 13 according to an embodiment of the present invention, and is a schematic cross-sectional view showing the semiconductor device shown in Figure 16 after a layer of metal material has been deposited to fill the contact openings with the metal material and the surface of the semiconductor device has been planarized to form MOL device contacts. [Figure 18] This figure schematically illustrates a method for fabricating the semiconductor device shown in Figure 13 according to an embodiment of the present invention, and is a schematic cross-sectional view showing the semiconductor device shown in Figure 17 after the gate capping layer and side wall spacer of the gate structure of the vertical transistor structure have been recessed. [Figure 19] This figure schematically illustrates a method for fabricating the semiconductor device shown in Figure 13 according to an embodiment of the present invention, and is a schematic cross-sectional view showing the semiconductor device shown in Figure 18 after a conformal layer of insulating material has been deposited to form an insulating liner that backs the exposed surfaces of the gate structure and MOL device contacts. [Figure 20] This figure schematically illustrates a method for fabricating the semiconductor device shown in Figure 13 according to an embodiment of the present invention, and is a schematic cross-sectional view showing the semiconductor device shown in Figure 19 after a non-conformal deposition process has been used to deposit dielectric material and create a pinch-off region that forms a gap in the space between the gate structure and the MOL device contact. [Figure 21] This figure schematically illustrates a method for fabricating the semiconductor device shown in Figure 13 according to an embodiment of the present invention, and is a schematic cross-sectional view showing the semiconductor device shown in Figure 20 after the surface of the semiconductor device has been planarized to the MOL device contacts and an ILD layer has been deposited as part of the first interconnection level of the BEOL structure. [Modes for carrying out the invention]

[0011] Next, embodiments will be described in further detail in connection with a semiconductor integrated circuit device having a void spacer formed as part of a BEOL layer or a MOL layer or both, and a method of fabricating a void spacer as part of a BEOL layer or a MOL layer or both of a semiconductor integrated circuit device. In particular, as will be described in further detail below, embodiments of the present invention utilize specific dielectric materials and deposition techniques to control the size and shape of void spacers formed, thereby optimizing void spacer formation for a target application field using a "pinch-off" deposition technique. The exemplary pinch-off deposition methods described herein for forming void spacers result in improved TDDB reliability and optimal capacitance reduction in the BEOL and MOL layers of semiconductor integrated circuit devices.

[0012] It should be understood that the various layers, structures, and regions shown in the accompanying drawings are schematically illustrated and not necessarily drawn to scale. Further, for ease of explanation, in a given figure, one or more types of layers, structures, and regions commonly used to form a semiconductor device or structure may not be explicitly illustrated. However, even if there are layers, structures, and regions that are not explicitly illustrated, it does not mean that they are omitted in an actual semiconductor structure.

[0013] Furthermore, it should be understood that the embodiments described herein are not limited to the specific materials, features, and processing steps illustrated and described herein. In particular, with respect to semiconductor processing steps, it is emphasized that the description provided herein is not intended to encompass all processing steps that may be required to form a practical semiconductor integrated circuit device. Rather, specific processing steps commonly used in forming semiconductor devices, such as wet cleaning steps and annealing steps, are not described herein in order to avoid unnecessary description.

[0014] Furthermore, throughout all drawings, the same or similar features, elements, or structures are referred to by the same or similar reference numbers; therefore, detailed descriptions of these same or similar features, elements, or structures are not repeated in each drawing. It should be understood that the terms “approximately” or “substantially” used herein in relation to thickness, width, proportion, range, etc., do not mean exactly that, but rather that they are close or approximate. For example, the terms “approximately” or “substantially” as used herein mean that there is a small margin of error, such as less than 1% of the quantity described.

[0015] Figures 1 and 2 are schematic diagrams showing a semiconductor device 100 comprising a gap spacer integrally formed within the BEOL structure of the semiconductor device according to an embodiment of the present invention. Figure 1 is a schematic cross-sectional view of the semiconductor device 100 taken along line 1A-1A in Figure 2, and Figure 2 is a schematic plan view of the semiconductor device 100 along a plane containing line 1B-1B shown in Figure 1. More specifically, Figure 1 is a schematic cross-sectional view of the semiconductor device 100 in the XZ plane, and Figure 2 is a plan view showing the layout of various elements in the XY plane, indicated in the XYZ Cartesian coordinates shown in Figures 1 and 2. The terms “vertical” or “vertical direction” as used herein refer to the Z direction of the Cartesian coordinates shown in the drawings, and the terms “horizontal” or “horizontal direction” as used herein refer to the X direction or the Y direction or both of the Cartesian coordinates shown in the drawings.

[0016] In particular, Figure 1 schematically shows a semiconductor device 100 comprising a substrate 110, a FEOL / MOL structure 120, and a BEOL structure 130. In one embodiment, the substrate 110 includes a bulk semiconductor substrate composed of other types of semiconductor substrate materials commonly used in bulk semiconductor fabrication processes, such as silicon, or germanium, silicon-germanium alloy, silicon carbide, silicon-germanium-carbide alloy, or compound semiconductor materials (e.g., III-V and II-VI). Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide. The thickness of the substrate 110 varies depending on the application field. In another embodiment, the substrate 110 is a silicon-on-insulator (SOI) substrate comprising an insulating layer (e.g., an oxide layer) disposed between a base semiconductor substrate (e.g., a silicon substrate) and an active semiconductor layer (e.g., an active silicon layer) in which active circuit components (e.g., field-effect transistors) are formed as part of the FEOL layer.

[0017] In particular, the FEOL / MOL structure 120 comprises a FEOL layer formed on a substrate 110. The FEOL layer comprises various semiconductor devices and components formed in or on the active surface of the semiconductor substrate 110 to form an integrated circuit for the target application field. For example, the FEOL layer comprises FET devices (FinFET devices, planar MOSFET devices, etc.), bipolar transistors, diodes, capacitors, inductors, resistors, isolation devices, etc., formed in or on the active surface of the semiconductor substrate 110. Generally, the FEOL process typically includes preparing the substrate 110 (or wafer), forming isolation structures (e.g., shallow trench isolation), forming device wells, patterning gate structures, forming spacers, forming source / drain regions (e.g., by injection), forming silicide contacts on the source / drain regions, and forming stress liners.

[0018] The FEOL / MOL structure 120 further comprises a MOL layer formed on the FEOL layer. Generally, the MOL layer comprises a PMD (premetal dielectric) layer and conductive contacts (e.g., via contacts) formed within the PMD layer. The PMD layer is formed on the components and devices of the FEOL layer. A pattern of openings is formed in the PMD layer, and these openings are filled with a conductive material such as tungsten to form conductive via contacts that electrically contact the device terminals (e.g., source / drain regions, gate contacts, etc.) of the integrated circuit of the FEOL layer. The conductive via contacts of the MOL layer provide an electrical connection between the integrated circuit of the FEOL layer and the first metallization level of the FEOL structure 130.

[0019] The BEOL structure 130 is formed on the FEOL / MOL structure 120 to connect various integrated circuit components of the FEOL layer. As is known in the art, a BEOL structure comprises multiple levels of dielectric material and multiple levels of metallization embedded in the dielectric material. The metallization of the BEOL includes horizontal wiring, interconnects, pads, and vertical wiring in the form of conductive vias that form connections between different interconnection levels of the BEOL structure. The BEOL fabrication process involves the continuous deposition and patterning of multiple layers of dielectric and metallic material to form a network of electrical connections between FEOL devices and to provide I / O connections with external components.

[0020] In the exemplary embodiment shown in Figure 1, the BEOL structure 130 includes a first interconnection level 140 and a second interconnection level 150. The first interconnection level 140, although schematically illustrated, may include one or more low-k-level inter-dielectric (ILD) layers and metal via and wiring levels (e.g., copper damascene structures). A capping layer 148 is formed between the first interconnection level 140 and the second interconnection level 150. The capping layer 148 serves to insulate the metallization of the first interconnection level 140 from the dielectric material of the ILD layer 151. For example, the capping layer 148 improves the reliability of the interconnection and prevents copper metallization from diffusing from the ILD layer 151 of the second interconnection level 150. The capping layer 148 may include any suitable insulating or dielectric material, but is not limited to, silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon carbide hydride (SiCH), or multilayer stacks containing the same or different dielectric materials. The capping layer 148 can be deposited using standard deposition techniques, such as chemical vapor deposition. The capping layer 148 can be formed with a thickness ranging from about 2 nm to about 60 nm.

[0021] The second interconnection level 150 comprises an ILD layer 151 and a metal wiring layer 152 formed within the ILD layer 151. The ILD layer 151 can be formed using any suitable dielectric material, including, but not limited to, silicon oxide (e.g., SiO2), SiN (e.g., (Si3N4)), silicon carbonate hydride (SiCOH), silicon-based low-k dielectrics, porous dielectrics, or other known ULK (ultra-low-k) dielectric materials. The ILD layer 151 can be deposited using known deposition techniques, such as ALD (atomic layer deposition), CVD (chemical vapor deposition), PECVD (plasma chemical vapor deposition), or PVD (physical vapor deposition). The thickness of the ILD layer 151 varies depending on the application and can range, for example, from about 30 nm to about 200 nm.

[0022] The metal wiring layer 152 comprises several adjacent metal wires 152-1, 152-2, 152-3, 152-4, 152-5, and 152-6, which are formed by filling patterned trenches / openings within the ILD layer 151 with a metallic material. The trenches / openings are backed with a conformal liner layer 153, which acts as a barrier diffusion layer to prevent the metallic material (e.g., Cu) from migrating into the ILD layer 151, as well as an adhesive layer to provide good adhesion to the metallic material (e.g., Cu) used to fill the trenches / openings in the ILD layer 151 and form the metal wires 152-1, ... 152-6.

[0023] As further shown in Figure 1, the second interconnection level 150 further comprises protective caps 154 selectively formed on the upper surfaces of metal wires 152-1, 152-2, 152-3, 152-4, 152-5, and 152-6, conformal insulating liners 155 conformally covering the metal wiring layer 152, and dielectric capping layers 156 deposited using a pinch-off deposition technique to form gap spacers 158 between the metal wires 152-1, 152-2, 152-3, 152-4, 152-5, and 152-6. The protective caps 154 and conformal insulating liners 155 serve to protect the metal wiring 152 from potential structural damage or contamination that may occur due to subsequent processing steps and environmental conditions. Exemplary materials and methods for forming the protective caps 154 and conformal insulating liners 155 are described in further detail below with reference to Figures 9 to 11.

[0024] The void spacers 158 are formed in the spaces between metal wires 152-1, 152-2, 152-3, 152-4, 152-5, and 152-6 of the metal wiring layer 152, as a means of reducing parasitic capacitive coupling between adjacent metal wires of the metal wiring layer 152. As will be described in more detail below, a dielectric void integration process is performed as part of the BEOL fabrication process to remove a portion of the dielectric material of the ILD layer 151 by etching to form spaces between the metal wires 152-1, 152-2, 152-3, 152-4, 152-5, and 152-6 of the wiring layer 152. A dielectric capping layer 156 is formed using a non-conformal deposition process (e.g., chemical vapor deposition) to deposit dielectric material that forms a "pinch-off" region 156-1 above the upper portion of the spaces between the metal wires of the wiring layer 152, thereby forming the void spacers 158. As shown in Figure 1, in one embodiment of the present invention, the pinch-off region 156-1 is formed above the upper surface of the metal wires 152-1, ..., 152-6 of the metal wiring layer 152, as indicated by the dashed line 1B-1B. In connection therewith, the gap spacers 158 formed between the metal wires 152-1, ..., 152-6 extend perpendicularly into the dielectric capping layer 156 above the metal wires 152-1, ..., 152-6.

[0025] Furthermore, in one embodiment of the present invention, as shown in Figure 2, the gap spacers 158 formed between metal wires 152-1, ..., 152-6 extend horizontally (e.g., in the Y direction) beyond the ends of adjacent metal wires. In particular, Figure 2 shows an exemplary comb-to-comb interlocking layout pattern of the metal wiring layer 152. In this layout pattern, metal wires 152-1, 152-3, and 152-5 are each connected at one end to elongated metal wire 152-7, and metal wires 152-2, 152-4, and 152-6 are each connected at one end to elongated metal wire 152-8. As shown in Figure 2, the gap spacers 158 extend horizontally beyond the open (unconnected) ends of metal wires 152-1, ..., 152-6. Compared to conventional gap structures, the size and shape of the gap spacers 158 shown in Figures 1 and 2 result in improved TDDB reliability and reduced capacitive coupling between metal wires. The reasons for this will be explained in more detail next, with reference to Figures 3 and 4.

[0026] Figures 3 and 4 schematically illustrate the improved TDDB reliability and reduced capacitive coupling between metal wires in the BEOL structure achieved by using the void structure formed using pinch-off deposition according to embodiments of the present invention, compared to void structures formed using conventional methods. In particular, Figure 3 schematically shows a portion of the metal wiring layer 152 of Figure 1, including metal wires 152-1 and 152-2 and voids 158 formed between these metal wires by forming a dielectric capping layer 156 using the pinch-off deposition process according to embodiments of the present invention. As shown in Figure 3, metal wire 152-1 and its associated liner 153 and metal wire 152-2 and its associated liner 153 are formed to have a width W and are spaced apart by a distance S. Furthermore, Figure 4 schematically shows a semiconductor structure that, similar to Figure 3, features a gap 168 positioned between two identical metal wires 152-1 and 152-2 having the same width W and spacing S, but where the gap 168 is formed by creating a dielectric capping layer 166 using a conventional pinch-off deposition process.

[0027] As shown in Figure 3, the "pinch-off" region 156-1 is formed within the dielectric capping layer 156, and the void 158 extends above the upper surfaces of the metal wires 152-1 and 152-2. In contrast, as shown in Figure 4, in the conventional pinch-off deposition process, the pinch-off region 166-1 is formed within the dielectric capping layer 166 below the upper surfaces of the metal wires 152-1 and 152-2, and the resulting void 168 does not extend above the metal wires 152-1 and 152-2. Furthermore, for comparison, as shown in Figures 3 and 4, the amount of dielectric material deposited on the side walls and bottom surfaces of the space between metal wires 152-1 and 152-2, as shown in Figure 4, using the conventional pinch-off deposition process is considerably larger than the amount of dielectric material deposited on the side walls and bottom surfaces of the space between metal wires 152-1 and 152-2, as shown in Figure 3, using the pinch-off deposition process according to an embodiment of the present invention. As a result, the volume V1 of the resulting void 158 shown in Figure 3 is considerably larger than the volume V2 of the resulting void 168 shown in Figure 4.

[0028] Compared to the conventional structure shown in Figure 4, the structure in Figure 3 has several advantages. For example, because the volume V1 of the void 158 is large (less dielectric material is deposited in the space between the metal wires), the parasitic capacitance between metal wires 152-1 and 152-2 is smaller (compared to the structure in Figure 4). In fact, in the space between metal wires 152-1 and 152-2 in Figure 3, there is less dielectric material and the volume V1 of air (k=1) is large, so the effective dielectric constant in the space between metal wires 152-1 and 152-2 in Figure 3 is lower compared to Figure 4.

[0029] Furthermore, the structure in Figure 3 provides improved TDDB reliability compared to the structure in Figure 4. In particular, as shown in Figure 3, since the void 158 extends above the metal wires 152-1 and 152-2, there is a long diffusion / conductivity path P1 between the critical interface of metal wire 152-1 and the critical interface of metal wire 152-2 (the critical interface is the interface between the dielectric capping layer 156 and the upper surfaces of metal wires 152-1 and 152-2). This is in contrast to the short diffusion / conductivity path P2 in the dielectric capping layer 166 between the critical interface of metal wire 152-1 and the critical interface of metal wire 152-2 in the structure shown in Figure 4. If a TDDB failure mechanism occurs in the structure of Figure 3 or Figure 4, it is caused by the breakdown of the dielectric material and the formation of a conductive path in the dielectric material between the upper surface of metal wire 152-1 and the upper surface of metal wire 152-2 due to electron tunneling current. The long diffusion path P1 in the structure shown in Figure 3, when used in conjunction with an optionally selected dense dielectric liner 155 material having excellent dielectric breakdown strength, will result in improved TDDB reliability for the structure in Figure 3 compared to the structure shown in Figure 4.

[0030] Furthermore, as shown in Figure 2, the fact that the gap spacer 158 extends horizontally beyond the end of the metal wire further improves TDDB reliability and reduces capacitive coupling for the same reasons as described with reference to Figure 3. In particular, as shown in Figure 2, the fact that the gap 158 extends beyond the end of, for example, metal wire 152-1, creates a long diffusion / conductive path between metal wire 152-1 and the critical interface at the open end of the adjacent metal wire 152-2. In an alternative embodiment of Figure 2, gap spacers can also be formed between elongated metal wire 152-8 and the adjacent open ends of metal wires 152-1, 152-3, and 152-5, and between elongated metal wire 152-7 and the adjacent open ends of metal wires 152-2, 152-4, and 152-6, thereby further optimizing TDDB reliability and reducing capacitive coupling between the interlocking comb structures.

[0031] Figure 5 is a schematic cross-sectional view showing a semiconductor device comprising a gap spacer integrally formed within the BEOL structure of the semiconductor device according to another embodiment of the present invention. In particular, Figure 5 schematically shows a semiconductor device 100' having a structure similar to the semiconductor device 100 shown in Figures 1 / 2. However, the gap spacer 158 shown in Figure 5 does not extend beyond the bottom surface of the metal wires of the metal wiring layer 152. In this structure, the ILD layer 151 is recessed to the height of the bottom of the metal wires (compared to recessing below the bottom of the metal wires as shown in Figure 10, forming a long gap spacer as shown in Figure 1). In other embodiments of the present invention, Figures 1 and 5 show a BEOL structure 130 having first and second interconnection levels 140 and 150, but the BEOL structure 130 may also have one or more additional interconnection levels formed above the second interconnection level 150. Such additional interconnection levels can be formed to comprise gap spacers using the techniques and materials described herein.

[0032] Next, with reference to Figures 6 to 12, which schematically show semiconductor devices 100 at various fabrication stages, the method for fabricating the semiconductor device 100 of Figure 1 (and Figure 5) will be described in more detail. For example, Figure 6 is a schematic cross-sectional view showing a semiconductor device 100 in an intermediate fabrication stage according to an embodiment of the present invention, in which a pattern of openings 151-1 (e.g., damascene openings including trenches and via openings) is formed in the ILD layer 151. In particular, Figure 6 schematically shows the semiconductor device 100 of Figure 1 in an intermediate fabrication stage after the FEOL / MOL structure 120, first interconnection level 140, capping layer 148, and ILD layer 151 are sequentially formed on a substrate 110, and the ILD layer 151 is patterned to form openings 151-1 in the ILD layer 151. After depositing the ILD layer 151, standard photolithography and etching processes can be performed to etch the openings 151-1 of the ILD layer 151, and then these openings 151-1 can be filled with metallic material to form the metallic wiring layer 152 shown in Figure 1. Note that although vertical vias are not shown within the ILD layer 151, vertical vias exist within the second interconnection level 150, providing a vertical connection to the metallization of the underlying interconnection level 140.

[0033] In Figure 6, the opening 151-1 is shown having a width W and being spaced apart by a distance S. In one embodiment of the present invention, in a situation where a gap spacer is formed between adjacent metal wires using a pinch-off deposition method, the width W of the opening (in which the metal wires are formed) can be in the range of about 2 nm to about 25 nm, with a preferred range of about 6 nm to about 10 nm. Furthermore, in one embodiment, the spacing S between the metal wires can be in the range of about 2 nm to about 25 nm, with a preferred range of about 6 nm to about 10 nm.

[0034] The next process module of the exemplary fabrication process includes forming the metal wiring layer 152 shown in Figure 1 using the process flow schematically shown in Figures 7 and 8. In particular, Figure 7 is a schematic cross-sectional view showing the semiconductor device of Figure 6 after depositing a conformal layer 153A of liner material and depositing a layer 152A of metal material on top of the conformal layer 153A of liner material to fill the openings 151-1 of the ILD layer 151. Furthermore, Figure 8 is a schematic cross-sectional view showing the semiconductor device of Figure 7 after planarizing the surface of the semiconductor structure to the ILD layer 151 to form the metal wiring layer 152. The metal wiring layer 152 can be formed using known materials and known techniques.

[0035] For example, the conformal layer 153A of the liner material is preferably deposited so as to back the sidewalls and bottom surface of the opening 151-1 of the ILD layer 151 with a thin liner layer. This thin liner layer can be formed by conformally depositing one or more thin layers of materials such as tantalum nitride (TaN), cobalt (Co), ruthenium (Ru), manganese (Mn) or manganese nitride (MnN), or other liner materials suitable for a given application field (or combinations of liner materials such as Ta / TaN, TiN, CoWP, NiMoP, NiMoB). This thin liner layer serves multiple purposes. For example, this thin liner layer functions as a diffusion barrier layer that prevents the movement / diffusion of metallic material (e.g., Cu) into the ILD layer 151. Furthermore, this thin liner layer functions as an adhesive layer that provides good adhesion of the metallic material (e.g., Cu) used to fill the opening 151-1 of the ILD layer 151 to layer 152A.

[0036] In one embodiment, the metallic material layer 152A includes a metallic material such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), or ruthenium (Ru), deposited using known techniques such as electroplating, electroless plating, CVD, PVD, or a combination thereof. Optionally, a thin seed layer (e.g., a Cu seed layer) may be deposited (on the conformal liner layer 153A) using a suitable deposition technique such as ALD, CVD, or PVD before filling the openings 151-1 of the ILD layer 151 with a conductive material. The seed layer may consist of a material that improves adhesion between the metallic material and the underlying material and acts as a catalytic material during the subsequent plating process. For example, a Cu metallization layer 152 may also be formed by depositing a thin conformal Cu seed layer on the surface of the substrate using PVD, and then electroplating Cu to fill the openings 151-1 (e.g., trenches and vias) formed in the ILD layer 151. Next, a chemical mechanical polishing (CMP) process is performed to remove excess liner, seed, and metallization materials, and the surface of the semiconductor structure is planarized down to the ILD layer 151 to obtain the intermediate structure shown in Figure 8.

[0037] In one embodiment of the present invention, after a CMP process, a protective layer can be formed on the exposed surfaces of the metal wires 152-1, ..., 152-6 to protect the metallization from potential damage due to subsequent processing conditions and environments. For example, Figure 9 is a schematic cross-sectional view showing the semiconductor device of Figure 8 after protective caps 154 have been formed on the metal wires 152-1, ..., 152-6 according to an embodiment of the present invention. In one embodiment, protective caps 154 can be formed using a selective Co deposition process, which selectively deposits a thin capping layer of Co on the exposed surfaces of the metal wires 152-1, ..., 152-6 for copper metallization. In other embodiments of the present invention, protective caps 154 may also be made of other materials, such as tantalum (Ta) or ruthenium (Ru). The protective caps 154 on the metal wires 152-1, ..., 152-6 are an optional mechanism that can be used as desired to allow for harsher etching conditions, etc., when forming void spacers and other structures using the techniques described below herein.

[0038] The next step in this fabrication process involves forming a gap spacer at the second interconnection level 150 using the process flow schematically shown in Figures 10, 11, and 12. In particular, Figure 10 is a schematic cross-sectional view showing the semiconductor device of Figure 9 after etching the exposed portion of the ILD layer 151 to form a space 151-2 between the metal wires 152-1, ..., 152-6, according to an embodiment of the present invention. In one embodiment, a portion of the ILD layer 151 can be recessed to form the space 151-2, as shown in Figure 10, using any suitable masking technique (e.g., a photoresist mask) and etching technique (e.g., RIE (reactive ion etching)). For example, in one embodiment, the dielectric material of the ILD layer 151 can be removed to form the space 151-2 using a dry etching technique with a fluorine-based etching solution. In one embodiment, the space 151-2 is formed such that the recessed surface of the ILD layer 151 is below the bottom surface of the metal wires 152-1, ..., 152-6, as shown in Figure 10. In another embodiment, the etching process can be carried out such that the space 151-2 is recessed to the height of the bottom surface of the metal wiring 152 (see Figure 5). Since the interwire capacitance between widely spaced metal wires can be assumed to be negligible, the ILD layer 151 is not removed in the region of the metal wiring 152 where the metal wires are relatively widely spaced.

[0039] The next step in this process involves depositing a conformal layer of insulating material on the semiconductor structure of Figure 8 to form a conformal insulating liner 155 as shown in Figure 11. The conformal insulating liner 155 is an optional protective mechanism and may also be formed before the pinch-off volumetric process to provide additional protection to the exposed surfaces of the ILD layer 151 and the metal wiring layer 152. For example, in the exemplary embodiment of Figure 11, the conformal liner layer 153 provides some protection to the sidewalls of the metal wires 152-1, ..., 152-6, but when the metal wires are made of copper and the liner layer 153 is insufficient to prevent the diffusion of oxygen from the subsequently formed void spacer 158 to the metal wires, the conformal insulating liner 155 can provide additional protection against oxidation of the metal wires 152-1, ..., 152-6. In practice, although the void spacer 158 is later formed to have a nearly vacuum environment, some oxygen is still present within the void spacer 158, and if the liner layer 153 allows residual oxygen in the void spacer 158 to diffuse through the liner layer 153 into the metal wire, this can lead to oxidation of the copper metal wire.

[0040] Furthermore, the conformal insulating liner 155 can be formed comprising one or more robust ultrathin dielectric material layers that have desirable electrical and mechanical properties such as low leakage, high dielectric breakdown, and hydrophobicity, and that require less damage in subsequent semiconductor processing steps. For example, the conformal insulating liner 155 can be composed of dielectric materials such as SiN, SiCN, SiNO, SiCNO, SiBN, SiCBN, SiC, or other dielectric materials having the desired electrical / mechanical properties described above. In one embodiment, the conformal insulating liner 155 is formed with a thickness ranging from about 0.5 nm to about 5 nm. The conformal insulating liner 155 can also be composed of multiple conformal layers of the same or different dielectric materials deposited using a periodic deposition process. For example, in one embodiment, the conformal insulating liner 155 can be composed of multiple thin conformal layers of SiN (e.g., SiN layers with a thickness of 0.1 nm to 0.2 nm) that are sequentially deposited to form a SiN liner layer with a desired overall thickness.

[0041] As shown in Figure 11, after the conformal insulating liner 155 is formed, the spaces 151-2 between the metal wires of the metal wiring layer 152 are shown to have an initial volume Vi. In particular, in one embodiment of forming the conformal insulating liner 155, this volume Vi is defined by the side walls and bottom surface of the conformal insulating liner 155 and the dashed line L indicating the upper surface of the conformal insulating liner 155 on the metal wiring layer 152. In another embodiment of the present invention, when the conformal insulating liner 155 is not formed, the initial volume Vi is defined by the exposed surface of the liner layer 153, the recessed surface of the ILD layer 151, and the upper surface of the metal wires of the metal wiring layer 152. As described below, after forming the void spacer 158 using the pinch-off deposition process according to embodiments of the present invention, a considerable portion of the initial volume Vi remains in the spaces 151-2 between the metal wires.

[0042] The next step in this fabrication process involves depositing dielectric material on the semiconductor structure of Figure 11 using a pinch-off deposition process to form void spacers 158 in the spaces 151-2 between the metal wires of the metal wiring layer 152. For example, Figure 12 schematically illustrates the process of depositing a layer 156A of dielectric material using a non-conformal deposition process (e.g., PECVD or PVD) that initiates the formation of pinch-off regions within the deposited dielectric material 156A on the spaces 151-2 between the metal wires of the metal wiring layer 152, according to an embodiment of the present invention. Figure 1 shows the semiconductor device 100 after the pinch-off deposition process is completed to form the dielectric capping layer 156 so that it has pinch-off regions 156-1 within the dielectric capping layer and void spacers 158 formed in the spaces 151-2 between the metal wires of the metal wiring layer 152.

[0043] According to embodiments of the present invention, the structural characteristics (e.g., size, shape, volume, etc.) of the void spacer formed by the pinch-off volume can be controlled based on, for example, (i) the type of dielectric material used to form the dielectric capping layer 156, or (ii) the deposition process and associated deposition parameters used to perform pinch-off deposition (e.g., gas flow rate, RF power, pressure, deposition rate, etc.), or both. For example, in one embodiment of the present invention, the capping layer 158 is formed by PECVD deposition of a low-k dielectric material (e.g., k in the range of about 2.0 to about 5.0). Examples of such low-k dielectric materials, but not limited to these, include SiCOH, porous p-SiCOH, SiCN, carbon-rich SiCNH, p-SiCNH, SiN, and SiC. SiCOH dielectric materials have a dielectric constant k=2.7, and porous SiCOH materials have a dielectric constant of about 2.3 to 2.4. In one exemplary embodiment of the present invention, the pinch-off deposition process is carried out by depositing a SiCN dielectric film by a plasma CVD deposition process using an industrial parallel-plate single-wafer 300 mm CVD apparatus with deposition parameters of trimethylsilane (200 to 500 standard cubic centimeters per minute (sccm)) and ammonia (300 to 800 sccm) as gases, an RF power of 300 to 600 watts, a pressure of 2 to 6 Torr, and a deposition rate of 0.5 to 5 nm / second.

[0044] Furthermore, by controlling the conformability level of the dielectric material deposited by PECVD, it is possible to achieve "pinch-off" of the dielectric capping layer above or below the surface of adjacent metal wires. The term "conformability level" of an insulating / dielectric film deposited on a trench with an aspect ratio R (R = trench depth / trench opening) of 2 is defined herein as the ratio of the thickness of the insulating / dielectric film deposited on the sidewall in the middle of the trench to the thickness of the insulating / dielectric film at the top of the trench location. For example, if the conformability level of an insulating / dielectric film with a thickness of 3 nm deposited on a trench structure with an opening of 12 nm and a depth of 24 nm (aspect ratio 2) is 33%, then the thickness will be approximately 1 nm on the sidewall in the middle of the trench and approximately 3 nm at the top of the trench (conformability level = 1 nm / 3 nm ~ 33%).

[0045] For example, if the conformability level is approximately 40% or less, the "pinch-off" region 156-1 shown in Figure 1 is formed within the dielectric capping layer 156 above the metal wires of the metal wiring layer 152. This results in the formation of a gap spacer 158 that extends above the metal wires of the metal wiring layer 152. On the other hand, if the conformability level is greater than approximately 40%, the "pinch-off" region is formed within the dielectric capping layer below the upper surface of the metal wires of the metal wiring layer 152. This results in the formation of a gap spacer that does not extend above the metal wires of the metal wiring layer 152.

[0046] Depending on the given application field and the dimensions of the void / air spacer structure, the target level of conformability of the dielectric material deposited by PECVD can be achieved by adjusting the parameters of the deposition process. For example, with PECVD dielectric materials such as SiN, SiCN, SiCOH, porous p-SiCOH, and other ULK dielectric materials, a lower level of conformability can be obtained by increasing the RF power, increasing the pressure, increasing the deposition rate (e.g., increasing the flow rate of the precursor material), or a combination thereof. When the level of conformability decreases, "pinch-off" regions are formed above the metal wires, minimizing the volume of dielectric material above the exposed sidewalls and bottom surfaces within the space 151-2, and a large-volume void spacer 158 is formed extending above the metal wires of the metal wiring layer 152, for example, as shown in Figures 1 and 5.

[0047] It should be noted that experimental BEOL test structures, such as those shown in Figures 1 and 5, have already been fabricated by forming a non-conformal capping layer (less than 40% conformability) containing ULK material (e.g., SiCOH, porous p-SiCOH) using the "pinch-off" deposition method described herein, thereby obtaining large-volume void spacers between adjacent metal wires, with these void spacers extending above the metal wires as shown in Figures 1 and 5. Furthermore, experimental results have shown that when such a non-conformal capping layer is deposited using the pinch-off method, only a very small amount of dielectric material is deposited on the sidewalls and bottom of the air space between the metal wires. In particular, experimental BEOL test structures have been fabricated in which, assuming that the space between the metal wires 151-2 has an initial volume Vi before the capping layer is formed (as shown in Figure 9), a volume of approximately nVi (where n ranges from approximately 0.70 to approximately 1.0) is obtained after forming void spacers using the non-conformal pinch-off deposition process described herein.

[0048] The dielectric constant of air is approximately 1, which is much lower than the dielectric constant of the dielectric material used to form the conformal insulating liner 155 and the dielectric capping layer 156. In this regard, the amount of dielectric material deposited in the spaces 151-2 between adjacent metal wires of the metal wiring layer 152 can be precisely controlled and minimized using the techniques described herein, thereby optimizing the electrical performance of the BEOL structure by reducing the effective dielectric constant (and thus parasitic capacitance) between adjacent metal wires of the metal wiring layer 152. Furthermore, by performing pinch-off deposition using ULK dielectric material to form a low-k dielectric capping layer 156 and a large-volume void spacer 158, the effective dielectric constant of the BEOL structure as a whole is reduced (and thus parasitic capacitance is reduced).

[0049] While the exemplary embodiments of the present invention described above illustrate the formation of a gap spacer as part of a BEOL structure, similar techniques can be applied to form a gap spacer as part of a FEOL / MOL structure to reduce parasitic coupling between adjacent FEOL / MOL structures. For example, a gap spacer can also be formed between the MOL device contacts of a FEOL / MOL structure and the metal gate structure of a vertical transistor device using techniques described in more detail below with reference to Figures 13 to 21.

[0050] Figure 13 is a schematic cross-sectional view showing a semiconductor device comprising a void spacer integrally formed within the FEOL / MOL structure of the semiconductor device according to another embodiment of the present invention. In particular, Figure 13 schematicly shows a semiconductor device 200 comprising a substrate 210 / 215 including a bulk substrate layer 210 and an insulating layer 215 (e.g., an embedded oxide layer of an SOI substrate), and a plurality of vertical transistor structures M1, M2, M3 (see Figure 14) formed on the substrate 210 / 215. The vertical transistor structures M1, M2, M3 have a standard structural framework comprising a semiconductor fin 220 (extending in the X direction along the substrate), an epitaxial growth source (S) / drain (D) region 225, and their respective metal gate structures 230-1, 230-2, 230-3. The semiconductor fins 220 function as vertical channels for vertical transistor structures M1, M2, and M3 in regions of the semiconductor fins 220 surrounded by metal gate structures 230-1, 230-2, and 230-3, respectively. The semiconductor fins 220 can be formed by etching / patterning an active silicon layer (e.g., the SOI layer of an SOI substrate) formed on the insulating layer 215. Although not shown in detail in Figure 13, the upper surface of the semiconductor fins 220 is also shown by a dashed line in Figure 13 (i.e., the channel portion of the semiconductor fins 220 is covered by gate structures 230-1, 230-2, and 230-3, and the portion of the semiconductor fins 220 extending from the gate structures is encapsulated by epitaxial material grown on the exposed surface of the semiconductor fins 220).

[0051] In one embodiment, the metal gate structures 230-1, 230-2, and 230-3 each comprise a conformal high-k metal gate stack structure formed on the vertical sidewall and top surface of the semiconductor fin 220, and a gate electrode formed on this high-k metal gate stack structure. Each conformal high-k metal gate stack structure comprises a conformal layer of gate dielectric material (e.g., a high-k dielectric material such as HfO2 or Al2O3) formed on the sidewall and top surface of the semiconductor fin 220, and a conformal layer of metal work function metal material (e.g., Zr, W, Ta, Hf, Ti, Al, Ru, Pa, TaN, TiN, etc.) formed on this conformal layer of gate dielectric material. The gate electrode material formed on the high-k metal gate stack structure includes, but is not limited to, tungsten, aluminum, or any metal or conductive material commonly used to form a gate electrode structure, as well as low-resistance conductive materials.

[0052] The epitaxial source (S) / drain (D) region 225 includes an epitaxial semiconductor material (e.g., SiGe, III-V compound semiconductor material, etc.) epitaxially grown on the exposed portion of the semiconductor fin structure 220 extending from the metal gate structure portions 230-1, 230-2, and 230-3. Multiple MOL device contacts 240 / 245 are formed as part of the MOL layer of the semiconductor device 200 to form perpendicular contacts to the source / drain region 225. Each MOL device contact 240 / 245 includes a liner / barrier layer 240 and a conductive via 245.

[0053] As further shown in Figure 13, the metal gate structures 230-1, 230-2, and 230-3 are electrically insulated from the MOL contacts 240 / 245 and other surrounding structures by insulating material layers 234, 250, and 260, and a gap spacer 262. These insulating material layers include a lower sidewall spacer 234, a conformal insulating liner 250, and a dielectric capping layer 260. The lower sidewall spacer 234 electrically insulates the metal gate structures 230-1, 230-2, and 230-3 from the adjacent source / drain region 223. The conformal insulating liner 250 (having a similar composition and function to the conformal insulating liner 155 of the BEOL structure in Figure 1) conformally covers the sidewall surfaces of the MOL device contacts 240 / 245 and the metal gate structures 230-1, 230-2, and 230-3. The conformal insulating liner 250 is an optional mechanism and can be formed to protect the MOL device contacts 240 / 245 and metal gate structures 230-1, 230-2, 230-3 from potential structural damage or contamination that may occur due to subsequent processing steps and environmental conditions.

[0054] According to embodiments of the present invention, the dielectric capping layer 260 is formed by depositing a low-k dielectric material using a pinch-off deposition process to encapsulate the upper regions of the metal gate structures 230-1, 230-2, and 230-3 with the low-k dielectric material, thereby forming a gap spacer 262 between the metal gate structures and the MOL device contacts. The process flow for fabricating the gap spacer 262 is described in further detail below. As shown in Figure 13, the gap spacer 262 is relatively large and has a large volume, extending vertically above the metal gate structures 230-1, 230-2, and 230-3. For the same reasons as described above in relation to the BEOL gap spacer 158 shown in Figure 3, the size and shape of this FEOL / MOL gap spacer 262 shown in Figure 13 result in improved TDDB reliability and reduced capacitive coupling between the MOL device contacts and the metal gate structures.

[0055] For example, the large volume of the void spacer 262 reduces the effective dielectric constant of the space between the metal gate structures 230-1, 230-2, 230-3 and the MOL device contacts 240 / 245. Furthermore, as shown in Figure 13, the void spacer 262 extends above the metal gate structures 230-1, 230-2, 230-3, so there is a relatively long diffusion / conductivity path P between the critical interface of the metal gate structures 230-1, 230-2, 230-3 (the critical interface is the interface between the dielectric capping layer 260 and the upper surfaces of the metal gate structures 230-1, 230-2, 230-3) and the adjacent MOL device contacts 240 / 245. Therefore, the void spacer 262 in Figure 13 contributes to improving the TDDB reliability of the FEOL / MOL semiconductor structure.

[0056] Figure 13 further illustrates a first interconnection level of a BEOL structure formed on a FEOL / MOL layer, which comprises an ILD layer 270 and a plurality of metal wires 272 / 274 formed within the ILD layer 270, which are in electrical contact with the respective MOL device contacts 240 / 245. The metal wires 272 / 274 are formed by etching openings (e.g., trenches or vias) into the ILD layer 270 using known techniques, backing these openings with a barrier-liner layer 272, and filling these openings with a metal material 274 such as copper.

[0057] Next, with reference to Figures 14 to 21 which schematically show semiconductor devices 200 at various fabrication stages, the process flow for fabricating the semiconductor device 200 of Figure 13 will be described in more detail. First, Figure 14 is a schematic cross-sectional view showing the semiconductor device 200 at an intermediate fabrication stage, in which vertical transistor structures M1, M2, and M3 are formed on a semiconductor substrate 210 / 215. In one embodiment, the substrate 210 / 215 includes an SOI (silicon-on-insulator) substrate, and the base substrate 210 is composed of silicon, or other types of semiconductor substrate materials commonly used in bulk semiconductor fabrication processes, such as germanium, silicon-germanium alloy, silicon carbide, silicon-germanium-carbide alloy, or compound semiconductor materials (e.g., III-V and II-VI). Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide. An insulating layer 215 (e.g., an oxide layer) is deposited between the base semiconductor substrate 210 and the active semiconductor layer (e.g., an active silicon layer), and the active semiconductor layer is patterned using a known method to fabricate a semiconductor fin structure 220. Furthermore, an epitaxial source / drain region 225 can be epitaxially grown on the exposed portion of the semiconductor fin structure 220 using a known method.

[0058] As further shown in Figure 14, the metal gate structures 230-1, 230-2, and 230-3 are encapsulated in an insulating / dielectric material structure including an insulating capping layer 232 and sidewall spacers 234. The capping layer 232 and sidewall spacers 234 are fabricated using known techniques and insulating materials (e.g., SiN). The metal gate structures 230-1, 230-2, and 230-3 can be formed by an RMG (Replacement Metal Gate) process, for example, in which a dummy gate structure is first formed, then the epitaxial source / drain region 225 is formed, and then this dummy gate structure is replaced with the metal gate structures 230-1, 230-2, and 230-3 before forming the MOL device contacts. In the embodiment shown in Figure 14, it is assumed that the RMG process has already been completed, the metal gate structures 230-1, 230-2, and 230-3 have been formed, and the PMD (premetal dielectric) layer 236 has already been deposited and planarized to obtain the structure shown in Figure 14.

[0059] The PMD layer 236 is formed by depositing a layer of dielectric material on the surface of a semiconductor device and then planarizing this dielectric material up to the top surface of the capping layer 232. The PMD layer 236 can be made of any suitable insulating / dielectric material, such as silicon oxide, silicon nitride, silicon hydride carbonate, silicon-based low-k dielectrics, porous dielectrics, or organic dielectrics such as porous organic dielectrics. The PMD layer 236 can be formed by using known deposition techniques such as ALD, CVD, PECVD, spin-on deposition, or PVD, followed by a standard planarization process (e.g., CMP).

[0060] The following process module involves forming MOL device contacts using the process flow schematically shown in Figures 15, 16, and 17. In particular, Figure 15 is a schematic cross-sectional view showing the semiconductor device of Figure 14 after the PMD layer 236 has been patterned to form contact openings 236-1 between the gate structures 230-1, 230-2, and 230-3 of the vertical transistor structures M1, M2, and M3, up to the source / drain region 225. The contact openings 236-1 can be formed using known etching techniques and etching chemicals to etch the material of the PMD layer 236 against the insulating material of the capping layer 232 and the sidewall spacer 234.

[0061] Next, Figure 16 is a schematic cross-sectional view showing the semiconductor device of Figure 15 after a conformal liner layer 240A has been deposited on the surface of the semiconductor device. The conformal liner layer 240A may contain a material such as TaN that acts as a diffusion barrier layer or adhesive layer or both of the metallic material used to fill the opening 236-1 and form the MOL device contacts. Next, Figure 17 is a schematic cross-sectional view showing the semiconductor device of Figure 16 after a metallic material layer has been deposited to fill the contact opening 236-1 between the metallic gate structures 230-1, 230-2, and 230-3 with conductive material 245, and the MOL device contacts 240 / 245 have been formed by planarizing the surface of the semiconductor device to the gate capping layer 232 and removing excess liner and conductive material. The conductive material 245 may contain copper, tungsten, cobalt, aluminum, or other conductive materials suitable for use in forming vertical MOL device contacts with the source / drain regions and gate electrodes.

[0062] Although not shown in detail in Figure 17, the MOL gate contacts can be formed within openings formed in the PMD layer 236 and the capping layer 232 up to the upper surfaces of the metal gate structures 230-1, 230-2, and 230-3. As will be understood by those skilled in the art, the metal gate structures 230-1, 230-2, and 230-3 extend in the YY direction (in and out of the plane of the drawing based on the Cartesian coordinate system shown in Figure 13), and therefore the MOL gate contacts can be formed within the PMD layer 236, aligned with the extended ends of the metal gate structures 230-1, 230-2, and 230-3.

[0063] After forming the MOL device contacts, the next process module includes forming a gap spacer between the metal gate structure and the MOL device contacts using the process flow schematically shown in Figures 18 to 21. The first step of this process includes etching the gate capping layer 232 and the sidewall spacers 234. In particular, Figure 18 is a cross-sectional view showing the semiconductor device of Figure 17 after the gate capping layer 232 has been removed by etching and the sidewall spacers 234 have been recessed to the upper surface of the semiconductor fin structure 220, thereby forming a narrow space S between the sidewalls of the metal gate structures 230-1, 230-2, 230-3 and the adjacent MOL device contacts 240 / 245. In the exemplary embodiment of Figure 18, the gate capping layer 232 is shown to be completely removed by etching, but in alternative embodiments, the etching process may also be carried out so that a thin layer of the gate capping layer 232 remains on the upper surface of the metal gate structures 230-1, 230-2, 230-3 after etching.

[0064] Next, Figure 19 is a schematic cross-sectional view showing the semiconductor device of Figure 18 after a conformal layer 250A of insulating material has been deposited to form an insulating liner on the exposed surfaces of the metal gate structures 230-1, 230-2, 230-3 and the MOL device contacts 240 / 245. The conformal insulating liner layer 250A is an optional protective mechanism and can be formed before the pinch-off deposition process to provide additional protection to the exposed surfaces of the metal gate structures 230-1, 230-2, 230-3 and the MOL device contacts 240 / 245 for the same or similar reasons described above.

[0065] Furthermore, the conformal insulating liner layer 250A can consist of one or more robust ultrathin dielectric material layers that have desirable electrical and mechanical properties such as low leakage, high dielectric breakdown, and hydrophobicity, resulting in less damage during subsequent semiconductor processing steps. For example, the conformal insulating liner layer 250A can consist of dielectric materials such as SiN, SiCN, SiNO, SiCNO, SiC, or other dielectric materials having the desired electrical / mechanical properties described above. In one embodiment, when the spacing S (Figure 18) is in the range of about 4 nm to about 15 nm, the liner layer 250A on the sidewall of the adjacent structure reduces the spacing S by about 2 nm to about 4 nm by forming the conformal insulating liner layer 250A with a thickness in the range of about 1.0 nm to about 2 nm.

[0066] Similar to the BEOL embodiments described above, the conformal insulating liner layer 250A may also consist of multiple conformal layers of the same or different dielectric materials deposited using a periodic deposition process. For example, in one embodiment, the conformal insulating liner layer 250A may consist of multiple thin conformal layers of SiN deposited sequentially to form a SiN liner layer of a desired overall thickness (e.g., periodically depositing SiN layers with a thickness of 0.1 nm to 0.2 nm using a plasma CVD or CVD process with silane and NH3).

[0067] The next step in this fabrication process involves depositing a dielectric material on the semiconductor structure of Figure 19 using a pinch-off deposition process to form a gap spacer between the metal gate structure and the MOL device contacts. For example, Figure 20 is a schematic cross-sectional view showing the semiconductor device of Figure 19 after a layer 260A of dielectric material has been deposited using a non-conformal deposition process to create a pinch-off region that forms a gap spacer 262 in the narrow space between the metal gate structures 230-1, 230-2, 230-3 and the adjacent MOL device contacts 240 / 245. As described above, according to embodiments of the present invention, the structural characteristics (e.g., size, shape, volume, etc.) of the gap spacer 262 formed by pinch-off deposition can be controlled based on, for example, (i) the type of dielectric material used to form the dielectric layer 260A, or (ii) the deposition process and associated deposition parameters (e.g., gas flow rate, RF power, pressure, deposition rate, etc.) used to perform pinch-off deposition, or both.

[0068] For example, in one embodiment of the present invention, the dielectric material layer 260A is formed by PECVD deposition of a low-k dielectric material (e.g., k in the range of about 2.0 to about 5.0). Examples of such low-k dielectric materials, but not limited to these, include SiCOH, porous p-SiCOH, SiCN, SiNO, carbon-rich SiCNH, p-SiCNH, SiN, and SiC. SiCOH dielectric materials have a dielectric constant k=2.7, and porous SiCOH materials have a dielectric constant of about 2.3 to 2.4. In one exemplary embodiment of the present invention, the pinch-off deposition process is carried out by depositing a SiN dielectric film by a plasma CVD deposition process using an industrial parallel-plate single-wafer 300 mm CVD apparatus with deposition parameters of silane (100 to 500 sccm) and ammonia (200 to 1000 sccm) as gases, an RF power of 200 to 600 watts, a pressure of 1 to 8 Torr, and a deposition rate of 0.5 to 8 nm / second.

[0069] Figure 21 is a schematic cross-sectional view showing the semiconductor device of Figure 20 after the surface of the semiconductor device has been planarized down to the MOL device contacts and the ILD layer 270 has been deposited as part of the first interconnection level of the BEOL structure. The semiconductor structure of Figure 20 can be planarized using a standard CMP process, which is carried out to remove excess dielectric material 260A and a portion of the insulating liner layer 250A deposited on the MOL device contacts to obtain the structure shown in Figure 21. As shown in Figure 21, the remaining portion of the pinch-off deposited dielectric material 260A forms the metal gate structures 230-1, 230-2, 230-3 and the separated dielectric capping structure 260 on the separated insulating liner 250. Although not shown in detail in Figures 13 and 21, an additional capping layer can be formed on the planarized FEOL / MOL surface before forming the ILD layer 270 to insulate the conductive material 245 of the MOL device contacts from the dielectric material of the ILD layer 270.

[0070] An experimental test structure has already been fabricated based on the semiconductor structure schematically shown in Figure 13. In this experimental test structure, the conformal insulating liner 250 is composed of periodic SiN films with thicknesses of 1 nm, 1.5 nm, 2 nm, and 3 nm, and pinch-off deposition is performed using PECVD SiCN films and PECVD ULK films with k=2.7 and 2.4. Experimental results have shown that a large-volume void spacer (void spacer 262 schematically shown in Figure 13) extending above the metal gate structure can be obtained. Furthermore, experimental results have shown that the size, shape, and volume of the void spacer can be optimized to suit various application fields by changing the parameters or materials of the deposition process used for pinch-off deposition.

[0071] It should be understood that the method for fabricating void spacers in FEOL / MOL or BEOL layers described herein can be incorporated into various semiconductor processing flows for fabricating semiconductor devices and integrated circuits with various analog and digital or mixed-signal circuits. In particular, integrated circuit dies can be fabricated to include various devices such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, capacitors, and inductors. Integrated circuits according to the present invention can be used in applications, hardware, or electronic systems, or combinations thereof. Suitable hardware and systems for carrying out the present invention include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., mobile phones), solid-state media storage devices, and functional circuits. Systems and hardware incorporating such integrated circuits are considered to be included in the embodiments described herein. With the teachings of the present invention given herein, those skilled in the art will be able to envision other embodiments and application areas of the technology of the present invention.

[0072] While exemplary embodiments have been described herein with reference to the accompanying drawings, the present invention is not strictly limited to these embodiments, and those skilled in the art should understand that various modifications and alterations can be made without departing from the scope of the appended claims.

Claims

1. A semiconductor integrated circuit device, circuit board and The first interconnection level, A second interconnection level above the first interconnection level, The second interconnection level is A first metal wire extending in a first direction parallel to the substrate, A second metal wire adjacent to and parallel to the first metal wire and extending in the first direction, A gap spacer extending in the first direction between the first and second metal wires and perpendicular to a pinch-off region formed in the dielectric capping material above a plane including the upper surfaces of the first and second metal wires, A first self-aligning conductive protective cap on the first metal wire, A second self-aligning conductive protective cap on the second metal wire, A conformal insulating liner is positioned directly on the conductive portions of the first and second self-aligning conductive protective caps and on the opposing sides of the first and second metal wires adjacent to the gap spacer, and is continuous below the gap spacer. Equipped with, The lateral distance between the first and second metal wires is in the range of 6 nm to 10 nm. The thickness of the conformal insulating liner is in the range of 0.5 nm to less than 5 nm, and the dielectric capping material is disposed above the gap spacer and in both (i) the vertical portion of the conformal insulating liner on the opposing sides of the first and second metal wires, and (ii) the horizontal portion of the conformal insulating liner below the gap spacer. The dielectric capping material is deposited on a trench with an aspect ratio of 2. A semiconductor integrated circuit device in which the dielectric capping material is formed with a conformability level of 40% or less.

2. The semiconductor integrated circuit device according to claim 1, wherein the conformal insulating liner comprises a plurality of conformal layers.

3. The semiconductor integrated circuit device according to claim 2, wherein each of the plurality of conformal layers has a thickness in the range of 0.1 nm to 0.2 nm.

4. The semiconductor integrated circuit device according to claim 2, wherein the plurality of conformal layers include SiN.

5. The semiconductor integrated circuit device according to claim 1, wherein the conformal insulating liner includes SiCNO.

6. The semiconductor integrated circuit device according to claim 1, wherein the conformal insulating liner includes SiCBN.

7. The semiconductor integrated circuit device according to claim 1, wherein the first and second self-aligning conductive protective caps are made of Co.

8. The semiconductor integrated circuit device according to claim 1, wherein the gap spacer encloses the end of the first metal wire.

9. The semiconductor integrated circuit device according to claim 1, wherein the gap spacer extends beyond the end of the first metal wire and the end of the second metal wire.

10. The semiconductor integrated circuit device according to claim 9, wherein the gap spacer extends vertically upward from a plane including the upper surface of the first self-aligning conductive protective cap and the upper surface of the second self-aligning conductive protective cap.

11. The semiconductor integrated circuit device according to claim 9, wherein the gap spacer extends vertically downward from the plane including the bottom surface of the first metal wire and downward from the bottom surface of the second metal wire.

12. The semiconductor integrated circuit device according to claim 9, wherein the dielectric capping material includes an ultra-low k material.

13. The semiconductor integrated circuit device according to claim 12, wherein the ultra-low k material includes porous SiCOH.

14. A semiconductor integrated circuit device, circuit board and The first interconnection level, A second interconnection level above the first interconnection level, The second interconnection level is A first metal wire extending in a first direction parallel to the substrate, A second metal wire adjacent to and parallel to the first metal wire and extending in the first direction, A gap spacer positioned between the first and second metal wires and extending in the first direction, A first self-aligning conductive protective cap on the first metal wire, A second self-aligning conductive protective cap on the second metal wire, A conformal insulating liner is positioned directly on the conductive portions of the first and second self-aligning conductive protective caps and on the opposing sides of the first and second metal wires adjacent to the gap spacer, and is continuous below the gap spacer. A dielectric capping material is disposed above the gap spacer and in both (i) the vertical portion of the conformal insulating liner on the opposing sides of the first and second metal wires, and (ii) the horizontal portion of the conformal insulating liner below the gap spacer. Equipped with, The dielectric capping material is deposited on a trench with an aspect ratio of 2. The dielectric capping material is formed with a conformability level of 40% or less. The aforementioned void spacer extends perpendicularly to the pinch-off region within the dielectric capping material, A semiconductor integrated circuit device in which the pinch-off region is formed above a plane that includes the upper surface of the first self-aligning conductive protective cap and the upper surface of the second self-aligning conductive protective cap on the second metal wire.

15. The semiconductor integrated circuit device according to claim 14, wherein the lateral distance between the first and second metal wires is in the range of 6 nm to 10 nm, and the thickness of the conformal insulating liner is in the range of 0.5 nm to less than 5 nm.

16. The semiconductor integrated circuit device according to claim 14, wherein the conformal insulating liner comprises a plurality of conformal layers.

17. The semiconductor integrated circuit device according to claim 16, wherein each of the plurality of conformal layers has a thickness in the range of 0.1 nm to 0.2 nm.

18. The semiconductor integrated circuit device according to claim 16, wherein the conformal layers of the plurality of conformal layers include SiN.

19. The semiconductor integrated circuit device according to claim 14, wherein the conformal insulating liner includes SiCNO.

20. The semiconductor integrated circuit device according to claim 14, wherein the conformal insulating liner includes SiCBN.

21. The semiconductor integrated circuit device according to claim 14, wherein the first and second self-aligning conductive protective caps are made of Co.

22. The semiconductor integrated circuit device according to claim 14, wherein the air gap spacer encloses the end of the first metal wire.

23. The semiconductor integrated circuit device according to claim 14, wherein the gap spacer extends beyond the end of the first metal wire and the end of the second metal wire.

24. The semiconductor integrated circuit device according to claim 14, wherein the gap spacer extends vertically downward from a plane including the bottom surface of the first metal wire and the bottom surface of the second metal wire.

25. The semiconductor integrated circuit device according to claim 14, wherein the dielectric capping material includes an ultra-low k material.

26. The semiconductor integrated circuit device according to claim 25, wherein the ultra-low k material includes porous SiCOH.

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