Semiconductor equipment

Abstract

To suppress an increase in a chip size while suppressing restriction of a level of a voltage for controlling power supply.SOLUTION: A semiconductor device of an embodiment comprises: a first terminal; a second terminal; a third terminal; a first circuit which outputs a signal at a first level when a temperature satisfies a condition; and a second circuit which is driven by a voltage supplied via the first terminal, and electrically insulates between the second terminal and the third terminal when the first circuit outputs the signal at the first level, wherein the first circuit includes an element provided between first electric wiring and the first terminal, and outputs the signal at the first level regardless of the temperature when a first voltage is supplied to the first electric wiring.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The embodiment relates to a semiconductor device.

Background Art

[0002] There is known a semiconductor device that protects surrounding devices from excessive temperature rise by stopping power supply. Such a semiconductor device includes a test circuit for determining whether or not the power supply is normally stopped.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] Suppress an increase in chip size while suppressing a limitation on the height of a voltage for controlling power supply.

Means for Solving the Problems

[0005] The semiconductor device of the embodiment includes a first terminal, a second terminal, a third terminal, a first circuit that outputs a signal of a first level when a temperature satisfies a condition, and a second circuit that is driven by a voltage supplied through the first terminal and electrically insulates between the second terminal and the third terminal when the first circuit outputs the signal of the first level. The first circuit includes an element provided between a first wiring and the first terminal, and outputs the signal of the first level regardless of the temperature when the first voltage is supplied to the first wiring.

Brief Description of the Drawings

[0006] [Figure 1] A block diagram showing an example of the configuration of a power supply system including a semiconductor device according to the embodiment. [Figure 2] A circuit diagram illustrating an example of the configuration of a power supply circuit according to an embodiment. [Figure 3] A circuit diagram illustrating an example of the configuration of an over-temperature detection circuit and a test circuit according to an embodiment. [Figure 4] A circuit diagram illustrating an example of the configuration of an over-temperature detection circuit and a test circuit for explaining the test operation in the first operational example of the embodiment. [Figure 5] A circuit diagram illustrating an example of the configuration of an over-temperature detection circuit and a test circuit for explaining the normal operation in the first operational example of the embodiment. [Figure 6] A graph illustrating an example of the voltage with respect to the temperature of the semiconductor device and the change in the signal supplied from the over-temperature detection circuit during normal operation in the first operational example of the embodiment. [Figure 7] A circuit diagram illustrating an example of the configuration of an over-temperature detection circuit and a test circuit for explaining the normal operation in the second operating example of the embodiment. [Figure 8] A circuit diagram illustrating an example of the configuration of an over-temperature detection circuit and a test circuit according to the first modified example. [Figure 9] A circuit diagram illustrating an example of the configuration of an over-temperature detection circuit and a test circuit related to the second modified example. [Figure 10] A circuit diagram illustrating an example of the configuration of an over-temperature detection circuit and a test circuit related to the third modified example. [Figure 11] A circuit diagram illustrating an example of the configuration of an over-temperature detection circuit and a test circuit related to the fourth modified example. [Figure 12] A circuit diagram illustrating an example of the configuration of an over-temperature detection circuit and a test circuit related to the fifth modified example. [Figure 13] A circuit diagram illustrating an example of the configuration of a power supply circuit according to the sixth modified example. [Figure 14]A block diagram showing an example of the configuration of a power supply system including a semiconductor device according to the seventh modification. [Figure 15] A circuit diagram for explaining an example of the configuration of a power supply circuit and a filter circuit according to the seventh modification.

Mode for Carrying Out the Invention

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration are denoted by common reference numerals.

[0008] 1. Embodiment A semiconductor device according to an embodiment will be described.

[0009] 1.1 Configuration 1.1.1 Power Supply System The configuration of a power supply system including a semiconductor device according to an embodiment will be described with reference to FIG. 1. FIG. 1 is a block diagram showing an example of the configuration of a power supply system including a semiconductor device according to an embodiment. The power supply system includes a semiconductor device 1, a power source 2, a drive circuit 3, and a load 4.

[0010] The semiconductor device 1 is, for example, an IC (Integrated Circuit) chip. The semiconductor device 1 outputs a voltage VOUT to the load 4 based on a voltage VIN supplied from the power source 2.

[0011] The semiconductor device 1 includes terminals PGND, PVIN, PVOUT, and PVSHARE.

[0012] The terminal PGND is a ground terminal. A voltage VSS is supplied to the terminal PGND. The voltage VSS is a ground voltage. The voltage VSS is, for example, 0V.

[0013] The terminal PVIN is connected to the power source 2. A voltage VIN is supplied to the terminal PVIN from the power source 2. The voltage VIN is a voltage higher than the voltage VSS.

[0014] The terminal PVSHARE is connected to the drive circuit 3. The drive circuit 3 is an external circuit used to drive the semiconductor device 1, and a tester used to determine whether the power supply is properly shut off if the temperature of the semiconductor device 1 rises excessively. Voltage VSHARE is supplied to the terminal PVSHARE from the drive circuit 3. Voltage VSHARE is the voltage used to drive the semiconductor device 1, and the voltage used to determine whether the power supply is properly shut off.

[0015] Terminal PVOUT is connected to load 4. Voltage VOUT is supplied from terminal PVOUT to load 4.

[0016] 1.1.2 Semiconductor Equipment The configuration of the semiconductor device 1 according to this embodiment will be described further with reference to Figure 1.

[0017] The semiconductor device 1 includes a power supply circuit 101, an over-temperature detection circuit 102, and a test circuit 103.

[0018] The power supply circuit 101 is connected to the over-temperature detection circuit 102, as well as terminals PVIN, PVSHARE, PVOUT, and PGND. The power supply circuit 101 is supplied with the signal OVT from the over-temperature detection circuit 102. The power supply circuit 101 is supplied with the voltage VSHARE via terminal PVSHARE. The power supply circuit 101 is enabled when the voltage VSHARE is at the "H (High)" level. The "H" level voltage VSHARE is, for example, greater than or equal to voltage V1. In the enabled state, the power supply circuit 101 supplies the voltage VOUT based on the voltage VIN, based on the signal OVT from the over-temperature detection circuit 102. The power supply circuit 101 is disabled when the voltage VSHARE is at the "L (Low)" level. The "L" level voltage VSHARE is, for example, less than voltage V1. The power supply circuit 101, which is in a disabled state, stops supplying the voltage VOUT based on the voltage VIN, regardless of the signal OVT from the over-temperature detection circuit 102.

[0019] The over-temperature detection circuit 102 detects whether the temperature of the semiconductor device 1 is above a threshold temperature T1. The threshold temperature T1 is, for example, about 200°C. Based on this detection result, the over-temperature detection circuit 102 supplies a signal OVT to the power supply circuit 101. More specifically, if the over-temperature detection circuit 102 detects that the temperature of the semiconductor device 1 is above the threshold temperature T1, it supplies a signal OVT to the power supply circuit 101 to stop supplying the voltage VOUT based on the voltage VIN. Also, if the over-temperature detection circuit 102 detects that the temperature of the semiconductor device 1 is below the threshold temperature T1, it supplies a signal OVT to the power supply circuit 101 to supply the voltage VOUT based on the voltage VIN.

[0020] The test circuit 103 is connected to terminal PVSHARE. Based on the voltage VSHARE, the test circuit 103 controls the over-temperature detection circuit 102 to determine whether or not the over-temperature detection circuit 102 is operating normally. Hereafter, the operation to determine whether or not the over-temperature detection circuit 102 is operating normally will be referred to as the test operation. Details of the test operation will be described later.

[0021] 1.1.2.1 Configuration of the power supply circuit An example of the configuration of the power supply circuit 101 according to the embodiment will be described with reference to Figure 2. Figure 2 is a circuit diagram illustrating an example of the configuration of the power supply circuit according to the embodiment. The power supply circuit 101 in the embodiment is an LDO (Low Dropout) regulator.

[0022] The power supply circuit 101 includes a switch element Q1, resistors R1 and R2, an error amplifier AMP1, a constant voltage source VS1, and a control circuit CNT. The switch element Q1 is a P-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor).

[0023] The first end of switch element Q1 is connected to terminal PVIN. The gate of switch element Q1 is connected to error amplifier AMP1. The second end of switch element Q1 is connected to terminal PVOUT.

[0024] The first end of resistor R1 is connected to terminal PVOUT. The second end of resistor R1 is connected to node N1.

[0025] The first end of resistor R2 is connected to node N1. The second end of resistor R2 is connected to terminal PGND.

[0026] With this configuration of resistors R1 and R2, the voltage VN1 at node N1 is a voltage division of the voltage VOUT, which is based on the ratio of the resistance values ​​of resistors R1 and R2.

[0027] The first terminal of the constant voltage source VS1 is connected to the error amplifier AMP1. Voltage V2 is supplied to the error amplifier AMP1 from the first terminal of the constant voltage source VS1. The second terminal of the constant voltage source VS1 is connected to terminal PGND.

[0028] The control circuit CNT has a first terminal, a second terminal, and a third terminal. The first terminal is connected to the terminal PVSHARE. The second terminal is connected to the error amplifier AMP1. The third terminal is connected to the terminal PGND. From the second terminal of the control circuit CNT, a signal ST based on the voltage VSHARE is supplied to the error amplifier AMP1. More specifically, the control circuit CNT supplies an "H" level signal ST to the error amplifier AMP1 so that the power supply circuit 101 is enabled while the voltage VSHARE is at an "H" level. The control circuit CNT also supplies an "L" level signal ST to the error amplifier AMP1 so that the power supply circuit 101 is disabled while the voltage VSHARE is at an "L" level.

[0029] The error amplifier AMP1 has a non-inverting input terminal (+), an inverting input terminal (-), an output terminal, a first control terminal, and a second control terminal. The non-inverting input terminal (+) is connected to node N1. The inverting input terminal (-) is connected to the first terminal of the constant voltage source VS1. The output terminal is connected to the gate of the switch element Q1. The first control terminal is connected to the over-temperature detection circuit 102. The second control terminal is connected to the second terminal of the control circuit CNT. The error amplifier AMP1 turns the switch element Q1 on or off based on the signal OVT from the over-temperature detection circuit 102 and the signal ST from the control circuit CNT.

[0030] More specifically, while voltage VSHARE and signal ST are at the "H" level (while power supply circuit 101 is enabled), if signal OVT is at the "L" level, error amplifier AMP1 turns on switch element Q1 to supply a voltage VOUT higher than voltage VSS, based on voltage VIN. While power supply circuit 101 is enabled, if signal OVT is at the "H" level, error amplifier AMP1 turns off switch element Q1. Also, while voltage VSHARE and signal ST are at the "L" level (while power supply circuit 101 is disabled), error amplifier AMP1 turns off switch element Q1 regardless of signal OVT.

[0031] With the above configuration, the power supply circuit 101 supplies voltage VOUT to the load 4 based on voltage VSHARE and signal OVT.

[0032] 1.1.2.2 Configuration of Over-Temperature Detection Circuit and Test Circuit The configuration of the over-temperature detection circuit 102 and test circuit 103 according to the embodiment will be explained with reference to Figure 3. Figure 3 is a circuit diagram illustrating an example of the configuration of the over-temperature detection circuit and test circuit according to the embodiment.

[0033] The configuration of the over-temperature detection circuit 102 will now be described.

[0034] The over-temperature detection circuit 102 includes a constant current source I1, a diode D1, an operational amplifier AMP2, a resistor R3, and a constant voltage source VS2. Diode D1 is a PN junction diode.

[0035] The constant current source I1 supplies current to node N2. The constant current source I1 is driven, for example, by a voltage VIN. The current value supplied by the constant current source I1 hardly changes with respect to temperature changes in the semiconductor device 1.

[0036] The anode of diode D1 is connected to node N2. The cathode of diode D1 is grounded. Diode D1 has a negative temperature characteristic, for example, in which the forward voltage decreases with increasing temperature.

[0037] The first terminal of the constant voltage source VS2 is connected to resistor R3. A voltage V3 is supplied to resistor R3 from the first terminal of the constant voltage source VS2. The second terminal of the constant voltage source VS2 is grounded. Voltage V3 is a voltage that hardly changes with respect to temperature changes in semiconductor device 1. Voltage V3 is higher than voltage VSS.

[0038] The first end of resistor R3 is connected to the first end of the constant voltage source VS2. The second end of resistor R3 is connected to node N3. The resistance value of resistor R3 hardly changes with temperature.

[0039] The operational amplifier AMP2 has a non-inverting input terminal (+), an inverting input terminal (-), and an output terminal. The non-inverting input terminal (+) is connected to node N3. The inverting input terminal (-) is connected to node N2. The output terminal is connected to the first control terminal of the error amplifier AMP1 of the power supply circuit 101. The signal OVT is supplied from the output terminal. The operational amplifier AMP2 compares the magnitude of the voltage VN2 at node N2 (voltage at the inverting input terminal (-)) and the voltage VN3 at node N3 (voltage at the non-inverting input terminal (-)). If voltage VN3 is higher than voltage VN2, the output terminal of the operational amplifier AMP2 supplies a "H" level signal OVT. If voltage VN3 is less than or equal to voltage VN2, the output terminal of the operational amplifier AMP2 supplies a "L" level signal OVT.

[0040] With the above configuration, the over-temperature detection circuit 102 supplies a signal OVT, based on the comparison result of voltages VN2 and VN3, to the power supply circuit 101.

[0041] Furthermore, as will be described later, the over-temperature detection circuit 102 is configured such that, when the over-temperature detection circuit 102 and the test circuit 103 are electrically isolated, the voltage VN2 and voltage V3 are equivalent when the temperature of the semiconductor device 1 is at the threshold temperature T1.

[0042] The configuration of test circuit 103 will be described below.

[0043] The test circuit 103 includes switch elements Q2 and Q3, a resistor R4, constant voltage sources VS3 and VS4, an operational amplifier AMP3, and element E1. Switch elements Q2 and Q3 are, for example, N-type MOSFETs.

[0044] Element E1 is connected to terminal PVSHARE and node N4. Node N4 is, for example, a wire in test circuit 103. Element E1 may have a conductive state that electrically connects terminal PVSHARE and node N4, and an insulating state that electrically insulates terminal PVSHARE and node N4.

[0045] More specifically, element E1 is, for example, a conductive wiring pattern provided on a semiconductor chip. This conductor includes, for example, polysilicon. Element E1 in a conductive state forms a conductive path that electrically connects terminal PVSHARE and node N4. Element E1 is configured to melt when irradiated with laser light. This physically severs the conductive path between terminal PVSHARE and node N4. In other words, element E1 in a conductive state irreversibly changes to an insulating state when the wiring pattern melts due to laser light irradiation.

[0046] In this embodiment, element E1 irreversibly changes, for example, from a conductive state to an insulating state. However, it is not limited to this. Element E1 may also change reversibly between a conductive state and an insulating state.

[0047] The first terminal of the constant voltage source VS3 is connected to resistor R4. A voltage V4 is supplied to resistor R4 from the first terminal of the constant voltage source VS3. The second terminal of the constant voltage source VS3 is grounded.

[0048] The first end of resistor R4 is connected to the first end of the constant voltage source VS3. The second end of resistor R4 is connected to node N4. The resistance value of resistor R4 is set so that when element E1 is in a conductive state, the voltage VN4 at node N4 is equal to the voltage VSHARE.

[0049] The first terminal of the constant voltage source VS4 is connected to the operational amplifier AMP3. Voltage V5 is supplied to the operational amplifier AMP3 from the first terminal of the constant voltage source VS4. The second terminal of the constant voltage source VS4 is grounded. Voltage V5 is higher than voltage V4.

[0050] The operational amplifier AMP3 has a non-inverting input terminal (+), an inverting input terminal (-), and an output terminal. The inverting input terminal (-) is connected to the first terminal of the constant voltage source VS4. The non-inverting input terminal (+) is connected to node N4. The output terminals are connected to switch elements Q2 and Q3. The operational amplifier AMP3 compares the magnitude of the voltage V5 (voltage at the inverting input terminal (-)) supplied from the constant voltage source VS4 with the voltage VN4 (voltage at the non-inverting input terminal (-)) at node N4. If voltage VN4 is higher than voltage V5, an "H" level signal is supplied from the output terminal of the operational amplifier AMP3. If voltage VN4 is less than or equal to voltage V5, an "L" level signal is supplied from the output terminal of the operational amplifier AMP3.

[0051] The first end of switch element Q2 is connected to node N2. The gate of switch element Q2 is connected to the output terminal of operational amplifier AMP3. The second end of switch element Q2 is grounded.

[0052] A voltage VIN is supplied to the first end of the switch element Q3, for example, via terminal PVIN. The gate of the switch element Q3 is connected to the output terminal of the operational amplifier AMP3. The second end of the switch element Q3 is connected to node N3.

[0053] With the above configuration, the test circuit 103 turns on or off switch elements Q2 and Q3 based on the comparison result between the voltage VN4 at the non-inverting input terminal (+) of op-amp AMP3 and the voltage V5 at the inverting input terminal (-) of op-amp AMP3. When switch element Q2 is on, voltage VN2 becomes voltage VSS. When switch element Q3 is on, voltage VN3 becomes voltage VIN. When switch elements Q2 and Q3 are off, the over-temperature detection circuit 102 and the test circuit 103 are electrically isolated. As a result, voltage VN2 depends on the constant current source I1 and diode D1. Also, voltage VN3 depends on the constant voltage source VS2 and resistor R3.

[0054] 1.2 Operation The operation of the semiconductor device 1 according to the embodiment will now be described. The operation of the semiconductor device 1 according to the embodiment includes test operation and operation of the semiconductor device 1 after the test operation. In the following description, the operation of the semiconductor device 1 after the test operation will be simply referred to as normal operation.

[0055] Below, we will describe a first operating example in which a semiconductor device 1 including element E1, which is in an insulating state during normal operation, is used, and a second operating example in which a semiconductor device 1 including element E1, which is in a conductive state during normal operation, is used.

[0056] In the first and second operation examples, the test operation is performed using semiconductor device 1, which includes element E1 in a conductive state.

[0057] 1.2.1 First Operation Example Let's explain the first example of operation.

[0058] In the first operational example, after the test operation is performed and before normal operation, the state of element E1 changes from a conductive state to an insulating state. Then, normal operation is performed using the semiconductor device 1, which includes element E1 in the insulating state.

[0059] 1.2.1.1 Test Operation The test operation will be explained using Figure 4. Figure 4 is a circuit diagram illustrating an example of the configuration of an over-temperature detection circuit and a test circuit for explaining the test operation according to the embodiment.

[0060] The test operation is performed in an environment where, for example, the temperature of the semiconductor device 1 is equivalent to room temperature. In this embodiment, the room temperature is below the threshold temperature T1. In this embodiment, the room temperature is, for example, about 25°C.

[0061] During the test operation, the test circuit 103 supplies voltages VN2 and VN3 to the over-temperature detection circuit 102 so that it can simulate detecting that the temperature of the semiconductor device 1 is above the threshold temperature T1. If the over-temperature detection circuit 102 simulates detecting that the temperature of the semiconductor device 1 is above the threshold temperature T1, it is determined that the over-temperature detection circuit 102 is operating normally. If the over-temperature detection circuit 102 detects that the temperature of the semiconductor device 1 is below the threshold temperature T1, it is determined that the over-temperature detection circuit 102 is malfunctioning.

[0062] During the test operation, element E1 is in a conductive state. In Figure 4, element E1, which is in a conductive state, is marked with a "○". This establishes an electrical connection between node N4 and terminal PVSHARE.

[0063] During the test operation, the voltage VIN is supplied to terminal PVIN.

[0064] The voltage VSHARE is supplied to the PVSHARE terminal. During test operation, the voltage VSHARE is a "H" level voltage, higher than voltages V1 and V5.

[0065] In test circuit 103, since element E1 is in a conductive state, voltage VN4 is equivalent to voltage VSHARE. As a result, the voltage VN4 at the non-inverting input terminal (+) of op-amp AMP3 becomes higher than the voltage V5 at the inverting input terminal (-) of op-amp AMP3. Therefore, due to the action of op-amp AMP3, switch elements Q2 and Q3 are turned on. In Figure 4, switch elements Q2 and Q3, which are in the on state, are marked with a "○". Consequently, node N2 (the inverting input terminal (-) of op-amp AMP2) is grounded via switch element Q2. Also, voltage VIN is supplied to node N3 (the non-inverting input terminal (+) of op-amp AMP2) via switch element Q3.

[0066] Based on the above, when the over-temperature detection circuit 102 is operating normally, a "H" level signal OVT is supplied to the first control terminal of the error amplifier AMP1 from the output terminal of the operational amplifier AMP2. In other words, the over-temperature detection circuit 102 simulates detecting that the temperature of the semiconductor device 1 is above the threshold temperature T1.

[0067] The power supply circuit 101 is enabled based on the "H" level voltage VSHARE supplied via terminal PVSHARE. While the power supply circuit 101 is enabled, the error amplifier AMP1 outputs a voltage equivalent to, for example, voltage VIN from its output terminal based on the "H" level signal OVT. This turns off the switch element Q1. Therefore, voltage VOUT becomes equivalent to voltage VSS.

[0068] On the other hand, if the over-temperature detection circuit 102 is faulty, an "L" level signal OVT may be supplied to the first control terminal of the error amplifier AMP1 from the output terminal of the operational amplifier AMP2. In this case, the over-temperature detection circuit 102 cannot pseudo-detect that the temperature of the semiconductor device 1 is above the threshold temperature T1.

[0069] In the enabled power supply circuit 101, the error amplifier AMP1 turns on the switch element Q1 based on the “L” level signal OVT supplied from the faulty over-temperature detection circuit 102. As a result, a voltage VOUT higher than the voltage VSS is supplied from the second terminal of the switch element Q1 based on the voltage VIN.

[0070] Based on the above, in the test operation, if the voltage VOUT is equal to the voltage VSS, it is determined that the over-temperature detection circuit 102 is operating normally. Conversely, in the test operation, if the voltage VOUT is higher than, for example, the voltage VSS, it is determined that the over-temperature detection circuit 102 is malfunctioning.

[0071] The test operation is now complete.

[0072] 1.2.1.2 Normal operation Normal operation will be explained using Figures 5 and 6. Figure 5 is a circuit diagram illustrating an example of the configuration of an over-temperature detection circuit and a test circuit for explaining normal operation in the first operating example of the embodiment. Figure 6 is a graph illustrating an example of the change in voltages VN2 and VN3 with respect to the temperature of the semiconductor device 1, and the signal OVT supplied from the over-temperature detection circuit 102, during normal operation in the first operating example of the embodiment.

[0073] If the semiconductor device is determined to be functioning normally during the test operation, as described above, the state of element E1 is changed from a conductive state to an insulating state before normal operation. More specifically, element E1 on the semiconductor chip is melted by irradiation with laser light. In Figure 5, element E1 in the insulating state is marked with an "×".

[0074] When element E1 melts, the voltage VN4 in test circuit 103 becomes equivalent to the voltage V4. As a result, the operational amplifier AMP3 turns off switch elements Q2 and Q3, regardless of the voltage VSHARE. In Figure 5, switch elements Q2 and Q3, which are in the off state, are marked with an "×".

[0075] With the switch element Q2 in the off state, the voltage VN2 in the over-temperature detection circuit 102 is determined based on the diode D1 and the constant current source I1. As a result, as shown in Figure 6, the voltage VN2 decreases as the temperature of the semiconductor device 1 rises due to the negative temperature characteristic of the diode D1. Also, with the switch element Q3 in the off state, the voltage VN3 becomes equivalent to the voltage V3.

[0076] First, we will explain the operation when the power supply circuit 101 is enabled.

[0077] When the power supply circuit 101 is enabled, a voltage of the "H" level is supplied to the terminal PVSHARE.

[0078] As shown in Figure 6, when the temperature of semiconductor device 1 is below the threshold temperature T1, voltage VN2 is higher than voltage VN3. Therefore, signal OVT is at the "L" level. In the power supply circuit 101, which is in the enabled state, when signal OVT is at the "L" level, error amplifier AMP1 supplies voltage to the gate of switch element Q1 so that the voltage VN1 at the non-inverting input terminal (+) of error amplifier AMP1 and V2 at the inverting input terminal (-) of error amplifier AMP1 are equal. That is, error amplifier AMP1 supplies voltage to the gate of switch element Q1 so that voltage VOUT is equal to the target voltage VTARG. More specifically, the voltage supplied from the output terminal of error amplifier AMP1 increases as the voltage obtained by subtracting voltage V2 from voltage VN1 increases. As a result, the on-resistance of switch element Q1 increases as the voltage obtained by subtracting voltage V2 from voltage VN1 increases. Therefore, the error amplifier AMP1 is configured to output a voltage from its output terminal that is higher than the voltage output when the voltage VOUT is equal to the target voltage VTARG, when the voltage VOUT is higher than the target voltage VTARG. Also, the error amplifier AMP1 is configured to output a voltage from its output terminal that is lower than the voltage output when the voltage VOUT is equal to the target voltage VTARG, when the voltage VOUT is less than the target voltage VTARG. In this way, the error amplifier AMP1 supplies voltage to the gate of the switch element Q1 so that the load 4 receives a voltage VOUT that is equal to the target voltage VTARG.

[0079] Furthermore, when the temperature of semiconductor device 1 is above the threshold temperature T1, voltage VN2 is below voltage VN3. As a result, signal OVT is at the "H" level. In the power supply circuit 101, which is in the enabled state, when signal OVT is at the "H" level, error amplifier AMP1 turns off the switch element Q1, just as in the test operation. Therefore, the supply of voltage VOUT based on voltage VIN is stopped. In other words, voltage VOUT becomes equivalent to voltage VSS.

[0080] Next, the operation when the power supply circuit 101 is disabled will be explained.

[0081] When the power supply circuit 101 is disabled, a "L" level voltage is supplied to terminal PVSHARE. In the disabled state of the power supply circuit 101, the error amplifier AMP1 turns off the switch element Q1, regardless of the signal OVT, just as in the test operation. Therefore, regardless of the temperature of the semiconductor device 1, the supply of voltage VOUT based on voltage VIN is stopped.

[0082] The normal operation is then performed as described above.

[0083] 1.2.2 Second Operation Example Next, the operation of the semiconductor device 1 in the second operation example will be explained using Figure 7. Figure 7 is a circuit diagram illustrating an example of the configuration of an over-temperature detection circuit and a test circuit for explaining the normal operation in the second operation example of the embodiment. The test operation in the second operation example is equivalent to the test operation in the first operation example, so its explanation will be omitted. In the following, the differences between the normal operation in the second operation example and the normal operation in the first operation example will be mainly explained. Note that in the second operation example, voltage V5 is higher than voltage V1.

[0084] As described above, the normal operation in the second example is performed using a semiconductor device that includes element E1, which is in a conductive state. That is, element E1 does not melt after the test operation is performed but before the normal operation is performed.

[0085] A voltage VSHARE is applied to terminal PVSHARE. In the normal operation in the second operating example, the voltage VSHARE is greater than or equal to voltage V1 and less than voltage V5. As a result, in test circuit 103, voltage VN4 becomes less than voltage V5. Therefore, due to the operation of op-amp AMP3, as shown in Figure 7, switching elements Q2 and Q3 are always in the off state.

[0086] The operation of the power supply circuit 101 and the over-temperature detection circuit 102 in the normal operation of the second operating example is substantially the same as the operation of the power supply circuit 101 and the over-temperature detection circuit 102 in the normal operation of the first operating example, so their explanation will be omitted.

[0087] Even through the normal operation described above, the semiconductor device 1 can supply voltage VOUT to the load 4 based on the temperature of the semiconductor device 1.

[0088] 1.3 Effects of the Embodiment According to the semiconductor device 1 of this embodiment, it is possible to suppress an increase in chip size while suppressing the limitation of the voltage level for controlling the power supply.

[0089] The semiconductor device 1 of this embodiment includes terminals PVSHARE, PVIN, and PVOUT, as well as a power supply circuit 101, an over-temperature detection circuit 102, and a test circuit 103. The power supply circuit 101 is driven based on the voltage VSHARE supplied via terminal PVSHARE. The over-temperature detection circuit 102 determines whether the temperature of the semiconductor device 1 has risen excessively. In the test circuit 103, an element E1 is provided between terminal PVSHARE and node N4. Element E1 is a conductive wiring pattern that can have both conductive and insulating states. The test circuit 103 is configured to cause the over-temperature detection circuit 102 to pseudo-determine that the temperature of the semiconductor device 1 has risen excessively when the voltage VN4 at node N4 becomes voltage V5 or higher. When the over-temperature detection circuit 102 determines that the temperature of the semiconductor device 1 has risen excessively, the power supply circuit 101 electrically insulates the space between terminals PVIN and PVOUT.

[0090] In the semiconductor device 1 of this embodiment, the power supply circuit 101 and the test circuit 103 share the terminal PVSHARE. This suppresses an increase in the chip size of the semiconductor device 1. Furthermore, in the first operation example of this embodiment, after the test operation is performed, the element E1 is melted by irradiation with laser light. This electrically isolates the terminal PVSHARE from the node N4. Therefore, in normal operation, it is possible to suppress the limitation of the voltage VSHARE height due to the configuration of the test circuit 103. Thus, with the semiconductor device 1 of this embodiment, it is possible to suppress an increase in chip size while suppressing the limitation of the voltage VSHARE height supplied in normal operation.

[0091] To elaborate, if the terminals supplying the voltage for normal operation and the terminals supplying the voltage for test operation are different, the number of pads on the semiconductor chip increases. This leads to the problem of increased area of ​​the semiconductor chip. To suppress the increase in the number of pads on the semiconductor chip, it is desirable to share the terminals supplying the voltage for normal operation and the terminals supplying the voltage for test operation.

[0092] However, if the terminals supplied with voltage for normal operation and the terminals supplied with voltage for test operation are the same, the voltage level supplied to those terminals during normal operation may be limited. More specifically, if there is no configuration that allows for electrical isolation between the test circuit and the aforementioned terminals, the voltage for normal operation will also be supplied to the test circuit. Therefore, in order to prevent test operation from being performed during normal operation, the voltage range supplied to the aforementioned terminals during test operation and the voltage range supplied to the aforementioned terminals during normal operation are set so as not to overlap.

[0093] According to the embodiment, the test circuit 103 includes element E1 between terminal PVSHARE and node N4. In the first operational example of the embodiment, after the test operation and before the normal operation is performed, element E1 melts, thereby electrically isolating the test circuit 103 from the over-temperature detection circuit 102. This prevents the test operation from being performed during normal operation, even if the terminal supplied with the voltage for normal operation and the terminal supplied with the voltage for test operation are shared. Therefore, it is possible to suppress an increase in chip size while suppressing the limitation of the voltage VSHARE during normal operation.

[0094] Furthermore, with the semiconductor device 1 according to the embodiment, even if element E1 does not electrically isolate terminal PVSHARE from node N4, as in the second operation example of the embodiment, normal operation can be performed.

[0095] 2. Variant Next, a semiconductor device relating to a modified example will be described. In the following, the description of configurations and operations equivalent to those of the embodiment will be omitted, and the description will mainly focus on configurations and operations that differ from those of the embodiment.

[0096] 2.1 First Variation In the above-described embodiment, an example was shown in which element E1 is melted by irradiation with laser light, but the invention is not limited to this. Element E1 may also be configured to melt based on, for example, the current flowing through it. Below, the configuration and operation of the semiconductor device 1 according to the first modified example will be mainly described in terms of the differences from the embodiment.

[0097] The configuration of the semiconductor device 1 according to the first modified example will be explained with reference to Figure 8. Figure 8 is a circuit diagram illustrating an example of the configuration of the over-temperature detection circuit and test circuit according to the first modified example.

[0098] The test circuit 103 of the first modified example includes switch elements Q2, Q3, Q4, Q5, and Q6, resistor R4, constant voltage sources VS3 and VS4, operational amplifier AMP3, and element E1. Switch elements Q4, Q5, and Q6 are, for example, N-type MOSFETs. The configuration of switch elements Q2 and Q3, resistor R4, constant voltage sources VS3 and VS4, and operational amplifier AMP3 is equivalent to the configuration of switch elements Q2 and Q3, resistor R4, constant voltage sources VS3 and VS4, and operational amplifier AMP3 in the embodiment.

[0099] The first end of switch element Q4 is connected to terminal PVSHARE. The second end of switch element Q4 is connected to node N5. A signal S is supplied to the gate of switch element Q4. Signal S is either a "H" level or a "L" level signal. The ON voltage of switch element Q4 is higher than the "L" level signal S and less than or equal to the "H" level signal S.

[0100] The first end of switch element Q5 is connected to terminal PVIN. The second end of switch element Q5 is connected to node N5. The gate of switch element Q5 is supplied with signal / S. Signal / S is the inverted signal of signal S. The on-voltage of switch element Q5 is equivalent to, for example, the on-voltage of switch element Q4.

[0101] The first end of switch element Q6 is grounded. The second end of switch element Q6 is connected to node N4. The gate of switch element Q6 is supplied with the signal / S. The on-voltage of switch element Q6 is equivalent to, for example, the on-voltage of switch element Q4 and the on-voltage of switch element Q5.

[0102] Element E1 is connected to nodes N4 and N5. Element E1 may have a conductive state that electrically connects nodes N4 and N5, and an insulating state that electrically insulates nodes N4 and N5. The wiring pattern of element E1 is configured to melt based on the current flowing through the wiring pattern. More specifically, element E1 is configured to melt, for example, if the current flowing through element E1 is greater than or equal to a first current value over a predetermined first period. Here, the first current value is set to be greater than, for example, the current flowing through the wiring pattern during a test operation. With this configuration, element E1 is configured to irreversibly change state from a conductive state to an insulating state by physically cutting the wiring pattern between nodes N4 and N5.

[0103] The configuration of the power supply circuit 101 and the over-temperature detection circuit 102 in the first modified example is equivalent to the configuration of the power supply circuit 101 and the over-temperature detection circuit 102 in the embodiment.

[0104] The operation of the semiconductor device 1 according to the first modified example will be described.

[0105] In the test operation of the first operational example of the first modification, signal S is set to the "H" level. This causes switch element Q4 to be in the ON state. Also, signal / S is set to the "L" level. This causes switch elements Q5 and Q6 to be in the OFF state. The test operation of the first operational example of the first modification is substantially equivalent to the test operation of the first operational example of the embodiment, except for the operation of switch elements Q4, Q5, and 6.

[0106] In the first operational example of the first modification, the signal S is set to the "L" level between the test operation and normal operation. This causes the switch element Q4 to be in the off state. The signal / S is set to the "H" level. This causes the switch elements Q5 and Q6 to be in the on state. Then, a current greater than or equal to the first current value flows through element E1 via terminal PVIN for the first period. This causes element E1 to melt.

[0107] The element E1 is cut by melting, for example, in a semiconductor chip where the semiconductor device 1 is not sealed with an insulator. The element E1 may also be cut by melting in a package where the semiconductor device 1 is sealed with an insulator.

[0108] In the normal operation of the first operating example of the first modification, signal S is set to the "H" level. Also, signal / S is set to the "L" level. The normal operation of the first operating example of the first modification is substantially equivalent to the normal operation of the first operating example of the embodiment, except for the operation of switch elements Q4, Q5, and 6.

[0109] The test operation of the second operational example of the first modified example is equivalent to the test operation of the first operational example of the first modified example.

[0110] The signals S and / S supplied in the normal operation of the second operating example of the first modification are equivalent to the signals S and / S supplied in the normal operation of the first operating example of the first modification. The normal operation of the second operating example of the first modification is substantially equivalent to the normal operation of the second operating example of the embodiment, except for the operation of the switch elements Q4, Q5, and 6.

[0111] In the first modified example, the same effects as in the embodiment are achieved.

[0112] In the first modified example described above, an example was shown in which element E1 melts due to the current flowing through terminal PVIN during the test operation and normal operation of the first operating example of the first modified example. However, it is not limited to this. Element E1 may be configured to melt due to the current flowing through terminal PVSHARE. In this case, for example, a signal S is supplied to the gate of the switch element Q6.

[0113] 2.2 Second Variation In the above embodiment, the test circuit 103 was shown to include switch elements Q2 and Q3, but it is not limited to this. The test circuit 103 may include only one of the switch elements Q2 and Q3. Below, the configuration and operation of the semiconductor device according to the second modification will be mainly described in terms of the differences from the configuration and operation of the semiconductor device according to the embodiment.

[0114] The configuration of the semiconductor device 1 according to the second modified example will be explained using Figure 9. Figure 9 is a circuit diagram illustrating an example of the configuration of the over-temperature detection circuit and test circuit according to the second modified example.

[0115] The test circuit 103 shown in Figure 9 includes a switch element Q3, a resistor R4, constant voltage sources VS3 and VS4, an operational amplifier AMP3, and element E1. In other words, the test circuit 103 includes only the switch element Q3 from the switch elements Q2 and Q3 in the embodiment. The configuration of the switch element Q3, resistor R4, constant voltage sources VS3 and VS4, operational amplifier AMP3, and element E1 is equivalent to the configuration of the switch element Q3, resistor R4, constant voltage sources VS3 and VS4, operational amplifier AMP3, and element E1 in the test circuit 103 of the embodiment.

[0116] The configuration of the power supply circuit 101 and the over-temperature detection circuit 102 in the second modified example is equivalent to the configuration of the power supply circuit 101 and the over-temperature detection circuit 102 in the embodiment.

[0117] Note that while Figure 9 shows an example where the test circuit 103 includes the switch element Q3, it is not limited to this. In the second modified example, the test circuit 103 may include only the switch element Q2 among the switch elements Q2 and Q3. In this case, the test circuit 103 includes the switch element Q2, resistor R4, constant voltage sources VS3 and VS4, operational amplifier AMP3, and element E1. The configuration of the switch element Q2, resistor R4, constant voltage sources VS3 and VS4, operational amplifier AMP3, and element E1 is equivalent to the configuration of the switch element Q2, resistor R4, constant voltage sources VS3 and VS4, operational amplifier AMP3, and element E1 in the test circuit 103 of the embodiment.

[0118] The operation of the semiconductor device 1 in the second modified example is substantially equivalent to the operation of the semiconductor device 1 in the embodiment, so this description is omitted.

[0119] The second modification also produces the same effects as the embodiment.

[0120] 2.3 Third Variation In the above embodiments, the first modification, and the second modification, a case in which a wiring pattern that is cut is used as element E1 is shown, but it is not limited to this. A switch element may be used as element E1. Below, the configuration and operation of the semiconductor device according to the third modification will be mainly described in terms of the differences from the configuration and operation of the semiconductor device 1 according to the embodiment.

[0121] The configuration of the semiconductor device 1 according to the third modified example will be explained using Figure 10. Figure 10 is a circuit diagram illustrating an example of the configuration of the over-temperature detection circuit and test circuit according to the third modified example.

[0122] The test circuit 103 of the third modified example includes switch elements Q2, Q3, and Q7, resistors R4 and R5, constant voltage sources VS3 and VS4, operational amplifier AMP3, and antifuse element E2. Switch element Q7 is, for example, a P-type MOSFET. The configuration of switch elements Q2 and Q3, resistor R4, constant voltage sources VS3 and VS4, and operational amplifier AMP3 is equivalent to the configuration of switch elements Q2 and Q3, resistor R4, constant voltage sources VS3 and VS4, and operational amplifier AMP3 in the test circuit 103 of the embodiment.

[0123] The antifuse element E2 includes, for example, a first end connected to terminal PVIN and a second end connected to node N6. The antifuse element E2 changes from an insulating state, electrically insulating the first end from the second end, to a conductive state, electrically connecting the first end from the second end. More specifically, in the insulating state, the antifuse element E2 includes an insulating film that electrically insulates the first end from the second end. The antifuse element E2 is configured to change irreversibly from the insulating state to the conductive state when the insulating film is destroyed by a voltage increase between the first end and the second end. The insulating film is destroyed, for example, when a voltage above a predetermined height is supplied to the first end of the antifuse element E2. This voltage is higher than the voltage VIN during normal operation.

[0124] The first end of resistor R5 is connected to node N6. The second end of resistor R5 is grounded.

[0125] The first end of switch element Q7 is connected to PVSHARE. The gate of switch element Q7 is connected to node N6. The second end of switch element Q7 is connected to node N4. The ON state of switch element Q7 is a conductive state in which terminal PVSHARE and node N4 are electrically connected. The OFF state of switch element Q7 is an insulated state in which terminal PVSHARE and node N4 are electrically isolated. In other words, switch element Q7 is an element whose state can reversibly change between a conductive state and an insulated state. The ON voltage of switch element Q7 is, for example, a voltage lower than the voltage VIN in normal operation.

[0126] With the above configuration, if the insulating film of the antifuse element E2 is not destroyed, the voltage VSS is supplied to the gate of the switch element Q7. This causes the switch element Q7 to turn ON. If the insulating film of the antifuse element E2 is destroyed, the voltage VIN is supplied to the gate of the switch element Q7 via the antifuse element E2. As a result, when the voltage VIN, which is the voltage under normal operation, is supplied to the gate of the switch element Q7, the switch element Q7 turns OFF.

[0127] The configuration of the power supply circuit 101 and the over-temperature detection circuit 102 in the third modified example is equivalent to the configuration of the power supply circuit 101 and the over-temperature detection circuit 102 in the embodiment.

[0128] The operation of the semiconductor device 1 according to the third modified example will be described.

[0129] In the test operation of the first operational example of the third modification, the voltage VIN is set to a height that does not destroy the insulating film of the antifuse element E2. As a result, the switch element Q7 is turned on. The test operation of the first operational example of the third modification is substantially equivalent to the test operation of the first operational example of the embodiment, except that the switch element Q7 is turned on.

[0130] In the first operational example of the third modification, the insulating film of the antifuse element E2 is destroyed by the supply of voltage VIN via terminal PVIN during test operation and normal operation. As a result, voltage VIN is supplied to the gate of the switch element Q7 via the antifuse element E2.

[0131] The insulating film of the antifuse element E2 is destroyed, for example, in a semiconductor chip where the semiconductor device 1 is not sealed with an insulator, but is not limited to this. The insulating film of the antifuse element E2 may also be destroyed in a package where the semiconductor device 1 is sealed with an insulator.

[0132] In the normal operation of the first operating example of the third modification, the switch element Q7 is turned off by supplying a voltage VIN to the gate of the switch element Q7. The normal operation is substantially the same as the normal operation of the first operating example of the embodiment, except that the switch element Q7 is in the off state.

[0133] The test operation of the second operational example of the third modified example is equivalent to the test operation of the first operational example of the third modified example.

[0134] The normal operation of the second operating example of the third modification is substantially the same as the normal operation of the second operating example of the embodiment, except that the switch element Q7 is in the ON state.

[0135] The third modification also produces the same effects as the embodiment, the first modification, and the second modification.

[0136] 2.4 Fourth Variation In the third modification, the case in which the switch element Q7 is turned on or off by an insulating film breakdown type fuse element is shown, but the invention is not limited to this. The state of the switch element Q7 may be configured to be turned on or off by a non-volatile memory. Below, the configuration and operation of the semiconductor device according to the fourth modification will be mainly described in terms of the differences from the configuration and operation of the semiconductor device 1 according to the third modification.

[0137] The configuration of the semiconductor device 1 according to the fourth modified example will be explained using Figure 11. Figure 11 is a circuit diagram illustrating an example of the configuration of the over-temperature detection circuit and test circuit according to the fourth modified example.

[0138] The test circuit 103 of the fourth modified example includes switch elements Q2, Q3, and Q7, resistor R4, constant voltage sources VS3 and VS4, operational amplifier AMP3, and memory circuit M. The configuration of the switch elements Q2, Q3, and Q7, resistor R4, constant voltage sources VS3 and VS4, and operational amplifier AMP3 in the fourth modified example is equivalent to the configuration of the switch elements Q2, Q3, and Q7, resistor R4, constant voltage sources VS3 and VS4, and operational amplifier AMP3 in the test circuit 103 of the third modified example.

[0139] In the fourth modified example, the memory circuit M has a first memory cell. The first memory cell is, for example, an EEPROM. TMThis element is included in Electrically Erasable Programmable Read-Only Memory (OTP), One Time Programmable (OTP) memory, and flash memory. The first memory cell stores "0" data (indicated as ""0" in Figure 11) and "1" data (indicated as ""1" in Figure 11). The memory circuit M is configured to allow the data in the first memory cell to be rewritten, for example, by an internal or external circuit of the semiconductor device 1. When the first memory cell stores "0" data, the memory circuit M is configured to supply a voltage Von to the gate of the switch element Q7 (indicated as ""0":Von" in Figure 11). The voltage Von is a voltage lower than or equal to the on-voltage of the switch element Q7. The memory circuit M is also configured to supply a voltage Voff to the gate of the switch element Q7 when the first memory element stores "1" data (indicated as ""1":Voff" in Figure 11). The voltage Voff is a voltage higher than the on-voltage of the switch element Q7.

[0140] The operation of the semiconductor device 1 according to the fourth modified example will be described.

[0141] In the test operation of the first operational example of the fourth modification, the first memory element stores the data "0". As a result, a voltage Von is supplied to the gate of the switch element Q7. This turns the switch element Q7 into the ON state. The test operation of the first operational example of the fourth modification is substantially equivalent to the test operation of the first operational example of the third modification.

[0142] In the first operational example of the fourth modification, after the test operation and before normal operation, the data in the first memory element is rewritten from "0" data to "1" data. As a result, a voltage Voff is supplied to the gate of the switch element Q7. Therefore, in normal operation, the switch element Q7 is in the off state.

[0143] The normal operation of the first operational example of the fourth modified example is equivalent to the normal operation of the first operational example of the third modified example, except that the first memory element stores the second data.

[0144] The test operation of the second operational example of the fourth modified example is equivalent to the test operation of the first operational example of the fourth modified example.

[0145] The normal operation of the second operating example of the fourth modification is equivalent to the test operation of the second operating example of the third modification, except that the first memory element stores "0" data.

[0146] The fourth modification also produces the same effects as the embodiment and the first to third modifications.

[0147] 2.5 Fifth Variation In the embodiments described above, and in the first to fourth modifications, the power supply circuit 101 is shown to be enabled based on a "H" level voltage VSHARE and disabled based on a "L" level voltage VSHARE, but it is not limited to this. The power supply circuit 101 may be enabled based on a "L" level voltage VSHARE and disabled based on a "H" level voltage VSHARE. Below, the configuration and operation of the semiconductor device according to the fifth modification will be mainly described in terms of the differences from the configuration and operation of the semiconductor device according to the embodiment.

[0148] 2.5.1 Configuration The power supply circuit 101 according to the fifth modified example includes a switch element Q1, resistors R1 and R2, an error amplifier AMP1, a constant voltage source VS1, and a control circuit CNT. The configuration of the switch element Q1, resistors R1 and R2, error amplifier AMP1, and constant voltage source VS1 is equivalent to the configuration of the switch element Q1, resistors R1 and R2, error amplifier AMP1, and constant voltage source VS1 according to the embodiment.

[0149] In the fifth modification, the control circuit CNT supplies an "H" level signal ST to the error amplifier AMP1 so that the power supply circuit 101 is enabled while the voltage VSHARE is at an "L" level (while the voltage VSHARE is less than the voltage V1). The control circuit CNT also supplies an "L" level signal ST to the error amplifier AMP1 so that the power supply circuit 101 is disabled while the voltage VSHARE is at an "H" level.

[0150] The configuration of the over-temperature detection circuit 102 and test circuit 103 according to the fifth modified example will be explained with reference to Figure 12. Figure 12 is a circuit diagram illustrating an example of the configuration of the over-temperature detection circuit and test circuit according to the fifth modified example.

[0151] The test circuit 103 includes switch elements Q2 and Q3, a resistor R4, constant voltage sources VS3 and VS4, an operational amplifier AMP3, and element E1. The configuration of switch elements Q2 and Q3, resistor R4, constant voltage sources VS3 and VS4, and element E1 is equivalent to the configuration of switch elements Q2 and Q3, resistor R4, constant voltage sources VS3 and VS4, and element E1 in the embodiment.

[0152] In the fifth modified example, the inverting input terminal (-) of the operational amplifier AMP3 is connected to node N4. The non-inverting input terminal (+) of the operational amplifier AMP3 is connected to the first terminal of the constant voltage source VS4.

[0153] In the fifth modified example, the voltage V4 supplied from the constant voltage source VS3 is higher than the voltage V5 supplied from the constant voltage source VS4.

[0154] The configuration of the over-temperature detection circuit 102 in the fifth modified example is equivalent to the configuration of the over-temperature detection circuit 102 in the embodiment.

[0155] 2.5.2 Operation The first and second operational examples of the fifth modified form will be described, primarily highlighting the differences from the first and second operational examples of the embodiment, respectively.

[0156] 2.5.2.1 First Operation Example The differences between the test operation and normal operation of the first operation example in the fifth modified example and the test operation and normal operation of the first operation example in the embodiment will be explained.

[0157] During the test operation, the voltage VSHARE is less than the voltages V1 and V5. As a result, in test circuit 103, the operational amplifier AMP3 causes the switching elements Q2 and Q3 to turn on.

[0158] Furthermore, the power supply circuit 101 is enabled based on the "L" level voltage VSHARE.

[0159] Other operations in the test operation of the first operational example of the fifth modified example are substantially equivalent to those in the test operation of the first operational example of the embodiment, and therefore their description is omitted.

[0160] Under normal operation, when the power supply circuit 101 is enabled, a voltage of "L" level, VSHARE, is supplied to terminal PVSHARE.

[0161] Furthermore, when the power supply circuit 101 is disabled, a voltage of the "H" level, VSHARE, is supplied to the terminal PVSHARE.

[0162] The other operations in the normal operation of the first operation example of the fifth modified example are substantially equivalent to the operations in the normal operation of the first operation example of the embodiment, so their description is omitted.

[0163] 2.5.2.2 Second Operation Example The differences between the test operation and normal operation of the second operation example in the fifth modified example and the test operation and normal operation in the second operation example in the embodiment will be explained. Note that in the second operation example, voltage V1 is a higher voltage than voltage V5.

[0164] The test operation in the second operational example of the fifth modified example is equivalent to the test operation in the first operational example of the fifth modified example, so its explanation is omitted.

[0165] In normal operation, element E1 is in a conductive state, similar to the normal operation in the second operating example of the embodiment.

[0166] The voltage VSHARE supplied to terminal PVSHARE is higher than voltage V5 and lower than voltage V1. As a result, the voltage VN4 at the non-inverting input terminal (+) of op-amp AMP3 becomes higher than the voltage V5 at the inverting input terminal (-) of op-amp AMP3. Therefore, due to the action of op-amp AMP3, switching elements Q2 and Q3 are turned off.

[0167] The other operations in the normal operation of the second operation example of the fifth modified example are substantially equivalent to the operations in the normal operation of the second operation example of the embodiment, so their description is omitted.

[0168] The fifth modification also produces the same effects as the embodiment and the first to fourth modifications.

[0169] 2.6 Sixth Variation In the embodiments described above, and in the first to fifth modifications, the power supply circuit 101 is shown to be an LDO regulator, but it is not limited to this. The power supply circuit 101 may also be a load switch. Below, the configuration and operation of the semiconductor device according to the sixth modification will be mainly described in terms of the differences from the configuration and operation of the semiconductor device according to the embodiment.

[0170] The configuration of the power supply circuit 101 will be explained using Figure 13. Figure 13 is a circuit diagram illustrating an example of the configuration of a power supply circuit according to the sixth modified example.

[0171] The power supply circuit 101 includes a switch element Q1, a driver DRV, and a control circuit CNT. As described above, the power supply circuit 101 is a load switch.

[0172] The gate of the switch element Q1 is connected to the driver DRV.

[0173] The second terminal of the control circuit CNT is connected to the driver DRV. From the second terminal, the driver DRV is supplied with a signal ST based on the voltage VSHARE.

[0174] The driver DRV has a first control terminal, a second control terminal, and an output terminal. The first control terminal is connected to the over-temperature detection circuit 102. The second control terminal is connected to the second end of the control circuit CNT. The output terminal is connected to the gate of the switch element Q1. The driver DRV turns the switch element Q1 on or off based on the signal OVT from the over-temperature detection circuit 102 and the signal ST from the control circuit CNT.

[0175] More specifically, while voltage VSHARE and signal ST are at the "H" level (while the power supply circuit 101 is enabled), if signal OVT is at the "L" level, driver DRV turns on switch element Q1 to supply a voltage VOUT higher than voltage VSS, based on voltage VIN. While the power supply circuit 101 is enabled, if signal OVT is at the "H" level, driver DRV turns off switch element Q1. Also, while voltage VSHARE and signal ST are at the "L" level (while the power supply circuit 101 is disabled), driver DRV turns off switch element Q1 regardless of signal OVT.

[0176] With the above configuration, the power supply circuit 101 supplies voltage VOUT to the load 4 based on voltage VSHARE and signal OVT.

[0177] The operation of the semiconductor device 1 according to the sixth modified example is substantially equivalent to the operation of the semiconductor device according to the embodiment, so its description is omitted.

[0178] The sixth modification also produces the same effects as the embodiment and the first to fifth modifications.

[0179] 2.7 Seventh Variation In the embodiments described above, and in the first to sixth modifications, the power supply circuit 101 is shown to be an LDO regulator and a load switch, but it is not limited to this. The power supply circuit 101 may also be included in a DC-DC converter. Below, the configuration and operation of the semiconductor device according to the seventh modification will be mainly described in terms of the differences from the configuration and operation of the semiconductor device according to the embodiment.

[0180] 2.7.1 Power supply system The configuration of a power supply system including a semiconductor device according to an embodiment will be described with reference to Figure 14. Figure 14 is a block diagram showing an example of the configuration of a power supply system including a semiconductor device according to the seventh modified example. The power supply system comprises a semiconductor device 1, a power source 2, a drive circuit 3, a load 4, and a filter circuit 5.

[0181] The semiconductor device 1 includes terminals PGND, PVIN, PVSHARE, PVSW, and PFB.

[0182] Terminal PVSW is connected to filter circuit 5. Voltage VSW is supplied to filter circuit 5 from terminal PVSW. Voltage VSW is the voltage used to generate voltage VOUT. Filter circuit 5 performs a smoothing process on voltage VSW supplied from semiconductor device 1. Filter circuit 5 supplies the voltage VOUT generated by the smoothing process to load 4.

[0183] Terminal PFB is connected to filter circuit 5. Voltage VOUT is supplied to terminal PFB from filter circuit 5.

[0184] 2.7.2 Semiconductor Equipment The configuration of the semiconductor device 1 according to the seventh modified example will be explained further with reference to Figure 14.

[0185] The power supply circuit 101 is connected to the over-temperature detection circuit 102, as well as terminals PVIN, PVSHARE, PVSW, PFB, and PGND. The power supply circuit 101 is supplied with the signal OVT from the over-temperature detection circuit 102. The power supply circuit 101 is supplied with the voltage VSHARE via terminal PVSHARE. The power supply circuit 101 is enabled while the voltage VSHARE is at the "H" level. The "H" level voltage VSHARE is, for example, above voltage V1. The power supply circuit 101 is supplied with the voltage VOUT via terminal PFB. While enabled, the power supply circuit 101 supplies the voltage VSW based on voltage VIN to the filter circuit 5, based on the signal OVT from the over-temperature detection circuit 102 and the voltage VOUT from the filter circuit 5. The power supply circuit 101 is disabled while the voltage VSHARE is at the "L" level. The power supply circuit 101, which is in a disabled state, stops supplying the voltage VSW based on the voltage VIN, regardless of the signal OVT from the over-temperature detection circuit 102 and the voltage VOUT from the filter circuit 5.

[0186] The configurations of the over-temperature detection circuit 102 and the test circuit 103 are equivalent to those of the over-temperature detection circuit 102 and the test circuit 103 according to the embodiment. The configuration of the power supply circuit 101 will be mainly described below.

[0187] 2.7.3 Power supply circuit The configuration of the power supply circuit 101 and the filter circuit 5 will be explained using Figure 15. Figure 15 is a circuit diagram illustrating an example of the configuration of the power supply circuit and filter circuit according to the seventh modified example. In the seventh modified example, the power supply circuit 101 and the filter circuit 5 constitute a DC-DC converter.

[0188] The power supply circuit 101 includes switch elements Q1 and Q8, a driver DRV, and a control circuit CNT. Switch element Q8 is an N-type MOSFET.

[0189] The gate of switch element Q1 is connected to driver DRV. The second end of switch element Q1 is connected to terminal PVSW.

[0190] The first end of switch element Q8 is connected to terminal PVSW. The gate of switch element Q8 is connected to driver DRV. The second end of switch element Q8 is connected to terminal PGND.

[0191] The second terminal of the control circuit CNT is connected to the driver DRV. From the second terminal, the driver DRV is supplied with a signal ST based on the voltage VSHARE.

[0192] The driver DRV has a first control terminal, a second control terminal, a third control terminal, a first output terminal, and a second output terminal. The first control terminal is connected to the over-temperature detection circuit 102. The second control terminal is connected to the second end of the control circuit CNT. The third control terminal is connected to terminal PFB. The first output terminal is connected to the gate of switch element Q1. The second output terminal is connected to the gate of switch element Q8. Based on the signal OVT from the over-temperature detection circuit 102, the signal ST from the control circuit CNT, and the voltage VOUT, the driver DRV turns switch elements Q1 and Q8 to the ON state or the OFF state, respectively.

[0193] More specifically, while the power supply circuit 101 is enabled, if the signal OVT is at the "L" level, the driver DRV turns on switch element Q1 and off switch element Q8 during the second period. As a result, during the second period, voltage VSW becomes the voltage based on voltage VIN. During the third period, the driver DRV turns off switch element Q1 and on switch element Q8. As a result, terminal PVSW is grounded. The driver DRV supplies voltage to the gates of switch element Q1 and switch element Q8, respectively, so that the second period, third period, second period, ... are consecutive in this order. The driver DRV increases the ratio of the second period to the third period, for example, when voltage VOUT is lower than the target voltage VTARG. The driver DRV maintains the ratio of the second period to the third period, for example, when voltage VOUT is equal to the target voltage VTARG. The driver DRV reduces the ratio of the second period to the third period when, for example, the voltage VOUT is higher than the target voltage VTARG. This changes the waveform of the voltage VSW. While the power supply circuit 101 is enabled, if the signal OVT is at a "H" level, the driver DRV turns off switch element Q1 and turns on switch element Q8. Also, while the power supply circuit 101 is disabled, the driver DRV turns off switch element Q1 and turns on switch element Q8, regardless of the signal OVT.

[0194] With the above configuration, the power supply circuit 101 supplies the voltage VSW to the filter circuit 5 based on the voltages VSHARE and VOUT, and the signal OVT.

[0195] The filter circuit 5 includes an inductor L and a capacitor C.

[0196] The first end of inductor L is connected to terminal PVSW. The second end of inductor L is connected to terminal PFB. Terminal PFB is connected to load 4.

[0197] The first terminal of capacitor C is connected to terminal PFB. The second terminal of capacitor C is grounded.

[0198] With the above configuration, the filter circuit 5 smooths the waveform of the voltage VSW supplied from the semiconductor device 1. As a result, the filter circuit 5 uses the voltage VSW to generate a voltage VOUT equivalent to the target voltage VTARG.

[0199] The operation of the semiconductor device 1 according to the seventh modified example is substantially equivalent to the operation of the semiconductor device according to the embodiment, so its description is omitted.

[0200] The seventh modification also produces the same effects as the embodiment and the first to sixth modifications.

[0201] 3. Others In the above embodiments and modifications, the semiconductor device 1 is shown to include the over-temperature detection circuit 102 and the test circuit 103 as separate circuits, but it is not limited to this. In the semiconductor device 1, for example, the configuration of the over-temperature detection circuit 102 and the configuration of the test circuit 103 may be included in a single circuit.

[0202] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0203] 1...Semiconductor device, 2...Power source, 3...Drive circuit, 4...Load, 5...Filter circuit, 101...Power supply circuit, 102...Over-temperature detection circuit, 103...Test circuit, AMP1...Error amplifier, AMP2, AMP3...Operational amplifier, Q1~Q8...Switching elements, R1, R2, R3, R4, R5...Resistors, VS1, VS2, VS3, VS4...Constant voltage source, I1...Constant current source, E1...Element, E2...Anti-fuse element, D1...Diode, PVIN, PVOUT, PVSHARE, PGND, PVSW, PFB...Terminals, M...Memory circuit, DRV...Driver, L...Inductor, C...Capacitor.

Claims

1. First terminal and, The second terminal and, The third terminal and A first circuit that outputs a first-level signal when the temperature conditions are met, A second circuit is provided to electrically isolate the second terminal from the third terminal when the first circuit is driven by a voltage supplied through the first terminal and outputs the signal at the first level, Equipped with, The first circuit is, Includes an element provided between the first wiring and the first terminal, When a first voltage is supplied to the first wiring, the signal of the first level is output regardless of the temperature. The element is configured to irreversibly change from a conductive state that electrically connects the first wiring and the first terminal to an insulating state that electrically insulates the first wiring and the first terminal. The first circuit is, A first operational amplifier having a first input terminal connected to the first wiring, a second input terminal to which a second voltage is supplied, and an output terminal, The load connected to the first input terminal of the first operational amplifier, A second operational amplifier having an inverting input terminal connected to a first node, a non-inverting input terminal connected to a second node, and an output terminal that outputs the signal based on a comparison of the voltage of the first node and the voltage of the second node, A current source that supplies current to the first node, A diode having an anode connected to the first node and a grounded cathode, A first switch element having a gate connected to the output terminal of the first operational amplifier, one end to which a third voltage is applied, and the other end connected to the second node, A resistor having one end connected to the second node and the other end to which a fourth voltage is applied, Further including, Semiconductor equipment.

2. When the temperature is equal to or greater than the first temperature, the first circuit outputs the signal at the first level. The semiconductor device according to claim 1.

3. The element is a conductor that melts when laser light is shone upon it. The semiconductor device according to claim 1.

4. The element is a conductor that melts when the current value of the current flowing through the element exceeds a first current value. The semiconductor device according to claim 1.

5. The first circuit is, The device is configured to output the first level signal based on the output of the output terminal when the voltage at the first input terminal is higher than the second voltage. The semiconductor device according to any one of claims 1 to 4.

6. The first circuit is, The device is configured to output the first level signal based on the output of the output terminal when the voltage at the first input terminal is lower than the second voltage. The semiconductor device according to any one of claims 1 to 4.

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