Method, apparatus, and device for controlling the delay of a write data signal.

Abstract

The present application relates to a delay control method for a write data signal, the method includes the steps of: setting an operation mode for a register circuit in a memory by a host computer to obtain a training register supporting read / write (202); sending a sampled write data signal to the memory by the host computer (204); sampling the sampled write data signal according to the sampling signal through the memory, and caching the sampled and obtained sampled write data signal in the training register (206); if the sampled write data signal read by the host computer from the training register does not match the sampled write data signal, performing delay adjustment training for a write data delay control circuit installed on the host computer according to the sampled write data signal to obtain a trained write data delay control circuit (208); and performing signal offset adjustment for the input write data signal by the trained write data delay control circuit to obtain a target write data signal that is aligned with the sampling edge of the sampling signal and is to be written into the memory (210).

Description

Technical Field

[0001] This application relates to the technical field of computers, and particularly to a method, apparatus, device, and medium for delaying control of write data signals.

[0002] This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on May 20, 2022, with an application number of No. 2022105488270 and an invention title of "Method, Apparatus, Device, and Medium for Delaying Control of Write Data Signals", and all of its content is incorporated herein by reference.

Background Art

[0003] In a high-bandwidth internal memory system, it is possible to realize corresponding write operation control for the memory by a host computer in the high-bandwidth internal memory system transmitting a write data signal to the memory in the high-bandwidth internal memory system. However, in the process of the host computer transmitting a write data signal to the memory, the transmission of the write data signal is easily affected by factors such as environmental changes and signal crosstalk, so an offset is likely to occur between the write data signal and the sampling signal in the memory, and as a result, a sampling error situation of the write data will occur. If a sampling error of the write data occurs, an error will occur in the write operation of the host computer to the memory, and similarly, an error will occur in the data written in the memory, thereby reducing the operating stability of the memory.

Summary of the Invention

Means for Solving the Problems

[0004] Based on this, it is necessary to provide a method, apparatus, device, and medium for delaying control of write data signals for the above technical problems.

[0005] In the first aspect, the present application provides a method for controlling the delay of a write data signal, which is performed by a computer device, and the method is The host computer sets the operating mode for the register circuit in memory and acquires training registers that support read / write operations. The host computer transmits a sample write data signal to the memory, The steps include sampling the sample write data signal based on the sampling signal through the memory, and caching the sampled sample write data signal obtained in the training register, If the sampling write data signal read by the host computer from the training register does not match the sample write data signal, the host computer performs delay adjustment training on a write data delay control circuit installed on the host computer based on the sample write data signal, thereby obtaining a trained write data delay control circuit. The method includes the step of performing a signal offset adjustment on the light data signal input by the trained light data delay control circuit to obtain a target light data signal that is aligned with the sampling edge of the sampling signal, wherein the target light data signal is used to write to the memory.

[0006] In a second aspect, the present application provides a delay control device for a write data signal, the device comprising: A setting module used by the host computer to set the operating mode for register circuits in memory and to acquire training registers that support read / write operations, A transmission module used by the host computer to transmit sample write data signals to the memory, A sampling module used to sample the sample write data signal based on the sampling signal through the memory, and to cache the sampled sample write data signal in the training register, If the sampling write data signal read by the host computer from the training register does not match the sample write data signal, a training module is used to perform delay adjustment training on a write data delay control circuit installed on the host computer based on the sample write data signal, and to acquire a trained write data delay control circuit. The adjustment module is used to perform signal offset adjustment on a light data signal input by the trained light data delay control circuit to obtain a target light data signal that is aligned with the sampling edge of the sampling signal, wherein the target light data signal is used to write to the memory.

[0007] In a third aspect, the present invention provides a computer device comprising memory and one or more processors, wherein computer-readable instructions are stored in the memory, and the one or more processors implement the steps of each embodiment of the present invention when executing the computer-readable instructions.

[0008] In a fourth aspect, the present invention provides one or more computer-readable storage media on which computer-readable instructions are stored, and which, when executed by one or more processors, realize the steps in each embodiment of the present invention.

[0009] In a fifth aspect, the present application provides a computer program product which includes computer-readable instructions, the computer-readable instructions which, when executed on one or more processors, realize the steps in each embodiment of the method of the present application.

[0010] Details of one or more embodiments of the present application are presented in the following drawings and description. Other features, purposes, and advantages of the present application will become apparent from the specification, drawings, and claims.

[0011] To more clearly explain the technical solutions in the embodiments of this application, the following is a brief introduction to the drawings that may be used in the description of the embodiments. As is clear, the drawings in the following description are only a few embodiments of this application, and those skilled in the art can obtain further drawings based on these without any creative work. [Brief explanation of the drawing]

[0012] [Figure 1] This is an application environment diagram of a delay control method for write data signals in one embodiment. [Figure 2] This is a schematic diagram of the process for controlling the delay of a write data signal in one embodiment. [Figure 3] This is a schematic diagram of the structure of a write data signal in one embodiment. [Figure 4] This is a schematic diagram of the timing of sending a write command in one embodiment. [Figure 5] This is a schematic diagram of the format of a write data signal in one embodiment. [Figure 6] This is a schematic diagram of the write data signal format when the burst length is 2 in one embodiment. [Figure 7] This is a schematic diagram of the write data signal format when the burst length is 4 in one embodiment. [Figure 8] This is a schematic diagram of the transmission process of a write data signal in one embodiment. [Figure 9] This is a schematic diagram of the transmission timing of a read command in one embodiment. [Figure 10] This is a schematic diagram illustrating a situation in one embodiment where the write data signal aligns with the sampling edge of the sampling signal. [Figure 11] It is a schematic diagram of a setting description table of a mode register in one embodiment. [Figure 12] It is a schematic diagram of the distribution of each sub - sample signal in a write data signal in one embodiment. [Figure 13] It is a basic structural diagram of a write data delay control circuit in one embodiment. [Figure 14] It is a schematic diagram of each sub - sample signal in a write data signal in one embodiment. [Figure 15] It is a schematic diagram of the situation where each sub - sample signal in a write data signal is aligned with the sampling edge of the sampling signal in one embodiment. [Figure 16] It is a schematic diagram of the process of performing single - circuit delay adjustment training for each sub - circuit in one embodiment. [Figure 17] It is a structural schematic diagram of each sub - circuit in a write data delay control circuit in one embodiment. [Figure 18] It is a basic structural diagram of a training circuit for delay control of a write data signal in one embodiment. [Figure 19] It is a schematic diagram of the process of a delay control method for a write data signal in another embodiment. [Figure 20] It is a structural block diagram of a delay control device for a write data signal in one embodiment. [Figure 21] It is an internal structural diagram of a computer device in one embodiment. [Figure 22] It is an internal structural diagram of a computer device in another embodiment.

Mode for Carrying Out the Invention

[0013] To further clarify the purpose, technical solutions, and advantages of this application, the application will be described in more detail below with reference to the drawings and examples. It should be understood that the specific examples described herein are for interpretation purposes only and are not intended to limit the application.

[0014] The delay control method for write data signals provided in this application can be applied in the application environment shown in Figure 1. Here, terminal 102 communicates with server 104 via a network. The data storage system can store data that server 104 needs to process. The data storage system may be integrated on server 104, or it may be located on the cloud or on another server. Here, terminal 102 may be, but is not limited to, various desktop computers, laptop computers, smartphones, tablet computers, Internet of Things devices, and portable wearable devices. Internet of Things devices may include smart speakers, smart TVs, smart air conditioners, and smart in-car devices. Portable wearable devices may include smartwatches, smart bracelets, and head-mounted devices. Server 104 may be an independent physical server, a server cluster consisting of multiple physical servers, or a distributed system, and may be a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms. The terminal 102 and the server 104 may be connected directly or indirectly by wired or wireless communication, and this invention is not limited to such connections.

[0015] Server 104 is equipped with a host computer and a high-bandwidth internal storage system including memory. Server 104 can set the operating mode for register circuits in memory via the host computer and acquire training registers that support read and write operations. Server 104 receives a sample write data signal from the host computer and sends it to memory. Through memory, Server 104 samples the sample write data signal based on the sampling signal and caches the sampled write data signal in the training register. If the sample write data signal read by the host computer from the training register does not match the sample write data signal, Server 104 performs delay adjustment training on a write data delay control circuit installed on the host computer based on the sample write data signal and acquires a trained write data delay control circuit. Server 104 performs signal offset adjustment on the input write data signal using the trained write data delay control circuit and acquires a target write data signal that aligns with the sampling edge of the sampling signal. This target write data signal is then used to write to memory.

[0016] To understand this, the host computer in server 104 can generate a sample write data signal and transmit the sample write data signal to the memory in server 104 to perform subsequent delay adjustment training. To further understand this, terminal 102 can also generate a sample write data signal and transmit the sample write data signal to server 104. Furthermore, server 104 can receive the sample write data signal from the host computer and transmit the received sample write data signal from the memory in server 104 to perform subsequent delay adjustment training. This embodiment is not limited thereto, and to understand this, the application scene in Figure 1 is merely illustrative and not limited thereto.

[0017] In one embodiment, a method for controlling the delay of a write data signal is provided, as shown in Figure 2. The method can be applied to computer equipment, which may be a terminal or a server, which may be executed independently by the terminal or server itself, or which may be implemented through interaction between the terminal and the server. This embodiment describes the application of the method to computer equipment as an example and includes the following steps 202 to 210.

[0018] Step 202: The host computer sets the operating mode for the register circuit in memory and acquires training registers that support read and write operations.

[0019] Here, the register circuit is an independent circuit in memory that supports setting multiple operating modes. For example, the register circuit can be set to read-write mode, read-only mode, and write-only mode. As can be understood, by setting the register circuit to read-write mode, a register that supports read-write operations, i.e., a training register that supports read-write operations, can be obtained. As can be understood, a training register is a register used to cache data during the training phase. By setting the register circuit to read-only mode, a register that supports read operations can be obtained. By setting the register circuit to write-only mode, a register that supports write operations can be obtained.

[0020] Specifically, computer equipment includes a host computer and memory. The computer equipment can acquire training registers that support read / write operations by having the host computer set the operating mode for the register circuits in memory. To understand this, the computer equipment can acquire training registers that support read / write operations by having the host computer set the operating mode of the register circuits in memory to read / write mode.

[0021] In one embodiment, the host computer and memory are components of a high-bandwidth internal storage system, which is provided in a computer device.

[0022] In one embodiment, the memory may be dynamic random access memory or random access memory. As should be noted, the embodiments of this application are illustrative and do not specifically limit the type of memory.

[0023] Step 204: The host computer sends the sample write data signal to memory.

[0024] Here, the sample write data signal is a write data signal used to train a write data delay control circuit installed on the host computer during the training phase. To understand it, the sample write data signal is a type of sample data used to train the write data delay control circuit. The write data delay control circuit is a circuit used to perform delay control on the write data signal, and by controlling it so that the sampling edge of the write data signal and the sampling signal of the memory are aligned, the memory sampling signal can correctly sample the write data signal. The sampling signal is a clock signal used in memory to sample the write data signal transmitted from the host computer.

[0025] Specifically, the computer equipment can acquire sample write data signals via a host computer and transmit sample write data signals to memory via the host computer.

[0026] In one embodiment, as shown in Figure 3, the write data signal includes three parts: a write data bus signal, a mask signal, and a data bus invert signal. Here, the data bit width of the write data bus signal is 128 bits, the data bit width of the mask signal is 16 bits, and the data bit width of the data bus invert signal is 16 bits.

[0027] In one embodiment, the computer equipment may first send a write instruction to memory before the host computer sends a sample write data signal to the memory. The sending of the write instruction must follow the timing shown in Figure 4, and as can be seen from Figure 4, the write instruction includes nine fields. Here, SID represents the stack identification number, the CA field represents the column address, the BA field represents the bank address, the PAR field represents the instruction check field, and the V field can represent 1 or 0, i.e., high level or low level. Here, clock 1 and clock 2 are two differential clocks.

[0028] In one embodiment, as shown in Figure 5, the write data signal includes three parts: a write data bus signal, a mask signal, and a data bus invert signal. After the computer device sends a write command to memory by the host computer, it may send the write data signal, i.e., the write data bus signal, mask signal, and data bus invert signal, to memory by the host computer at 4-cycle intervals. Each part of the write data signal corresponds to its respective sampling signal. Each part of the write data signal may contain multiple sets of data (for example, four sets, i.e., data 1, data 2, data 3, and data 4).

[0029] In one embodiment, the transmission of write data signals from a computer to memory by a host computer is achieved on a burst basis. That is, multiple sets can be transmitted together each time a write data signal is transmitted. As shown in Figure 6, the burst length for the computer to transmit write data signals to memory by the host computer is 2, and the computer device can transmit a write command to memory by the host computer at time T0, and four cycles after the transmission of the write command, i.e., at time T4, the computer device can transmit two sets of write data signals (i.e., data 1 and data 2) to memory by the host computer. Here, the numerical value of the write command transmitted to memory by the host computer includes BAx (bank address) and CAa (column address).

[0030] In one embodiment, as shown in Figure 7, the burst length for which the computer sends write data signals to memory by the host computer is 4, and the computer device can send a write command to memory by the host computer at time T0, and 4 cycles after sending the write command, i.e., at time T4, the computer device can send 4 sets of write data signals (i.e., data 1, data 2, data 3, and data 4) to memory by the host computer. Here, the numerical value of the write command sent to memory by the host computer includes BAx (bank address) and CAa (column address).

[0031] In one embodiment, as shown in Figure 8, the computer device can initiate the data write by having the host computer send an activation command to the memory. After sending the activation command, the computer device can have the host computer send write commands (i.e., write command 1, write command 2, and write command 3) to the memory. Furthermore, the computer device can have the host computer send write data signals (i.e., data 1, data 2, and data 3) to the memory. As needs to be explained, simultaneously with sending the write data signals, the host computer can also send a write data selection pulse signal that matches the write data signals as a sampling signal to the memory. Finally, the computer device can terminate the data write by having the host computer send a precharge command to the memory.

[0032] Step 206: Sample the sample write data signal based on the sampling signal via memory, and cache the sampled sample write data signal in the training register.

[0033] Here, the sampled write data signal is the write data signal obtained by the memory by sampling based on the sampling signal.

[0034] Specifically, the computer device transmits a sample write data signal to memory via the host computer, and simultaneously transmits a corresponding sampling signal to the memory. Furthermore, the computer device can sample the sample write data signal based on the received sampling signal via memory, and cache the sampled sample write data signal in a training register.

[0035] In one embodiment, a computer device can transmit both a sample write data signal and a write data selection pulse signal, which matches the sample write data signal, to a memory via a host computer. The memory can use the received write data selection pulse signal as a sampling signal and sample the sample write data signal transmitted from the host computer based on the sampling signal to obtain a sample write data signal. As can be understood, since the sampling signal is a write data selection pulse signal that matches the sample write data signal, the sample write data signal can be sampled through the sampling signal, thereby improving the sampling accuracy of the data signal.

[0036] Step 208: If the sampling write data signal read by the host computer from the training register does not match the sample write data signal, delay adjustment training is performed on the write data delay control circuit installed on the host computer based on the sample write data signal, and the trained write data delay control circuit is obtained.

[0037] Specifically, the computer device can read the sampling write data signal from the training register in memory by the host computer, and compare the sampling write data signal read by the host computer from the training register with the sample write data signal transmitted by the host computer to memory. If the sampling write data signal does not match the sample write data signal, it means that the sample write data signal is offset from the sampling edge of the sampling signal during transmission, that the sample write data signal was not correctly sampled by the sampling signal, and furthermore, that the sample write data signal was not successfully cached in the training register. In this case, in order to ensure that the sampling edge of the subsequent write data signal and the sampling signal are aligned, the computer device can perform delay adjustment training on the write data delay control circuit installed on the host computer based on the sample write data signal, and obtain a trained write data delay control circuit.

[0038] To make it easier to understand, when we say that the write data signal is aligned with the sampling edge of the sampling signal, it specifically means that the center of the write data signal aligns with the sampling edge of the memory's sampling signal.

[0039] In one embodiment, the sampling edge of the sampling signal includes the rising edge and the falling edge of the sampling signal. If the computer equipment samples the write data signal using the rising edge of the memory sampling signal, the center of the write data signal aligns with the rising edge of the memory sampling signal. If the computer equipment samples the write data signal using the falling edge of the memory sampling signal, the center of the write data signal aligns with the falling edge of the memory sampling signal. As can be seen, because the sampling edge of the sampling signal includes both a rising and a falling edge, the sampling accuracy of the data signal can be further improved by deciding at a finer granularity whether to sample the write data signal using the rising edge or the falling edge of the sampling signal, thereby avoiding situations where the data is incorrectly aligned.

[0040] In one embodiment, the sample write data signal includes multiple subsample signals, and the write data delay control circuit installed on the host computer includes multiple subcircuits, where one subcircuit is used to control the delay of one subsample signal. The computer equipment can perform delay adjustment training on each of the subcircuits installed on the host computer based on the multiple subsample signals, thereby obtaining a trained write data delay control circuit.

[0041] In one embodiment, the computer equipment may first send a read instruction to memory before the host computer reads the sample write data signal from the memory training register by the host computer. The transmission of the read instruction must follow the timing shown in Figure 9, and as shown in Figure 9, the read instruction includes nine fields, where SID represents the stack identification number, the CA field represents the column address, the BA field represents the bank address, the PAR field represents the instruction check field, and the V field can represent 1 or 0, i.e., high level or low level.

[0042] Step 210: The trained write data delay control circuit performs signal offset adjustment on the input write data signal to obtain a target write data signal that aligns with the sampling edge of the sampled signal. The target write data signal is used to write to memory.

[0043] Here, the input light data signal refers to the light data signal acquired by the host computer in an actual application scenario after the training phase is complete. The target light data signal is the light data signal that has undergone offset adjustment and is aligned with the sampling edge of the sampled signal.

[0044] Specifically, in the actual application phase after delay adjustment training, the computer device acquires the light data signal in the actual application scenario using a host computer, and inputs the acquired light data signal to a trained light data delay control circuit. The trained light data delay control circuit then performs signal offset adjustment on the input light data signal, thereby obtaining a target light data signal that aligns with the sampling edge of the sampling signal in memory. Furthermore, the computer device can transmit the adjusted target light data signal to memory, and the memory can write the target light data signal to memory by sampling the target light data signal through the sampling signal.

[0045] In one embodiment, a computer device samples a write data signal using the rising edge of the memory's sampling signal. As shown in Figure 10, in (a), the center of the write data signal aligns perfectly with the rising edge of the sampling signal, allowing the memory to accurately sample the write data signal through the sampling signal. In (b), an offset exists between the center of the write data signal and the rising edge of the sampling signal, and the rising edge of the sampling signal falls outside the data window of the write data signal. In this case, the memory cannot sample the write data signal through the sampling signal. In (c), an offset also exists between the center of the write data signal and the rising edge of the sampling signal, making it difficult for the memory to accurately sample the write data signal through the sampling signal.

[0046] In the above method for controlling the delay of a write data signal, the host computer sets the operating mode for the register circuit in the memory and acquires training registers that support read and write operations. The host computer sends a sample write data signal to the memory, samples the sample write data signal based on the sampling signal through the memory, caches the sampled write data signal in the training register, and compares the sample write data signal with the sample write data signal sent from the host computer. If the sample write data signal read by the host computer from the training register does not match the sample write data signal, it means that the sample write data signal transmitted from the host computer is offset from the sampling signal in the memory. At this time, delay adjustment training can be performed on the write data delay control circuit installed on the host computer based on the sample write data signal, and a trained write data delay control circuit can be acquired. Furthermore, in the actual application process, the trained write data delay control circuit can perform signal offset adjustment on the input write data signal and send the adjusted target write data signal to the memory. In this way, the target write data signal received by the memory can be aligned with the sampling edge of the memory's sampling signal, thereby enabling the memory to correctly sample the write data signal transmitted from the host computer. This ensures that the data written to the memory is correct, thereby improving the operational stability of the memory.

[0047] In one embodiment, the steps of setting the operating mode for a register circuit in memory using a host computer and acquiring training registers that support read / write operations include: setting the value of a mode register in memory using a host computer to a target value, wherein the mode register is a register used to set the operating mode of the register circuit, and the target value is a value corresponding to the read / write mode supported by the register circuit; and controlling the register circuit to operate in read / write mode through the target value and acquiring training registers that support read / write operations.

[0048] Specifically, a mode register is provided in the memory, and this mode register can set the operating mode of the register circuit in the memory. To understand this, the computer equipment can be controlled by the host computer to set the value of the mode register in the memory to a target value corresponding to the read / write mode, and further control the register circuit to operate in read / write mode through the target value, and the register circuit operating in read / write mode can be used as a training register that supports read / write.

[0049] In one embodiment, the setting of the operating mode of the mode register is shown in Figure 11, and the value of the mode register contains 8 bits of data. The first bit is used to set the self-loop test of the data word, the second and third bits are used to set the control of the read multiplexer of the data word, the fourth and sixth bits are used to set the control of the multi-input shift register of the data word, the seventh bit is used to set a reservation, and the eighth bit is used to set the CATTRIP pin of the memory. For example, by setting the mode register to an 8-bit binary number, i.e., 00000001, the default value in the register circuit can be reset to a hexadecimal number, i.e., 0xAAAAAh. By setting the mode register to an 8-bit binary number, i.e., 00010011, the operating mode of the register circuit can be set to register mode (read-write direction), i.e., read-write mode, and the training register can be acquired. To make it easier to understand, if the host computer writes new data to memory, the newly written data will overwrite the original default value of 0xAAAAAh.

[0050] In the above embodiment, the mode register in the memory can be used to set the operating mode of the register circuit. Therefore, by setting the value of the mode register in the memory, the operating mode of the register circuit can be set, thereby improving the setting efficiency and setting accuracy of the register circuit.

[0051] In one embodiment, the sampled light data signal includes multiple subsample signals, and the light data delay control circuit installed on the host computer includes multiple subcircuits. One subcircuit is used to control the delay of one subsample signal. The steps of obtaining a trained light data delay control circuit by performing delay adjustment training on the light data delay control circuit installed on the host computer based on the sampled light data signal include: for each subcircuit in the light data delay control circuit, performing single-circuit delay adjustment training on the subcircuit based on the subcircuit and the corresponding subsample signal to obtain a trained initial subcircuit, where the subsample signal after signal offset adjustment by the initial subcircuit is aligned with the sampling edge of the sampled signal; and performing multi-circuit delay adjustment training on each initial subcircuit based on multiple subsample signals to obtain a trained light data delay control circuit, where the trained light data delay control circuit includes multiple trained target subcircuits, and each subsample signal after signal offset adjustment by each target subcircuit is aligned with the same sampling edge of the sampled signal.

[0052] Here, the initial subcircuit is the initially trained circuit obtained after performing single-circuit delay adjustment training on the subcircuit. The target subcircuit is the final circuit obtained by performing step-up delay adjustment training on the initial subcircuit.

[0053] Specifically, for each subcircuit in a write data delay control circuit, the computer can perform single-circuit delay adjustment training on the subcircuit based on the subcircuit and its corresponding subsample signal, thereby acquiring a trained initial subcircuit. As can be understood, if the computer inputs a subsample signal to the initial subcircuit, the subsample signal after signal offset adjustment by the initial subcircuit will be aligned with the sampling edge of the sampled signal. The computer can perform multi-circuit delay adjustment training on each initial subcircuit based on multiple subsample signals, acquiring multiple trained target subcircuits, and then determine a trained write data delay control circuit based on these multiple trained target subcircuits. As can be understood, if the computer inputs a subsample signal to a target subcircuit, each subsample signal after signal offset adjustment by each target subcircuit will be aligned with the same sampling edge of the sampled signal.

[0054] In one embodiment, as shown in Figure 12, the sample write data signal contains 160 subsample signals. As can be understood, the sample write data signal consists of 160 bits of subsample signals. The 160 bits of sample write data signal can be divided into four parts, namely the first part, the second part, the third part, and the fourth part. Here, each part contains four byte spaces, and each byte space contains 10 bits of data, i.e., each part contains 40 bits of data. As can be understood, 128 bits are the write data bus signal, 16 bits are the mask signal, and 16 bits are the data bus invert signal.

[0055] In one embodiment, as shown in Figure 13, a 160-bit sample write data signal can be divided into four parts: a first part, a second part, a third part, and a fourth part. Each part contains a 40-bit subsample signal. The write data delay control circuit installed on the host computer includes 160 subcircuits, where one subcircuit contains multiple write data delay control units, and one subcircuit is used to control the delay of one subsample signal.

[0056] In one embodiment, as shown in Figure 14, the sample write data signal includes a 160-bit subsample signal, and the write data delay control circuit includes 160 subcircuits, each subcircuit used to control the delay of one subsample signal. For each of the 160 subcircuits, single-circuit delay adjustment training is performed on the subcircuit based on the subcircuit and its corresponding subsample signal to obtain a trained initial subcircuit, where the subsample signal after signal offset adjustment by the initial subcircuit is aligned with the sampling edge of the sampled signal. To understand this, the 160-bit subsample signals after signal offset adjustment by the initial subcircuit only satisfy the condition that each is aligned with its respective sampling edge of the sampled signal, and not necessarily with the same sampling edge of the sampled signal. As shown in Figure 15, the 160-bit subsample signals are not aligned with the same sampling edge of the sampled signal. At this point, the training is not yet complete, and adjustment training must be continuously performed on each sub-circuit until all 160-bit subsample signals align with the same sampling edge of the sampled signal. The adjustment training is then completed, and the trained write data delay control circuit is obtained.

[0057] In the above embodiment, first, single-circuit delay adjustment training is performed on each subcircuit in the write data delay control circuit to acquire an initial subcircuit, so that each subsample signal in the sampled write data signal aligns with the sampling edge of the sampling signal. Since the sampling edges of the sampling signal that align with each subsample signal are not necessarily the same sampling edge, multi-circuit delay adjustment training can be performed on the initial subcircuit acquired through single-circuit delay adjustment training to ensure that the sampling edges of the sampling signal that aligns with each subsample signal are the same sampling edge. By making the sampling edges of the sampling signal that aligns with each subsample signal the same sampling edge, the training effect of the write data delay control circuit can be improved.

[0058] In one embodiment, the sampled write data signal includes multiple subsample signals and multiple corresponding subsampling signals. The step of performing multi-circuit delay adjustment training on each initial subcircuit based on the multiple subsample signals to acquire a trained write data delay control circuit includes, if the host computer cannot read multiple subsampling signals from the training register at once, the step of continuously performing delay adjustment training on the initial subcircuit to be stepped up to be trained based on the initial adjustment information of the initial subcircuit to be stepped up to be trained until the host computer can read multiple subsampling signals from the training register at once to acquire a trained write data delay control circuit, where the initial subcircuit to be stepped up to be trained is the initial subcircuit corresponding to the unread subsample signals, and the initial adjustment information of the initial subcircuit to be stepped up to be trained is the adjustment information used in the process of acquiring the initial subcircuit by single-circuit delay adjustment training.

[0059] Specifically, the computer equipment can use the initial subcircuit corresponding to an unread subsampled signal as the initial subcircuit for step-up training. Furthermore, the computer equipment can use the adjustment information used in the process of acquiring the initial subcircuit through single-circuit delay adjustment training as the initial adjustment information for the initial subcircuit for step-up training. The computer equipment can read each subsampled signal from the training register in memory via the host computer. If the host computer cannot read multiple subsampled signals from the training register simultaneously, it means that the sampling edges of the sampling signals aligned with each subsampled signal are not the same sampling edge. In this case, the computer equipment can continuously perform delay adjustment training on the initial subcircuit for step-up training based on its initial adjustment information until the host computer can read multiple subsampled signals from the training register simultaneously. To understand this, if the host computer can read multiple subsampled signals from the training register simultaneously, it means that the sampling edges of the sampling signals aligned with each subsampled signal are the same sampling edge. In this case, the trained write data delay control circuit can be determined based on the multiple trained target subcircuits acquired through continuous training.

[0060] In the above embodiment, it is explained that the host computer cannot read multiple subsampling signals from the training register at once, and that the sampling edges of the sampling signal aligned with each subsample signal are not the same sampling edges. In this case, the training effect of the write data delay control circuit can be further improved by continuously performing delay adjustment training on the initial subcircuit targeted for step-up training based on the initial adjustment information of the initial subcircuit targeted for step-up training until the host computer can read multiple subsampling signals from the training register at once, thereby aligning each subsample signal with the same sampling edge of the sampling signal.

[0061] In one embodiment, the step of continuously performing delay adjustment training on the initial subcircuit to be step-up trained, based on the initial adjustment information of the initial subcircuit to be step-up trained, until the host computer can read multiple subsampling signals from the training register at once, and obtaining a trained write data delay control circuit, includes the step of gradually adjusting the initial subcircuit to be step-up trained in a direction that increases or decreases the delay of the target subsample signal, based on the initial adjustment information of the initial subcircuit to be step-up trained, until the host computer can read multiple subsampling signals from the training register at once, and obtaining a trained write data delay control circuit, where the target subsample signal is the subsample signal corresponding to the initial subcircuit to be step-up trained.

[0062] Specifically, the computer equipment can use the initial subcircuit and its corresponding subsample signal as the target subsample signal for step-up training. Furthermore, the computer equipment can gradually adjust the initial subcircuit for step-up training based on its initial adjustment information, increasing or decreasing the delay of the target subsample signal, until the host computer can read multiple subsample signals from the training register at once, thereby acquiring a trained write data delay control circuit.

[0063] To enable understanding, it is possible to adjust the initial subcircuit targeted for step-up training based on initial adjustment information, thereby shifting the target subsample signal in a direction that increases or decreases the delay over the entire clock cycle.

[0064] To illustrate with an example, a computer can adjust the initial subcircuit of a step-up training target based on its initial adjustment information. First, it can adjust the initial subcircuit of the target subsample signal in a direction that increases the delay of one clock cycle of the target subsample signal. If the host computer is not yet able to read multiple subsampling signals simultaneously from the training register, it will revert the target subsample signal to its state before the delay adjustment and then adjust the initial subcircuit of the step-up training target in a direction that further decreases the delay of one clock cycle of the target subsample signal. If the host computer is still unable to read multiple subsampling signals simultaneously from the training register, it will continue to adjust the initial subcircuit of the step-up training target in a direction that increases the delay of two clock cycles of the target subsample signal. If the host computer is still unable to read multiple subsampling signals simultaneously from the training register, it will continue to adjust the initial subcircuit of the step-up training target in a direction that decreases the delay of two clock cycles of the target subsample signal. In this way, the initial subcircuit of the step-up training target is gradually adjusted until the host computer can read multiple subsampling signals simultaneously from the training register, thereby acquiring a trained write data delay control circuit.

[0065] In the above embodiment, in situations where the host computer cannot read multiple subsampling signals from the training register at once, the initial subcircuit of the step-up training target can be gradually adjusted based on the initial adjustment information of the initial subcircuit of the step-up training target to increase or decrease the delay of the target subsample signal, until the host computer can read multiple subsampling signals from the training register at once. By aligning each subsample signal with the same sampling edge of the sampling signal, the training effect of the write data delay control circuit can be further improved.

[0066] In one embodiment, the delay control method for the write data signal further includes the step of obtaining a trained write data delay control circuit, where each initial subcircuit is the respective target subcircuit, if the host computer can read multiple subsampled signals from the training register at once.

[0067] Specifically, the computer equipment can read each subsampling signal from the training register in memory by the host computer. If the host computer can read multiple subsampling signals from the training register at once, it means that the sampling edges of the sampling signal that aligns with each subsampling signal are the same sampling edge. In this case, the trained write data delay control circuit is obtained, with each initial subcircuit as its respective target subcircuit.

[0068] In the above embodiment, it is explained that the host computer can read multiple subsampled signals from the training register at once, and that the sampling edge of the sampling signal that aligns with each subsampled signal is the same sampling edge. At this time, the trained write data delay control circuit can be obtained by directly using each initial subcircuit as the respective target subcircuit. In this way, the training effect of the write data delay control circuit can be ensured, while at the same time improving the training efficiency of the write data delay control circuit.

[0069] In one embodiment, the subcircuit includes sequentially connected write data delay units, each of which is followed by a tap interface that supports the derivation of a signal from within the subcircuit, and the initial subcircuit is a circuit in which the target tap interface has already been determined. For each subcircuit in the write data delay control circuit, the step of obtaining a trained initial subcircuit is to perform single-circuit delay adjustment training on the subcircuit based on the subcircuit and the corresponding subsample signal, and the step of determining delay adjustment information for the subcircuit by performing single-circuit delay adjustment training on the subcircuit based on the subcircuit and the corresponding subsample signal for each subcircuit in the write data delay control circuit, and the step of determining a target tap interface from within the subcircuit based on the delay adjustment information, wherein the target write data delay unit before the target tap interface is used to perform signal offset adjustment on the subcircuit and the corresponding subsample signal by delay processing, and to obtain a signal that is aligned with the sampling edge of the sampling signal.

[0070] Here, a write data delay unit is the smallest unit used in a subcircuit to perform delay control processing on a write data signal. As you can see, the more write data delay units there are that perform delay control processing on the write data signal, the greater the delay of the write data signal; conversely, the fewer write data delay units there are, the smaller the delay of the write data signal. A tap interface is an interface placed after each write data delay unit in a subcircuit, and the tap interface supports the derivation of signals from within the subcircuit. As you can see, the write data signal is derived from within the subcircuit by being read out from any one of the tap interfaces as it is transmitted and passes through the subcircuit. As you can see, a write data delay unit before the tap interface responsible for deriving the write data signal in the subcircuit can perform delay control processing on the write data signal, but a write data delay unit after the tap interface cannot. Delay adjustment information is information used to adjust the subcircuit. To understand this, adjusting a subcircuit means adjusting the number of light data delay units in the subcircuit through which the light data signal is transmitted, thereby increasing or decreasing the delay of the light data signal. The target tap interface is a tap interface used to derive the light data signal from the subcircuit. The target light data delay units are all light data delay units located in the subcircuit before the target tap interface.

[0071] Specifically, for each subcircuit in the write data delay control circuit, the computer can perform delay adjustment training on the subcircuit based on the subcircuit and its corresponding subsample signal. After the training is complete, the computer can obtain delay adjustment information for the subcircuit on the host computer. Based on the delay adjustment information, the computer can determine the target tap interface from among the tap interfaces in the subcircuit. To understand this, the computer can adjust the offset between the subcircuit and its corresponding subsample signal and the sampling edge of the sampling signal by performing delay processing on the subcircuit and its corresponding subsample signal using a target delay unit located before the target tap interface, thereby realigning the subcircuit and its corresponding subsample signal with the sampling edge of the sampling signal in memory.

[0072] In one embodiment, the computer equipment performing delay adjustment training on a subcircuit based on a subsampled signal corresponding to the subcircuit may specifically involve the computer equipment adjusting the subcircuit on the host computer in a direction that increases the delay of the subsampled signal corresponding to the subcircuit, and adjusting the subcircuit on the host computer in a direction that decreases the delay of the subsampled signal corresponding to the subcircuit, thereby completing the delay adjustment training on the subcircuit and obtaining delay adjustment information.

[0073] In one embodiment, the computer device can increase the delay between the subcircuit and the corresponding subsample signal by increasing the number of write data delay units through which the subcircuit and the corresponding subsample signal are transmitted, and reduce the delay between the subcircuit and the corresponding subsample signal by decreasing the number of write data delay units through which the subcircuit and the corresponding subsample signal are transmitted.

[0074] In the above embodiment, by performing single-circuit delay adjustment training on each corresponding subcircuit based on the subcircuit and the corresponding subsample signal, the delay adjustment information for each subcircuit can be determined. Based on the delay adjustment information corresponding to each subcircuit, a target tap interface can be determined from among the respective subcircuits, an initial subcircuit can be acquired, and the training effect of the initial subcircuit can be improved.

[0075] In one embodiment, the step of determining delay adjustment information for each subcircuit in a write data delay control circuit by performing single-circuit delay adjustment training on the subcircuit based on the subcircuit and the corresponding subsample signal includes the steps of: adjusting the subcircuit in a direction that increases the delay of the subcircuit and the corresponding subsample signal until a second state occurs in which the memory does not sample the subcircuit and the corresponding subsample signal based on the sampling signal, in a first state in which the memory has sampled the subcircuit and the corresponding subsample signal based on the sampling signal, thereby obtaining first adjustment information for the subcircuit; adjusting the subcircuit in a direction that decreases the delay of the subcircuit and the corresponding subsample signal until a second state occurs in which the memory does not sample the subcircuit and the corresponding subsample signal based on the sampling signal, thereby obtaining second adjustment information for the subcircuit; and determining delay adjustment information for the subcircuit based on the first and second adjustment information.

[0076] Here, the first state is when the memory has sampled the sub-circuit and the corresponding sub-sampled signal through the sampling signal. The second state is when the memory has not sampled the sub-circuit and the corresponding sub-sampled signal through the sampling signal. The first adjustment information is the adjustment information recorded when the sub-circuit and the corresponding sub-sampled signal is in a critical state, from the state in which the memory has sampled the sub-circuit and the corresponding sub-sampled signal through the sampling signal to the state in which the memory has not sampled the sub-circuit and the corresponding sub-sampled signal, in the process of increasing the delay of the sub-circuit and the corresponding sub-sampled signal. The second adjustment information is the adjustment information recorded when the sub-circuit and the corresponding sub-sampled signal is in a critical state, from the state in which the memory has sampled the sub-circuit and the corresponding sub-sampled signal through the sampling signal to the state in which the memory has not sampled the sub-circuit and the corresponding sub-sampled signal, in the process of decreasing the delay of the sub-circuit and the corresponding sub-sampled signal.

[0077] Specifically, for each subcircuit in the write data delay control circuit, the computer device can transmit the subcircuit and the corresponding subsample signal to memory via the host computer, and can sample the subcircuit and the corresponding subsample signal through the sampling signal in memory. In a first state where memory has sampled the subcircuit and the corresponding subsample signal through the sampling signal, the computer device can adjust the subcircuit in a direction that increases the delay of the subcircuit and the corresponding subsample signal until a second state occurs where memory has not sampled the subcircuit and the corresponding subsample signal through the sampling signal. That is, it can gradually increase the number of write data delay units through which the subcircuit and the corresponding subsample signal is transmitted and record first adjustment information for the subcircuit. The second state is restored to the first state, that is, the second state in which the memory has not sampled the subcircuit and the corresponding subsample signal through the sampling signal is restored to the first state in which the memory sampled the subcircuit and the corresponding subsample signal through the sampling signal during initial training. The subcircuit is then adjusted in a direction that reduces the delay of the subcircuit and the corresponding subsample signal until the second state in which the memory has not sampled the subcircuit and the corresponding subsample signal occurs again, that is, the number of write data delay units through which the subcircuit and the corresponding subsample signal are transmitted is gradually reduced, and the second adjustment information for the subcircuit is recorded. Furthermore, the computer equipment can determine delay adjustment information for the subcircuit based on the recorded first adjustment information and the recorded second adjustment information.

[0078] In one embodiment, the computer equipment may gradually increase or decrease the number of write data delay units through which the sub-circuit and the corresponding subsample signal are transmitted, and the number of write data delay units increased or decreased in each step may be at least one. For example, one write data delay unit may be increased or decreased in one step, two write data delay units may be increased or decreased in one step, or three write data delay units may be increased or decreased in one step.

[0079] In one embodiment, as shown in Figure 16, the computer equipment can sample a sub-circuit and a corresponding subsample signal through a sampling signal in memory. In the first stage of delay adjustment training, in a first state where the memory has sampled a sub-circuit and a corresponding subsample signal through a sampling signal, the computer equipment can reach the second stage of delay adjustment training by adjusting the write data delay control circuit on the host computer in a direction that increases the delay of the sub-circuit and the corresponding subsample signal, until a second state occurs where the memory has not sampled a sub-circuit and a corresponding subsample signal through a sampling signal. At this time, the first adjustment information for the sub-circuit can be immediately recorded. Furthermore, the computer equipment can reach the third stage of delay adjustment training by adjusting the sub-circuit in a direction that decreases the delay of the sub-circuit and the corresponding subsample signal, until the second state occurs again where the memory has not sampled a sub-circuit and a corresponding subsample signal through a sampling signal. At this time, the second adjustment information for the sub-circuit can be immediately recorded.

[0080] In the above embodiment, the memory can sample a subcircuit and a corresponding subsampled signal based on the sampling signal before performing delay adjustment, and it is explained that the sampling edge of the sampling signal is still located within the data window of the subsampled signal. At this time, the subcircuit can be adjusted in a direction that increases the delay of the subcircuit and the corresponding subsampled signal, thereby increasing the delay of the subsampled signal. If, during the process of increasing the delay, it occurs that the subsampled signal has not been sampled, first adjustment information representing the critical state of one side of the data window can be immediately recorded. After resetting the subcircuit and the corresponding subsampled signal, the subcircuit can be adjusted in a direction that decreases the delay of the subcircuit and the corresponding subsampled signal, thereby reducing the delay of the subsampled signal. If, during the process of reducing the delay, it occurs that the subsampled signal has not been sampled, second adjustment information representing the critical state of the other side of the data window can be immediately recorded. Since the first and second adjustment information can determine exactly one clock cycle, the delay adjustment information for the subcircuit can be accurately determined based on the first and second adjustment information.

[0081] In one embodiment, the subcircuit includes a first component circuit and a second component circuit, the second component circuit being connected after the first component circuit. The first and second component circuits each include sequentially connected write data delay units. The first adjustment information includes a first number of write data delay units in the second component circuit through which the sub-sample signal corresponding to the subcircuit has already been transmitted. For each subcircuit in the write data delay control circuit, the step of adjusting the subcircuit in the direction of increasing the delay of the sub-sample signal corresponding to the subcircuit, from a first state in which the memory has sampled the subcircuit and the corresponding sub-sample signal based on the sampling signal, until a second state occurs in which the memory has not sampled the subcircuit and the corresponding sub-sample signal based on the sampling signal, and obtaining the first adjustment information for the subcircuit, includes an initial delay control process by controlling the sub-sample signal corresponding to the subcircuit to pass sequentially through each write data delay unit in the first component circuit, and a step of obtaining the sub-sample signal corresponding to the subcircuit after the initial control, and The process includes the steps of: in a first state in which Mori has sampled a sub-circuit and a corresponding subsample signal based on the sampling signal, continuously controlling the transmission of the sub-circuit and corresponding subsample signal one by one in the direction of increasing the delay of the sub-circuit and corresponding subsample signal after the initial control, until a second state occurs in which the memory has not sampled a sub-circuit and corresponding subsample signal from the corresponding tap interface of the second configuration circuit based on the sampling signal, so that the sub-circuit and corresponding subsample signal is transmitted one by one and passes through the write data delay units in the second configuration circuit, and recording a first number of write data delay units in the second configuration circuit through which the sub-circuit and corresponding subsample signal has already been transmitted.

[0082] Here, the first and second configuration circuits are the configuration circuits within the sub-circuits, respectively.

[0083] Specifically, for each sub-circuit in the write data delay control circuit, the computer device can perform initial delay control processing on the sub-sample signal corresponding to the sub-circuit by controlling it via the host computer so that the sub-sample signal corresponding to the sub-circuit passes sequentially through each write data delay unit in the first configuration circuit, thereby obtaining the sub-sample signal corresponding to the sub-circuit after initial control. The computer device can sample the sub-sample signal corresponding to the sub-circuit after initial control through the sampling signal in memory. In the first state, where memory has sampled the sub-sample signal corresponding to the sub-circuit after initial control via the sampling signal, the computer device can continuously control the transmission of the sub-sample signal corresponding to the sub-circuit after initial control, one by one, to pass through the write data delay units in the second configuration circuit, increasing the delay of the sub-sample signal corresponding to the sub-circuit after initial control, until a second state occurs in which the sub-sample signal corresponding to the sub-circuit has not been sampled from the corresponding tap interface of the second configuration circuit based on the sampling signal, and can record a first number of write data delay units in the second configuration circuit through which the sub-sample signal corresponding to the sub-circuit has already been transmitted and passed.

[0084] In the above embodiment, first, the first configuration circuit performs initial delay control processing on the sub-sampled signal corresponding to the sub-circuit, and obtains the sub-sampled signal corresponding to the sub-circuit after initial control. At this time, the sub-sampled signal corresponding to the sub-circuit after initial control may not be aligned with the sampling edge of the sampling signal. In the first state after initial control, when the sub-sampled signal corresponding to the sub-circuit has been sampled, the system continuously controls the transmission of the sub-sampled signal corresponding to the sub-circuit one by one through the write data delay unit in the second configuration circuit in a direction that increases the delay of the sub-sampled signal corresponding to the sub-circuit after initial control, until a second state occurs in which the sub-sampled signal corresponding to the sub-circuit has not been sampled from the corresponding tap interface of the second configuration circuit based on the sampling signal, and immediately records the first number of write data delay units in the second configuration circuit through which the sub-sampled signal corresponding to the sub-circuit has already been transmitted. In this way, first adjustment information that accurately represents the critical state of one side of the data window of the sub-sampled signal corresponding to the sub-circuit can be recorded, thereby further improving the accuracy of the acquired delay adjustment information.

[0085] In one embodiment, the second adjustment information includes a second number of write data delay units through which the subcircuit and corresponding subsample signal are transmitted and passed, and the step of acquiring the second adjustment information for the subcircuit includes adjusting the subcircuit in a direction that reduces the delay of the subcircuit and corresponding subsample signal until a second state occurs in which the memory does not sample the subcircuit and corresponding subsample signal based on the sampling signal, and controlling to decrease by one write data delay unit in the first configuration circuit through which the subcircuit and corresponding subsample signal are transmitted and passed after the initial control in a direction that reduces the delay of the subcircuit and corresponding subsample signal after the initial control, until a second state occurs in which the memory does not sample the subcircuit and corresponding subsample signal from the corresponding tap interface of the first configuration circuit based on the sampling signal, and recording the second number of write data delay units through which the subcircuit and corresponding subsample signal are transmitted and passed.

[0086] Specifically, the computer equipment can restore the second state to the first state, that is, it can restore the second state, in which the memory has not sampled the sub-circuit and the corresponding sub-sample signal after initial control via the sampling signal, to the first state, in which the memory has sampled the sub-circuit and the corresponding sub-sample signal after initial control via the sampling signal when it is first trained. Furthermore, the computer equipment can control the write data delay units in the first component circuit through which the sub-circuit and the corresponding sub-sample signal is transmitted, decreasing one by one in the direction of reducing the delay of the sub-circuit and the corresponding sub-sample signal after initial control, until the second state occurs in which the sub-circuit and the corresponding sub-sample signal is not sampled from the corresponding tap interface of the first component circuit based on the sampling signal, and the computer equipment can record a second number of write data delay units through which the sub-circuit and the corresponding sub-sample signal is not transmitted.

[0087] In the above embodiment, based on the sampling signal, the write data delay units in the first component circuit through which the sub-sampled signal corresponding to the sub-circuit is transmitted are reduced one by one in the direction of reducing the delay of the sub-sampled signal corresponding to the sub-circuit after the initial control, until a second state occurs in which the sub-sampled signal corresponding to the sub-circuit is not sampled from the corresponding tap interface of the first component circuit. The second number of write data delay units through which the sub-sampled signal corresponding to the sub-circuit is not transmitted is immediately recorded. In this way, second adjustment information that accurately represents the critical state of the other side of the data window of the sub-sampled signal corresponding to the sub-circuit can be recorded, thereby further improving the accuracy of the acquired delay adjustment information.

[0088] In one embodiment, the step of determining delay adjustment information for a subcircuit based on first adjustment information and second adjustment information includes the step of determining delay adjustment information for a subcircuit based on the average value of the first quantity and the second quantity.

[0089] Specifically, the computer equipment can calculate the average value of the first quantity and the second quantity, and then calculate and obtain delay adjustment information for the sub-circuit based on the average value of the first and second quantities.

[0090] In one embodiment, the computer equipment can use the average of the first and second quantities obtained by calculation as delay adjustment information for the subcircuit directly.

[0091] In the above embodiment, the accuracy of the delay adjustment information can be further improved by determining the delay adjustment information using the average value of the first quantity and the second quantity.

[0092] In one embodiment, as shown in Figure 17, each subcircuit of the write data delay control circuit includes a step size counter, which can be used to record a first number of write data delay units in a second configuration circuit through which the write data signal has already been transmitted, and a second number of write data delay units through which the write data signal has not yet been transmitted.

[0093] In one embodiment, for each subcircuit in a write data delay control circuit, the method further includes, before the step of adjusting the subcircuit in a direction that increases the delay of the subcircuit and the corresponding subsample signal, in a first state in which the memory has sampled the subcircuit and the corresponding subsample signal based on a sampling signal, the method performs a frequency reduction adjustment on the current operating frequency of the memory to obtain a reduced target operating frequency, the target operating frequency being the operating frequency at which the memory samples the subcircuit and the corresponding subsample signal based on a sampling signal, and the step of the memory sampling the subcircuit and the corresponding subsample signal based on a sampling signal in the memory operating on the target operating frequency.

[0094] Here, the current operating frequency is the current operating frequency of the memory, i.e., the operating frequency of the memory when the memory is not sampling the sub-circuit and the corresponding sub-sample signal through the sampling signal. The target operating frequency is the frequency obtained after performing a frequency reduction adjustment process on the current operating frequency.

[0095] Specifically, for each sub-circuit in the write data delay control circuit, the computer equipment can send the sub-circuit and its corresponding sub-sample signal to memory via the host computer, and can sample the sub-circuit and its corresponding sub-sample signal through the memory's sampling signal. In the second state, where the memory is not sampling the sub-circuit and its corresponding sub-sample signal through the sampling signal, the memory's current operating frequency is too high, causing the duration for which the sub-circuit and its corresponding sub-sample signal remains high to be relatively short, thus preventing the memory from sampling the sub-circuit and its corresponding sub-sample signal through the sampling signal. At this point, the computer equipment can perform a frequency reduction adjustment on the memory's current operating frequency to obtain a reduced target operating frequency. As can be understood, by reducing the memory's operating frequency, the duration for which the sub-circuit and its corresponding sub-sample signal remains high can be extended, and the memory operating at the target operating frequency can smoothly sample the sub-circuit and its corresponding sub-sample signal. Furthermore, the computer equipment can sample the sub-circuit and its corresponding sub-sample signal based on the memory operating at the target operating frequency, thereby enabling the memory to sample the sub-circuit and its corresponding sub-sample signal. Subsequently, in the first state in which the memory has sampled the subcircuit and the corresponding subsampled signal through the sampling signal, the above step of adjusting the subcircuit in a direction that increases the delay of the subcircuit and the corresponding subsampled signal, and the subsequent steps are performed.

[0096] In the above embodiment, after the memory receives the sub-circuit and corresponding subsample signal transmitted by the host computer, if the memory has not sampled the sub-circuit and corresponding subsample signal through the sampling signal, it means that the sampling edge of the sampling signal is outside the data window where the sub-circuit and corresponding subsample signal are located. At this time, by reducing the memory's current operating frequency to the target operating frequency, the memory operating at the target operating frequency can extend the time during which the sub-circuit and corresponding subsample signal remains high, and furthermore, the memory's sampling signal can sample the sub-circuit and corresponding subsample signal, thereby improving the success rate of delay adjustment training.

[0097] In one embodiment, after the step of performing delay adjustment training on a light data delay control circuit installed on a host computer based on a sample light data signal and acquiring a trained light data delay control circuit, the delay control method for the light data signal further includes the step of triggering delay adjustment training again by periodically triggering a timer to perform a step of acquiring a training register used to cache data, which is performed by hardware control to cause the host computer to set the register mode for a register circuit in memory.

[0098] Specifically, a computer device is equipped with a timer, which, through hardware control, periodically triggers a step by the timer to acquire training registers used for caching data, thereby triggering a repeat of delay adjustment training. In other words, the computer device can time itself using a timer, and can trigger a repeat of delay adjustment training once at pre-set time intervals via hardware control.

[0099] To illustrate with an example, a computer device can use a timer to keep track of time, and can trigger a hardware-controlled delay adjustment training cycle once every 24 hours.

[0100] In the above embodiment, by periodically triggering a timer to retrain the write data delay control circuit using hardware control, it is possible to ensure that a situation does not occur in which the write data signal is offset from the sampling edge of the sampling signal during the operation of the computer equipment, and further improve the operational stability of memory instructions.

[0101] In one embodiment, after the step of performing delay adjustment training on a write data delay control circuit installed on a host computer based on a sample write data signal to acquire a trained write data delay control circuit, the method further includes the step of monitoring the system operating state of a high-bandwidth internal memory system, the high-bandwidth internal memory system including a host computer and memory, and if the system operating state is in a non-busy state, the step of triggering the delay adjustment training again by software control, by performing again the step of setting an operating mode for a register circuit in memory and acquiring training registers used to cache data.

[0102] Specifically, a computer device may be equipped with a high-bandwidth internal memory system, and the computer device may monitor the operating state of the high-bandwidth internal memory system. If the system operating state of the high-bandwidth internal memory system is monitored to be in a non-busy state, the computer device may, through software control, trigger a repeat of the delay adjustment training by having the host computer set the operating mode for the register circuit in memory and acquire training registers used for caching data. If the system operating state of the high-bandwidth internal memory system is monitored to be in a busy state, the computer device may, through software control, temporarily refrain from performing delay adjustment training and then perform delay adjustment training the next time the system operating state of the high-bandwidth internal memory system is monitored to be in a non-busy state.

[0103] In the above embodiment, the software control method allows for the option to retrain the write data delay control circuit when the high-bandwidth internal memory system is not busy. This further ensures that the write data signal does not become offset from the sampling edge of the sampling signal during the operation of the computer equipment, thereby further improving the operational stability of memory instructions. At the same time, retraining the write data delay control circuit when the high-bandwidth internal memory system is not busy also ensures the overall operational efficiency of the high-bandwidth internal memory system.

[0104] In one embodiment, as shown in Figure 18, a high-bandwidth internal memory system operates in a computer device, which includes a host computer and memory. The host computer includes a setting unit, a write instruction transmission unit, a write data delay control circuit, a read instruction transmission unit, a read data reception unit, a comparison unit, and a write data training unit. The memory includes a write instruction analysis unit, a write data reception unit, a read instruction analysis unit, a read data transmission unit, and register circuits. The computer device sets the memory circuits to operate in read-write mode by setting the operating mode for the register circuits in the memory using the setting unit, and acquires training registers. The host computer can send write instructions to the memory, and the memory can analyze the write instructions using the write instruction analysis unit. After the analysis of the write instructions is complete, the host computer can send sample write data signals to the memory, and the memory can receive the sample write data signals using the write reception unit. Furthermore, the memory can sample the sample write data signals through the sampling signal and write the sampled write data signals acquired through sampling to the training registers. The host computer can send read commands to memory via a read command transmission unit, and the memory can analyze the read commands via a read command analysis unit. After the analysis of the read commands is complete, the memory can read the sampling write data signal from the training register and transmit the sampling write data signal to the host computer via the read transmission unit. The host computer can receive the sampling write data signal via a read data reception unit and transfer the sampling write data signal to a comparison unit. The host computer can then compare the sampling write data signal and the sample write data signal using the comparison unit.If the sampling write data signal read by the host computer from the training register does not match the sample write data signal, the computer device can perform delay adjustment training on the write data delay control circuit installed on the host computer based on the sample write data signal, and obtain a trained write data delay control circuit. Furthermore, in actual application scenarios, the computer device can perform signal offset adjustment on the input write data signal using the trained write data delay control circuit, obtain a target write data signal that aligns with the sampling edge of the sampled signal, and write the target write data signal to memory.

[0105] As shown in Figure 19, one embodiment provides a method for controlling the delay of a write data signal, which can be applied to computer equipment. The computer equipment may be a terminal or a server, which may be run independently by the terminal or server itself, or which may be implemented by interaction between the terminal and the server. The method specifically includes the following steps 1902 to 1922.

[0106] Step 1902: The host computer sets the value of the mode register in memory to the target value. The mode register is a register used to set the operating mode of the register circuit, and the target value is a value corresponding to the read / write mode supported by the register circuit. A write data delay control circuit is installed on the host computer, and the write data delay control circuit includes multiple subcircuits. One subcircuit is used to control the delay of one subsample signal and includes sequentially connected write data delay units, each of which has a tap interface connected after it, and the tap interface supports the derivation of signals from within the subcircuit.

[0107] Step 1904: Control the register circuit to operate in read / write mode through the target value and acquire the training register that supports read / write.

[0108] Step 1906: The host computer sends a sample write data signal to memory, which includes multiple sub-sample signals.

[0109] Step 1908: Sample the sample write data signal based on the sampling signal via memory, and cache the sampled sample write data signal in the training register. The sample write data signal includes multiple subsample signals and multiple corresponding subsample signals.

[0110] Step 1910: If the sampling write data signal read by the host computer from the training register does not match the sample write data signal, the subcircuits in the write data delay control circuit are adjusted in a direction that increases the delay of the subcircuit and the corresponding subsample signal until a second state occurs in which the memory does not sample the subcircuit and the corresponding subsample signal based on the sampling signal, in which case the memory has sampled the subcircuit and the corresponding subsample signal based on the sampling signal, and first adjustment information for the subcircuits is obtained.

[0111] Step 1912: Restore the second state to the first state, adjust the subcircuit in a direction that reduces the delay of the subcircuit and the corresponding subsample signal until a second state occurs in which the memory has not sampled the subcircuit and the corresponding subsample signal based on the sampling signal, and obtain second adjustment information for the subcircuit.

[0112] Step 1914: Based on the first and second adjustment information, determine the delay adjustment information for the sub-circuit.

[0113] Step 1916: Based on the delay adjustment information, the target tap interface is determined from among the subcircuits and the trained initial subcircuit is obtained. Here, the target write data delay unit before the target tap interface is used to perform signal offset adjustment on the subcircuit and the corresponding subsample signal through delay processing, and to obtain a signal that is aligned with the sampling edge of the sampling signal. The subsample signal after signal offset adjustment by the initial subcircuit is aligned with the sampling edge of the sampling signal.

[0114] Step 1918: If the host computer cannot read multiple subsampling signals from the training register at once, the initial subcircuit of the step-up training target is gradually adjusted in the direction of increasing or decreasing the delay of the target subsample signal, based on the initial adjustment information of the initial subcircuit of the step-up training target, until the host computer can read multiple subsampling signals from the training register at once, thereby acquiring a trained write data delay control circuit. Here, the target subsample signal is the subsample signal corresponding to the initial subcircuit of the step-up training target, and the initial subcircuit of the step-up training target is the initial subcircuit corresponding to the unread subsample signal. The initial adjustment information of the initial subcircuit of the step-up training target is the adjustment information used in the process of acquiring the initial subcircuit by single-circuit delay adjustment training, and the trained write data delay control circuit includes multiple trained target subcircuits. Each subsample signal after signal offset adjustment by each target subcircuit is aligned with the same sampling edge of the sampling signal.

[0115] Step 1920: If the host computer can read multiple subsampling signals from the training registers at once, obtain a trained write data delay control circuit using each initial subcircuit as its respective target subcircuit.

[0116] Step 1922: The trained write data delay control circuit performs signal offset adjustment on the input write data signal to obtain a target write data signal that aligns with the sampling edge of the sampled signal. The target write data signal is used to write to memory.

[0117] This invention further provides an application scenario in which the above-described delay control method for write data signals is applied. Specifically, a computer device is equipped with a high-bandwidth internal memory system, which includes a host computer and dynamic random access memory, and the delay control method for write data signals can be applied to a scenario of delay control for write data signals when the high-bandwidth internal memory system is in operation. The computer device can have the host computer set the value of a mode register in the dynamic random access memory to a target value. The mode register is a register used to set the operating mode of a register circuit. The target value is a value corresponding to the read-write mode supported by the register circuit. A write data delay control circuit is installed on the host computer, and the write data delay control circuit includes a plurality of subcircuits, one of which is used to control the delay of one subsample signal. The subcircuits include sequentially connected write data delay units, each of which has a tap interface connected after it. The tap interface supports the derivation of signals from within the subcircuits. The register circuit is controlled to operate in read-write mode through the target value, and a training register that supports read-write is obtained. The host computer sends a sample write data signal to dynamic random access memory, and the sample write data signal contains multiple subsample signals.

[0118] Computer equipment can sample a sample write data signal based on a sampling signal through dynamic random access memory, and cache the sampled sample write data signal in a training register. The sample write data signal includes multiple subsample signals and multiple corresponding subsample signals. If the sample write data signal read by the host computer from the training register does not match the sample write data signal, the computer adjusts each subcircuit in the write data delay control circuit in a direction that increases the delay of the subcircuit and the corresponding subsample signal until a second state occurs where the dynamic random access memory does not sample the subcircuit and the corresponding subsample signal based on the sampling signal, thereby acquiring first adjustment information for the subcircuit. The computer adjusts the subcircuit in a direction that decreases the delay of the subcircuit and the corresponding subsample signal until the second state occurs where the dynamic random access memory does not sample the subcircuit and the corresponding subsample signal based on the sampling signal, thereby acquiring second adjustment information for the subcircuit. Based on the first and second adjustment information, the computer determines the delay adjustment information for the subcircuit. Based on the delay adjustment information, the target tap interface is determined from among the subcircuits, and the trained initial subcircuit is obtained. Here, the target write data delay unit before the target tap interface is used to perform signal offset adjustment on the subcircuit and the corresponding subsample signal through delay processing, and to obtain a signal that is aligned with the sampling edge of the sampling signal. The subsample signal after signal offset adjustment by the initial subcircuit is aligned with the sampling edge of the sampling signal.

[0119] If the host computer cannot read multiple subsample signals from the training register simultaneously, the computer equipment can acquire a trained write data delay control circuit by gradually adjusting the initial subcircuit of the step-up training target in the direction of increasing or decreasing the delay of the target subsample signal, based on the initial adjustment information of the initial subcircuit of the step-up training target, until the host computer can read multiple subsample signals from the training register simultaneously. Here, the target subsample signal is the subsample signal corresponding to the initial subcircuit of the step-up training target, and the initial subcircuit of the step-up training target is the initial subcircuit corresponding to the unread subsample signal. The initial adjustment information of the initial subcircuit of the step-up training target is the adjustment information used in the process of acquiring the initial subcircuit by single-circuit delay adjustment training, and the trained write data delay control circuit includes multiple trained target subcircuits. Each subsample signal after signal offset adjustment by each target subcircuit is aligned with the same sampling edge of the sampling signal. If the host computer can read multiple subsample signals from the training register simultaneously, a trained write data delay control circuit is acquired using each initial subcircuit as its respective target subcircuit.

[0120] The computer equipment can perform signal offset adjustment on the input write data signal using a trained write data delay control circuit to obtain a target write data signal that aligns with the sampling edge of the sampled signal. This target write data signal is then used to write to dynamic random access memory.

[0121] The present invention further provides another application scenario in which the above-described delay control method for write data signals is applied. Specifically, a computer device is equipped with a high-bandwidth internal memory system, which includes a host computer and memory, and the delay control method for write data signals can be applied to a scenario of delay control of write data signals when the high-bandwidth internal memory system is in a non-operating state. The delay control method for write data signals of the present invention can perform delay adjustment training on the write data delay control circuit in the high-bandwidth internal memory system when it is in a non-operating state, thereby improving the operational stability of the memory by ensuring that the data written to the memory is correct in the subsequent operating state of the high-bandwidth internal memory system.

[0122] As should be understood, although the steps in the flowcharts of each embodiment described above are shown sequentially in order, these steps are not necessarily performed sequentially in order. Unless expressly stated herein, there are no strict order restrictions on the execution of these steps, and they may be performed in other orders. Furthermore, at least some of the steps in each embodiment described above may include multiple substeps or stages. These substeps or stages do not necessarily have to be executed and completed at the same time, but may be executed at different times. Also, the execution order of these substeps or stages is not necessarily sequential, and they may be performed in place of or alternately with at least some of the other steps, or the substeps or stages of other steps.

[0123] In one embodiment, a delay control device 2000 for write data signals is provided, as shown in Figure 20. The device may employ a software module, a hardware module, or a combination of both as part of a computer device. Specifically, the device includes a setting module 2002, a transmission module 2004, a sampling module 2006, a training module 2008, and an adjustment module 2010.

[0124] The setting module 2002 is used by the host computer to set the operating mode for the register circuit in memory and to acquire training registers that support read and write operations.

[0125] The transmitter module 2004 is used by the host computer to transmit sample write data signals to memory.

[0126] The sampling module 2006 is used to sample a sample write data signal based on a sampling signal via memory, and to cache the sampled sample write data signal in a training register.

[0127] Training module 2008 is used to perform delay adjustment training on a write data delay control circuit installed on the host computer based on the sample write data signal if the sampling write data signal read by the host computer from the training register does not match the sample write data signal, thereby obtaining a trained write data delay control circuit.

[0128] The adjustment module 2010 is used to perform signal offset adjustment on the light data signal input by the trained light data delay control circuit to obtain a target light data signal that is aligned with the sampling edge of the sampled signal, and this target light data signal is used to write to memory.

[0129] In one embodiment, the setting module 2002 is further used by the host computer to set the value of a mode register in memory to a target value, wherein the mode register is a register used to set the operating mode of a register circuit, and the target value is a value corresponding to the read / write mode supported by the register circuit, and to control the register circuit to operate in read / write mode through the target value and to acquire training registers that support read / write.

[0130] In one embodiment, the sampled write data signal includes multiple subsample signals. The write data delay control circuit installed on the host computer includes multiple subcircuits, with each subcircuit used to control the delay of one subsample signal. The training module 2008 is further used to obtain a trained initial subcircuit by performing single-circuit delay adjustment training on each subcircuit in the write data delay control circuit based on the subcircuit and the corresponding subsample signal, where the subsample signal after signal offset adjustment by the initial subcircuit is aligned with the sampling edge of the sampled signal; and to obtain a trained write data delay control circuit by performing multi-circuit delay adjustment training on each initial subcircuit based on multiple subsample signals, where the trained write data delay control circuit includes multiple trained target subcircuits, where each subsample signal after signal offset adjustment by each target subcircuit is aligned with the same sampling edge of the sampled signal.

[0131] In one embodiment, the sampled write data signal includes multiple subsample signals and multiple corresponding subsampling signals. The training module 2008 is further used to acquire a trained write data delay control circuit by continuously performing delay adjustment training on the initial subcircuit to be stepped up, based on the initial adjustment information of the initial subcircuit to be stepped up, until the host computer can read multiple subsampling signals from the training register at once. Here, the initial subcircuit to be stepped up is the initial subcircuit corresponding to the unread subsample signals, and the initial adjustment information of the initial subcircuit to be stepped up is the adjustment information used in the process of acquiring the initial subcircuit by single-circuit delay adjustment training.

[0132] In one embodiment, the training module 2008 is further used to acquire a trained write data delay control circuit by gradually adjusting the initial subcircuit to be stepped up to be trained in a direction that increases or decreases the delay of the target subsample signal, based on the initial adjustment information of the initial subcircuit to be stepped up to be trained, until the host computer can read multiple subsample signals from the training register at once. Here, the target subsample signal is the subsample signal corresponding to the initial subcircuit to be stepped up to be trained.

[0133] In one embodiment, the training module 2008 is further used to acquire a trained write data delay control circuit, with each initial subcircuit as its respective target subcircuit, provided that the host computer can read multiple subsampling signals from the training registers at once.

[0134] In one embodiment, a subcircuit includes sequentially connected write data delay units, each of which is followed by a tap interface. The tap interface supports the derivation of signals from within the subcircuit, and the initial subcircuit is a circuit whose target tap interface has already been determined. The training module 2008 further determines delay adjustment information for each subcircuit in the write data delay control circuit by performing single-circuit delay adjustment training on the subcircuit based on the subcircuit and its corresponding subsample signal, and determines a target tap interface from within the subcircuit based on the delay adjustment information, where the target write data delay unit before the target tap interface is used to perform signal offset adjustment on the subcircuit and its corresponding subsample signal by delay processing, thereby obtaining a signal that aligns with the sampling edge of the sampling signal.

[0135] In one embodiment, the training module 2008 is further used to: adjust each subcircuit in the write data delay control circuit in a direction that increases the delay of the subcircuit and the corresponding subsample signal until a second state occurs in which the memory does not sample the subcircuit and the corresponding subsample signal based on the sampling signal, thereby obtaining first adjustment information for the subcircuit; adjust the subcircuit in a direction that decreases the delay of the subcircuit and the corresponding subsample signal until a second state occurs in which the memory does not sample the subcircuit and the corresponding subsample signal based on the sampling signal, thereby obtaining second adjustment information for the subcircuit; and determine delay adjustment information for the subcircuit based on the first and second adjustment information.

[0136] In one embodiment, the subcircuit includes a first configuration circuit and a second configuration circuit, the second configuration circuit being connected after the first configuration circuit, and the first and second configuration circuits each include sequentially connected write data delay units, the first adjustment information includes a first number of write data delay units in the second configuration circuit through which the sub-sample signal corresponding to the subcircuit has already been transmitted, the training module 2008 further performs initial delay control processing by controlling the sub-sample signal corresponding to the subcircuit to sequentially pass through each write data delay unit in the first configuration circuit, and after initial control, acquires the sub-sample signal corresponding to the subcircuit and the memory samples In a first state in which a sub-circuit and a corresponding subsample signal are sampled based on a signal, the memory continuously controls the transmission of the subsample signals corresponding to the sub-circuit one by one in the direction of increasing the delay of the subsample signals corresponding to the sub-circuit after the initial control, until a second state occurs in which the memory has not sampled the subsample signals corresponding to the sub-circuit from the corresponding tap interface of the second configuration circuit based on the sampling signal, and records a first number of write data delay units in the second configuration circuit through which the subsample signals corresponding to the sub-circuit have already been transmitted.

[0137] In one embodiment, the second adjustment information includes a second number of write data delay units through which the sub-circuit and corresponding subsample signal have not been transmitted. The training module 2008 is further used to restore the second state to the first state, and to record the second number of write data delay units in the first configuration through which the sub-circuit and corresponding subsample signal have been transmitted, in a direction that reduces the delay of the sub-circuit and corresponding subsample signal after the initial control, until a second state occurs in which the memory has not sampled the sub-circuit and corresponding subsample signal from the corresponding tap interface of the first configuration circuit based on the sampling signal, and in a direction that reduces the delay of the sub-circuit and corresponding subsample signal after the initial control.

[0138] In one embodiment, the training module 2008 is used to perform a frequency reduction adjustment on the current operating frequency of the memory in a second state in which the memory has not sampled a sub-circuit and a corresponding sub-sampled signal based on the sampling signal, thereby obtaining a reduced target operating frequency, wherein the target operating frequency is the operating frequency at which the memory samples a sub-circuit and a corresponding sub-sampled signal based on the sampling signal, and to sample a sub-circuit and a corresponding sub-sampled signal based on the sampling signal in the memory operating at the target operating frequency, thereby causing the memory to sample a sub-circuit and a corresponding sub-sampled signal based on the sampling signal.

[0139] In one embodiment, the training module 2008 is further used to monitor the system operating state of a high-bandwidth internal memory system, the high-bandwidth internal memory system including a host computer and memory, and, if the system operating state is in a non-busy state, to trigger a delay-adjusted training again by notifying the setting module 2002, via software control, to perform again the step of setting the operating mode for the register circuit in memory by the host computer and acquiring training registers used to cache data.

[0140] In one embodiment, the transmitting module 2004 is further used by the host computer to transmit a sample write data signal and a write data selection pulse signal that matches the sample write data signal to the memory. The sampling module 2006 is further used by the memory to use the received write data selection pulse signal as a sampling signal, to sample the sample write data signal based on the sampling signal through the memory, and to cache the sampled write data signal obtained in the training register.

[0141] In one embodiment, the sampling edge of the sampling signal includes the rising edge of the sampling signal, and the sampling module 2006 is further used to sample the sample light data signal based on the rising edge of the sampling signal via memory. The adjustment module 2010 is further used to perform signal offset adjustment on the light data signal input by the trained light data delay control circuit to obtain a target light data signal that is aligned with the rising edge of the sampling signal.

[0142] In one embodiment, the sampling edge of the sampling signal includes the falling edge of the sampling signal. The sampling module 2006 is further used to sample a sample light data signal based on the falling edge of the sampling signal via memory. The adjustment module 2010 is further used to perform signal offset adjustment on the light data signal input by a trained light data delay control circuit to obtain a target light data signal that is aligned with the falling edge of the sampling signal.

[0143] The above-described delay control device for write data signals sets the operating mode for the register circuit in the memory using the host computer, acquires training registers that support read and write, sends a sample write data signal to the memory using the host computer, samples the sample write data signal based on the sampling signal through the memory, caches the sampled write data signal in the training register, compares the sample write data signal with the sample write data signal sent from the host computer, and if the sample write data signal read by the host computer from the training register does not match the sample write data signal, it means that an offset occurs between the sample write data signal transmitted from the host computer and the sampling signal in the memory. At this time, delay adjustment training can be performed on the write data delay control circuit installed on the host computer based on the sample write data signal, and a trained write data delay control circuit can be acquired. Furthermore, in the actual application process, the trained write data delay control circuit can perform signal offset adjustment on the input write data signal and send the adjusted target write data signal to the memory. In this way, by aligning the target write data signal received by the memory with the sampling edge of the memory's sampling signal, the memory can correctly sample the write data signal transmitted from the host computer, ensuring that the data written to the memory is correct, thereby improving the operational stability of the memory.

[0144] Each module in the delay control device for the write data signal described above can be implemented entirely or partially by software, hardware, or a combination thereof. Each module may be embedded in the processor of a computer device in hardware form, or it may be independent, or it may be stored in the memory of a computer device in software form. This facilitates the processor to call and execute operations corresponding to each of the above modules.

[0145] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram can be shown in Figure 21. The computer device includes a processor, memory, an input / output interface (abbreviated as I / O), and a communication interface. Here, the processor, memory, and input / output interface are connected by a system bus, and the communication interface is connected to the system bus by the input / output interface. Here, the processor of the computer device is used to provide computation and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer-readable instructions, and a database. The internal memory provides an environment for the operation of the operating system and computer-readable instructions in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals via a network connection. The computer-readable instructions implement a delay control method for write data signals when executed by the processor.

[0146] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram can be shown in Figure 22. The computer device includes a processor, memory, an input / output interface, a communication interface, a display unit, and an input device. Here, the processor, memory, and input / output interface are connected by a system bus, and the communication interface, display unit, and input device are connected to the system bus by the input / output interface. Here, the processor of the computer device is used to provide computation and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer-readable instructions. The internal memory provides an environment for the operation of the operating system and computer-readable instructions in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with an external terminal by wired or wireless means, and the wireless method can be implemented by Wi-Fi, mobile cellular network, NFC (Near Field Communication), or other technology. The computer-readable instruction implements a delay control method for the write data signal when executed by the processor. The display unit of the computer device is used to form a visually visible screen and may be a display screen, a projection device, or a virtual reality image forming device. The display screen may be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device may be a touch layer covering the display screen, a button, trackball, or touch control pad mounted on the housing of the computer device, or an external keyboard, touch control pad, or mouse, etc.

[0147] As those skilled in the art will understand, the structures shown in Figures 21 and 22 are merely block diagrams of partial structures related to the means of the present invention and do not limit computer equipment to which the means of the present invention may be applied. Specific computer equipment may include more or fewer components than those shown in the figures, or may combine several components, or may have a different component layout.

[0148] In one embodiment, a computer device is provided, further comprising memory and one or more processors, wherein computer-readable instructions are stored in the memory, and the one or more processors implement the steps of each embodiment of the above method when executing the computer-readable instructions.

[0149] In one embodiment, one or more computer-readable storage media are provided, in which computer-readable instructions are stored, and the steps in each embodiment of the above method are realized when the computer-readable instructions are executed by one or more processors.

[0150] In one embodiment, a computer program product is provided, which includes computer-readable instructions, and when executed on one or more processors, the computer-readable instructions realize the steps in each embodiment of the above method.

[0151] As requires explanation, user information (including, but not limited to, user device information and user personal information) and data (including, but not limited to, data used for analysis, stored data, and displayed data) relating to this application are all information and data authorized through the user or fully authorized through each party, and the collection, use, and processing of the relevant data must comply with the relevant laws, regulations, and standards of the relevant countries and regions.

[0152] As those skilled in the art will understand, all or part of the processes in the methods of the above embodiments can be implemented by issuing instructions to the relevant hardware via computer-readable instructions. These computer-readable instructions may be stored in a non-volatile readable storage medium, and when the computer-readable instructions are executed, the processes of each embodiment of the above methods may be included. Any reference to memory, storage, database, or other media used in each embodiment provided herein may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical memory, etc. Volatile memory may include random access memory (RAM) or external high-speed cache memory. RAM may take multiple forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0153] The technical features of the above embodiments can be combined in any way; however, for the sake of brevity, not all possible combinations of each technical feature in the above embodiments are described. Nevertheless, as long as there is no inconsistency in these combinations of technical features, they should be considered to fall within the scope of what is described herein.

[0154] The above embodiments merely embody some of the embodiments of the present application, and their descriptions are relatively specific and detailed, and therefore cannot be understood as limiting the scope of the patentable invention. As should be pointed out, for those skilled in the art, various further modifications and improvements can be made without departing from the concept of the present application, and all of these fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent should be based on the attached claims.

Claims

1. A method for controlling the delay of a write data signal, which is performed by a computer device, The host computer sets the operating mode for the register circuit in memory and acquires training registers that support read / write operations. A step of transmitting a sample write data signal to the memory by the host computer, wherein the sample write data signal includes a plurality of subsample signals, The steps include sampling the sample write data signal based on the sampling signal through the memory, and caching the sampled sample write data signal obtained in the training register, If the sampling write data signal read by the host computer from the training register does not match the sample write data signal, the following steps are taken: Based on the sample write data signal, a single-circuit delay adjustment training is performed on each subcircuit in the write data delay control circuit installed on the host computer, based on the sub-sample signal corresponding to the subcircuit, thereby obtaining a trained initial subcircuit, wherein the write data delay control circuit includes a plurality of subcircuits, one of the plurality of subcircuits is used to control the delay of one sub-sample signal, and the sub-sample signal after signal offset adjustment by the initial subcircuit is aligned with the sampling edge of the sample signal. A step of obtaining a trained write data delay control circuit by performing multi-circuit delay adjustment training on each of the initial subcircuits based on the plurality of subsample signals, wherein the trained write data delay control circuit includes a plurality of trained target subcircuits, and each subsample signal after signal offset adjustment by each of the target subcircuits is aligned with the same sampling edge of the sampling signal. The steps include performing signal offset adjustment on the light data signal input by the trained light data delay control circuit to obtain a target light data signal that is aligned with the sampling edge of the sampling signal, wherein the target light data signal is used to write to the memory, and Methods that include...

2. The host computer sets the operating mode for the register circuit in memory and acquires training registers that support read / write operations. A step of setting the value of a mode register in memory to a target value by a host computer, wherein the mode register is a register used to set the operating mode of the register circuit, and the target value is a value corresponding to the read / write mode supported by the register circuit, The steps include controlling the register circuit to operate in read / write mode through the target value, and acquiring a training register that supports read / write operations. The method according to claim 1, including the method described in claim 1.

3. The sampling write data signal includes the plurality of subsample signals and the plurality of subsampling signals corresponding to each of them. The step of performing multi-circuit delay adjustment training on each of the initial subcircuits based on the plurality of subsample signals to obtain a trained write data delay control circuit is: If the host computer cannot read the multiple subsampling signals from the training register at once, the host computer may continue to perform delay adjustment training on the initial subcircuit to be step-up training based on the initial adjustment information of the initial subcircuit to be step-up training until it can read the multiple subsampling signals from the training register at once, thereby obtaining a trained write data delay control circuit. The initial subcircuit targeted for step-up training is an initial subcircuit corresponding to an unread subsampled signal, and the initial adjustment information for the initial subcircuit targeted for step-up training is the adjustment information used in the process of acquiring the initial subcircuit through single-circuit delay adjustment training. The method according to claim 1.

4. If the host computer cannot read the multiple subsampling signals from the training register at once, the step of continuously performing delay adjustment training on the initial subcircuit of the step-up training target based on the initial adjustment information of the initial subcircuit of the step-up training target until the host computer can read the multiple subsampling signals from the training register at once, thereby obtaining a trained write data delay control circuit, is as follows: The process includes gradually adjusting the initial subcircuit to be step-up trained in a direction that increases or decreases the delay of the target subsample signal, based on the initial adjustment information of the initial subcircuit to be step-up trained, until the host computer can read the multiple subsampling signals from the training register at once, thereby obtaining a trained write data delay control circuit. The target subsample signal is a subsample signal corresponding to the initial subcircuit targeted for step-up training. The method according to claim 3.

5. If the host computer can read the multiple subsampling signals from the training register at once, the process further includes the step of acquiring a trained write data delay control circuit with each of the initial subcircuits as the respective target subcircuit. The method according to claim 3.

6. The subcircuit includes sequentially connected write data delay units, each of which has a tap interface connected after it, the tap interface supporting the derivation of a signal from within the subcircuit, and the initial subcircuit is a circuit in which the target tap interface has already been determined. For each subcircuit in the aforementioned write data delay control circuit, the step of performing single-circuit delay adjustment training on the subcircuit based on the subsample signal corresponding to the subcircuit, and obtaining a trained initial subcircuit, is: The steps include determining delay adjustment information for each subcircuit in the write data delay control circuit by performing single-circuit delay adjustment training on the subcircuit based on the subsample signal corresponding to the subcircuit, A step of determining a target tap interface from among the subcircuits based on the delay adjustment information, wherein the target write data delay unit before the target tap interface is used to perform a signal offset adjustment on the subsample signal corresponding to the subcircuit by delay processing, and to obtain a signal that is aligned with the sampling edge of the sampling signal. The method according to claim 1, including the method described in claim 1.

7. The step of determining delay adjustment information for each subcircuit in the write data delay control circuit by performing single-circuit delay adjustment training on the subcircuit based on the subsample signal corresponding to the subcircuit is as follows: With respect to each subcircuit in the write data delay control circuit, the steps include: adjusting the subcircuit in a direction that increases the delay of the subsample signal corresponding to the subcircuit until a second state occurs in which the memory has sampled a subsample signal corresponding to the subcircuit based on the sampling signal, and obtaining first adjustment information for the subcircuit; The steps include: restoring the second state to the first state, adjusting the subcircuit in a direction that reduces the delay of the subsample signal corresponding to the subcircuit until a second state occurs in which the memory has not sampled the subcircuit and the corresponding subsample signal based on the sampling signal, and obtaining second adjustment information for the subcircuit; A step of determining delay adjustment information for the sub-circuit based on the first adjustment information and the second adjustment information. The method according to claim 6, including the method described in claim 6.

8. The subcircuit includes a first configuration circuit and a second configuration circuit, the second configuration circuit being connected after the first configuration circuit, the first and second configuration circuits each including sequentially connected write data delay units, and the first adjustment information includes a first number of write data delay units in the second configuration circuit through which the subsample signal corresponding to the subcircuit has already been transmitted and passed. With respect to each subcircuit in the write data delay control circuit, the step of adjusting the subcircuit in a direction that increases the delay of the subsample signal corresponding to the subcircuit until a second state occurs in which the memory has sampled a subsample signal corresponding to the subcircuit based on the sampling signal, and acquiring first adjustment information for the subcircuit, is as follows: The steps include: performing initial delay control processing by controlling the sub-sample signal corresponding to the sub-circuit to pass sequentially through each write data delay unit in the first configuration circuit, and obtaining the sub-sample signal corresponding to the sub-circuit after the initial control; In a first state in which the memory has sampled a sub-sample signal corresponding to the sub-circuit based on the sampling signal, the memory continuously controls the transmission of the sub-sample signals corresponding to the sub-circuit one by one in the direction of increasing the delay of the sub-sample signals corresponding to the sub-circuit after the initial control, until a second state occurs in which the memory has not sampled the sub-sample signal corresponding to the sub-circuit from the corresponding tap interface of the second configuration circuit based on the sampling signal, so that the sub-sample signals corresponding to the sub-circuit are transmitted one by one and pass through the write data delay units in the second configuration circuit, and records a first number of write data delay units in the second configuration circuit through which the sub-sample signals corresponding to the sub-circuit have already been transmitted and passed. The method according to claim 7, including the method described in claim 7.

9. The second adjustment information includes a second number of write data delay units that have not been transmitted through to the sub-circuit and the corresponding sub-sample signal. The steps of restoring the second state to the first state, adjusting the subcircuit in a direction that reduces the delay of the subsample signal corresponding to the subcircuit until a second state occurs in which the memory has not sampled the subcircuit and the corresponding subsample signal based on the sampling signal, and obtaining second adjustment information for the subcircuit are: The process includes the steps of restoring the second state to the first state, controlling the write data delay units in the first configuration circuit through which the subsample signal corresponding to the subcircuit is transmitted, one by one, in a direction that reduces the delay of the subsample signal corresponding to the subcircuit after the initial control, until a second state occurs in which the memory has not sampled the subsample signal corresponding to the subcircuit from the corresponding tap interface of the first configuration circuit based on the sampling signal, and recording a second number of write data delay units through which the subsample signal corresponding to the subcircuit has not been transmitted. The method according to claim 8.

10. With respect to each subcircuit in the write data delay control circuit, in the first state in which the memory has sampled a subsample signal corresponding to the subcircuit based on the sampling signal, before adjusting the subcircuit in a direction that increases the delay of the subsample signal corresponding to the subcircuit, In a second state in which the memory is not sampling the sub-sample signal corresponding to the sub-circuit based on the sampling signal, the memory performs a frequency reduction adjustment process on its current operating frequency to obtain a reduced target operating frequency, wherein the target operating frequency is the operating frequency at which the memory causes the memory to sample the sub-sample signal corresponding to the sub-circuit based on the sampling signal. The memory samples the sub-sampled signal corresponding to the sub-circuit based on the sampling signal in the memory operating at the target operating frequency, thereby a step in which the memory samples the sub-sampled signal corresponding to the sub-circuit based on the sampling signal. The method according to claim 7, further comprising:

11. If the sampling write data signal read by the host computer from the training register does not match the sample write data signal, then, after performing delay adjustment training on the write data delay control circuit installed on the host computer based on the sample write data signal and obtaining the trained write data delay control circuit, A step of monitoring the system operating status of a high-bandwidth internal storage system, wherein the high-bandwidth internal storage system includes the host computer and the memory. If the system is in a non-busy state, the software controls the host computer to set the operating mode for the register circuit in memory and acquire the training register used to cache data, thereby triggering a re-execution of delay-adjusted training. The method according to claim 1, further comprising:

12. The step of transmitting a sample write data signal to the memory by the host computer is: The host computer transmits a sample light data signal and a light data selection pulse signal that matches the sample light data signal to the memory. The steps of sampling the sample write data signal based on the sampling signal through the memory and caching the sampled sample write data signal in the training register are: The memory receives the write data selection pulse signal as a sampling signal, and the memory samples the sample write data signal based on the sampling signal, and the sampled write data signal obtained is cached in the training register. The method according to claim 1.

13. The sampling edge of the sampling signal includes the rising edge of the sampling signal, and sampling the sample write data signal based on the sampling signal through the memory is: This includes sampling the sample write data signal based on the rising edge of the sampling signal through the memory, The step of performing signal offset adjustment on the light data signal input by the aforementioned trained light data delay control circuit to obtain a target light data signal that is aligned with the sampling edge of the sampled signal is: The trained light data delay control circuit performs signal offset adjustment on the input light data signal to obtain a target light data signal that is aligned with the rising edge of the sampling signal. The method according to claim 1.

14. The sampling edge of the sampling signal includes the falling edge of the sampling signal, and the step of sampling the sample write data signal based on the sampling signal through the memory is: The step includes sampling the sample write data signal based on the falling edge of the sampling signal through the memory, The step of performing signal offset adjustment on the light data signal input by the aforementioned trained light data delay control circuit to obtain a target light data signal that is aligned with the sampling edge of the sampled signal is: The process includes performing a signal offset adjustment on the light data signal input by the aforementioned trained light data delay control circuit to obtain a target light data signal that aligns with the falling edge of the sampled signal. The method according to claim 1.

15. A delay control device for write data signals, A setting module used by the host computer to set the operating mode for register circuits in memory and to acquire training registers that support read / write operations, A transmitting module used by the host computer to transmit a sample write data signal to the memory, wherein the sample write data signal includes a plurality of subsample signals. A sampling module used to sample the sample write data signal based on the sampling signal through the memory, and to cache the sampled sample write data signal in the training register, It is a training module, If the sampling write data signal read by the host computer from the training register does not match the sample write data signal, then, based on the sample write data signal, a single-circuit delay adjustment training is performed on each subcircuit in the write data delay control circuit installed on the host computer, based on the sub-sample signal corresponding to the subcircuit, thereby obtaining a trained initial subcircuit, wherein the write data delay control circuit includes a plurality of subcircuits, one of which is used to control the delay of a single sub-sample signal, and the sub-sample signal after signal offset adjustment by the initial subcircuit is aligned with the sampling edge of the sample signal. Based on the aforementioned multiple subsample signals, multi-circuit delay adjustment training is performed on each of the initial subcircuits to obtain a trained write data delay control circuit, wherein the trained write data delay control circuit includes a plurality of trained target subcircuits, and each subsample signal after signal offset adjustment by each of the target subcircuits is aligned with the same sampling edge of the sampling signal. The training module used in this, An adjustment module used to perform signal offset adjustment on a light data signal input by the aforementioned trained light data delay control circuit, thereby obtaining a target light data signal that aligns with the sampling edge of the sampling signal, wherein the target light data signal is used to write to the memory, and the adjustment module and A device including a device.

16. A computer device comprising memory and one or more processors, wherein computer-readable instructions are stored in the memory, and the one or more processors implement the method according to any one of claims 1 to 14 when executing the computer-readable instructions.

17. A computer program that, when executed on one or more processors, implements the method described in any one of claims 1 to 14.

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