High-speed serial interface and data transmission method

Abstract

The embodiments of the present application relate to the field of chip technology, and provide a high-speed serial interface and a data transmission method, so as to reduce the power consumption of the physical layer circuit of the high-speed serial interface when service data is not being transmitted. The high-speed serial interface includes a physical layer circuit of a transmitting end, a monitor, a clock gating circuit, a control bit stream generating circuit, and a random bit stream generating circuit, and further, the monitor is configured to indicate to the clock gating circuit to stop sending a clock signal to a partial module in the physical layer circuit of the transmitting end when service data is not being transmitted. The control bit stream generating circuit transmits a first control bit stream through the serializer / deserializer to indicate that the transmitting end has turned off the partial module in the physical layer circuit of the transmitting end, or to indicate that the transmitting end turns off the partial module in the physical layer circuit of the transmitting end, or to indicate to the receiving end to turn off the partial module in the physical layer circuit of the receiving end. The random bit stream generating circuit transmits a random bit stream. The embodiments of the present application are used in the process of reducing the power consumption of the physical layer circuit.

Description

[Technical Field]

[0001] This application claims priority to Chinese Patent Application No. 202111679102.7, titled "HIGH-SPEED SERIAL INTERFACE AND DATA TRANSMISSION METHOD," filed with the China National Intellectual Property Administration on 31 December 2021, which is incorporated herein by reference in its entirety.

[0002] Embodiments of this application relate to the field of chip technology, and more particularly to high-speed serial interfaces and data transmission methods. [Background technology]

[0003] After the rate of high-speed serial interfaces increases to 64 GT / s or higher, the bit error rate increases. Forward error correction (FEC) technique must be used at the transmitting end to encode the data to be transmitted. In addition, at the receiving end, FEC decoding and error correction must be performed on the data output by the receiver (RX) circuit of the serializer and deserializer (SerDes). Furthermore, to ensure that the number of 0s and 1s in the data transmitted from the transmitting end to the SerDes is balanced, a scrambler must be used to scramble the data obtained by FEC encoding to ensure that the number of 0s and 1s in the data is balanced.

[0004] In conventional physical layer devices, such as Peripheral Component Interface Express (PCIe), if no service packets are transmitted on the link within a short period, the transmitting end must insert an idle bitstream in the transmission direction for data padding to ensure that the SerDes at the transmitting end can transmit data continuously. However, in this case, high power consumption occurs at both the transmitting and receiving ends when the transmitting end sends the idle bitstream, resulting in high power consumption for the devices. [Overview of the project]

[0005] Embodiments of this application provide a high-speed serial interface and a data transmission method to reduce power consumption of the physical layer circuitry of the high-speed serial interface when no service data is being transmitted. [Means for solving the problem]

[0006] To achieve the aforementioned objectives, the following technical solutions are used in the embodiments of this application.

[0007] According to a first embodiment, a high-speed serial interface is provided. The high-speed serial interface includes a physical layer circuit at the transmitting end, a monitor, a clock gating circuit, a control bitstream generation circuit, a random bitstream generation circuit, and a serializer / deserializer. The monitor is configured to indicate to the clock gating circuit that it will stop transmitting a clock signal to a submodule in the physical layer circuit at the transmitting end when the transmitting end is not transmitting service data. The clock gating circuit is configured to stop transmitting a clock signal to a submodule in the physical layer circuit at the transmitting end. The control bitstream generation circuit, when it determines that the clock gating circuit has stopped transmitting a clock signal, transmits a first control bitstream via the serializer / deserializer, the first control bitstream is used to indicate that the transmitting end has turned off a submodule in the physical layer circuit at the transmitting end, or the first control bitstream is used to indicate to the receiving end that it will turn off a submodule in the physical layer circuit at the receiving end. The random bitstream generation circuit is configured to send a random bitstream to a serializer / deserializer.

[0008] Therefore, if there is no need to transmit service data at the moment, the high-speed serial interface may stop transmitting the clock signal to the submodule in the physical layer circuit of the transmitting end, resulting in the submodule in the physical layer circuit of the transmitting end remaining in a non-driven state. This can reduce the power consumption of the physical layer circuit of the transmitting end. In addition, the control bitstream generation circuit may further transmit a first control bitstream to indicate that the physical layer circuit needs to be turned off. Thus, the first control bitstream is equivalent to an on / off instruction indicating that the receiving end may also turn off the submodule in the physical layer circuit of the receiving end without receiving service data. A random bitstream is further transmitted after the first control bitstream to allow the serializer / deserializer clock and data recovery CDR circuit to remain locked to avoid errors. Neither the first control bitstream nor the random bitstream passes through the submodule in the physical layer circuit of the transmitting end nor the submodule in the physical layer circuit of the receiving end. In this way, both the physical layer circuit of the transmitting end and the physical layer circuit of the receiving end can perform the function of reducing power consumption.

[0009] In one possible design, a submodule in the physical layer circuit at the transmitting end includes at least one of either a forward error correction (FEC) coding circuit or a scrambling circuit, and a submodule in the physical layer circuit at the receiving end includes at least one of either an FEC decoding circuit or a descrambling circuit. In the physical layer circuit at the transmitting end, the FEC circuit and the scrambling / descrambling circuit consume power. Therefore, when no service data is currently being transmitted, the FEC circuit and the scrambling / descrambling circuit may be turned off to reduce power consumption. Of course, in this application, the submodule in the physical layer circuit at the transmitting end that needs to be turned off is not limited to the FEC coding circuit and the scrambling circuit, nor is the submodule in the physical layer circuit at the receiving end limited to the FEC decoding circuit and the descrambling circuit. Other power-consuming circuits may be included. For example, the submodule in the physical layer circuit at the transmitting end may further include a data distribution circuit, and the submodule in the physical layer circuit at the receiving end may further include a symbol lock circuit, a deskew circuit, and so on.

[0010] In one possible design, the high-speed serial interface is specifically configured to include an additional data link layer at the transmitting end, and the monitor monitors whether the transmitting end's data link layer is sending service data to the transmitting end's physical layer circuitry, and if it is determined that the transmitting end's data link layer is not sending service data to the transmitting end's physical layer circuitry, it determines that the transmitting end is not sending service data. Specifically, the fact that the transmitting end's data link layer is not sending service data is equivalent to the transmitting end not currently sending service data, and a submodule within the transmitting end's physical layer circuitry may be turned off to reduce power consumption.

[0011] In one possible design, the monitor is further configured to send a first signal to a control bitstream generator circuit when it determines that the clock gating circuit has stopped transmitting a clock signal to a submodule in the physical layer circuit at the transmitting end, the first signal being used to indicate to the control bitstream generator circuit that it should transmit a first control bitstream, and when it determines that the control bitstream generator circuit has completed transmitting the first control bitstream, it sends a second signal to a random bitstream generator circuit, the second signal being used to indicate to the random bitstream generator circuit that it should transmit a random bitstream. Specifically, in this application, if it determines that no service data has been transmitted, the monitor may trigger a bitstream generator circuit to transmit a first control bitstream, and may further trigger a random bitstream generator circuit to transmit a random bitstream. Neither bitstream passes through a submodule in the physical layer circuit at the transmitting end. Naturally, the monitor does not have to trigger the transmission of the two bitstreams alternatively, and control circuits other than the monitor may alternatively monitor the state of each circuit. If the control circuit determines that no service data has been transmitted, it may indicate to the bitstream generation circuit to transmit a first control bitstream, and further indicate to the random bitstream generation circuit to transmit a random bitstream.

[0012] In one possible design, the monitor is further configured to direct a clock gating circuit to send a clock signal to a submodule in the physical layer circuit of the transmitting end when the transmitting end resumes transmitting service data, the clock gating circuit is further configured to send a clock signal to a submodule in the physical layer circuit of the transmitting end, the random bitstream generator is further configured to stop transmitting a random bitstream when it determines that the clock gating circuit has started transmitting a clock signal, the control bitstream generator is further configured to send a second control bitstream via a serializer / deserializer when it determines that the transmitting end resumes transmitting service data, the second control bitstream is used to indicate that the transmitting end has turned on a submodule in the physical layer circuit of the transmitting end, or the second control bitstream is used to indicate that the transmitting end is turning on a submodule in the physical layer circuit of the transmitting end, or the second control bitstream is used to indicate to the receiving end to turn on a submodule in the physical layer circuit of the receiving end, and the physical layer circuit of the transmitting end is configured to start transmitting service data via a serializer / deserializer.

[0013] Specifically, once service data transmission is resumed, the monitor may be further configured to indicate to the random bitstream generation circuit to stop transmitting a random bitstream and to indicate to the control bitstream generation circuit to transmit a second control bitstream, the second control bitstream may be used to indicate to the physical layer circuit at the receiving end to turn on a subset module in the physical layer circuit at the receiving end so that the physical layer circuit at the receiving end can resume transmitting service data.

[0014] In one possible design, the first control bitstream includes multiple repeating bitstream identifiers, a first marker end identifier, and a first bitstream content, the first bitstream content being used to indicate that the transmitting end has turned off a subset module in the transmitting end's physical layer circuitry, or the first control bitstream is used to indicate that the transmitting end is turning off a subset module in the transmitting end's physical layer circuitry, or the first control bitstream is used to indicate to the receiving end to turn off a subset module in the receiving end's physical layer circuitry, and the first marker end identifier is used to indicate the position of the end bit of the first control bitstream. The second control bitstream includes a plurality of repeating bitstream identifiers, a second marker end identifier, and a second bitstream content, the second bitstream content being used to indicate that the transmitting end has turned on a subset module in the transmitting end's physical layer circuitry, or the second control bitstream is used to indicate that the transmitting end is turning on a subset module in the transmitting end's physical layer circuitry, or the second control bitstream is used to indicate to the receiving end to turn on a subset module in the receiving end's physical layer circuitry, and the second marker end identifier is used to indicate the position of the end bit of the second control bitstream. A random bitstream is used to allow the serializer / deserializer clock and data recovery CDR circuitry to remain locked, and the random bitstream includes a balanced quantity of 0s and 1s. Embodiments of the first and second control bitstreams are not limited in this application.

[0015] According to a second embodiment, a high-speed serial interface is provided. The high-speed serial interface includes a physical layer circuit at the receiving end, a bitstream detection circuit, a clock gating circuit, and a serializer / deserializer. The bitstream detection circuit is configured to receive a first control bitstream via the serializer / deserializer, the first control bitstream being used to indicate that the transmitting end has turned off a submodule in the transmitting end's physical layer circuit, or the first control bitstream being used to indicate that the transmitting end will turn off a submodule in the transmitting end's physical layer circuit, or the first control bitstream being used to indicate to the receiving end to turn off a submodule in the receiving end's physical layer circuit. The bitstream detection circuit is further configured to indicate to the clock gating circuit that it will stop transmitting a clock signal to a submodule in the receiving end's physical layer circuit. The clock gating circuit is configured to stop transmitting a clock signal to a submodule in the receiving end's physical layer circuit. The bitstream detection circuit is further configured to receive a random bitstream via the serializer / deserializer.

[0016] Thus, upon receiving the first control bitstream, the receiving end knows that the transmitting end has no service data to transmit, and the receiving end may turn off a partial module in its physical layer circuitry to reduce power consumption. In addition, to allow the CDR circuitry of the receiving end's serializer / deserializer to remain locked, the receiving end's serializer / deserializer can continue to receive random bitstreams after receiving the first control bitstream.

[0017] In one possible design, a submodule in the physical layer circuit at the transmitting end includes at least one of either a forward error correction (FEC) coding circuit or a scrambling circuit, and a submodule in the physical layer circuit at the receiving end includes at least one of either an FEC decoding circuit or a descrambling circuit. For the beneficial effects of this design, please refer to the description of the first embodiment.

[0018] In one possible design, the high-speed serial interface further includes a data link layer at the receiving end, and the clock gating circuit is specifically configured to stop transmitting a clock signal to a submodule within the receiving end's physical layer circuit when it is determined that the interval since the last time the receiving end's physical layer circuit sent service data to the receiving end's data link layer exceeds a preset time period. When it is determined that the interval since the last time the receiving end's physical layer circuit sent service data to the receiving end's data link layer exceeds a preset time period, it may be determined that no service data is currently being received, or that any received service data has been fully transmitted to the receiving end's data link layer.

[0019] In one possible design, the bitstream detection circuit is further configured to control the serializer / deserializer to receive a second control bitstream, and to show the clock gating circuit that it transmits a clock signal to the submodule in the physical layer circuit at the receiving end when the second control bitstream is used to indicate that the transmitting end has turned on a submodule in the physical layer circuit at the transmitting end, or when the second control bitstream is used to indicate that the transmitting end will turn on a submodule in the physical layer circuit at the transmitting end, or when the second control bitstream is used to indicate to the receiving end that it will turn on a submodule in the physical layer circuit at the receiving end. The clock gating circuit is further configured to transmit a clock signal to the submodule in the physical layer circuit at the receiving end. The bitstream detection circuit is further configured to transmit the service data received from the serializer / deserializer to the physical layer circuit at the receiving end. For the beneficial effects of this design, see the description of the first embodiment.

[0020] In one possible design, the first control bitstream includes multiple repeating marker identifiers, a first marker end identifier, and a first bitstream content, the first bitstream content being used to indicate that the transmitting end has turned off a subset module in the transmitting end's physical layer circuitry, or the first control bitstream is used to indicate that the transmitting end is turning off a subset module in the transmitting end's physical layer circuitry, or the first control bitstream is used to indicate that the receiving end should turn off a subset module in the receiving end's physical layer circuitry, and the first marker end identifier is used to indicate the position of the end bit of the first control bitstream. The second control bitstream includes multiple repeating marker identifiers, a second marker end identifier, and a second bitstream content, the second bitstream content being used to indicate that the transmitting end has turned on a subset module in the transmitting end's physical layer circuitry, or the second control bitstream is used to indicate that the transmitting end is turning on a subset module in the transmitting end's physical layer circuitry, or the second control bitstream is used to indicate to the receiving end to turn on a subset module in the receiving end's physical layer circuitry, and the second marker end identifier is used to indicate the position of the end bit of the second control bitstream. A random bitstream is used to allow the serializer / deserializer clock and data recovery CDR circuitry to remain locked, and the random bitstream contains a balanced amount of 0s and 1s. A bitstream detection circuitry is further configured to discard the random bitstream when it is identified. For the beneficial effects of this design, see the description of the first embodiment.

[0021] According to the third aspect, a data transmission method is provided and applied to a high-speed serial interface. The high-speed serial interface includes a physical layer circuit at the transmitting end. The method includes the step that when the transmitting end is not transmitting service data, the transmitting end transmits a first control bit stream, where the first control bit stream is used to indicate that the transmitting end has turned off a partial module in the physical layer circuit of the transmitting end, or the first control bit stream is used to indicate that the transmitting end turns off a partial module in the physical layer circuit of the transmitting end, or the first control bit stream is used to indicate to the receiving end to turn off a partial module in the physical layer circuit of the receiving end. The transmitting end turns off a partial module in the physical layer circuit of the transmitting end. The transmitting end transmits a random bit stream.

[0022] For the beneficial effects of the third aspect, please refer to the description of the first aspect.

[0023] In one possible design, the partial module in the physical layer circuit of the transmitting end includes at least one of a forward error correction FEC encoding circuit or a scrambling circuit, and the partial module in the physical layer circuit of the receiving end includes at least one of a FEC decoding circuit or a descrambling circuit.

[0024] In one possible design, the high-speed serial interface further includes a partial module in the data link layer of the transmitting end, and the fact that the transmitting end is not transmitting service data includes that when the data link layer of the transmitting end is not transmitting service data to the physical layer circuit of the transmitting end, it is determined that the transmitting end is not transmitting service data.

[0025] In one possible design, the high-speed serial interface further includes a serializer / deserializer, and the method includes, when the transmitting end resumes transmission of service data, the transmitting end transmitting a second control bit stream, where the second control bit stream is used to indicate that the transmitting end has turned on a sub-module within the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate that the transmitting end turns on a sub-module within the physical layer circuit of the transmitting end, or the second control bit stream is used to indicate to the receiving end to turn on a sub-module within the physical layer circuit of the receiving end. The transmitting end turns on a sub-module within the physical layer circuit of the transmitting end. The transmitting end controls the physical layer circuit of the transmitting end to transmit service data to the serializer / deserializer.

[0026] In one possible design, the first control bitstream includes multiple repeating bitstream identifiers, a first marker end identifier, and a first bitstream content, the first bitstream content being used to indicate that the transmitting end has turned off a subset module in the transmitting end's physical layer circuitry, or the first control bitstream is used to indicate that the transmitting end is turning off a subset module in the transmitting end's physical layer circuitry, or the first control bitstream is used to indicate to the receiving end to turn off a subset module in the receiving end's physical layer circuitry, and the first marker end identifier is used to indicate the position of the end bit of the first control bitstream. The second control bitstream includes multiple repeating bitstream identifiers, a second marker end identifier, and a second bitstream content, the second bitstream content being used to indicate that the transmitting end has turned on a subset module in the transmitting end's physical layer circuitry, or the second control bitstream is used to indicate that the transmitting end is turning on a subset module in the transmitting end's physical layer circuitry, or the second control bitstream is used to indicate to the receiving end to turn on a subset module in the receiving end's physical layer circuitry, and the second marker end identifier is used to indicate the position of the end bit of the second control bitstream. The random bitstream is used to allow the serializer / deserializer clock and data recovery CDR circuitry to be locked, and the random bitstream contains a balanced amount of 0s and 1s.

[0027] According to a fourth aspect, a data transmission method is provided which is applied to a high-speed serial interface. The high-speed serial interface includes a physical layer circuit at the receiving end. The method includes the step of the receiving end receiving a first control bitstream, the first control bitstream being used to indicate that the transmitting end has turned off a submodule in the transmitting end's physical layer circuit, or the first control bitstream being used to indicate that the transmitting end will turn off a submodule in the transmitting end's physical layer circuit, or the first control bitstream being used to indicate to the receiving end to turn off a submodule in the receiving end's physical layer circuit. The receiving end turns off a submodule in the receiving end's physical layer circuit. The receiving end receives a random bitstream.

[0028] For the beneficial effects of the fourth embodiment, please refer to the description of the second embodiment.

[0029] In one possible design, several modules in the physical layer circuit at the receiving end include at least one of either a forward error correction (FEC) coding circuit or a scrambling circuit, and a sub-module in the physical layer circuit at the receiving end includes at least one of either an FEC decoding circuit or a descrambling circuit.

[0030] In one possible design, the high-speed serial interface further includes a serializer / deserializer, and the method further includes the step of controlling the serializer / deserializer so that the receiving end receives a second control bitstream, the second control bitstream being used to indicate that the transmitting end has turned on a partial module in the transmitting end's physical layer circuitry, or the second control bitstream being used to indicate that the transmitting end will turn on a partial module in the transmitting end's physical layer circuitry, or the second control bitstream being used to indicate to the receiving end to turn on a partial module in the receiving end's physical layer circuitry. The receiving end turns on a partial module in the receiving end's physical layer circuitry. The receiving end controls its physical layer circuitry to receive the service data transmitted through the serializer / deserializer.

[0031] In one possible design, the first control bitstream includes multiple repeating marker identifiers, a first marker end identifier, and a first bitstream content, the first bitstream content being used to indicate that the transmitting end has turned off a subset module in the transmitting end's physical layer circuitry, or the first control bitstream is used to indicate that the transmitting end is turning off a subset module in the transmitting end's physical layer circuitry, or the first control bitstream is used to indicate that the receiving end should turn off a subset module in the receiving end's physical layer circuitry, and the first marker end identifier is used to indicate the position of the end bit of the first control bitstream. The second control bitstream includes a plurality of repeating marker identifiers, a second marker end identifier, and a second bitstream content, the second bitstream content being used to indicate that the transmitting end has turned on a subset of the physical layer circuitry at the transmitting end, or the second control bitstream is used to indicate that the transmitting end is turning on a subset of the physical layer circuitry at the transmitting end, or the second control bitstream is used to indicate to the receiving end to turn on a subset of the physical layer circuitry at the receiving end, and the second marker end identifier is used to indicate the position of the end bit of the second control bitstream. A random bitstream is used to allow the serializer / deserializer clock and data recovery CDR circuitry to remain locked, and the random bitstream contains a balanced amount of 0s and 1s. The method further includes the step of discarding the random bitstream when it is identified.

[0032] According to a fifth aspect, a communication device is provided, the communication device including at least one processor. The at least one processor is connected to memory, and the at least one processor is configured to read and execute a program stored in memory, so that the device performs a method corresponding to any one of the third aspect or a possible design of the third aspect, or a method according to any one of the fourth aspect or a possible design of the fourth aspect.

[0033] According to the sixth aspect, a chip is provided. The chip is coupled to memory and configured to read and execute program instructions stored in memory, and to perform a method corresponding to either the third aspect or a possible design of the third aspect, or a method according to either the fourth aspect or a possible design of the fourth aspect.

[0034] According to a seventh aspect, the present application provides a chip system for use in a cloud center. The chip system includes one or more interface circuits and one or more processors. The interface circuits and processors are interconnected via a line. The interface circuits are configured to receive signals from the memory of the cloud center and transmit signals to the processors. The signals include computer instructions stored in the memory. When the processors execute the computer instructions, the cloud center performs a data transmission method provided in the first aspect or a corresponding possible design of the first aspect.

[0035] According to the eighth aspect, an embodiment of the present application provides a serial interface circuit. The circuit is included in an electronic device, and the device has the function of performing the behavior of the electronic device in any of the preceding aspects or any possible embodiments thereof. This function may be implemented by hardware or by hardware running corresponding software.

[0036] According to the ninth aspect, a computer-readable storage medium is provided, which includes computer instructions. When the computer instructions are executed on an electronic device, the electronic device becomes capable of performing a method according to the third aspect or a possible design of the third aspect.

[0037] According to the tenth aspect, a computer-readable storage medium is provided, which includes computer instructions. When the computer instructions are executed on an electronic device, the electronic device becomes capable of performing a method according to the third aspect or a possible design of the third aspect.

[0038] The corresponding methods provided above may be applied to any one of the high-speed serial interfaces, communication devices, chip systems, computer-readable storage media, or computer program products provided above. Therefore, for the beneficial effects that can be achieved by the high-speed serial interfaces, communication devices, chip systems, computer-readable storage media, or computer program products, please refer to the beneficial effects of the corresponding methods. Details will not be repeated here.

[0039] These or other aspects of this application are made clearer and easier to understand in the following description. [Brief explanation of the drawing]

[0040] [Figure 1] This is a schematic diagram of an application architecture for a high-speed serial interface according to one embodiment of this application. [Figure 2] This is a schematic diagram of the signal flow according to one embodiment of the present application, in which the DL, PHY, and SerDes on one side communicate with the peer side of the link in the transmit and receive directions. [Figure 3A] This is a schematic diagram of a high-speed serial interface circuit at the transmitting end according to one embodiment of this application. [Figure 3B]This is a schematic diagram of a high-speed serial interface circuit at the transmitting end according to one embodiment of this application. [Figure 4] This is a schematic diagram of a high-speed serial interface circuit at the receiving end according to one embodiment of this application. [Figure 5] This is a schematic diagram of a high-speed serial interface circuit at the transmitting end according to one embodiment of this application. [Figure 6] This is a schematic diagram of a high-speed serial interface circuit at the receiving end according to one embodiment of this application. [Figure 7] This is a schematic flowchart of a data transmission method applied to a transmitting end according to one embodiment of this application. [Figure 8] This is a schematic flowchart of a data transmission method applied to a receiving end according to one embodiment of this application. [Figure 9] This is a schematic flowchart for turning off PL_TX and PL_RX according to one embodiment of this application. [Figure 10] This is a schematic flowchart of a data transmission method applied to a transmitting end according to one embodiment of this application. [Figure 11] This is a schematic flowchart of a data transmission method applied to a receiving end according to one embodiment of this application. [Figure 12] This is a schematic flowchart for turning on PL_TX and PL_RX according to one embodiment of this application. [Figure 13] This is a schematic diagram of the structure of a network device according to one embodiment of this application. [Modes for carrying out the invention]

[0041] For the sake of ease of understanding, several concepts related to the embodiments of this application are described below as examples for reference.

[0042] Serializer / Deserializer (SerDes): A time-division multiplexing (TDM) and point-to-point (P2P) serial communication technology. Multiple low-speed parallel signals are converted into high-speed serial signals at the SerDes transmitting end. The high-speed serial signals travel through a transmission medium (optical cable or copper wire). Finally, the high-speed serial signals are converted back into low-speed parallel signals at the SerDes receiving end. This point-to-point serial communication technology significantly reduces communication costs because it fully utilizes the channel capacity of the transmission medium, reduces the number of transmission channels and device pins used, and improves signal transmission speed.

[0043] Peripheral Component Interface Express (PCIe): High-bandwidth, high-speed serial point-to-point dual-channel transmission. Devices connected via PCIe are allocated exclusive channel bandwidth, and devices do not share bus bandwidth. PCIe primarily supports active power management, error reporting, end-to-end reliable transmission, hot-swapping, Quality of Service (QoS), and other features.

[0044] Hamming codes (Bose Ray-Chaudhuri Hocquenghem, BCH): A widely studied coding method among error correction codes, used for multi-level, cyclic, error correction, and variable-length digital codes of multiple random error patterns.

[0045] The following describes the technical solutions of the embodiments of this application with reference to the accompanying drawings of the embodiments of this application. In the description of the embodiments of this application, " / " means "or" unless otherwise specified. For example, A / B may mean A or B. The term "and / or" in this specification describes only the relationship between the relevant objects and indicates that three relationships may exist. For example, A and / or B may mean the following three cases: that only A exists, that both A and B exist, and that only B exists. In addition, in the description of the embodiments of this application, "multiple" means two or more.

[0046] The terms “first” and “second” used herein are intended solely for illustrative purposes and should not be understood as indicating or implying relative importance, or as an implicit indication of the quantity of the technical features described. Thus, features limited by “first” or “second” may explicitly or implicitly include one or more features. In the description of embodiments, “multiple” means two or more unless otherwise specified.

[0047] The PCIe specification defines low-power states such as L0s, L1, and L2. When no service packets are transmitted over the link for a certain period of time, a low-power state is initiated to reduce the link's power consumption.

[0048] Specifically, L0s indicates that the local transmitter (Transmitter, TX) and peer receiver (Receiver, RX) pair enter or exit a low-power state, with a delay of a few microseconds. L1 indicates that the low-power state has been exited simultaneously in both the TX and RX directions, with a delay of several tens of microseconds. L1 consumes significantly less power than L0s, and L2 consumes even less power than L1. The L1 low-power state is used as an example. The operational process for a link to enter a low-power state may be as follows:

[0049] (1) The PCIe power management module monitors whether transaction layer packets (TLPs) are transmitted in either the transmit or receive direction of the link within a duration T.

[0050] (2) After determining that T is greater than the configured threshold, the PCIe power management module determines to initiate the process of entering the L1 low-power state.

[0051] (3) The PCIe power management module sends a request to enter the L1 low-power state to the PCIe physical layer.

[0052] (4) After receiving a request from the power management module, the PCIe physical layer negotiates with the peer device to enter the L1 low-power state. In the L1 state, the PCIe physical layer, as well as the PCIe SerDes TX and RX, are in a low-power state.

[0053] (5) After determining that the process of negotiating with the peer device to enter the L1 low-power state is complete, the PCIe physical layer reports to the PCIe power management module that it has successfully entered the L1 low-power state.

[0054] (6) After receiving an instruction that the physical layer has entered the L1 state, the PCIe power management module instructs the PCIe controller to enter the L1 low-power state.

[0055] The L1 low-power state is still used as an example. The operational process for exiting the low-power state may be as follows:

[0056] (1) The PCIe power management module monitors whether a TLP request is being sent in the transmit direction of the link.

[0057] (2) Upon detecting that a TLP has been transmitted, the PCIe power management module initiates the process of exiting the L1 low-power state.

[0058] (3) The PCIe power management module sends a request to exit the L1 low-power state to the PCIe physical layer.

[0059] (4) After receiving a request from the PCIe power management module, the PCIe physical layer negotiates with the peer device as it exits the L1 low-power state. In this process, the PCIe physical layer controls both the TX and RX of the PCIe SerDes. This is equivalent to both the PCIe physical layer and the SerDes exiting the low-power state.

[0060] (5) After completing the process of negotiating with the peer device when exiting the L1 low-power state, the PCIe physical layer reports to the power management module an instruction indicating that it has successfully entered the L0 low-power state.

[0061] (6) After receiving an instruction that the PCIe physical layer has entered the L0 low-power state, the PCIe power management module also instructs the PCIe controller to enter the L0 low-power state.

[0062] First, from the processes entering and exiting the L1 low-power state, it is clear that the PCIe physical layer and PCIe controllers, including SerDes, must have a period of inactivity before entering the low-power state. This period is typically a few microseconds or milliseconds. However, if the interval for transmitting service data is shorter than this, the low-power mechanism will not be effective, and the link's power consumption will still not be reduced.

[0063] In addition, the PCIe protocol requires that invalid IDLE data be inserted in the TX direction for data padding when service data is not transmitted over the link within a short period of time. However, IDLE data still passes through circuits such as the physical layer FEC circuit and scrambling circuit, which still cause high power consumption, and the power consumption of the link cannot be reduced.

[0064] In addition, with PCIe, when the PCIe controller enters or exits a low-power state, the SerDes within the PCIe controller also enters a low-power state. Therefore, the delay in entering and exiting the low-power state is significant, typically tens of microseconds. Furthermore, when a link enters or exits a low-power state, service data is blocked. If the link frequently enters and exits a low-power state, the high-speed input / output (I / O) interface of the SerDes within the link is frequently used for the switching process and cannot transmit service data. This affects the performance of the high-speed I / O interface to some extent, and high-speed switching cannot be performed.

[0065] Therefore, this application provides a high-speed serial interface. For example, the high-speed serial interface may be used in particular with PCIe, Ethernet, or other network architectures.

[0066] In this application, when the transmitting end transmits service data, a monitor in the high-speed serial interface may monitor whether the service data is still being transmitted at the physical layer. If it determines that no service data is being transmitted, the monitor triggers a clock gating circuit to stop transmitting a clock signal to a submodule in the transmitting end's physical layer circuit. This is equivalent to turning off the submodule in the transmitting end's physical layer circuit. In addition, a control bitstream generation circuit is triggered to generate a first control bitstream. The first control bitstream acts as a switch to execute instructions to a submodule in the physical layer circuit of the remote end, i.e., the receiving end, and is used to indicate that the submodule in the receiving end's physical layer circuit should be turned off. Upon detecting the first control bitstream, the receiving end's bitstream detection circuit also triggers the receiving end's clock gating circuit to turn off the submodule in the receiving end's physical layer circuit. In this method, where the clock gating circuit and control bitstream are used to bring the submodules in the transmitting end's physical layer circuit and the receiving end's physical layer circuit into a low-power state, the response speed is typically several nanoseconds. Compared to conventional technologies that require several microseconds or milliseconds to enter low-power states such as L1 or L0s in PCIe, the response speed is significantly slower, resulting in a substantial reduction in link power consumption.

[0067] Similarly, in this application, the process of exiting a low-power state and entering normal service data transmission may be carried out using a second control bitstream. Thus, the switching time spent exiting a low-power state and entering normal service data transmission is shorter than the time spent exiting an L1 or L0s low-power state in PCIe, resulting in a faster response time.

[0068] In addition, in the high-speed serial interface of this application, when the clock gating circuit at the transmitting end does not transmit a clock signal to the physical layer circuit at the transmitting end, a submodule in the physical layer circuit at the transmitting end may be turned off. This includes the FEC coding circuit, scrambling circuit, etc., in the physical layer circuit at the transmitting end being turned off and not functioning properly. When the clock gating circuit at the receiving end does not transmit a clock signal to a submodule in the physical layer circuit at the receiving end, the submodule in the physical layer circuit at the receiving end is turned off. This includes the FEC decoding circuit, descrambling circuit, etc., in the physical layer at the receiving end being turned off and not functioning properly. In existing PCIe protocols, when service data is not transmitted in a low-power state, IDLE data is still inserted in the transmit direction and passes through the FEC circuit, scrambling / descrambling circuit, etc. This still causes high power consumption. However, in this application, the submodules in the physical layer circuit at the transmitting end and the submodules in the physical layer circuit at the receiving end cannot function properly. This includes the FEC circuit, scrambling / descrambling circuit, etc., in the physical layer not functioning properly. Therefore, the power consumption of the link can be significantly reduced.

[0069] In addition, in conventional PCIe, when the link enters a low-power operating state, the SerDes within the link also enter a low-power state. However, in this application, after the first control bitstream has been transmitted and the physical layer circuit has been turned off, the transmitter circuit of the SerDes may still be operational and continue to transmit a random bitstream. Naturally, the receiver circuit of the SerDes at the receiving end may also be operational and continue to receive a random bitstream. This ensures that the Clock and Data Recovery (CDR) circuit within the SerDes remains in a stable locked state, thereby reducing the impact on high-speed I / O performance.

[0070] It should be understood that the high-speed serial interface in this application includes a receiver circuit and a transmitter circuit. When there are high-speed serial interfaces on both sides for transmitting service data, the transmitter circuit of one side of the high-speed serial interface may cooperate with the receiver circuit of the other side of the high-speed serial interface.

[0071] In some embodiments, as shown in Figure 1, the high-speed serial interface on one side may be included in the system-on-a-chip (SoC), and the high-speed serial interface on the other side may be included in a network interface card, such as an Ethernet network interface card. The SoC may be connected to the network interface card via the high-speed serial interface. Service data may be transmitted between the SoC and the network interface card, and the SoC may communicate with an external network using the network interface card.

[0072] As shown in Figure 1, the high-speed serial interface is integrated into the SoC's I / O controller and connected to the SoC's system bus. The central processing unit (CPU), direct memory access controller (DMAC), memory, and other components are further connected to the system bus.

[0073] In some embodiments, the high-speed serial interface of the SoC is considered in this application to be the high-speed serial interface at the transmitting end. This is equivalent to an improvement in the physical layer circuitry in the high-speed serial interface. Based on the fact that the high-speed serial interface of the SoC includes application layer (AP) / transport layer (TL) / data link layer (DL), physical layer (PHY), and SerDes circuitry, monitor, clock gating circuitry, control bitstream generation circuitry, and other circuitry are added to the high-speed serial interface.

[0074] Similarly, the network interface card also includes a high-speed serial interface, which is integrated into the SoC's I / O controller. The high-speed serial interface within the network interface card can also be considered as the high-speed serial interface at the receiving end, and the high-speed serial interface at the receiving end is also improved. Based on the fact that the high-speed serial interface controller within the network interface card includes AP / TL / DL, PHY, and SerDes, clock gating circuits, bitstream detection circuits, etc., are added.

[0075] A high-speed serial interface within the SoC can be connected to an external network interface card via SerDes within the high-speed serial interface, thereby configuring a chip system with a high-speed I / O interface.

[0076] It should be understood that a high-speed serial interface within an SoC may function as a substitute high-speed serial interface at the receiving end, and a high-speed serial interface within a network interface card may function as a substitute high-speed serial interface at the transmitting end. Specifically, the high-speed serial interface of an SoC includes a high-speed serial interface at both the transmitting and receiving ends, and the high-speed serial interface of a network interface card includes a high-speed serial interface at both the transmitting and receiving ends.

[0077] The following further describes the system framework, including the DL and PHY in the high-speed serial interface at the transmitting end and the DL and PHY in the high-speed serial interface at the receiving end. See Figure 2. Understand that the transmitting end also includes receiver circuitry, and the receiving end also includes transmitter circuitry. Figure 2 shows the signal flow as the DL, PHY, and SerDes on one side communicate with the peer side of the link in the transmitting and receiving directions. The DL data path includes two directions, DL_TX and DL_RX. The PHY data path also includes two directions, PL_TX and PL_RX. The PHY includes high-power circuits such as FEC circuits and scrambling / descrambling circuits. DL_TX is a submodule of the data link layer at the transmitting end, and specifically may be the transmitter circuit of the data link layer at the transmitting end. DL_RX is a submodule of the data link layer at the receiving end, and specifically may be the receiver circuit of the data link layer at the receiving end. PL_TX is a submodule in the physical layer circuitry at the transmitting end, and specifically may be the transmitter circuitry in the physical layer circuitry at the transmitting end. PL_RX is a submodule within the physical layer circuit at the receiving end, and specifically, it may be a receiver circuit within the physical layer circuit at the receiving end. PL_TX may receive data from DL_TX, which is encoded by an FEC encoding circuit or scrambling circuit within the PHY, and then the encoded data is sent to SerDes. PL_RX may receive data from the peer's SerDes, which is decoded by a descrambling circuit within the PHY, and then the decoded data is sent to the peer's DL_RX for further processing.

[0078] It should be noted that in this application, the transmitter circuit (PL_TX) in the physical layer circuit at the transmitting end is not limited to including only the FEC coding circuit and the scrambling circuit, but may further include other power-consuming transmitter circuits. Similarly, in this application, the receiver circuit (PL_RX) in the physical layer circuit at the receiving end is not limited to including only the FEC decoding circuit and the descrambling circuit, but may further include other power-consuming receiver circuits. For example, the transmitter circuit in the physical layer circuit at the transmitting end may further include a data distribution circuit, and the receiver circuit in the physical layer circuit at the receiving end may further include a symbol lock circuit, a deskew circuit, and so on.

[0079] This application relates to improvements to the peripheral circuits of the PHY. At the transmitting end, monitors, clock gating circuits, control bitstream generation circuits, etc., are added to the peripheral circuits of the PHY. At the receiving end, bitstream detection circuits, clock gating circuits, etc., are added to the peripheral circuits of the PHY.

[0080] In some embodiments, a random bitstream generation circuit is added around the PHY at the transmitting end and configured to generate a random bitstream.

[0081] The high-speed serial interface at the transmitting end in this application will be described first. The high-speed serial interface includes a data link layer circuit at the transmitting end, a physical layer circuit at the transmitting end, a monitor, a clock gating circuit, a control bitstream generation circuit, a random bitstream generation circuit, and a serializer / deserializer, and further includes the following circuits. Figure 3A is a schematic diagram of the structure of the high-speed serial interface at the transmitting end.

[0082] The monitor is configured to indicate to the clock gating circuit that when the transmitting end is not transmitting service data, it will stop transmitting the clock signal to the submodule in the transmitting end's physical layer circuit.

[0083] The clock gating circuit is configured to stop the transmission of the clock signal to a submodule within the physical layer circuit at the transmitting end.

[0084] The control bitstream generation circuit is configured to transmit a first control bitstream via the serializer / deserializer when it determines that the clock gating circuit has stopped transmitting the clock signal, the first control bitstream being used to indicate that the transmitting end has turned off a submodule in the transmitting end's physical layer circuit, or the first control bitstream being used to indicate that the transmitting end will turn off a submodule in the transmitting end's physical layer circuit, or the first control bitstream being used to indicate to the receiving end to turn off a submodule in the receiving end's physical layer circuit. This is equivalent to the first control bitstream not passing through the submodule in the transmitting end's physical layer circuit after the submodule in the transmitting end's physical layer circuit has been turned off.

[0085] The random bitstream generation circuit is configured to send the random bitstream to a serializer / deserializer. This is equivalent to the random bitstream not passing through the submodule in the physical layer circuit at the transmitting end after the submodule in the physical layer circuit at the transmitting end is turned off.

[0086] Thus, when the transmitting end is not transmitting service data, a submodule in the physical layer circuitry of the transmitting end's high-speed serial interface is turned off, and the transmitting end also transmits a first control bitstream to indicate that the transmitting end has turned off a submodule in the transmitting end's physical layer circuitry, or the first control bitstream is used to indicate that the transmitting end is turning off a submodule in the transmitting end's physical layer circuitry, or the first control bitstream is used to indicate to the receiving end that it should turn off a submodule in the receiving end's physical layer circuitry. This is equivalent to the receiving end also being able to turn off its physical layer circuitry when it determines that there is no service data to send to the transmitting end, in order to reduce power consumption at both the transmitting and receiving ends. In this application, a random bitstream may be transmitted to keep the serializer / deserializer, i.e., SerDes, in the high-speed serial interface operational.

[0087] For example, as shown in Figure 3B, the submodule within the physical layer circuit at the transmitting end is the transmitter circuit within the physical layer circuit at the transmitting end, i.e., PL_TX.

[0088] In this case, the monitor monitors whether DL_TX is sending service data to PL_TX, and if it determines that DL_TX is not sending service data to PL_TX, the clock gating circuit (CLK_GAT) is configured to stop sending the clock signal to PL_TX as shown below. The clock gating circuit is configured to stop the transmission of the clock signal to PL_TX. The control bitstream generation circuit (marker insert) is configured to transmit a first control bitstream when it determines that the clock gating circuit has stopped transmitting the clock signal, and the first control bitstream is used to indicate to the service data receiving end that PL_RX should be turned off.

[0089] In some embodiments, a multiplexer circuit (MUX) is further included and configured to choose to output service data or to output a first control bitstream when it receives an instruction indicating that it will output a first control bitstream.

[0090] When the clock gating circuit is configured to stop sending the clock signal to PL_TX, this is equivalent to stopping the transmission of the pulse signal used to send service data to PL_TX. If PL_TX does not receive the clock signal, the FEC encoding and scrambling circuits within PL_TX cannot function properly, and PL_TX will not output service data to MUX.

[0091] Therefore, if it is determined that DL_TX is not sending service data to PL_TX, the high-speed serial interface at the generating end may use a clock gating circuit to turn off PL_TX. In addition, the control bitstream generation circuit may also generate a first control bitstream indicating that PL_RX should be turned off at the receiving end.

[0092] It should be noted in this application that the transmission of the clock signal may be stopped in order to turn off some corresponding modules. In other words, stopping the transmission of the clock signal to a partial module is equivalent to turning off the partial module.

[0093] For example, a clock gating circuit stops transmitting a clock signal in order to turn off a subset of the physical layer circuit at the transmitting end. In other words, when a clock gating circuit stops transmitting a clock signal to a subset of the physical layer circuit at the transmitting end, it is equivalent to turning off that subset of the physical layer circuit at the transmitting end.

[0094] In response to this, the high-speed serial interface of the receiving end in this application is further described.

[0095] At the receiving end, as shown in Figure 4(a), the high-speed serial interface includes a data link layer circuit at the receiving end, a physical layer circuit at the receiving end, a bitstream detection circuit, a clock gating circuit, and a serializer / deserializer. The bitstream detection circuit is configured to receive a first control bitstream via the serializer / deserializer, which is used to indicate that the transmitting end has turned off a submodule in the transmitting end's physical layer circuit, or the first control bitstream is used to indicate that the transmitting end will turn off a submodule in the transmitting end's physical layer circuit, or the first control bitstream is used to indicate to the receiving end to turn off a submodule in the receiving end's physical layer circuit.

[0096] The bitstream detection circuit is further configured to stop the transmission of the clock signal to the submodule in the physical layer circuit at the receiving end, as shown in the clock gating circuit.

[0097] The clock gating circuit is configured to stop the transmission of the clock signal to the submodule in the physical layer circuit at the receiving end.

[0098] The bitstream detection circuit is further configured to receive a random bitstream via a serializer / deserializer.

[0099] For example, as shown in Figure 4(b), a submodule in the physical layer circuit within the high-speed serial interface at the receiving end includes PL_RX at the receiving end, and the high-speed serial interface further includes DL_RX, a bitstream detection circuit (marker check), and a clock gating circuit at the receiving end.

[0100] The bitstream detection circuit is configured, as shown in the clock gating circuit, to stop transmitting the clock signal to PL_RX when the first control bitstream is received and used to indicate that the first control bitstream is turning off PL_RX.

[0101] The clock gating circuit is configured to stop the transmission of the clock signal to PL_RX.

[0102] The bitstream detection circuit is further configured to receive a random bitstream via SerDes, and the random bitstream does not pass through PL_RX at the receiving end.

[0103] Specifically, if a first control bitstream indicating that PL_RX should be turned off is received at the receiving end's high-speed serial interface, the clock gating circuit will no longer send a clock signal to PL_RX. When the clock gating circuit stops sending a clock signal to PL_RX, this is equivalent to skipping sending the pulse signal used to receive service data to PL_RX. If PL_TX does not receive a clock signal, the FEC decoding and descrambling circuits within PL_RX cannot operate correctly, and PL_RX will no longer output service data to DL_RX.

[0104] It should be noted in this application that the transmission of the clock signal may be stopped in order to turn off some corresponding modules. In other words, stopping the transmission of the clock signal to a partial module is equivalent to turning off the partial module.

[0105] For example, a clock gating circuit stops transmitting the clock signal in order to turn off a subset of the physical layer circuit at the receiving end. In other words, the clock gating circuit stopping the transmission of the clock signal to a subset of the physical layer circuit at the receiving end is equivalent to turning off that subset of the physical layer circuit at the receiving end.

[0106] Thus, in this application, if it is determined that there is no service data to be transmitted over the link in a short period of time, the high-speed serial interface can be controlled to turn off the PL_TX at the transmitting end and the PL_RX at the receiving end. For example, high-power circuits such as the FEC circuit and scrambling circuit in PL_TX, and high-power circuits such as the FEC circuit and descrambling circuit in PL_RX are turned off. This reduces the power consumption of the link.

[0107] In addition, in this application, the first control bitstream is used to indicate PL_RX, which should also be turned off, based on the fact that PL_TX at the transmitting end is turned off. The first control bitstream then acts as a switch to indicate that the circuit is turned off. Compared to existing PCIe protocols, etc., where the delay to enter or exit a low-power state is several microseconds or several milliseconds, the response speed of the switch used in this application can be several nanoseconds, which is fast.

[0108] Figure 5 shows the high-speed serial interface at the transmitting end, based on the high-speed serial interfaces shown in Figures 3A, 3B, and 4. The high-speed serial interface at the transmitting end further includes a SerDes TX, i.e., a transmitter circuit for the SerDes, configured to output service data or a first control bitstream.

[0109] In some embodiments, after the transmitting end has completed transmitting a first control bitstream, the high-speed serial interface of the transmitting end may further include a random bitstream generation circuit configured to generate a random bitstream so that the CDR circuit in the SerDes is locked, in order to ensure that the SerDes transmits data continuously and does not fail. The random bitstream contains balanced quantities of 0s and 1s.

[0110] In this application, the locked state of the CDR circuit within the SerDes can be understood as the CDR circuit within the SerDes remaining in a data transmission state and not entering a low-power state. At the transmitting end, the locked state of the CDR circuit within the SerDes can be understood as the CDR circuit within the SerDes being configured to transmit data continuously, for example, service data, a first control bitstream, or a random bitstream. At the receiving end, the locked state of the CDR circuit within the SerDes can be understood as the CDR circuit within the SerDes being configured to receive data continuously, for example, service data, a first control bitstream, or a random bitstream.

[0111] Specifically, as shown in Figure 5, the first end a of DL_TX is connected to the first end b of PL_TX, the second end c of PL_TX is connected to the first end d of the MUX circuit, the first end e of the monitor is connected between the first end a and the first end b, the second end f of the monitor is connected to the first end g of the clock gating circuit, the second end h of the clock gating circuit is connected to the third end i of PL_TX, the first end j of the control bitstream generation circuit is connected to the second end k of the MUX circuit, the first end l of the random bitstream generation circuit is connected to the third end m of the MUX circuit, the third end n of the monitor is connected to the fourth end o of the MUX, and the fifth end p of the MUX is connected to the first end q of SerDes TX, establishing a link between the output end of SerDes TX and the receiving end SerDes RX.

[0112] DL_TX is a transmit-direction circuit in the data link layer and is configured to send service data to PL_TX.

[0113] PL_TX is a physical layer transmit-direction circuit that receives service data from DL_TX, encodes the service data using FEC and scrambling circuits within PL_TX, and then transmits the encoded service data to SerDes TX via the MUX circuit.

[0114] The clock gating circuit is configured to perform gating for the clock input to each module in PL_TX. For example, it indicates that the clock gating circuit should be turned on when the enable value of the input clock signal is 1, or that the clock gating circuit should be turned off when the enable value of the input clock signal is 0.

[0115] The monitor is configured to check whether DL_TX is sending service data to PL_TX.

[0116] The control bitstream generation circuit is configured to insert a marker indicating that the circuit is off into the data to be transmitted when it is determined that PL_TX is off, or to insert a marker indicating that the circuit is on when it is determined that PL_TX is on, and to transmit data to SerDes TX via the MUX circuit so that the receiving end can identify the operation of turning the physical layer circuit on or off.

[0117] The random bitstream generation circuit is configured to send an invalid random bitstream to SerDes TX via MUX if it determines that the local PL_TX is turned off.

[0118] SerDes TX is the SerDes transmit direction circuit, configured to convert the parallel data transmitted by PL_TX into a serial bitstream and transmit the serial bitstream to the link.

[0119] Based on the above description of the high-speed serial interface at the transmitting end, the process of transmitting data via the high-speed serial interface at the transmitting end includes the following processes:

[0120] (1) DL_TX sends service data to PL_TX.

[0121] (2) PL_TX performs physical layer coding such as FEC coding and byte distribution on the service data, scrambles the service data using a scrambling circuit, and then sends the processed service data to the MUX circuit, which in turn sends the processed service data to the receiving end via SerDes TX.

[0122] (3) If the monitor determines that DL_TX is not sending service data, the monitor instructs the clock gating circuit to stop sending a clock signal to PL_TX and triggers the control bitstream generation circuit to send a first control bitstream to SerDes TX via the MUX circuit.

[0123] (4) When the monitor determines that the transmission of the first control bitstream is complete, it triggers the random bitstream generation circuit to transmit a random bitstream, specifically by sending the random bitstream to SerDes TX via MUX.

[0124] Correspondingly, based on the high-speed serial interfaces shown in Figures 3 and 4, Figure 6 shows the high-speed serial interface at the receiving end. The high-speed serial interface at the receiving end further includes a SerDes RX, i.e., a receiver circuit for the SerDes, configured to receive service data, a first control bitstream, random bitstreams, etc.

[0125] Specifically, as shown in Figure 6, the first end a' of SerDes RX is coupled to the first end b' of the bitstream detection circuit, the second end c' of the bitstream detection circuit is coupled to the first end d' of PL_RX, the second end e' of PL_RX is coupled to the first end f' of DL_RX, the third end g' of the bitstream detection circuit is coupled to the first end h' of the clock gating circuit, and the second end i' of the clock gating circuit is coupled to the third end j' of PL_RX.

[0126] The SerDes RX is configured to receive serial data from the link, perform serial-to-parallel conversion, and send the parallel data to PL_RX via a bitstream detection circuit.

[0127] The bitstream detection circuit is configured to detect whether the bitstream output by the SerDes RX contains a control bitstream indicating whether to turn the circuit on or off, and to decide whether to turn PL_RX on or off based on the control bitstream.

[0128] The clock gating circuit is configured to perform gating on the clock signals input to each module in PL_RX, so that the clock signals indicate whether PL_RX should be turned on or off. For example, an enable value of 1 for the input clock signal indicates that the PL_RX circuit should be turned on, or an enable value of 0 indicates that the PL_RX circuit should be turned off.

[0129] PL_RX is a physical layer receiving module configured to receive service data transmitted by SerDes RX via a bitstream detection circuit, perform physical layer decoding and descrambling on the service data, and then transmit the processed service data to DL_RX.

[0130] DL_RX is a receive-direction module in the data link layer, configured to receive and process service data output by PL_RX.

[0131] Based on the above description of the high-speed serial interface at the receiving end, the process of receiving data via the high-speed serial interface at the receiving end includes the following processes:

[0132] (1) The SerDes RX receives the serial data transmitted by the transmitting end, converts the serial data into parallel data, and transmits the parallel data to the bitstream detection circuit.

[0133] (2) The bitstream detection circuit detects the received data and, if service data is detected, sends the service data to the PL_RX circuit; or, if the first control bitstream is detected, triggers the clock gating circuit to stop the transmission of the clock signal to the PL_RX circuit; or, if a random bitstream is detected, discards the random bitstream.

[0134] (3) The bitstream detection circuit sends service data to the PL_RX circuit. The PL_RX circuit performs descrambling, FEC decoding, etc. on the service data and sends the processed data to DL_RX.

[0135] Therefore, in this application, when no service data is currently being transmitted over the link, the high-speed serial interface may control the PL at the transmitting end and the PL at the receiving end to reduce the power consumption of the link. In addition, in this application, a control bitstream is used to indicate whether a circuit is on or off, and as a result, the response speed can be increased. Furthermore, in this application, after the transmission of the control bitstream is complete, a random bitstream may be transmitted to ensure that the CDR in the transmitting end SerDes and the receiving end SerDes in the high-speed serial interface are in a stable locked state, and as a result, there is no possibility of interface bit errors and other problems occurring.

[0136] If a first control bitstream is transmitted to turn off the physical layer circuit of the peer end in response to a process that reduces power consumption, a second control bitstream may be transmitted to turn on the physical layer circuit of the peer end when the transmission of service data is resumed. Referring to embodiments of the transmitting and receiving end circuits of the high-speed serial interface in this application, the processes for turning off PL_TX and PL_RX, and for turning on PL_TX and PL_RX, will be further described below.

[0137] A: This application provides a data transmission method. As shown in Figure 7, the method is applied to a high-speed serial interface at the transmitting end. The high-speed serial interface includes physical layer circuitry. The method includes the following steps:

[0138] 701: When the transmitting end is not transmitting service data, the transmitting end transmits a first control bitstream, which is used to indicate that the transmitting end has turned off a subset module in the transmitting end's physical layer circuitry, or the first control bitstream is used to indicate that the transmitting end will turn off a subset module in the transmitting end's physical layer circuitry, or the first control bitstream is used to indicate to the receiving end to turn off a subset module in the receiving end's physical layer circuitry.

[0139] For specific embodiments of step 701, please refer to the following descriptions of steps (1), (2), and (5) in Figure 9.

[0140] 702: The transmitting end turns off a subset module within the physical layer circuit of the transmitting end.

[0141] For specific embodiments of step 701, please refer to the following descriptions of steps (3) and (4) in Figure 9.

[0142] It should be noted that the sequence in which the transmitting end turns off a submodule in its physical layer circuit and the transmitting end transmits a first control bitstream is not limited in this application. Specifically, optionally, the transmitting end transmits a first control bitstream after it has turned off a submodule in its physical layer circuit; optionally, the transmitting end turns off a submodule in its physical layer circuit during the process of the transmitting end transmitting a first control bitstream; or optionally, the transmitting end turns off a submodule in its physical layer circuit after it has completed transmitting a first control bitstream.

[0143] 703: The transmitting end sends a random bitstream.

[0144] For a specific embodiment of step 703, please refer to the following description of step (6) in Figure 9.

[0145] The present application is not limited to sequences in which the transmitting end turns off a submodule in the transmitting end's physical layer circuitry and the transmitting end transmits a random bitstream. Specifically, optionally, the transmitting end transmits a random bitstream after turning off a submodule in the transmitting end's physical layer circuitry; optionally, the transmitting end turns off a submodule in the transmitting end's physical layer circuitry during the process of the transmitting end transmitting a random bitstream; or optionally, the transmitting end turns off a submodule in the transmitting end's physical layer circuitry after the transmitting end has completed transmitting the random bitstream.

[0146] In response to this, in the case of a high-speed serial interface, the high-speed serial interface includes a physical layer circuit at the receiving end. As shown in Figure 8, this method includes the following steps.

[0147] 801: The receiving end receives a first control bitstream, which is used to indicate that the transmitting end has turned off a subset module in the transmitting end's physical layer circuitry, or the first control bitstream is used to indicate that the transmitting end will turn off a subset module in the transmitting end's physical layer circuitry, or the first control bitstream is used to indicate to the receiving end to turn off a subset module in the receiving end's physical layer circuitry.

[0148] For a specific embodiment of step 801, please refer to the following description of step (7) in Figure 9.

[0149] 802: The receiving end turns off a submodule within the physical layer circuit of the receiving end.

[0150] For specific embodiments of step 802, please refer to the following descriptions of steps (8) and (9) in Figure 9.

[0151] 803: The receiving end receives a random bitstream.

[0152] The random bitstream does not pass through the submodules in the physical layer circuitry at the receiving end.

[0153] The present application is not limited to sequences in which a receiving end turns off a submodule in its physical layer circuitry and the receiving end receives a random bitstream. Specifically, optionally, the receiving end receives a random bitstream after it has turned off a submodule in its physical layer circuitry; optionally, the receiving end turns off a submodule in its physical layer circuitry during the process of receiving a random bitstream; or optionally, the receiving end turns off a submodule in its physical layer circuitry after it has finished receiving a random bitstream.

[0154] For a specific embodiment of step 803, please refer to the following description of step (10) in Figure 9.

[0155] It should be noted that methods for turning off a sub-module within a physical layer circuit include turning off the power to the associated module, turning off the clock of the associated module, or stopping the transmission of a clock signal to the associated module, so that the sub-module within the physical layer circuit becomes inoperable.

[0156] For example, in the circuit structure shown in Figure 9, the submodule in the physical layer circuit at the transmitting end is PL_TX, and the submodule in the physical layer circuit at the receiving end is PL_RX. The process for turning off PL_TX and PL_RX may be as follows:

[0157] (1) After completing the transmission of service data, DL_TX stops transmitting service data to PL_TX.

[0158] (2) The monitor detects that DL_TX is not sending service data.

[0159] Each time DL_TX sends service data to PL_TX, the monitor receives a first signal, which indicates that DL_TX is sending service data to PL_TX.

[0160] If the time during which DL_TX does not receive the first signal exceeds the preset time period, the monitor determines that DL_TX has not sent service data to PL_TX. For example, the preset time period here could be 1 μs or 1 ns.

[0161] (3) After waiting for PL_TX to finish transmitting the service data output by DL_TX, the monitor sends a request to the first clock gating circuit to turn off the PL_TX subcircuit.

[0162] If the monitor determines that DL_TX has not sent service data to PL_TX, PL_TX may not have finished sending the service data it received from PL_TX to MUX. Therefore, after waiting for PL_TX to finish sending the service data output by DL_TX, for example, after waiting for a time period to elapse since PL_TX last completed sending service data, the monitor determines that PL_TX has finished sending the service data output by DL_TX. In this case, the monitor initiates the process of entering a low-power state and sends a request to the first clock gating circuit to turn off the PL_TX subcircuit. The PL_TX subcircuit here may include high-power circuits such as FEC circuits or scrambling circuits.

[0163] (4) The first clock gating circuit turns off the PL_TX subcircuit.

[0164] It should be understood that PL_TX can be triggered by continuously receiving a clock signal from a first clock gating circuit in order to transmit service data. When the first clock gating circuit receives a request to turn off a subset of PL_TX, it may turn off a subset of PL_TX by ceasing to transmit a clock signal to that subset of PL_TX.

[0165] For example, the first clock gating circuit updates the enable value of the clock signal output to the PL_TX subcircuit from 1 to 0 to indicate that the PL_TX subcircuit is turned off.

[0166] (5) The control bitstream generation circuit sends a first control bitstream to SerDes TX, which indicates that the PL_RX subset should be turned off. SerDes TX converts the parallel data of the first control bitstream into serial data and then sends the serial data to the link.

[0167] In some embodiments, when the monitor determines that the first clock gating circuit has turned off the PL_TX subset, the monitor may trigger a control bitstream generation circuit to generate a first control bitstream and control the PL_RX subset to turn off at the receiving end. For example, the monitor may send a second signal to the control bitstream generation circuit, which is used to indicate to the control bitstream generation circuit that it should send the first control bitstream. In this case, the monitor is coupled to the control bitstream generation circuit. The monitor may trigger a MUX circuit to choose to send the first control bitstream to SerDes TX.

[0168] In some embodiments, a global control circuit operates at the transmitting end of a high-speed serial interface to control the high-speed serial interface. When the control circuit determines that a first clock gating circuit has turned off a subset of PL_TX, the control circuit may trigger a control bitstream generation circuit to generate a first control bitstream, and the control circuit may choose to trigger a MUX circuit to transmit the first control bitstream to SerDes TX.

[0169] (6) The random bitstream generation circuit sends a random bitstream to SerDes TX. SerDes TX converts the parallel data of the random bitstream into serial data and then sends the serial data to the link.

[0170] In some embodiments, when the control bitstream generation circuit determines that it has completed transmitting the first control bitstream, the monitor may trigger a random bitstream generation circuit to generate a random bitstream, and as a result, the SerDes TX transmits the random bitstream to the link. For example, when the control bitstream generation circuit determines that it has completed transmitting the first control bitstream, the monitor sends a third signal to the random bitstream generation circuit, which is used to indicate to the random bitstream generation circuit that it should transmit a random bitstream. In this case, the monitor is coupled to the random bitstream generation circuit. The monitor may trigger a MUX circuit to choose to transmit a random bitstream to the SerDes TX.

[0171] In some embodiments, once the control bitstream generation circuit determines that it has completed transmitting the first control bitstream, the control circuit may trigger a random bitstream generation circuit to generate a random bitstream, and the control circuit may trigger a MUX circuit to select to transmit the random bitstream to SerDes TX.

[0172] (7) The SerDes RX converts the serial data of the received first control bitstream into parallel data, and then transmits the parallel data to the bitstream detection circuit.

[0173] (8) When the bitstream detection circuit identifies the first control bitstream as a bitstream indicating that the PL_RX subset should be turned off, it sends an instruction to the second clock gating circuit indicating that the PL_RX subset should be turned off.

[0174] In some embodiments, the first control bitstream includes a plurality of repeating marker identifiers, a first marker end identifier, and a first bitstream content, the first bitstream content indicating to the receiving end to turn off the PL_RX subset. For specific embodiments of the first control bitstream, see the detailed description of the first control bitstream below. The first marker end identifier is used to indicate the position of the end bits of the first control bitstream. The plurality of repeating marker identifiers is used to indicate that the first control bitstream is a control bitstream distinct from the service data bitstream.

[0175] It can be understood that the bitstream detection circuit continuously detects the bitstream output by the SerDes RX. When a first control bitstream is received and identified as a request to turn off a subset of the PL_RX, the bitstream detection circuit may immediately send an instruction to the second clock gating circuit indicating that the subset of the PL_RX should be turned off.

[0176] (9) Upon receiving an instruction to turn off the PL_RX subcircuit, the second clock gating circuit waits until PL_RX has completed processing the service data, and then turns off the PL_RX subcircuit.

[0177] When the second clock gating circuit receives an instruction to turn off the PL_RX subset, PL_RX may not have finished sending the service data received from SerDes RX to DL_RX. Therefore, the second clock gating circuit stops sending the clock signal to PL_RX if it determines that the interval since the last time PL_RX sent service data to DL_RX exceeds the preset time period. For example, the preset time period may be 1 ns or 2 ns.

[0178] When the PL_RX subcircuit is turned off, the PL_RX subcircuit enters a low-power state.

[0179] (10) (Not shown in Figure 9) The SerDes RX receives a random bitstream and sends it to the bitstream detection circuit. The bitstream detection circuit identifies the random bitstream and then discards it.

[0180] B: When the physical layer circuit is turned on, the process at the transmitting end may further include the following steps, as shown in Figure 10.

[0181] 101: When the transmitting end resumes transmitting service data, it transmits a second control bitstream, which is used to indicate that the transmitting end has turned on a subset module in the transmitting end's physical layer circuitry, or the transmitting end is used to indicate that it will turn on a subset module in the transmitting end's physical layer circuitry, or the receiving end is used to indicate that it will turn on a subset module in the receiving end's physical layer circuitry.

[0182] For specific embodiments of step 101, please refer to the following descriptions of steps (1), (2), and (6) in Figure 12.

[0183] 102: The transmitting end turns on a partial module within the physical layer circuit of the transmitting end.

[0184] For specific embodiments of step 102, please refer to the following descriptions of steps (3) and (4) in Figure 12.

[0185] The present application is not limited to a sequence in which the transmitting end turns on its physical layer circuit and the transmitting end transmits a second control bitstream. Specifically, optionally, the transmitting end transmits a second control bitstream after the transmitting end turns on its physical layer circuit, optionally, the transmitting end turns on its physical layer circuit in the process of the transmitting end transmitting a second control bitstream, or optionally, the transmitting end turns on its physical layer circuit after the transmitting end has completed transmitting a second control bitstream.

[0186] 103: The transmitting end controls the physical layer circuitry at the transmitting end to send service data to the serializer / deserializer.

[0187] For specific embodiments of step 102, please refer to the following descriptions of steps (5) and (7) in Figure 12.

[0188] In response to this, as shown in Figure 11, the method may further include the following steps in the process at the receiving end.

[0189] 111: The receiving end controls the serializer / deserializer to receive a second control bitstream, which is used to indicate that the transmitting end has turned on a subset module in the transmitting end's physical layer circuitry, or the second control bitstream is used to indicate that the transmitting end will turn on a subset module in the transmitting end's physical layer circuitry, or the second control bitstream is used to indicate to the receiving end to turn on a subset module in the receiving end's physical layer circuitry.

[0190] For a specific embodiment of Step 111, please refer to the following description of Step (9) in Figure 12.

[0191] 112: The receiving end turns on a partial module within the physical layer circuit of the receiving end.

[0192] For a specific embodiment of step 112, please refer to the following description of step (10) in Figure 12.

[0193] 113: The receiving end controls the physical layer circuitry at the receiving end to receive service data transmitted via the serializer / deserializer.

[0194] For specific embodiments of step 113, please refer to the following descriptions of steps (8), (11), and (12) in Figure 12.

[0195] It should be noted that the method for turning on a sub-module within a physical layer circuit includes turning on the clock of the corresponding module, turning on the power supply of the corresponding module, or controlling the clock circuit to send a clock signal to the corresponding module, so that the physical layer module becomes operational.

[0196] For example, in the circuit structure shown in Figure 12, the submodule in the physical layer circuit at the transmitting end is PL_TX, and the submodule in the physical layer circuit at the receiving end is PL_RX. The process for turning on PL_TX and PL_RX may be as follows:

[0197] (1) DL_TX receives the service data sent by the upper layer and starts sending the service data to PL_TX.

[0198] Specifically, DL_TX is restored to its service data transmission state.

[0199] (2) The monitor detects that DL_TX has started sending service data.

[0200] When DL_TX begins sending service data to PL_TX, DL_TX also sends a first signal to the monitor. The monitor receiving the first signal means that the monitor detects that DL_TX has resumed sending service data to PL_TX.

[0201] (3) The monitor indicates the first clock gating circuit to turn on the PL_TX subcircuit.

[0202] Specifically, the monitor initiates a process to exit the low-power state.

[0203] (4) The first clock gating circuit turns on the PL_TX subcircuit.

[0204] Specifically, the first clock gating circuit begins sending a clock signal to the PL_TX subcircuit. For example, the enable value of the clock signal is updated from 0 to 1.

[0205] (5) The random bitstream generation circuit stops transmitting the random bitstream.

[0206] In some embodiments, after sending an instruction to the first clock gating, the monitor may send a fourth signal to the random bitstream generator to indicate to the random bitstream generator that it should stop transmitting the random bitstream. This is also equivalent to the random bitstream generator determining that the first clock gating circuit has begun transmitting a clock signal to the PL_TX subset.

[0207] In addition, the monitor indicates to the MUX circuit to stop selecting to send random bitstreams and start selecting to send service data.

[0208] (6) The control bitstream generation circuit transmits a second control bitstream, which is used to indicate to the receiving end that PL_RX should be turned on.

[0209] In some embodiments, when the monitor signals the first clock gating circuit to begin transmitting a clock signal, it may further signal the control bitstream generation circuit to transmit a second control bitstream.

[0210] In some embodiments, the second control bitstream includes a plurality of repeating marker identifiers, a second marker end identifier, and a second bitstream content, the second bitstream content indicating to the receiving end to turn on PL_RX. The second bitstream content is used to indicate turning off the physical layer circuit. The second marker end identifier is used to indicate the position of the end bit of the second control bitstream. The plurality of repeating marker identifiers is used to indicate that the second control bitstream is a control bitstream distinct from the service data bitstream.

[0211] (7) When the monitor determines that the transmission of the second control bitstream is complete, it instructs the MUX circuit to begin transmitting the service data.

[0212] In some embodiments, the monitor determines that transmission of the second control bitstream is complete when it determines that the interval since the control bitstream generation circuit finished transmitting the last data piece of the second control bitstream exceeds a certain time period. In this case, the monitor may indicate to the MUX circuit that it chooses to send the service data received from PL_RX to SerDes TX. SerDes TX converts the parallel service data to serial data and then transmits the serial data to the link.

[0213] (8) The SerDes RX converts the received serial service data into parallel data and then sends the parallel data to the bitstream detection module.

[0214] (9) The bitstream detection module continuously detects the bitstream output by SerDes RX, and when a second control bitstream is identified, it directs the second clock gating circuit to send a clock signal to PL_RX.

[0215] Specifically, the bitstream detection module directs the second clock gating circuit to turn on the PL_RX subset.

[0216] (10) The second clock gating circuit begins transmitting the clock signal to PL_RX.

[0217] (11) The bitstream detection circuit transmits the service data received after the second control bitstream to PL_RX.

[0218] (12) PL_RX performs physical layer decoding and descrambling on the received service data, and then outputs the processed service data to DL_RX.

[0219] In this way, the monitor, clock gating circuit, control bitstream generation circuit, bitstream detection circuit, and other circuits work together to avoid power waste that occurs when the physical layer circuit is still operating when the high-speed serial interface is not transmitting service data for a short period of time. In this application, the transmitter circuit of the PL at the transmitting end may be controlled to turn off, and the receiver circuit of the PL at the receiving end may be controlled to turn off, in order to reduce the power consumption of the link during periods when no service data is being transmitted on the link for a short period of time. The first and second control bitstreams correspond to switches for controlling the PL layer circuit. The response speed of the switches is typically a few nanoseconds, which is much faster than the switching speed of low-power states such as L0s, L1, or L2 in PCIe. This eliminates the problem of long on / off processes during power switching by the high-speed serial interface.

[0220] In addition, assuming that the transmitting and receiving ends in the embodiments are an SoC and a network interface card, respectively, it should be understood that in the direction in which the SoC transmits data to the network interface card, the transmitter circuit of the PL in the SoC may be controlled to be off or on, and the receiver circuit of the PL in the network interface card may be controlled to be off or on. In addition, the SoC may function alternatively as the receiving end, and the network interface card may function as the transmitting end. In this application, in the direction in which the network interface card transmits data to the SoC, the transmitter circuit of the PL in the network interface card may also be controlled to be off or on, and the receiver circuit of the PL in the SoC may also be controlled to be off or on. Specifically, in this application, the architecture and process for turning the physical layer circuit on or off in the transmitting direction is completely independent of those in the receiving direction on one side. In this application, during the task execution phase, the service data transmission status in the transmitting and receiving directions on one side may be distinguished. Specifically, the transmitting and receiving directions in the link may be monitored independently, and the physical layer circuit in the transmitting or receiving direction may be controlled independently. In other words, the transmit and receive directions of a link can be enabled or disabled in parallel and independently, without affecting each other. However, conventional physical layer power switching cannot distinguish between directions. Specifically, in conventional methods, turning a physical layer circuit on or off is equivalent to turning off both the transmitter and receiver circuits on one side of the physical layer.

[0221] The embodiments of the first control bitstream, the second control bitstream, and the random bitstream in this application will be described further below.

[0222] Control bitstream From the above description, it is understood that the first control bitstream in this application may be used to indicate to the receiving end that the transmission of service data is complete and the receiving end can turn off the PL_RX subcircuit. When the transmitting end resumes transmitting service data, the second control bitstream is used to indicate to the receiving end that the transmitting end has started or will start transmitting service data, and the receiving end can turn on the PL_RX subcircuit.

[0223] In this application, the first and second control bitstreams may have a certain bit error tolerance after being uniquely identified by the physical layer and transmitted over the link, ensuring that the bitstreams can still be accurately identified when bit errors occur. In addition, the bitstreams include instructions indicating whether to turn a subset of the physical layer on or off. The structure and content of the control bitstreams are not limited in this application.

[0224] It should be noted that the first and second control bitstreams in this application may further have error detection and error correction capabilities to ensure that the receiving end can correctly identify the first and second control bitstreams when bit errors occur during transmission over the link.

[0225] In addition, it should be understood that the first and second control bitstreams in this application must be distinguished from the service data.

[0226] In some embodiments, a control bitstream structure that satisfies the aforementioned requirements may be shown in Table 1.

[0227] [Table 1]

[0228] Specifically, the control bitstream contains multiple fields: N+1 repeating marker identifiers, a marker end identifier, and a bitstream content (marker payload), where N is a non-negative integer.

[0229] The N+1 repeating marker identifiers are marker identifier 0 (marker Identifier0), marker identifier 1 (marker Identifier1), ..., and marker identifier N (marker IdentifierN) in Figure 9. The N+1 repeating marker identifiers are used to identify whether the current data is a control bitstream.

[0230] To ensure that the control bitstream has a specific error tolerance, marker identifiers may be constructed using Hamming codes. At the receiving end, a bitstream detection circuit may perform error detection and error correction on the received control bitstream according to the detection and error correction principles of Hamming codes to ensure that the control bitstream is distinguishable from multiple bitstreams.

[0231] The marker end identifier is used to indicate the end of the control bitstream. When the receiving end receives the marker end identifier, the receiving end will have finished receiving the control bitstream content after the next bitstream content is received.

[0232] The bitstream content is used to indicate whether the current control bitstream is used to turn off or turn on a physical layer circuit. The bitstream content may be constructed using Hamming codes. Different Hamming codes indicate turning on or off a subset of the physical layer, for example, turning on or off an FEC circuit and a scramble / descramble circuit.

[0233] For example, when the eBCH (extended Bose Ray-Chaudhuri Hocquenghem) code is used in this application, let us assume that eBCH-16 is specifically used. eBCH-16 includes BCH(15,5) and one parity check bit. The payload portion of BCH(15,5) contains 5 bits, and the code length is 15 bits. The generator polynomial of the eBCH code is g BCH(15,5) (x) = x 10 +x 8 +x 5 +x 4 +x 2 It can be expressed as +x+x+1. The complete eBCH codeword set contains a total of 32 codewords. Table 2 shows the BCH(15,5) codeword set.

[0234] [Table 2A] [Table 2B]

[0235] During the transmission of the first or second control bitstream, the balance between 0s and 1s (the number of 0s and 1s in the data transmitted within a unit time) must be further considered. After the encoding result is obtained using the BCH(15,5) codeword set, a codeword with balanced 0s and 1s can be determined based on the codeword sets that satisfy the DC balance in Table 3.

[0236] [Table 3]

[0237] When a control bitstream generation circuit generates a code similar to the original BCH Code, the balancing of 0s and 1s in the encoded data can be achieved using Non-Return to Zero (NRZ) or Level Pulse Amplitude Modulation (PAM) 4-code patterns. Each symbol in the PAM 4-code pattern represents 2 bits. For example, when NRZ is used, if the pre-modulated codeword is 01000111_10101100, the modulated codeword obtained by balancing based on the positional correspondence between (43275160_75432160) and (76543210_76543210) in NRZ is 00100111_11011000.

[0238] The following provides an example of a control bitstream. Please refer to Table 4.

[0239] [Table 4]

[0240] Referring to Table 4, the Symbol Number indicates the number of symbols occupied by each type of description information. In this example, the following is described. The codewords used for Marker identify, i.e., the marker identifier, are CW21 and CW28 in Table 2, the codewords used for Marker END, i.e., the marker end identifier, are CW22 and CW3, and the codewords used for Marker Payload, i.e., the marker content, are CW3 and CW8. When the content of the control bit stream indicates that the physical layer circuit is turned off (closed), the codewords used for the marker content are CW23 and CW3. When the content of the control bit stream indicates that the physical layer circuit is turned on (open), the codewords used for the marker content are CW28 and CW8. After the codewords used for the control bit stream are determined, the positions of 0s and 1s in the codewords can be adjusted based on the modulation codeword set shown in Table 3 where 0s and 1s are balanced.

[0241] Random bit stream From the above description, it can be seen that in order to ensure that the transmitting end continues to input a bit stream to the SerDes in the link after PL_TX stops transmitting service data, a random bit stream is transmitted after the transmitting end transmits the first control bit stream. This can avoid an exception occurring when the receiving end's SerDes receives data when the SerDes does not transmit the bit stream. Thus, the CDR in the SerDes remains in the locked state.

[0242] In the present application, it is necessary to ensure randomness for generating the random bit stream, and the amounts of 0s and 1s need to be balanced.

[0243] In some embodiments, the random bit stream generation circuit has a polynomial G(X)=X 23 +X 21 +X 16 +X8 +X 5 +X 2 A pseudo-random bitstream can be generated using +1. Segments of data within the pseudo-random bitstream are considered to be random bitstreams transmitted in this application.

[0244] Naturally, the control bitstream and random bitstream in this application may be implemented in alternative ways, and are not limited to this application.

[0245] To implement the functions described herein, it can be understood that the high-speed serial interface includes corresponding hardware and / or software modules for performing the functions. Referring to the algorithms and steps in the examples described in the embodiments disclosed herein, the application may be implemented in hardware form or in combination of hardware and computer software. Whether the functions are performed by hardware or by hardware driven by computer software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the functions described for each specific application with reference to the embodiments. However, the embodiments should not be considered to exceed the scope of this application.

[0246] In embodiments, the high-speed serial interface may be divided into functional modules based on the method examples described above. For example, each functional module may be obtained by dividing the corresponding function, or two or more functions may be integrated into a single processing module. The integrated module may be implemented in hardware form. Note that in embodiments, the division into modules is an example and is merely a logical functional division. In actual implementation, other division methods may be used.

[0247] When each functional module is obtained by dividing the corresponding function, Figure 13 is a schematic diagram of a possible configuration of the network device 130 in the embodiment described above. The network device may include a serial interface circuit. When the network device includes a transmitting end and a receiving end for transmitting a bitstream, as shown in Figure 13, for example, the transmitting end is the SoC in the above description and the receiving end is the network interface card in the above description. The network device 130 may include a determination unit 1301, a bitstream generation unit 1302, a first control unit 1303, a transmission unit 1304, a receiving unit 1305, a detection unit 1306, and a second control unit 1307.

[0248] The determination unit 1301 may be configured to support the network device 130 when performing the above process of determining whether the high-speed serial interface has stopped or resumed transmitting service data, and / or another process of the technology described herein. The determination unit 1301 corresponds to the function of the monitor in this application.

[0249] The bitstream generation unit 1302 may be configured to support the network device 130 when performing the aforementioned process of generating a first control bitstream, a second control bitstream, a random bitstream, and / or another process of the technology described herein. The bitstream generation unit 1302 equivalently includes the functions of the control bitstream generation circuit and the random bitstream generation circuit in this application.

[0250] The first control unit 1303 may be configured to support the network device 130 in performing the aforementioned processes, such as generating and transmitting a clock signal at the transmitting end, and / or other processes of the technology described herein. The first control unit 1303 equivalently includes the function of the clock gating circuit at the transmitting end in this application.

[0251] The transmitting unit 1304 may be configured to support the network device 130 when performing the aforementioned process of transmitting a first control bitstream, a second control bitstream, a random bitstream, service data, etc., and / or another process of the technology described herein. The transmitting unit 1304 includes the functionality of the transmitter circuit of the SerDes in this application.

[0252] The receiving unit 1305 may be configured to support the network device 130 when performing the aforementioned process of receiving a first control bitstream, a second control bitstream, a random bitstream, service data, etc., and / or another process of the technology described herein. The receiving unit 1305 includes the function of the receiver circuit of the SerDes in this application.

[0253] The detection unit 1306 may be configured to support the network device 130 when performing the aforementioned process of detecting a first control bitstream, a second control bitstream, a random bitstream, and so on.

[0254] The second control unit 1307 may be configured to support the network device 130 when performing the aforementioned processes, such as generating and transmitting a clock signal at the receiving end, and / or other processes of the technology described herein. The second control unit 1307 equivalently includes the function of the clock gating circuit at the receiving end in this application.

[0255] It should be noted that all relevant details of the steps in the aforementioned method embodiment may be referenced in the description of the function of the corresponding functional module. Details will not be repeated here.

[0256] The network device 130 provided in this embodiment is configured to perform the data transmission method described above, and therefore can achieve the same effects as the method of the previously described embodiment.

[0257] When an integrated unit is used, the network device 130 may include a processing module, a storage module, and a communication module. The processing module may be configured to control and manage the operation of the network device 130. For example, the processing module may be configured to support the network device 130 when performing steps performed by the determination unit 1301, the bitstream generation unit 1302, the first control unit 1303, the detection unit 1306, and the second control unit 1307. The storage module may be configured to support the network device 130 when storing program code, data, etc. The communication module may be configured to support communication between the transmitting and receiving ends within the network device 130. In this application, the communication module may be configured to support the network device 130 when performing steps performed by the transmitting unit 1304 and the receiving unit 1305.

[0258] The processing module may be a processor or a controller. The processing module may implement or execute various exemplary logic blocks, modules, and circuits described with reference to what is disclosed in this application. The processor may alternatively be a combination of processors that implement computing functions, for example, a combination including one or more microprocessors, or a combination of a digital signal processor (DSP) and a microprocessor. The storage module may be memory. The communication module may specifically be a circuit, for example, a SerDes.

[0259] One embodiment of this application further provides an electronic device comprising one or more processors and one or more memories. The one or more memories are coupled to one or more processors. The one or more memories are configured to store computer program code, which includes computer instructions. When one or more processors execute computer instructions, the electronic device becomes capable of performing the associated method steps described above to implement the data transmission method in the above embodiment.

[0260] One embodiment of this application further provides a computer storage medium. The computer storage medium stores computer instructions. When the computer instructions are executed on an electronic device, the electronic device becomes capable of performing the associated method steps described above to implement the data transmission method in the above embodiment.

[0261] One embodiment of this application further provides a computer program product. When the computer program product is executed on a computer, the computer is able to perform the aforementioned related steps to implement a data transmission method performed by an electronic device including a high-speed serial interface in the above embodiment.

[0262] In addition, one embodiment of the present application further provides an apparatus, which may specifically be a chip, a component, or a module. The apparatus may include a processor and memory connected to each other. The memory is configured to store computer executable instructions. When the apparatus is in operation, the processor can execute the computer executable instructions stored in the memory, and as a result, the chip performs a data transmission method that is executed by an electronic device including a high-speed serial interface in the embodiments of the method described above.

[0263] The electronic devices, computer storage media, computer program products, or chips provided in the embodiments are configured to perform the corresponding methods provided above. Therefore, for the beneficial effects that can be achieved by the electronic devices, computer storage media, computer program products, or chips, please refer to the beneficial effects of the corresponding methods provided above. Details will not be repeated here.

[0264] Based on the description of the embodiments described above, those skilled in the art will understand that, for the sake of convenience and conciseness, the division into functional modules described above is used only as an illustrative example. In actual applications, the functions described above may be assigned to different functional modules and implemented as needed. In other words, the internal structure of the device is divided into different functional modules to implement all or some of the functions described above.

[0265] In the various embodiments provided in this application, it should be understood that the disclosed devices and methods may be implemented in other ways. For example, the embodiments of the devices described are merely examples. For example, the division into modules or units is merely a logical functional division, and other divisions may be possible in actual implementation. For example, multiple units or components may be combined, integrated into another device, and some features may be ignored or not performed. In addition, the illustrated or described mutual coupling or direct coupling or communication connection may be implemented through some interfaces. Indirect coupling or communication connection between devices or units may be implemented electrically, mechanically or in other forms.

[0266] Units described as separate parts may or may not be physically separate, and a part shown as a unit may be one or more physical units, that is, they may be located in one place or distributed in multiple different locations. Some or all of the units may be selected according to the actual requirements to achieve the objectives of the solution of the embodiment.

[0267] In addition, the functional units in the embodiments of this application may be integrated into a single processing unit, and each unit may exist physically independently, or two or more units may be integrated into a single unit. The integrated unit may be implemented in the form of hardware, or in the form of a software functional unit.

[0268] If the integrated unit is implemented in the form of a software function unit and sold or used as an independent product, the integrated unit may be stored in a readable storage medium. Based on this understanding, the technical solutions in the embodiments of this application, or parts that contribute to the prior art, or all or part of the technical solutions, may be implemented in the form of a software product. The software product is stored in a storage medium and includes several instructions for instructing a device (which may be a single-chip microcomputer, chip, etc.) or processor to perform all or part of the steps of the method of the embodiments of this application. The storage medium is any medium capable of storing program code, including, for example, a USB flash drive, a removable hard disk drive, read-only memory (ROM), random access memory (RAM), a magnetic disk, or an optical disk.

[0269] The foregoing description is merely a specific embodiment of the present application and is not intended to limit the scope of protection of this application. Any modifications or substitutions that are readily conceivable by a person skilled in the art within the scope of the art disclosed herein shall also fall within the scope of protection of this application. Accordingly, the scope of protection of this application shall be subject to the scope of protection of the claims. [Explanation of symbols]

[0270] 130 network devices 1301 Judgment Unit 1302 Bitstream Generation Unit 1303 First control unit 1304 Transmitter Unit 1305 Receiving Unit 1306 Detection Unit 1307 Second control unit

Claims

1. A high-speed serial interface comprising a physical layer circuit at the transmitting end, a monitor, a clock gating circuit, a control bitstream generation circuit, a random bitstream generation circuit, and a serializer / deserializer, The Monitor is configured to stop the transmission of a clock signal from the transmitting end to a submodule in the physical layer circuit of the transmitting end when the transmitting end is not transmitting service data, as shown in the clock gating circuit. The clock gating circuit is configured to stop the transmission of the clock signal to the submodule in the physical layer circuit of the transmitting end. The control bitstream generation circuit, upon determining that the clock gating circuit has stopped transmitting the clock signal, transmits a first control bitstream via the serializer / deserializer, the first control bitstream being used to indicate that the transmitting end has turned off the submodule in the physical layer circuit of the transmitting end, or the first control bitstream being used to indicate that the transmitting end will turn off the submodule in the physical layer circuit of the transmitting end, or the first control bitstream being used to indicate to the receiving end to turn off the submodule in the physical layer circuit of the receiving end. The random bitstream generation circuit is configured to transmit a random bitstream to the serializer / deserializer and to maintain a stable locked state of the clock and data recovery CDR circuit in the serializer / deserializer at the transmitting end and the CDR circuit in the serializer / deserializer at the receiving end of the high-speed serial interface. High-speed serial interface.

2. The sub-module within the physical layer circuit of the transmitting end includes at least one of forward error correction, FEC coding circuitry, or scrambling circuitry. The sub-module within the physical layer circuit of the receiving end includes at least one of an FEC decoding circuit or a descramble circuit. The high-speed serial interface according to claim 1.

3. The high-speed serial interface further includes a data link layer at the transmitting end, and the monitor is The data link layer of the transmitting end monitors whether it is transmitting service data to the physical layer circuit of the transmitting end. If it is determined that the data link layer of the transmitting end has not transmitted the service data to the physical layer circuit of the transmitting end, then it is determined that the transmitting end has not transmitted the service data. A high-speed serial interface according to claim 1 or 2, particularly configured as such.

4. The aforementioned monitor, When the clock gating circuit determines that it has stopped transmitting the clock signal to the submodule in the physical layer circuit of the transmitting end, it transmits a first signal to the control bitstream generation circuit, and the first signal is used to indicate to the control bitstream generation circuit that it should transmit the first control bitstream. When the control bitstream generation circuit determines that it has completed transmitting the first control bitstream, it transmits a second signal to the random bitstream generation circuit, and the second signal is used to indicate to the random bitstream generation circuit that it should transmit the random bitstream. A high-speed serial interface according to claim 1 or 2, further configured as follows.

5. The Monitor is further configured, as shown in the clock gating circuit, to transmit the clock signal to the submodule in the physical layer circuit of the transmitting end when the transmitting end resumes transmitting the service data. The clock gating circuit is further configured to transmit the clock signal to the submodule in the physical layer circuit of the transmitting end, The random bitstream generation circuit is further configured to stop transmitting the random bitstream when the clock gating circuit determines that it has started transmitting the clock signal. The control bitstream generation circuit is further configured such that, when it determines that the transmitting end has resumed transmitting the service data, it transmits a second control bitstream via the serializer / deserializer, the second control bitstream being used to indicate that the transmitting end has turned on the submodule in the physical layer circuit of the transmitting end, or the second control bitstream being used to indicate that the transmitting end will turn on the submodule in the physical layer circuit of the transmitting end, or the second control bitstream being used to indicate to the receiving end to turn on the submodule in the physical layer circuit of the receiving end. The physical layer circuit at the transmitting end is configured to initiate the transmission of the service data via the serializer / deserializer. The high-speed serial interface according to claim 1.

6. The first control bitstream includes a plurality of repeating marker identifiers, a first marker end identifier, and a first bitstream content, wherein the first bitstream content indicates that the transmitting end has turned off the submodule in the physical layer circuit of the transmitting end, or the first control bitstream is used to indicate that the transmitting end will turn off the submodule in the physical layer circuit of the transmitting end, or the first control bitstream is used to indicate that the receiving end will turn off the submodule in the physical layer circuit of the receiving end, and the first marker end identifier is used to indicate the position of the end bit of the first control bitstream. The second control bitstream includes a plurality of repeating marker identifiers, a second marker end identifier, and a second bitstream content, wherein the second bitstream content indicates that the transmitting end has turned on the submodule in the physical layer circuit of the transmitting end, or the second control bitstream is used to indicate that the transmitting end will turn on the submodule in the physical layer circuit of the transmitting end, or the second control bitstream is used to indicate that the receiving end will turn on the submodule in the physical layer circuit of the receiving end, and the second marker end identifier is used to indicate the position of the end bit of the second control bitstream. The random bitstream is used to enable the clock and data recovery CDR circuit in the serializer / deserializer to be locked, and the random bitstream includes a balanced quantity of 0s and 1s. The high-speed serial interface according to claim 5.

7. A high-speed serial interface comprising a physical layer circuit at the receiving end, a bitstream detection circuit, a clock gating circuit, and a serializer / deserializer, The bitstream detection circuit is configured to receive a first control bitstream via the serializer / deserializer, and the first control bitstream is used to indicate that the transmitting end has turned off a subset module in the physical layer circuit of the transmitting end, or the first control bitstream is used to indicate that the transmitting end will turn off a subset module in the physical layer circuit of the transmitting end, or the first control bitstream is used to indicate to the receiving end to turn off a subset module in the physical layer circuit of the receiving end. The bitstream detection circuit is further configured, as shown in the clock gating circuit, to stop transmitting the clock signal to the submodule in the physical layer circuit at the receiving end, The clock gating circuit is configured to stop the transmission of the clock signal to the submodule in the physical layer circuit of the receiving end. The bitstream detection circuit is further configured to receive a random bitstream via the serializer / deserializer and to maintain the clock and data recovery CDR circuit in the serializer / deserializer at the transmitting end and the CDR circuit in the serializer / deserializer at the receiving end in a stable locked state in the high-speed serial interface. High-speed serial interface.

8. The sub-module within the physical layer circuit of the transmitting end includes at least one of a forward error correction (FEC) coding circuit or a scrambling circuit. The sub-module within the physical layer circuit of the receiving end includes at least one of an FEC decoding circuit or a descramble circuit. The high-speed serial interface according to claim 7.

9. The high-speed serial interface further includes a data link layer at the receiving end, The clock gating circuit is particularly configured to stop transmitting the clock signal to the submodule within the physical layer circuit of the receiving end when it is determined that the interval from the last time the physical layer circuit of the receiving end transmits service data to the data link layer of the receiving end exceeds a preset time period. The high-speed serial interface according to claim 7 or 8.

10. The bitstream detection circuit is further configured to control the serializer / deserializer to receive a second control bitstream, and when the second control bitstream is used to indicate that the transmitting end has turned on the submodule in the physical layer circuit of the transmitting end, or when the second control bitstream is used to indicate that the transmitting end will turn on the submodule in the physical layer circuit of the transmitting end, or when the second control bitstream is used to indicate to the receiving end to turn on the submodule in the physical layer circuit of the receiving end, it further configures to indicate to the clock gating circuit to transmit the clock signal to the submodule in the physical layer circuit of the receiving end, The clock gating circuit is further configured to transmit the clock signal to the submodule in the physical layer circuit of the receiving end, The bitstream detection circuit is further configured to transmit the service data received from the serializer / deserializer to the physical layer circuit at the receiving end. The high-speed serial interface according to claim 7 or 8.

11. The first control bitstream includes a plurality of repeating marker identifiers, a first marker end identifier, and a first bitstream content, wherein the first bitstream content indicates that the transmitting end has turned off the submodule in the physical layer circuit of the transmitting end, or the first control bitstream is used to indicate that the transmitting end will turn off the submodule in the physical layer circuit of the transmitting end, or the first control bitstream is used to indicate that the receiving end will turn off the submodule in the physical layer circuit of the receiving end, and the first marker end identifier is used to indicate the position of the end bit of the first control bitstream. The second control bitstream includes a plurality of repeating marker identifiers, a second marker end identifier, and a second bitstream content, wherein the second bitstream content indicates that the transmitting end has turned on the submodule in the physical layer circuit of the transmitting end, or the second control bitstream is used to indicate that the transmitting end will turn on the submodule in the physical layer circuit of the transmitting end, or the second control bitstream is used to indicate that the receiving end will turn on the submodule in the physical layer circuit of the receiving end, and the second marker end identifier is used to indicate the position of the end bit of the second control bitstream. The random bitstream is used to allow the clock and data recovery CDR circuit in the serializer / deserializer to remain locked, and the random bitstream includes a balanced quantity of 0s and 1s. The bitstream detection circuit is further configured to discard the random bitstream when it is identified. The high-speed serial interface according to claim 10.

12. A data transmission method applicable to a high-speed serial interface, wherein the high-speed serial interface includes a physical layer circuit at the transmitting end, and the method is Steps of transmitting a first control bitstream by the transmitting end when the transmitting end is not transmitting service data, wherein the first control bitstream is used to indicate that the transmitting end has turned off a subset module in the physical layer circuit of the transmitting end, or the first control bitstream is used to indicate that the transmitting end will turn off a subset module in the physical layer circuit of the transmitting end, or the first control bitstream is used to indicate to the receiving end to turn off a subset module in the physical layer circuit of the receiving end, The steps include: turning off the sub-module in the physical layer circuit of the transmitting end at the transmitting end; The transmitting end transmits a random bitstream, and the steps include maintaining the clock and data recovery CDR circuit in the serializer / deserializer of the transmitting end and the CDR circuit in the serializer / deserializer of the receiving end in a stable locked state in the high-speed serial interface. A data transmission method, including a data transmission method.

13. The sub-module within the physical layer circuit of the transmitting end includes at least one of a forward error correction (FEC) coding circuit or a scrambling circuit. The sub-module within the physical layer circuit of the receiving end includes at least one of an FEC decoding circuit or a descramble circuit. The method according to claim 12.

14. The high-speed serial interface further includes a data link layer at the transmitting end, The fact that the aforementioned transmitting end has not transmitted service data means that When the data link layer of the transmitting end does not transmit the service data to the physical layer circuit of the transmitting end, the transmitting end determines that it has not transmitted the service data. The method according to claim 12, including the method described in claim 12.

15. The high-speed serial interface further comprises a serializer / deserializer, and the method is Steps include: when the transmitting end resumes transmitting the service data, the transmitting end transmits a second control bitstream, the second control bitstream being used to indicate that the transmitting end has turned on the submodule in the physical layer circuit of the transmitting end, or the second control bitstream being used to indicate that the transmitting end will turn on the submodule in the physical layer circuit of the transmitting end, or the second control bitstream being used to indicate to the receiving end to turn on the submodule in the physical layer circuit of the receiving end; The steps include: turning on the sub-module in the physical layer circuit of the transmitting end using the transmitting end; The steps include: controlling the physical layer circuit of the transmitting end to transmit the service data to the serializer / deserializer; The method according to claim 12, further comprising:

16. The first control bitstream includes a plurality of repeating marker identifiers, a first marker end identifier, and a first bitstream content, wherein the first bitstream content indicates that the transmitting end has turned off the submodule in the physical layer circuit of the transmitting end, or the first control bitstream is used to indicate that the transmitting end will turn off the submodule in the physical layer circuit of the transmitting end, or the first control bitstream is used to indicate that the receiving end will turn off the submodule in the physical layer circuit of the receiving end, and the first marker end identifier is used to indicate the position of the end bit of the first control bitstream. The second control bitstream includes a plurality of repeating marker identifiers, a second marker end identifier, and a second bitstream content, wherein the second bitstream content indicates that the transmitting end has turned on the submodule in the physical layer circuit of the transmitting end, or the second control bitstream is used to indicate that the transmitting end will turn on the submodule in the physical layer circuit of the transmitting end, or the second control bitstream is used to indicate that the receiving end will turn on the submodule in the physical layer circuit of the receiving end, and the second marker end identifier is used to indicate the position of the end bit of the second control bitstream. The random bitstream is used to enable the clock and data recovery CDR circuit in the serializer / deserializer to be locked, and the random bitstream includes a balanced quantity of 0s and 1s. The method according to claim 15.

17. A data transmission method applicable to a high-speed serial interface, wherein the high-speed serial interface includes a physical layer circuit at the receiving end, and the method is A step of receiving a first control bitstream at the receiving end, wherein the first control bitstream is used to indicate that the transmitting end has turned off a subset module in the physical layer circuit of the transmitting end, or the first control bitstream is used to indicate that the transmitting end will turn off a subset module in the physical layer circuit of the transmitting end, or the first control bitstream is used to indicate to the receiving end to turn off a subset module in the physical layer circuit of the receiving end, The receiving terminal performs the step of turning off the partial module in the physical layer circuit of the receiving terminal, The receiving end receives a random bitstream and maintains the clock and data recovery CDR circuit in the serializer / deserializer of the transmitting end and the CDR circuit in the serializer / deserializer of the receiving end in a stable locked state. A data transmission method, including a data transmission method.

18. The sub-module within the physical layer circuit of the transmitting end includes at least one of a forward error correction (FEC) coding circuit or a scrambling circuit. The sub-module within the physical layer circuit of the receiving end includes at least one of an FEC decoding circuit or a descramble circuit. The method according to claim 17.

19. The high-speed serial interface further comprises a serializer / deserializer, and the method is A step of controlling the serializer / deserializer at the receiving end to receive a second control bitstream, wherein the second control bitstream is used to indicate that the transmitting end has turned on the submodule in the physical layer circuit of the transmitting end, or the second control bitstream is used to indicate that the transmitting end will turn on the submodule in the physical layer circuit of the transmitting end, or the second control bitstream is used to indicate to the receiving end to turn on the submodule in the physical layer circuit of the receiving end, The receiving end turns on the sub-module in the physical layer circuit of the receiving end, The receiving end controls the physical layer circuit of the receiving end to receive the service data transmitted via the serializer / deserializer. The method according to claim 17, further comprising:

20. The first control bitstream includes a plurality of repeating marker identifiers, a first marker end identifier, and a first bitstream content, wherein the first bitstream content indicates that the transmitting end has turned off the submodule in the physical layer circuit of the transmitting end, or the first control bitstream is used to indicate that the transmitting end will turn off the submodule in the physical layer circuit of the transmitting end, or the first control bitstream is used to indicate that the receiving end will turn off the submodule in the physical layer circuit of the receiving end, and the first marker end identifier is used to indicate the position of the end bit of the first control bitstream. The second control bitstream includes a plurality of repeating marker identifiers, a second marker end identifier, and a second bitstream content, wherein the second bitstream content indicates that the transmitting end has turned on the submodule in the physical layer circuit of the transmitting end, or the second control bitstream is used to indicate that the transmitting end will turn on the submodule in the physical layer circuit of the transmitting end, or the second control bitstream is used to indicate that the receiving end will turn on the submodule in the physical layer circuit of the receiving end, and the second marker end identifier is used to indicate the position of the end bit of the second control bitstream. The random bitstream is used to enable the clock and data recovery CDR circuit in the serializer / deserializer to be locked, and the random bitstream includes a balanced quantity of 0s and 1s. The method further includes the step of discarding the random bitstream when the random bitstream is identified. The method according to claim 19.

21. A computer-readable storage medium containing computer instructions, wherein when the computer instructions are executed on an electronic device, the electronic device becomes capable of performing the method according to any one of claims 12 to 16.

22. A computer-readable storage medium containing computer instructions, wherein when the computer instructions are executed on an electronic device, the electronic device becomes capable of performing the method according to any one of claims 17 to 20.

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