Variable error correction codeword packing that supports bit error rate targeting.

Abstract

To provide a computing system, a memory controller, a device, a method, a program, and a recording medium, which reduce errors to be faced when accessing a multi-level NAND memory.SOLUTION: A method for operating a memory controller includes programming first multiple error correction codewords into a first set of a page within a block of a non-volatile memory, in which the first multiple error correction codewords are programmed in first density, and programming second multiple error correction codewords into a second set of the page within the block, in which the second multiple error correction codewords are programmed in second density. In one example, the first density and the second density are different from each other.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Embodiments generally relate to memory structures. More specifically, embodiments relate to variable error correction codeword packing that supports bit error rate targets within a memory structure.

Background Art

[0002] A multi-level NAND flash memory (NAND memory) can be organized into multiple cells, with each cell storing data for multiple bits. In such a case, the number of bits per cell can depend on how many distinct voltage levels can be achieved during a program operation without reaching an unacceptable low bit error rate (RBER). In fact, increasing the number of bits per cell reduces cost but can present challenges related to RBER and performance. More specifically, error correction code (ECC) techniques can be utilized to mitigate errors encountered when accessing (e.g., programming, reading) a multi-level NAND memory, but there is still significant room for improvement.

[0003] 5 For example, to support 5 bits per cell, 32 voltage levels (2

Brief Description of the Drawings

[0004] The various advantages of the embodiments will become apparent to those skilled in the art by reading the following specification and appended claims, and by referring to the following drawings.

[0005] [Figure 1] This figure shows an example of an error correction codeword distribution for a pentalevel cell (PLC) architecture according to one embodiment.

[0006] [Figure 2] This is a flowchart of an example of a method for operating a memory controller according to one embodiment.

[0007] [Figure 3] This is a plot of an example of level crossing spacing according to one embodiment.

[0008] [Figure 4] This is a block diagram of an example of a performance-enhanced computing system according to one embodiment. [Modes for carrying out the invention]

[0009] Referring to Figure 1, a pentalevel cell (PLC) architecture is shown in which block 10 of non-volatile memory (NVM) supports 5 bits per cell. Block 10 in the figure is a multilevel NVM cell (cell 0, cell 1, ..., cell 1 nThe set comprises ), and each cell stores 5 bits (bit 1, bit 2, bit 3, bit 4, bit 5). The cells may be programmed (e.g., written) and read page by page, with each page corresponding to a specific bit. More specifically, the lower page (LP) may correspond to bit 5, the upper page (e.g., UP) may correspond to bit 4, the first extra page (XP1) may correspond to bit 3, the second extra page (XP2) may correspond to bit 2, and the most significant page (TP) may correspond to bit 1. The group of 5 bits determines which voltage level the cell should be programmed to, and requests a total number of voltage levels (e.g., 32 in this case) so that all possible bit combinations can be distinguished from one another.

[0010] In one embodiment, a first set of error correction codewords 12 (12a-12l) are programmed into a first set 14 (LP, XP1, TP) of pages within a block 10, and the first set of error correction codewords 12 are programmed at a first density (e.g., codeword density). In the illustrated example, the first density is 4 codewords per page (e.g., 32 / 32 packing, 32 sectors stored in one 18592 byte page), and each codeword 12 stores and / or corrects 8 sectors of host data. More specifically, error correction codewords 12a-12d are programmed into lower pages, error correction codewords 12e-12h are programmed into a first extra page, and error correction codewords 12i-12l are programmed into the top-level page. The first set of error correction codewords 12 may be associated with a first error mitigation level, for example, about 1.5e-2. As should be noted, a non-uniform codeword density may be used to achieve a higher error reduction level of approximately 2e-2.

[0011] More specifically, the second set of error correction codewords 16 (16a-16f) are programmed into a second set 18 (UP, XP2) of pages within block 10, and the second set of error correction codewords 16 are programmed at a second density (e.g., codeword density). In the illustrated example, the second density is 3 codewords per page (e.g., 24 / 32 packing, 24 sectors stored in one 18592 byte page), and each codeword 16 stores and / or corrects 8 sectors of host data. More specifically, the error correction codewords 16a-16c are programmed into the upper pages, and the error correction codewords 16d-16f are programmed into a second extra page. Each of the codewords 16 contains more parity bits than the codeword 12. Thus, the second set of error correction codewords 16 may be associated with a second error mitigation level, for example, about 6.5e-2.

[0012] Therefore, to support an average RBER of 2e-2, the illustrated solution utilizes different packing for these five pages. A 4KB ECC engine with 24 / 32 packing supports a higher RBER of 6.5e-2, but stores 0.75 bits per page per cell instead of 1 bit per page per cell. Variable packing with 2 pages in 24 / 32 packing and 3 pages in 32 / 32 packing reduces the bits per cell in block 10 to 4.5 bits per cell, but still allows the target RBER goal of 5 bits per cell media to be met.

[0013] More specifically, with 5 bits per cell NAND, the RBER for any two level crossings is expected to be about 2e-2. Such a high RBER may not be supported by 4KB code in 32 / 32 packing mode. As a compromise, capacity is sacrificed by programming 2 pages in 24 / 32 packing and 3 pages in 32 / 32 packing. A second set of pages 18 (e.g., 24 / 32 packed pages) stores 3 4KB ECC codewords per page instead of 4 codewords, but 24 / 32 packed codewords are more powerful and can support an RBER of about 6.5e-2. As will be explained in more detail, level crossings with reads of the second set of pages 18 can be placed closer to each other. Level crossings with reads of the first set of pages 14 (e.g., pages containing 32 / 32 packed codewords) can be separated further apart due to the weaker 4KB code that supports an RBER of 1.5e-2. Overall, the average RBER of 5 bits per cell NAND is satisfied by variable packing, at the expense of a reduced capacity of 4.5 bits stored per cell.

[0014] A multilevel NVM cell may be part of a memory device that includes non-volatile memory and / or volatile memory. Non-volatile memory is a storage medium that does not require power to maintain the state of data stored in the medium. In one embodiment, the memory structure is a block-addressable storage device, such as one based on NAND or NOR technology. The storage device may include future-generation non-volatile devices, such as a three-dimensional (3D) crosspoint memory device or other byte-addressable, fixed-location write non-volatile memory devices. In one embodiment, the storage device may be a memory device that uses or includes, a silicon-oxide-nitride-oxide-silicon (SONOS) memory, electrically erasable programmable read-only memory (EEPROM), chalcogenide glass, multiple threshold level NAND flash memory, NOR flash memory, single or multilevel phase-change memory (PCM), resistive random-access memory, nanowire memory, ferroelectric transistor random-access memory (FeTRAM), antiferroelectric memory, magnetoresistive random-access memory (MRAM) memory incorporating memristor technology, metal oxide substrates, oxygen vacancy substrates, and resistive random-access memory including conductive bridge random-access memory (CB-RAM), or spin transfer torque (STT)-MRAM, spintronic magnetic junction memory-based devices, magnetic tunnel junction (MTJ)-based devices, DW (domain wall) and SOT (spin-orbit transfer)-based devices, thyristor-based memory devices, or any combination of the above, or other memory. The term "storage device" may refer to the die itself and / or packaged memory products. In some embodiments, 3D crosspoint memory may include a transistorless stackable crosspoint architecture, where memory cells are located at the intersections of word lines and bit lines, are individually addressable, and bit storage is based on changes in bulk resistance.In certain embodiments, a memory module with non-volatile memory may conform to one or more standards published by the Joint Electronic Devices Committee (JEDEC), such as JESD235, JESD218, JESD219, JESD220-1, JESD223B, and JESD223-1, or other preferred standards (the JEDEC standards described herein are available at jedec.org).

[0015] Volatile memory is a storage medium that requires power to maintain the state of data stored in it. Examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In certain embodiments, the DRAM of a memory module conforms to standards published by JEDEC (these standards are available at jedec.org), such as JESD79F for double data rate (DDR) SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, or JESD79-4A for DDR4 SDRAM. Such standards (and similar standards) may be referred to as DDR-based standards, and the communication interface of a storage device implementing such standards may be referred to as a DDR-based interface.

[0016] Figure 2 shows a method 20 for operating a chip controller device (e.g., a memory controller). Method 20 may be implemented in one or more modules as a set of logic instructions stored in a machine or computer-readable storage medium such as random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., in configurable logic such as programmable logic arrays (PLAs), field-programmable gate arrays (FPGAs), complex-programmable logic devices (CPLDs), in fixed-function hardware logic utilizing circuit technologies such as application-specific integrated circuits (ASICs), complementary metal-oxide-semiconductor (CMOS) or transistor-transistor logic (TTL) technology, or in any combination thereof.

[0017] The illustrated processing block 22 provides a step of programming a first set of error correction codewords into a first set of pages in a block of non-volatile memory (e.g., NAND memory pages), where the first set of error correction codewords is programmed at a first density. Processing block 24 programs a second set of error correction codewords into a second set of pages in the block (e.g., NAND memory pages), where the second set of error correction codewords is programmed at a second density. In the illustrated example, the first and second densities are different from each other.

[0018] In one embodiment, a first set of error correction codewords is associated with a first error mitigation level, and a second set of error correction codewords is associated with a second error mitigation level. In addition, the first and second error mitigation levels may be different from each other.

[0019] With respect to the PLC, the first set of pages may consist of three pages, and the first density is four codewords per page. In such a case, the second set of pages may consist of two pages, and the second density is three codewords per page. As a result, the block may have a storage capacity of less than one bit per page per cell.

[0020] Figure 3 demonstrates that level crossings associated with a second set of pages may be more closely spaced than those associated with a first set of pages. More specifically, plot 30 shows the level distribution of 32 levels (levels A-f) with 5 bits per cell NAND. On average, the RBER is expected to be in the range of 2e-2 (e.g., all pairs of levels that intersect each other with respect to a given page read have a total RBER of 2e-2). To satisfy such a relatively high RBER (e.g., with a page size of 18592B), a 4KB code may not be powerful enough. As already mentioned, a 4KB code where each page stores 32 sectors may be able to support an RBER of about 1.5e-2. To mitigate higher RBERs of 2e-2, 8KB or 16KB codes may be used. However, many memory architectures may only support 4KB codewords. Also, the gate count from an 8KB or 16KB code may increase the cost by about 5%.

[0021] With 4KB code, one option might be to use inefficient packing that stores fewer than 32 sectors per page. Such an approach reduces storage capacity from 5 bits per cell. For example, 24 sectors instead of 32 are packed per page, storing 3 units of 4KB code instead of 4 units of 4KB code. Code for 24 / 32 packing is more powerful, but stores only 0.75 bits per cell per page, and the memory device is equivalent to 3.75 bits per cell device. This is less than the capacity of a QLC (Quad-Level Cell) architecture.

[0022] The hybrid or variable packing approaches described herein store two pages in 24 / 32-packed mode and three pages in 32 / 32-packed mode. 24 / 32-packed pages store 0.75 bits per page, and 32 / 32-packed pages store 1 bit per page. Therefore, the capacity is 2 × 0.75 + 3 × 1 = 4.5 bits per cell, which is larger than the QLC capacity. The RBER mitigation capability is approximately 6.5e-2 for 24 / 32-packed codewords and 1.5e-2 for 32 / 32-packed codewords. The average RBER from this hybrid / variable packing meets the requirement of 5 bits per cell. Pairs of level crossings involved in 24 / 32-packed pages can be spaced closer together than crossings involved in 32 / 32-packed pages, as shown in plot 30. Given a read window budget (RWB), a closer spacing between 24 / 32 packed levels may generate enough windowing for 32 / 32 packed pages to support the relaxed spacing required for less heavily packed 4KB code.

[0023] From an ECC perspective, the extra gate count supporting one extra code is approximately 5% gates. Firmware support incorporating two different ECC schemes may already be available depending on the architecture. Also, 24 / 32 packed codes may be aligned with the boundaries for a 16KB indirect reference unit (IU) size.

[0024] Referring now to FIG. 4, a performance enhanced computing system 40 is shown. In the illustrated example, a solid state drive (SSD) 42 includes a device controller device 44 coupled to NAND 46. The illustrated NAND 46 includes a set of multi-level NVM cells 48 and a chip controller device 50 including a substrate 52 (e.g., silicon, sapphire, gallium arsenide) and logic 54 (e.g., transistor array and other integrated circuit / IC components) coupled to the substrate 52. Logic 54, which may include one or more of configurable or fixed function hardware, may be configured to perform one or more aspects of the method 20 (FIG. 2) already described.

[0025] More specifically, logic 54 may program a first plurality of error correction code words to a first set of pages within a block of NVM cells 48, the first plurality of error correction code words being programmed at a first density. Additionally, logic 54 may program a second plurality of error correction code words to a second set of pages within the block, the second plurality of error correction code words being programmed at a second density. In one embodiment, the first density and the second density are different from each other.

[0026] Also, the illustrated system 40 includes a system on chip (SoC) 56 having a host processor 58 (e.g., central processing unit / CPU) and an input / output (IO) module 60. The host processor 58 may include an integrated memory controller (IMC) 62 that communicates with a system memory 64 (e.g., RAM dual in-line memory module / DIMM). The illustrated IO module 60 is coupled to other system components such as SSD 42 and network controller 66.

[0027] In one example, logic 54 includes transistor channel regions located (e.g., embedded) within the substrate 52. Therefore, the interface between logic 54 and the substrate 52 may not be a step junction. Furthermore, logic 54 may be considered to include an epitaxial layer growing on the initial wafer of the substrate 52.

[0028] Therefore, the computing system 40 is considered to be enhanced in performance to the extent that a more efficient trade-off between error reduction and memory capacity is achieved by programming codewords at different densities. For example, a PLC architecture can be supported without resulting in a significant increase in gate count.

[0029] Further notes and examples

[0030] Example 1 includes a memory controller comprising one or more boards and logic coupled to the one or more boards, the logic being at least partially implemented in one or more configurable or fixed-function hardware, the logic coupled to the one or more boards comprising: a first plurality of error correction codewords programmed into a first set of pages in a block of non-volatile memory, wherein the first plurality of error correction codewords are programmed at a first density; and a second plurality of error correction codewords programmed into a second set of pages in the block, wherein the second plurality of error correction codewords are programmed at a second density, the first density and the second density being different from each other.

[0031] Example 2 includes the memory controller of Example 1, wherein the first set of error correction codewords are associated with a first error mitigation level, and the second set of error correction codewords are associated with a second error mitigation level, and the first and second error mitigation levels are different from each other.

[0032] Example 3 includes the memory controller of Example 1, wherein the first set of pages consists of 3 pages, and the first density is 4 codewords per page, and the second set of pages consists of 2 pages, and the second density is 3 codewords per page.

[0033] Example 4 includes the memory controller of Example 3, and the level crossings associated with the second set on the above page will be more closely spaced than the level crossings associated with the first set on the above page.

[0034] Example 5 includes the memory controller of Example 1, and the above block will have a storage capacity of less than 1 bit per page per cell.

[0035] Example 6 includes one of the memory controllers from Examples 1 to 5, and the first plurality of error correction codewords and the second plurality of error correction codewords are programmed into a NAND memory page.

[0036] Example 7 includes a computing system comprising a memory controller and a non-volatile memory (NVM) coupled to the memory controller, the NVM including a set of instructions which, when executed by the memory controller, causes the memory controller to program a first plurality of error correction codewords into a first set of pages in a block of the NVM, the first plurality of error correction codewords being programmed at a first density, and a second plurality of error correction codewords being programmed into a second set of pages in the block, the second plurality of error correction codewords being programmed at a second density, the first density and the second density being different from each other.

[0037] Example 8 includes the computing system of Example 7, wherein the first set of error correction codewords are associated with a first error mitigation level, and the second set of error correction codewords are associated with a second error mitigation level, and the first and second error mitigation levels are different from each other.

[0038] Example 9 includes the computing system of Example 7, wherein the first set of pages consists of 3 pages, and the first density is 4 codewords per page, and the second set of pages consists of 2 pages, and the second density is 3 codewords per page.

[0039] Example 10 includes the computing system of Example 9, and the level crossings associated with the second set on the above page will be more closely spaced than the level crossings associated with the first set on the above page.

[0040] Example 11 includes the computing system of Example 7, where the block has a storage capacity of less than 1 bit per page per cell.

[0041] Example 12 includes one of the computing systems from Examples 7-11, where the block includes NAND memory.

[0042] Example 13 includes at least one computer-readable storage medium having a set of instructions, which, when executed by the memory controller, causes the memory controller to program a first plurality of error correction codewords into a first set of pages in a block of non-volatile memory, the first plurality of error correction codewords being programmed at a first density, and a second plurality of error correction codewords into a second set of pages in the block, the second plurality of error correction codewords being programmed at a second density, the first density and the second density being different from each other.

[0043] Example 14 includes at least one computer-readable storage medium of Example 13, wherein the first plurality of error correction codewords are associated with a first error mitigation level, and the second plurality of error correction codewords are associated with a second error mitigation level, and the first error mitigation level and the second error mitigation level are different from each other.

[0044] Example 15 includes at least one computer-readable storage medium of Example 13, wherein the first set of pages consists of 3 pages and the first density is 4 codewords per page, and the second set of pages consists of 2 pages and the second density is 3 codewords per page.

[0045] Example 16 includes at least one computer-readable storage medium of Example 15, wherein the level crossings associated with the second set of pages above are more closely spaced than the level crossings associated with the first set of pages above.

[0046] Example 17 includes at least one computer-readable storage medium of Example 13, wherein the block has a storage capacity of less than 1 bit per cell per page.

[0047] Example 18 includes at least one computer-readable storage medium from any one of Examples 13 to 17, wherein the first plurality of error correction codewords and the second plurality of error correction codewords are programmed into NAND memory pages.

[0048] Example 19 includes a method comprising the steps of: programming a first plurality of error correction codewords into a first set of pages in a block of non-volatile memory, wherein the first plurality of error correction codewords are programmed at a first density; and programming a second plurality of error correction codewords into a second set of pages in the block, wherein the second plurality of error correction codewords are programmed at a second density, such that the first density and the second density are different from each other.

[0049] Example 20 includes the method of Example 19, wherein a first set of error correction codewords is associated with a first error mitigation level, a second set of error correction codewords is associated with a second error mitigation level, and the first and second error mitigation levels are different from each other.

[0050] Example 21 includes means for carrying out any one of the methods of claims 19 to 20.

[0051] The embodiments are applicable to use with all types of semiconductor integrated circuit ("IC") chips. Examples of these IC chips include, but are not limited to, processors, controllers, chipset components, programmable logic arrays (PLAs), memory chips, network chips, system-on-a-chip (SoCs), SSD / NAND controller ASICs, etc. In addition, in some of the drawings, signal lines are represented by lines. Some may be different to indicate more component signal paths, may have numbered labels to indicate multiple component signal paths, and / or may have arrows at one or more ends to indicate the main information flow direction. However, this should not be interpreted restrictively. Rather, such additional details may be used in relation to one or more exemplary embodiments to facilitate a more easily understood circuit. Any signal line presented, whether or not it has additional information, may actually contain one or more signals that can travel in multiple directions and may be implemented in any preferred type of signaling scheme, such as digital or analog lines implemented in differential pairs, optical fiber lines, and / or single-ended lines.

[0052] While exemplary sizes / models / values / ranges may be given, embodiments are not limited thereto. Over time, as manufacturing technologies (e.g., photolithography) mature, smaller devices are expected to be manufactured. Additionally, for the sake of illustrative and concise discussion, and to avoid obscuring specific aspects of the embodiments, known power / ground connections to IC chips and other components may or may not be shown in the figures. Furthermore, to avoid obscuring embodiments, and given that details regarding the implementation of such block diagram configurations depend heavily on the platform on which the embodiment is to be implemented—that is, such details are well within the knowledge of those skilled in the art—configurations may be shown in block diagram form. Where specific details (e.g., circuits) are described to illustrate exemplary embodiments, it will be apparent to those skilled in the art that embodiments can be carried out without these specific details, or with variations of these specific details. Therefore, the descriptions should be considered illustrative, not restrictive.

[0053] The term “connection” may be used herein to refer to any type of direct or indirect relationship between the components in question, and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical, or other connections. Furthermore, terms such as “first,” “second,” etc., may be used herein solely for the purpose of facilitating discussion and, unless otherwise indicated, have no specific temporal or chronological meaning.

[0054] The enumeration of items linked by the term "one or more of" as used in this application and claims may mean any combination of the enumerated terms. For example, the expression "one or more of A, B, or C" may mean A, B, C, A and B, A and C, B and C, or A, B, and C.

[0055] Those skilled in the art will understand from the foregoing description that the broad technology of the embodiments can be implemented in various forms. Therefore, although the embodiments have been described in relation to those specific examples, the true scope of the embodiments should not be limited thereto, for other variations will become apparent to those skilled in the art upon examination of the drawings, specification, and the following claims. According to this specification, the following items are also disclosed: [Item 1] One or more substrates, Logic coupled to the one or more boards, wherein the logic is at least partially implemented in one or more configurable or fixed-function hardware, and the logic coupled to the one or more boards is A first set of error correction codewords are programmed into a first set of pages in a block of non-volatile memory, wherein the first set of error correction codewords are programmed at a first density. A second set of error correction codewords is programmed into a second set of pages within the block, wherein the second set of error correction codewords is programmed at a second density, and the first density and the second density are different from each other. This is the logic, A memory controller equipped with the following features. [Item 2] The memory controller according to item 1, wherein the first set of error correction codewords are associated with a first error mitigation level, and the second set of error correction codewords are associated with a second error mitigation level, and the first and second error mitigation levels are different from each other. [Item 3] The memory controller according to item 1 or 2, wherein the first set of pages consists of 3 pages, and the first density is 4 codewords per page, and the second set of pages consists of 2 pages, and the second density is 3 codewords per page. [Item 4] The memory controller described in item 3, wherein the level crossings associated with the second set on the aforementioned page are spaced more closely together than the level crossings associated with the first set on the aforementioned page. [Item 5] The memory controller described in any one of items 1 to 4, wherein the block has a storage capacity of less than 1 bit per page per cell. [Item 6] The first plurality of error correction codewords and the second plurality of error correction codewords are programmed into a NAND memory page, and the memory controller is one of the items described in any one of items 1 to 5. [Item 7] Memory controller and Non-volatile memory (NVM) coupled to the memory controller, wherein when the NVM is executed by the memory controller, the memory controller A first set of error correction codewords is programmed into a first set of pages within a block of the NVM, the first set of error correction codewords being programmed at a first density. A second set of error correction codewords is programmed into a second set of pages within the block, the second set of error correction codewords being programmed at a second density, such that the first density and the second density are different from each other. NVM, which includes a set of instructions, A computing system equipped with [the following features]. [Item 8] The computing system according to item 7, wherein the first plurality of error correction codewords are associated with a first error mitigation level, and the second plurality of error correction codewords are associated with a second error mitigation level, and the first error mitigation level and the second error mitigation level are different from each other. [Item 9] The computing system according to item 7 or 8, wherein the first set of pages consists of 3 pages and the first density is 4 codewords per page, and the second set of pages consists of 2 pages and the second density is 3 codewords per page. [Item 10] The computing system described in item 9, wherein the level crossings associated with the second set of pages are spaced more closely together than the level crossings associated with the first set of pages. [Item 11] The computing system according to any one of items 7 to 10, wherein the block has a memory capacity of less than 1 bit per cell per page. [Item 12] The aforementioned block is a computing system as described in any one of items 7 to 11, including NAND memory. [Item 13] A step of programming a first plurality of error correction codewords into a first set of pages in a block of non-volatile memory, wherein the first plurality of error correction codewords are programmed at a first density, A step of programming a second set of error correction codewords into a second set of pages within the block, wherein the second set of error correction codewords are programmed at a second density, and the first density and the second density are different from each other. A method that includes [a certain feature]. [Item 14] The method according to item 13, wherein the first set of error correction codewords are associated with a first error mitigation level, the second set of error correction codewords are associated with a second error mitigation level, and the first and second error mitigation levels are different from each other. [Item 15] The method according to item 13 or 14, wherein the first set of pages consists of 3 pages and the first density is 4 codewords per page, and the second set of pages consists of 2 pages and the second density is 3 codewords per page. [Item 16] The method according to item 15, wherein the level crossings associated with the second set of pages are more closely spaced than the level crossings associated with the first set of pages. [Item 17] The method according to any one of items 13 to 16, wherein the block has a storage capacity of less than 1 bit per cell per page. [Item 18] The first plurality of error correction codewords and the second plurality of error correction codewords are programmed into a NAND memory page, as described in any one of items 13 to 17. [Item 19] A computer program that causes a processor to perform any of the methods described in items 13 through 18. [Item 20] A machine-readable recording medium for storing the computer program described in item 19. [Item 21] An apparatus comprising means for performing the method described in any one of items 13 to 18.

Claims

1. One or more substrates, Logic coupled to the one or more boards, wherein the logic is at least partially implemented in one or more configurable or fixed-function hardware, and the logic coupled to the one or more boards is A first set of error correction codewords are programmed into a first set of pages in a block of non-volatile memory, wherein the first set of error correction codewords are programmed at a first density. A second set of error correction codewords is programmed into a second set of pages within the block, wherein the second set of error correction codewords is programmed at a second density, and the first density and the second density are different from each other. This is the logic, Equipped with, The level crossings associated with the second set of the aforementioned pages are spaced more closely together than the level crossings associated with the first set of the aforementioned pages, and the level crossings are overlapping distributions of voltage levels for distinguishing bit combinations per cell of the block, in a memory controller.

2. The memory controller according to claim 1, wherein the first plurality of error correction codewords are associated with a first error mitigation level, and the second plurality of error correction codewords are associated with a second error mitigation level, and the first error mitigation level and the second error mitigation level are different from each other.

3. The memory controller according to claim 1 or 2, wherein the first set of pages consists of three pages, and the first density is four codewords per page, and the second set of pages consists of two pages, and the second density is three codewords per page.

4. The memory controller according to any one of claims 1 to 3, wherein the block has a storage capacity of less than 1 bit per cell for each page.

5. The memory controller according to any one of claims 1 to 4, wherein the first plurality of error correction codewords and the second plurality of error correction codewords are programmed into a NAND memory page.

6. Memory controller and Non-volatile memory (NVM) coupled to the memory controller, wherein when the NVM is executed by the memory controller, the memory controller A first set of error correction codewords is programmed into a first set of pages within a block of the NVM, the first set of error correction codewords being programmed at a first density. A second set of error correction codewords is programmed into a second set of pages within the block, the second set of error correction codewords being programmed at a second density, such that the first density and the second density are different from each other. NVM, which includes a set of instructions, Equipped with, The level crossings associated with the second set of the aforementioned pages are spaced more closely together than the level crossings associated with the first set of the aforementioned pages, and the level crossings are overlapping distributions of voltage levels for distinguishing combinations of bits per cell of the block, in a computing system.

7. The computing system according to claim 6, wherein the first plurality of error correction codewords are associated with a first error mitigation level, the second plurality of error correction codewords are associated with a second error mitigation level, and the first error mitigation level and the second error mitigation level are different from each other.

8. The computing system according to claim 6 or 7, wherein the first set of pages consists of three pages, and the first density is four codewords per page, and the second set of pages consists of two pages, and the second density is three codewords per page.

9. The computing system according to any one of claims 6 to 8, wherein the block has a storage capacity of less than 1 bit per cell for each page.

10. The computing system according to any one of claims 6 to 9, wherein the block includes NAND memory.

11. A step of programming a first plurality of error correction codewords into a first set of pages in a block of non-volatile memory, wherein the first plurality of error correction codewords are programmed at a first density, A step of programming a second set of error correction codewords into a second set of pages within the block, wherein the second set of error correction codewords are programmed at a second density, and the first density and the second density are different from each other. Equipped with, The level crossings associated with the second set of the aforementioned pages are spaced more closely together than the level crossings associated with the first set of the aforementioned pages, and the level crossings are an overlap of distributions of voltage levels for distinguishing the combination of bits per cell of the block, in this manner.

12. The method according to claim 11, wherein the first plurality of error correction codewords are associated with a first error mitigation level, the second plurality of error correction codewords are associated with a second error mitigation level, and the first error mitigation level and the second error mitigation level are different from each other.

13. The method according to claim 11 or 12, wherein the first set of pages consists of three pages, and the first density is four codewords per page, and the second set of pages consists of two pages, and the second density is three codewords per page.

14. The method according to any one of claims 11 to 13, wherein the block has a storage capacity of less than 1 bit per cell for each page.

15. The method according to any one of claims 11 to 14, wherein the first plurality of error correction codewords and the second plurality of error correction codewords are programmed into a NAND memory page.

16. A computer program for causing a processor to perform the method described in any one of claims 11 to 15.

17. A machine-readable recording medium for storing the computer program described in claim 16.

18. An apparatus comprising means for performing the method described in any one of claims 11 to 15.

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