Semiconductor equipment

Abstract

To provide a semiconductor device that can improve the stability of withstand voltage between the bottom electrode and the top electrode.SOLUTION: A semiconductor device has a substrate having a first top surface, a semiconductor layer on the substrate, a first insulating layer on the semiconductor layer and having a second top surface, a bottom electrode on the first insulating layer, a dielectric layer on the bottom electrode, and a top electrode on the dielectric layer, and the difference between the maximum and minimum distance between the first top surface and the second top surface is smaller than the thickness of the semiconductor layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] In a semiconductor integrated circuit such as a monolithic microwave integrated circuit (MMIC), a MIM (metal insulator metal) type capacitor in which a lower electrode, an insulating film, and an upper electrode are laminated may be formed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a conventional MIM type capacitor, sufficient breakdown voltage may not be obtained between the lower electrode and the upper electrode.

[0005] An object of this disclosure is to provide a semiconductor device capable of improving the breakdown voltage stability between a lower electrode and an upper electrode.

Means for Solving the Problems

[0006] The semiconductor device of this disclosure includes a substrate having a first upper surface, a semiconductor layer provided on the substrate, a first insulator layer provided on the semiconductor layer and having a second upper surface, a lower electrode provided on the first insulator layer, a dielectric layer provided on the lower electrode, and an upper electrode provided on the dielectric layer. A third insulating layer containing silicon is provided between the semiconductor layer and the first insulating layer, and has The first insulating layer is a polyimide layer,The difference between the maximum and minimum distances between the first upper surface and the second upper surface is smaller than the thickness of the semiconductor layer. [Effects of the Invention]

[0007] According to this disclosure, the stability of the pressure resistance between the lower electrode and the upper electrode can be improved. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a cross-sectional view showing a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a cross-sectional view (part 1) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 3] Figure 3 is a cross-sectional view (part 2) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] Figure 4 is a cross-sectional view (part 3) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] Figure 5 is a cross-sectional view (part 4) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] Figure 6 is a cross-sectional view (part 5) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] Figure 7 is a cross-sectional view (part 6) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] Figure 8 is a cross-sectional view (part 7) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] Figure 9 is a cross-sectional view showing a semiconductor device according to a reference example. [Figure 10] Figure 10 is a cross-sectional view showing a modified semiconductor device according to the first embodiment. [Figure 11] Figure 11 is a cross-sectional view showing a semiconductor device according to the second embodiment. [Modes for carrying out the invention]

[0009] [Description of Embodiments in this Disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] 〔1〕 A semiconductor device according to an aspect of the present disclosure includes a substrate having a first upper surface, a semiconductor layer provided on the substrate, a first insulator layer provided on the semiconductor layer and having a second upper surface, a lower electrode provided on the first insulator layer, a dielectric layer provided on the lower electrode, and an upper electrode provided on the dielectric layer, and a difference between a maximum value and a minimum value of a distance between the first upper surface and the second upper surface is smaller than a thickness of the semiconductor layer.

[0011] The first insulator layer is provided on the semiconductor layer, and a difference between a maximum value and a minimum value of a distance between the first upper surface of the substrate and the second upper surface of the first insulator layer is smaller than the thickness of the semiconductor layer. Therefore, even if there are defects such as pits in the semiconductor layer, the flatness of the lower electrode and the upper electrode on the first insulator layer can be made higher than in the case where the first insulator layer is not provided. Accordingly, breakdown between the lower electrode and the upper electrode can be suppressed, and the stability of the breakdown voltage between the lower electrode and the upper electrode can be improved.

[0012] 〔2〕 In 〔1〕, the first insulator layer may be a polyimide layer. In this case, it is easy to obtain excellent flatness on the second upper surface.

[0013] 〔3〕 In 〔2〕, a second insulator layer containing silicon may be provided between the first insulator layer and the lower electrode. In this case, good adhesion is easily obtained between the first insulator layer (polyimide layer) and the second insulator layer, and good adhesion is easily obtained between the second insulator layer and the lower electrode. Accordingly, better adhesion can be obtained than in the case where the first insulator layer and the lower electrode are in direct contact.

[0014] In [4], [2] or [3], a third insulating layer containing silicon may be provided between the semiconductor layer and the first insulating layer. In this case, good adhesion is likely to be obtained between the semiconductor layer and the third insulating layer, and good adhesion is likely to be obtained between the third insulating layer and the first insulating layer (polyimide layer). Therefore, better adhesion can be obtained than when the semiconductor layer and the first insulating layer are in direct contact.

[0015] 〔5〕 In [2], a second insulating layer containing silicon provided between the first insulating layer and the lower electrode, and a third insulating layer containing silicon provided between the substrate and the first insulating layer, may be provided, and the second insulating layer and the third insulating layer may be in direct contact. In this case, better adhesion can be obtained than when the first insulating layer (polyimide layer) and the lower electrode are in direct contact, and better adhesion can be obtained than when the substrate and the first insulating layer are in direct contact. Further, since the directions of the stresses generated in the second insulating layer and the third insulating layer are the same as viewed from the first insulating layer, the first insulating layer can be made less likely to warp.

[0016] 〔6〕 In any of [1] to [5], the difference between the maximum value and the minimum value may be 100 nm or less. In this case, it is easier to further improve the breakdown voltage stability between the lower electrode and the upper electrode.

[0017] 〔7〕 In any of [1] to [5], the difference between the maximum value and the minimum value may be 50 nm or less. In this case, it is easier to further improve the breakdown voltage stability between the lower electrode and the upper electrode.

[0018] 〔8〕 In any of [1] to [7], the semiconductor layer may be a nitride semiconductor layer. In this case, a high electron mobility transistor using a nitride semiconductor layer and a MIM type capacitor can be monolithically integrated.

[0019] [End of detailed description of embodiments of the present disclosure] [Details of Embodiments of the Present Disclosure] The embodiments of this disclosure will be described in detail below, but this disclosure is not limited to these embodiments. In this specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to avoid redundant descriptions.

[0020] (First Embodiment) First, the first embodiment will be described. The first embodiment relates to a semiconductor device including a MIM type capacitor. Figure 1 is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0021] As shown in Figure 1, the semiconductor device 1 according to the first embodiment mainly comprises a substrate 10, a semiconductor layer 20, a first insulating layer 40, a second insulating layer 50, a third insulating layer 30, a lower electrode 60, a dielectric layer 70, and an upper electrode 80.

[0022] The substrate 10 is, for example, a polytype 4H or 6H silicon carbide (SiC) substrate. The upper surface of the silicon carbide substrate may be either a silicon polar surface or a carbon polar surface. The substrate 10 may also be a silicon substrate. The upper surface of the silicon substrate is, for example, the (111) plane.

[0023] The semiconductor layer 20 is provided on the substrate 10. The semiconductor layer 20 is, for example, a nitride semiconductor layer. The nitride semiconductor layer constitutes part of a high electron mobility transistor (HEMT), such as an electron transport layer and an electron supply layer. The HEMT (not shown) is provided separately from the MIM type capacitor. Defects 21, such as pits, may be present in the semiconductor layer 20. As will be described in detail later, the semiconductor layer 20 is formed on the substrate 10 by an epitaxial growth method. If defects exist on the upper surface 11 of the substrate 10, defects 21 may occur.

[0024] The third insulating layer 30 is provided on top of the semiconductor layer 20. The third insulating layer 30 is, for example, a silicon oxide (SiO2) layer. The third insulating layer 30 is formed to conform to the upper surface of the semiconductor layer 20, and the upper surface of the third insulating layer 30 may have recesses that reflect the shape of the defect 21. The third insulating layer 30 constitutes, for example, a part of the HEMT.

[0025] The first insulating layer 40 is provided on top of the third insulating layer 30. The first insulating layer 40 is provided on a portion of the third insulating layer 30. The first insulating layer 40 is, for example, a polyimide layer. The first insulating layer 40 may also be a silicon oxide layer. As will be described in detail later, the first insulating layer 40 is formed by coating and curing a raw material. Therefore, even if there is a recess on the upper surface of the third insulating layer 30, the first insulating layer 40 fills the recess on the upper surface of the third insulating layer 30, and the upper surface 41 of the first insulating layer 40 is flat. For example, the distance between the upper surface 11 of the substrate 10 and the upper surface 41 of the first insulating layer 40 is constant, and the maximum value Lmax and minimum value Lmin of this distance are equal to each other. Therefore, the difference between the maximum value Lmax and the minimum value Lmin is smaller than the thickness T1 of the semiconductor layer 20. It should be noted that "flat" in this context does not mean completely free of any irregularities on the nanometer scale, but rather refers to a state that is considered "flat" according to generally accepted social standards.

[0026] The second insulating layer 50 is provided on top of the first insulating layer 40 and the third insulating layer 30. The second insulating layer 50 covers the first insulating layer 40. The second insulating layer 50 is, for example, a silicon nitride (SiN) layer or a silicon oxide layer. The second insulating layer 50 is in direct contact with the third insulating layer 30.

[0027] The lower electrode 60 is provided on the second insulating layer 50. The lower electrode 60 is provided on the second insulating layer 50 above the first insulating layer 40. In a plan view, that is, viewed from a direction perpendicular to the top surface 11, the lower electrode 60 is inside the contour of the first insulating layer 40. The lower electrode 60 has, for example, a titanium (Ti) film and a gold (Au) film on top of it.

[0028] The dielectric layer 70 is provided on the lower electrode 60 and the second insulator layer 50. The dielectric layer 70 covers the upper and side surfaces of the lower electrode 60. The dielectric layer 70 includes, for example, a nitride or oxide of silicon, aluminum (Al), hafnium (Hf), or zirconium (Zr). For example, the dielectric layer 70 is a silicon nitride layer, an aluminum oxide (AlO) layer, or a silicon oxide layer. The dielectric layer 70 may contain multiple of the above metal species. The dielectric layer 70 may contain oxynitrides of the above metal species.

[0029] The upper electrode 80 is provided on the dielectric layer 70. The upper electrode 80 is provided on the dielectric layer 70 above the lower electrode 60. In a plan view, the upper electrode 80 is inside the contour of the lower electrode 60. The upper electrode 80 has, for example, a titanium film and a gold film on top of it.

[0030] Next, a method for manufacturing the semiconductor device 1 according to the first embodiment will be described. Figures 2 to 8 are cross-sectional views showing the method for manufacturing the semiconductor device 1 according to the first embodiment.

[0031] First, as shown in Figure 2, a semiconductor layer 20 is formed on the substrate 10 by epitaxial growth. The semiconductor layer 20 can be formed, for example, by metal-organic chemical vapor deposition (MOCVD). Defects may exist on the upper surface 11 of the substrate 10, and defects 21 such as pits may be formed in the semiconductor layer 20.

[0032] Next, as shown in Figure 3, a third insulating layer 30 is formed on the semiconductor layer 20 by chemical vapor deposition (CVD).

[0033] Next, as shown in Figure 4, a first insulating layer 40 is formed on the third insulating layer 30. The first insulating layer 40 is, for example, a polyimide layer or a silicon oxide layer. If the first insulating layer 40 is a polyimide layer, it can be formed by spin coating, exposure, development, and firing of a photosensitive polyimide. Alternatively, the first insulating layer 40 may be formed by spin coating, firing, and etching of a non-photosensitive polyimide. If the first insulating layer 40 is a silicon oxide layer, it can be formed by spin coating, firing, and etching of a spin-on-glass.

[0034] Next, as shown in Figure 5, a second insulating layer 50 is formed on the first insulating layer 40 and the third insulating layer 30 by the CVD method. The first insulating layer 40 is covered by the second insulating layer 50.

[0035] Next, as shown in Figure 6, a lower electrode 60 is formed on the second insulator layer 50. In forming the lower electrode 60, for example, a titanium film and a gold film are formed over the entire surface, and then the titanium film and gold film are etched. The etching can be either dry etching or wet etching. The lower electrode 60 may also be formed by deposition and lift-off of the titanium film and gold film. In any case, since the first insulator layer 40 is covered by the second insulator layer 50, the first insulator layer 40 is not exposed to the process environment during the formation of the lower electrode 60.

[0036] Next, as shown in Figure 7, a dielectric layer 70 is formed on the lower electrode 60 and the second insulating layer 50 by CVD. The lower electrode 60 is covered by the dielectric layer 70.

[0037] Next, as shown in Figure 8, an upper electrode 80 is formed on the dielectric layer 70. The upper electrode 80 can be formed, for example, by deposition and lift-off of a titanium film and a gold film.

[0038] In this way, the semiconductor device 1 according to the first embodiment can be manufactured.

[0039] Here, the effects of the first embodiment will be explained with reference to a reference example. Figure 9 is a cross-sectional view showing a semiconductor device according to a reference example. Note that Figure 9 is used for the purpose of facilitating understanding of this disclosure and does not describe the prior art.

[0040] The semiconductor device 9 according to the reference example differs from the first embodiment mainly in that it does not have a first insulating layer 40 and a second insulating layer 50. The lower electrode 60 is provided on the third insulating layer 30. The dielectric layer 70 is provided on the lower electrode 60 and the third insulating layer 30. The dielectric layer 70 covers the lower electrode 60. The upper electrode 80 is provided on the dielectric layer 70. The lower electrode 60, the dielectric layer 70 and the upper electrode 80 have shapes that reflect the shape of the defect 21.

[0041] In the semiconductor device 9 according to the reference example, the lower electrode 60, dielectric layer 70, and upper electrode 80 have shapes that reflect the shape of the defect 21, resulting in locally thinned dielectric layer 70 and areas on the lower electrode 60 and upper electrode 80 where electric fields tend to concentrate particularly easily. On the other hand, in the semiconductor device 1 according to the first embodiment, since the first insulator layer 40 is provided, the shape of the defect 21 is hardly reflected in the shapes of the lower electrode 60, dielectric layer 70, and upper electrode 80. Therefore, the thickness of the dielectric layer 70 is constant between the lower electrode 60 and the upper electrode 80, and electric field concentration at the lower electrode 60 and upper electrode 80 is suppressed. Accordingly, according to the first embodiment, the stability of the breakdown voltage between the lower electrode 60 and the upper electrode 80 can be improved.

[0042] When the first insulating layer 40 is a polyimide layer, it is easy to obtain excellent flatness on the upper surface 41 of the first insulating layer 40. Therefore, it is easy to improve the stability of the dielectric strength.

[0043] The provision of a silicon-containing second insulating layer 50 between the first insulating layer 40 and the lower electrode 60 makes it easier to obtain good adhesion between the first insulating layer 40 and the lower electrode 60 compared to the case where the second insulating layer 50 is not provided. This is because it is easier to obtain good adhesion between the first insulating layer 40 and the second insulating layer 50, and good adhesion between the second insulating layer 50 and the lower electrode 60. In addition, the first insulating layer 40 can be kept from being exposed to the process environment during the formation of the lower electrode 60.

[0044] The provision of a third insulating layer 30 containing silicon between the semiconductor layer 20 and the first insulating layer 40 makes it easier to obtain good adhesion between the semiconductor layer 20 and the first insulating layer 40 compared to the case where the third insulating layer 30 is not provided. This is because it is easier to obtain good adhesion between the semiconductor layer 20 and the third insulating layer 30, and good adhesion between the third insulating layer 30 and the first insulating layer 40.

[0045] Since the direction of stress generated in the second insulator layer 50 and the third insulator layer 30 is the same when viewed from the first insulator layer 40, the direct contact between the second insulator layer 50 and the third insulator layer 30 makes the first insulator layer 40 less prone to warping.

[0046] The maximum value Lmax and minimum value Lmin of the distance between the upper surface 11 of the substrate 10 and the upper surface 41 of the first insulating layer 40 do not need to be equal to each other. Figure 10 is a cross-sectional view showing a semiconductor device according to a modification of the first embodiment. As shown in Figure 10, in the semiconductor device 1A according to a modification of the first embodiment, a small recess is formed on the upper surface 41 of the first insulating layer 40. In the semiconductor device 1A as well, if the difference between the maximum value Lmax and the minimum value Lmin is smaller than the thickness T1 of the semiconductor layer 20, electric field concentration at the lower electrode 60 and the upper electrode 80 is suppressed, and the stability of the breakdown voltage between the lower electrode 60 and the upper electrode 80 can be improved.

[0047] The difference between the maximum value Lmax and the minimum value Lmin is preferably 100 nm or less, more preferably 50 nm or less, and even more preferably 20 nm or less. The smaller the difference between the maximum value Lmax and the minimum value Lmin, the easier it is to increase the flatness of the lower electrode 60 and the upper electrode 80, and the easier it is to improve the stability of the pressure resistance between the lower electrode 60 and the upper electrode 80.

[0048] Because the semiconductor layer 20 is a nitride semiconductor layer, a HEMT and a MIM type capacitor using a nitride semiconductor layer can be monolithically integrated.

[0049] (Second Embodiment) Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in that the second insulating layer 50 is not provided. Figure 11 is a cross-sectional view showing a semiconductor device according to the second embodiment.

[0050] As shown in Figure 11, the semiconductor device 2 according to the second embodiment does not have a second insulating layer 50, and the lower electrode 60 is in direct contact with the first insulating layer 40. The lower electrode 60 covers the upper surface 41 and the side surface of the first insulating layer 40. The lower electrode 60 is also in direct contact with the third insulating layer 30. The dielectric layer 70 is provided on the lower electrode 60 and the third insulating layer 30. The dielectric layer 70 covers the upper surface and the side surface of the lower electrode 60.

[0051] The other components are the same as those of the first embodiment.

[0052] In the second embodiment, as in the first embodiment, the stability of the withstand voltage between the lower electrode 60 and the upper electrode 80 can be improved. However, because the second insulating layer 50 is not provided, the adhesion between the lower electrode 60 and the first insulating layer 40 may be lower than in the first embodiment. Nevertheless, since the lower electrode 60 is in direct contact with the third insulating layer 30, delamination of the lower electrode 60 is unlikely to occur.

[0053] In the first embodiment, the lower electrode 60 may cover the side surface of the first insulating layer 40 from above the second insulating layer 50.

[0054] Although embodiments have been described in detail above, the invention is not limited to any particular embodiment, and various modifications and changes are possible within the scope described in the claims. [Explanation of Symbols]

[0055] 1, 1A, 2, 9: Semiconductor equipment 10: Circuit board 11, 41:Top surface 20: Semiconductor layer 21: Defect 30: Third insulating layer 40: First insulating layer 50: Second insulating layer 60: Lower electrode 70: Dielectric layer 80:Top electrode

Claims

1. A substrate having a first upper surface, A semiconductor layer provided on the substrate, A first insulating layer having a second upper surface is provided on the semiconductor layer, A lower electrode provided on the first insulating layer, A dielectric layer provided on the lower electrode, An upper electrode provided on the dielectric layer, A third insulating layer containing silicon is provided between the semiconductor layer and the first insulating layer, It has, The first insulating layer is a polyimide layer, A semiconductor device in which the difference between the maximum and minimum distances between the first upper surface and the second upper surface is smaller than the thickness of the semiconductor layer.

2. The semiconductor device according to claim 1, further comprising a second insulating layer containing silicon, provided between the first insulating layer and the lower electrode.

3. A second insulating layer containing silicon is provided between the first insulating layer and the lower electrode, The semiconductor device according to claim 1, wherein the second insulating layer and the third insulating layer are in direct contact.

4. The semiconductor device according to any one of claims 1 to 3, wherein the difference between the maximum value and the minimum value is 100 nm or less.

5. The semiconductor device according to any one of claims 1 to 3, wherein the difference between the maximum value and the minimum value is 50 nm or less.

6. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor layer is a nitride semiconductor layer.

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