Real-time clock modules and electronic devices

Abstract

To provide a real-time clock module capable of reducing power consumption of a memory device that writes time data.SOLUTION: A real-time clock module connected to a memory device is provided with: a clock circuit that performs time measurement and generates time data; a first interface circuit that functions as a master interface for the memory device; a power supply circuit that supplies a power supply voltage to the memory device; and a control circuit that writes target time data corresponding to at least some time digits of the time data in the memory device through the first interface after starting the supply of the power supply voltage to the memory device, and stops supplying the power supply voltage after writing the target time data.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a real-time clock module and an electronic device.

Background Art

[0002] In Patent Document 1, upon initial power-on, real-time data stored in a non-volatile memory is transferred to a volatile memory. When the transfer of the real-time data is completed, the current supply to the non-volatile memory is stopped, and timekeeping is performed by a real-time clock circuit using the real-time data stored in the volatile memory and the source oscillation input from an oscillation circuit, thereby disclosing a real-time clock device that operates at low voltage and low current.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, the real-time clock device described in Patent Document 1 reduces the power consumption of the non-volatile memory by controlling the current supply immediately after the initial power-on to the built-in non-volatile memory, but it cannot reduce the power consumption of the memory device when an external memory device is used for writing time data.

Means for Solving the Problems

[0005] One aspect of the real-time clock module according to the present invention is <000003​​​​A first interface circuit that functions as a master interface to the memory device, A power supply circuit that supplies power supply voltage to the memory device, A control circuit that, after starting to supply the power supply voltage to the memory device, writes target time data corresponding to at least some of the time digits of the time data to the memory device via the first interface circuit, and stops supplying the power supply voltage to the memory device after writing the target time data to the memory device, It is equipped with.

[0006] One aspect of the electronic device according to the present invention is: One embodiment of the real-time clock module, The memory device and the above-mentioned memory device are included. [Brief explanation of the drawing]

[0007] [Figure 1] A diagram showing an example configuration of a system including a real-time clock module of the first embodiment. [Figure 2] Functional block diagram of the real-time clock module of the first embodiment. [Figure 3] A timing chart illustrating an example of timestamp processing based on event trigger signals by a control circuit. [Figure 4] A diagram showing an example of a processor configuration. [Figure 5] A figure showing an example of captured data in the first embodiment. [Figure 6] A diagram showing an example configuration of a system including a real-time clock module according to the second embodiment. [Figure 7] Functional block diagram of the real-time clock module of the second embodiment. [Figure 8] A timing chart illustrating an example of timestamp processing based on a timer trigger signal from a control circuit. [Figure 9] A figure showing an example of captured data in the second embodiment. [Figure 10] Functional block diagram of an electronic device.

Embodiments for Carrying Out the Invention

[0008] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. Note that the embodiments described below do not unduly limit the content of the present invention described in the claims. Also, not all of the configurations described below are essential constituent elements of the present invention.

[0009] 1. Real-time clock module 1-1. First embodiment FIG. 1 is a diagram showing a configuration example of a system including a real-time clock module according to the first embodiment.

[0010] As shown in FIG. 1, the real-time clock module 1 according to the first embodiment is connected to a main power supply 4, a backup power supply 5, a host device 6, and a memory device 7.

[0011] The real-time clock module 1 is supplied with a power supply voltage VDD from the main power supply 4 and a power supply voltage VBAT from the backup power supply 5. When the power supply voltage VDD is supplied from the main power supply 4, the real-time clock module 1 operates with the power supply voltage VDD, and when the supply of the power supply voltage VDD from the main power supply 4 is interrupted, it operates with the power supply voltage VBAT. Therefore, the real-time clock module 1 can continue the timing operation even while the supply of the power supply voltage VDD from the main power supply 4 is interrupted.

[0012] The host device 6 operates with the power supply voltage VDD supplied from the main power supply 4. In this embodiment, the host device 6 and the real-time clock module 1 communicate via an I 2 C bus with the host device 6 as the master and the real-time clock module 1 as the slave. I 2C is the abbreviation of Inter-Integrated Circuit. The host device 6 is realized by, for example, an MCU or an MPU. MCU is the abbreviation of Micro Controller Unit, and MPU is the abbreviation of Micro Processor Unit.

[0013] The memory device 7 operates with the power supply voltage MVDD supplied from the real-time clock module 1. The memory device 7 is, for example, a non-volatile memory such as an EEPROM. EEPROM is the abbreviation of Electrically Erasable Programmable Read-Only Memory.

[0014] In this embodiment, the real-time clock module 1 and the memory device 7 communicate via an I 2 C bus with the real-time clock module 1 as the master and the memory device 7 as the slave.

[0015] Figure 2 is a functional block diagram of the real-time clock module 1 of the first embodiment. As shown in Figure 2, the real-time clock module 1 includes a resonator 2 and a real-time clock circuit 3.

[0016] The real-time clock module 1 is supplied with the power supply voltage VDD from the main power supply 4 via the terminal P1 of the real-time clock circuit 3, and the power supply voltage VBAT from the backup power supply 5 via the terminal P2 of the real-time clock circuit 3.

[0017] The resonator 2 may be a tuning fork type crystal resonator, an AT cut crystal resonator, an SC cut crystal resonator, etc., or a piezoelectric resonator other than a SAW resonator or a crystal resonator. SAW is the abbreviation of Surface Acoustic Wave. Also, the resonator 2 may be a MEMS resonator made of a silicon semiconductor. MEMS is the abbreviation of Micro Electro Mechanical Systems. The resonator 2 may be excited by the piezoelectric effect or driven by the Coulomb force.

[0018] The real-time clock circuit 3 comprises an oscillator circuit 10, a frequency divider circuit 20, a timing circuit 30, an event trigger circuit 40, a control circuit 50, a first interface circuit 60, a group of registers 70, a second interface circuit 80, a temperature sensor 90, an oscillator monitoring circuit 100, a power supply voltage monitoring circuit 110, a power supply voltage selection circuit 120, a power supply circuit 130, and an interrupt generation circuit 140. However, the real-time clock circuit 3 may be configured by omitting or changing some of these elements, or by adding other elements. In this embodiment, the real-time clock circuit 3 is a single-chip integrated circuit, but it may be composed of multiple chip integrated circuits, or at least a part of it may be composed of discrete components.

[0019] The power supply voltage monitoring circuit 110 monitors the power supply voltage VDD, determines whether the power supply voltage VDD is greater than or equal to a predetermined voltage value VT1, and outputs a determination signal VDET. In this embodiment, the power supply voltage monitoring circuit 110 outputs a high-level determination signal VDET if it determines that the power supply voltage VDD is greater than or equal to the voltage value VT1, and outputs a low-level determination signal VDET if it determines that the power supply voltage VDD is less than the voltage value VT1.

[0020] Furthermore, the power supply voltage monitoring circuit 110 monitors the power supply voltage VDD, determines whether the power supply voltage VDD is less than or equal to a predetermined voltage value VT2, and outputs a first power supply voltage drop signal VDDLOW. In this embodiment, if the power supply voltage monitoring circuit 110 determines that the power supply voltage VDD is less than or equal to the voltage value VT2, it outputs a high-level first power supply voltage drop signal VDDLOW, and if it determines that the power supply voltage VDD is greater than the voltage value VT2, it outputs a low-level first power supply voltage drop signal VDDLOW. Note that the voltage value VT2 may be the same as or different from the voltage value VT1.

[0021] Furthermore, the power supply voltage monitoring circuit 110 monitors the power supply voltage VBAT, determines whether the power supply voltage VBAT is less than or equal to a predetermined voltage value VT3, and outputs a second power supply voltage drop signal VBATLOW. In this embodiment, if the power supply voltage monitoring circuit 110 determines that the power supply voltage VBAT is less than or equal to the voltage value VT3, it outputs a high-level second power supply voltage drop signal VBATLOW, and if it determines that the power supply voltage VBAT is greater than the voltage value VT3, it outputs a low-level second power supply voltage drop signal VBATLOW.

[0022] Furthermore, the power supply voltage monitoring circuit 110 monitors the power supply voltage VOUT output from the power supply voltage selection circuit 120, determines whether the power supply voltage VOUT is less than or equal to a predetermined voltage value VT4, and outputs a third power supply voltage drop signal VTMPLOW. In this embodiment, if the power supply voltage monitoring circuit 110 determines that the power supply voltage VOUT is less than or equal to the voltage value VT4, it outputs a high-level third power supply voltage drop signal VTMPLOW, and if it determines that the power supply voltage VOUT is greater than the voltage value VT4, it outputs a low-level third power supply voltage drop signal VTMPLOW.

[0023] In this way, the power supply voltage monitoring circuit 110 monitors the power supply voltages VDD, VBAT, and VOUT, and generates power supply voltage monitoring data, namely the first power supply voltage drop signal VDDLOW, the second power supply voltage drop signal VBATLOW, and the third power supply voltage drop signal VTMPLOW, respectively.

[0024] The power supply voltage selection circuit 120 selects either the power supply voltage VDD or the power supply voltage VBAT based on the determination signal VDET and outputs it as the power supply voltage VOUT. Specifically, the power supply voltage selection circuit 120 selects the power supply voltage VDD when the determination signal VDET is at a high level, that is, when the power supply voltage monitoring circuit 110 determines that the power supply voltage VDD is greater than or equal to the voltage value VT1. Conversely, the power supply voltage selection circuit 120 selects the power supply voltage VBAT when the determination signal VDET is at a low level, that is, when the power supply voltage monitoring circuit 110 determines that the power supply voltage VDD is less than the voltage value VT1.

[0025] Therefore, when the power supply voltage VDD is supplied from the main power supply 4 to the real-time clock module 1, the power supply voltage VOUT is the power supply voltage VDD and is a predetermined voltage value greater than or equal to VT1. When the supply of power supply voltage VDD from the main power supply 4 to the real-time clock module 1 is cut off, the power supply voltage VOUT immediately switches to the power supply voltage VBAT and becomes a predetermined voltage value less than or equal to VT1. Therefore, the real-time clock module 1 can continue its timing operation even when the supply of power supply voltage VDD from the main power supply 4 is cut off. In contrast, the host device 6 that controls the operation of the real-time clock module 1 operates when power supply voltage VDD is supplied from the main power supply 4, and stops operating when the supply of power supply voltage VDD from the main power supply 4 is cut off.

[0026] The power supply circuit 130 generates stabilized power supply voltages VOSC and VLOGIC with constant voltage values ​​based on the power supply voltage VOUT. The power supply circuit 130 is implemented, for example, by a regulator.

[0027] The power supply voltage VOSC is supplied to the oscillation circuit 10. The power supply voltage VLOGIC is supplied to the frequency divider circuit 20, the timing circuit 30, the event trigger circuit 40, the control circuit 50, the first interface circuit 60, the register group 70, the second interface circuit 80, the temperature sensor 90, the oscillation monitoring circuit 100, the power supply voltage monitoring circuit 110, and the interrupt generation circuit 140.

[0028] Furthermore, the power supply circuit 130 generates a power supply voltage MVDD in response to instructions from the control circuit 50 and supplies the power supply voltage MVDD to the memory device 7 via terminal P5 of the real-time clock circuit 3.

[0029] The temperature sensor 90 outputs a temperature signal VTMP whose magnitude changes according to the temperature. The temperature signal VTMP may be a digital signal or an analog signal.

[0030] The oscillation circuit 10 generates a first clock signal CK1 by causing the resonator 2 to oscillate. Specifically, the oscillation circuit 10 is electrically connected to both ends of the resonator 2 via terminals P3 and P4 of the real-time clock circuit 3, and oscillates the resonator 2 by amplifying the output signal of the resonator 2 and feeding it back, thereby outputting the first clock signal CK1. The oscillation circuit 10 also incorporates a temperature compensation circuit that controls the frequency of the first clock signal CK1 to remain constant regardless of temperature by changing the frequency of the first clock signal CK1 according to the temperature signal VTMP output from the temperature sensor 90. In this embodiment, the frequency of the first clock signal CK1 is 32.768 kHz. However, the frequency of the first clock signal CK1 is not particularly limited. In this embodiment, when the power supply voltage VOUT is greater than the voltage value VT4, that is, when the third power supply voltage drop signal VTMPLOW is at a low level, the temperature compensation circuit operates normally. On the other hand, if the power supply voltage VOUT is less than or equal to the voltage value VT4, that is, if the third power supply voltage drop signal VTMPLOW is at a high level, the normal operation of the temperature compensation circuit cannot be guaranteed, and therefore the temperature compensation circuit will stop operating.

[0031] The oscillation monitoring circuit 100 monitors the first clock signal CK1, determines whether the oscillation circuit 10 has stopped oscillating, and outputs an oscillation stop signal FST. In this embodiment, the oscillation monitoring circuit 100 determines that the oscillation circuit 10 has stopped oscillating if the logic level of the first clock signal CK1 does not invert for a predetermined time, and outputs a high-level oscillation stop signal FST. Also, the oscillation monitoring circuit 100 determines that the oscillation circuit 10 has not stopped oscillating if the logic level of the first clock signal CK1 inverts within a predetermined time, and outputs a low-level oscillation stop signal FST. In this way, the oscillation monitoring circuit 100 monitors the first clock signal CK1 and generates the oscillation stop signal FST, which is oscillation monitoring data.

[0032] The frequency divider circuit 20 divides the first clock signal CK1 to generate a second clock signal CK2 having a desired frequency. In this embodiment, the division ratio of the frequency divider circuit 20 is 32, and the frequency of the second clock signal CK2 is 1.024 kHz. However, the division ratio of the frequency divider circuit 20 and the frequency of the second clock signal CK2 are not particularly limited.

[0033] The timing circuit 30 performs timing based on the second clock signal CK2 and generates time data TM. In this embodiment, the time data TM has time digits of 1 / 1024 seconds, seconds, minutes, hours, days, months, and years. Specifically, the time data TM consists of binary subsecond data representing time in units of 1 / 1024 seconds as 0 to 1023, BCD format second data representing time in units of seconds as 0 to 59, BCD format minute data representing time in units of minutes as 0 to 59, BCD format hour data representing time in units of hours as 0 to 23, BCD format day data representing time in units of days as 1 to 31, BCD format month data representing time in units of months as 1 to 12, and BCD format year data representing time in units of years as 0 to 9999. BCD stands for Binary Coded Decimal.

[0034] The event trigger circuit 40 receives the first event signal EVIN1, the second event signal EVIN2, and the third event signal EVIN3, which are input from the host device 6 via terminals P10, P11, and P12 of the real-time clock circuit 3, respectively. The event trigger circuit 40 also receives the event command detection signal WRCom, output from the second interface circuit 80. Furthermore, the event trigger circuit 40 receives the first power supply voltage drop signal VDDLOW, the second power supply voltage drop signal VBATLOW, and the third power supply voltage drop signal VTMPLOW, output from the power supply voltage monitoring circuit 110. Finally, the event trigger circuit 40 receives the oscillation stop signal FST, output from the oscillation monitoring circuit 100. When at least one rising edge occurs in the event command detection signal WRCom, the first power supply voltage drop signal VDDLOW, the second power supply voltage drop signal VBATLOW, the third power supply voltage drop signal VTMPLOW, and the oscillation stop signal FST, the event trigger circuit 40 outputs a high-pulse event trigger signal EVTRG. Furthermore, the event trigger circuit 40 also outputs a high-pulse event trigger signal EVTRG when at least one of the specified edges of the first event signal EVIN1, the second event signal EVIN2, and the third event signal EVIN3 occurs. The edges of the first event signal EVIN1, the second event signal EVIN2, and the third event signal EVIN3 that generate the event trigger signal EVTRG may be specified as rising edges, falling edges, or both edges, respectively, by the event control registers included in the register group 70.

[0035] The control circuit 50 controls the supply of the power supply voltage MVDD from the power supply circuit 130 to the memory device 7, and also controls the writing of time data TM to the memory device 7 via the first interface circuit 60. Specifically, the control circuit 50 controls the power supply circuit 130 to start supplying the power supply voltage MVDD to the memory device 7, then writes target time data corresponding to at least some of the time digits of the time data TM to the memory device 7 via the first interface circuit 60, and after writing the target time data to the memory device 7, controls the power supply circuit 130 to stop supplying the power supply voltage MVDD to the memory device 7.

[0036] In particular, in this embodiment, the control circuit 50 starts supplying the power supply voltage MVDD to the memory device 7 in response to the occurrence of an event. The control circuit 50 also selects at least one of several types of event data as the target event data to be stored in response to the occurrence of an event, and selects data corresponding to at least some of the time digits of the time data TM generated by the timing circuit 30 as the target time data to be stored. That is, the control circuit 50 starts supplying the power supply voltage MVDD to the memory device 7 in response to the event trigger signal EVTRG output from the event trigger circuit 40, and selects the target event data and target time data.

[0037] The multiple types of event data may include the first power supply voltage drop signal VDDLOW, the second power supply voltage drop signal VBATLOW, and the third power supply voltage drop signal VTMPLOW, which are power supply voltage monitoring data generated by the power supply voltage monitoring circuit 110. Furthermore, the multiple types of event data may also include the oscillation stop signal FST, which is oscillation monitoring data generated by the oscillation monitoring circuit 100.

[0038] Furthermore, events are generated by external input signals input from outside the real-time clock module 1, and multiple types of event data may include data corresponding to said external input signals. In this embodiment, said external input signals are a first event signal EVIN1, a second event signal EVIN2, a third event signal EVIN3, and an event generation command that generates an event, and the data corresponding to said external input signals are the first event signal EVIN1, the second event signal EVIN2, the third event signal EVIN3, and an event command detection signal WRCom.

[0039] The control circuit 50 then stores the captured data CPDT, which includes the target time data and the target event data, in the memory device 7 via the first interface circuit 60. In other words, the control circuit 50 performs a timestamp processing in response to the event trigger signal EVTRG, associating the target time data and the target event data and storing them in the memory device 7.

[0040] Furthermore, after the timestamp processing is completed, the control circuit 50 stops supplying the power supply voltage MVDD to the memory device 7.

[0041] Figure 3 is a timing chart diagram showing an example of timestamp processing based on the event trigger signal EVTRG by the control circuit 50. In the example in Figure 3, at time t1, the event trigger signal EVTRG changes from a low level to a high level, and at time t2, the control circuit 50 starts supplying the power supply voltage MVDD from the power supply circuit 130 to the memory device 7. Next, during the period from time t2 to t3, the control circuit 50 continues to supply the power supply voltage MVDD from the power supply circuit 130 to the memory device 7 and writes the capture data CPDT to the memory device 7 via the first interface circuit 60. Then, at time t3, after the writing of the capture data CPDT to the memory device 7 is completed, the control circuit 50 stops supplying the power supply voltage MVDD from the power supply circuit 130 to the memory device 7.

[0042] In this embodiment, the control circuit 50 includes a processor 51 and a non-volatile memory 52. ​​The non-volatile memory 52 stores an instruction set 521 that specifies target time data and target event data. The processor 51, in synchronization with the first clock signal CK1, starts supplying the power supply voltage MVDD from the power supply circuit 130 to the memory device 7 based on the instruction set 521, selects the target time data and target event data, stores them in the memory device 7 via the first interface circuit 60, and then stops supplying the power supply voltage MVDD from the power supply circuit 130 to the memory device 7. In other words, the instruction set 521 consists of a plurality of instruction codes necessary for the control circuit 50 to perform timestamp processing.

[0043] In order to reduce power consumption, the processor 51 may wake from sleep mode when an event trigger signal EVTRG is generated, perform control processing and timestamp processing for the power supply circuit 130, and then return to sleep mode once these processes are completed.

[0044] Figure 4 shows an example configuration of the processor 51. As shown in Figure 4, the processor 51 includes a fetch circuit 511, a decode circuit 512, a logic operation circuit 513, a data buffer 514, and a capture circuit 515.

[0045] The fetch circuit 511 fetches each instruction code included in the instruction set 521 in sequence, synchronized with the first clock signal CK1.

[0046] The decode circuit 512, synchronized with the first clock signal CK1, sequentially decodes each instruction code fetched by the fetch circuit 511 and outputs a control signal corresponding to the decoding result.

[0047] The logic operation circuit 513 performs a logic operation selected from multiple types of logic operations according to the control signal output from the decoding circuit 512 on one or two input data selected from multiple input data. The multiple input data include subsecond data, second data, minute data, hour data, day data, month data, and year data included in the time data TM, and the first power supply voltage drop signal VDDLOW, second power supply voltage drop signal VBATLOW, third power supply voltage drop signal VTMPLOW, oscillation stop signal FST, first event signal EVIN1, second event signal EVIN2, third event signal EVIN3, and event command detection signal WRCom included in multiple types of event data. The multiple types of logic operations include, for example, through operation, NOT operation, AND operation, OR operation, XOR operation, bit shift operation, addition, subtraction, etc.

[0048] The data buffer 514 holds the data output from the logic circuit 513 in synchronization with the first clock signal CK1.

[0049] The capture circuit 515, in accordance with the control signal output from the decode circuit 512 and synchronized with the first clock signal CK1, writes the data held in the data buffer 514 to a predetermined address in the memory device 7 via the first interface circuit 60, and increments the address. The data buffer 514 holds, for example, each 8-bit data that constitutes the captured data CPDT in order, and the capture circuit 515 writes each of these data to the memory device 7 via the first interface circuit 60.

[0050] In this embodiment, the processor 51, in accordance with the instruction set 521, can store the captured data CPDT, which includes the selected target time data and target event data, in the memory device 7 when the event trigger signal EVTRG occurs. That is, each data item constituting the captured data CPDT can be arbitrarily selected by the instruction set 521.

[0051] Furthermore, according to the instruction set 521, the processor 51 can also perform timestamp processing only if the cause of the event trigger signal EVTRG is one or more signals selected from the first power supply voltage drop signal VDDLOW, the second power supply voltage drop signal VBATLOW, the third power supply voltage drop signal VTMPLOW, the oscillation stop signal FST, the first event signal EVIN1, the second event signal EVIN2, the third event signal EVIN3, and the event command detection signal WRCom, when the event trigger signal EVTRG occurs. In other words, the signal that triggers timestamp processing can be arbitrarily selected by the instruction set 521. For example, if the instruction set 521 selects only the first event signal EVIN1 as the signal that triggers timestamp processing, the processor 51 can determine whether the cause of the event trigger signal EVTRG is the first event signal EVIN1 based on the logic level of the first event signal EVIN1 when the event trigger signal EVTRG occurs, and then decide whether or not to perform timestamp processing based on the determination result.

[0052] Returning to the explanation of Figure 2, the first interface circuit 60 is an interface circuit for communication between the real-time clock module 1 and the memory device 7. In the communication via the first interface circuit 60, the real-time clock module 1 is the master and the memory device 7 is the slave. That is, the first interface circuit 60 functions as a master interface to the memory device 7. In this embodiment, the first interface circuit 60 is I 2This is a C-bus compatible interface circuit that communicates with the memory device 7 based on the serial clock signal SCL1 output via terminal P6 of the real-time clock circuit 3 and the serial data signal SDA1 input / output via terminal P7 of the real-time clock circuit 3. However, the first interface circuit 60 may be another serial bus compatible interface circuit such as SPI, or a parallel bus compatible interface circuit. SPI stands for Serial Peripheral Interface.

[0053] The first interface circuit 60 transmits commands to the memory device 7 via terminals P6 and P7 in response to instructions from the processor 51. The memory device 7 receives these commands and performs various processing in accordance with them. For example, the first interface circuit 60 sequentially acquires each of the 8-bit data that constitute the captured data CPDT output from the control circuit 50 and writes each of these data to the memory device 7.

[0054] Furthermore, when the first interface circuit 60 receives a control signal from the second interface circuit 80 requesting the reading of the captured data CPDT, it reads the captured data CPDT from the memory device 7 and outputs it to the second interface circuit 80.

[0055] The memory device 7 stores the capture data CPDT, which includes the target time data and target event data selected by the control circuit 50. In this embodiment, the memory device 7 is a non-volatile memory such as an EEPROM and functions as an N-stage FIFO capable of storing N capture data CPDTs. That is, the memory device 7 can simultaneously store N capture data CPDTs for N occurrences of events. FIFO stands for First In First Out.

[0056] Figure 5 shows an example of capture data CPDT stored in memory device 7. In the example in Figure 5, the capture data CPDT is 64 bits of data and is stored, for example, at addresses 0x0 to 0x07 of memory device 7.

[0057] Specifically, at address 0x0 of memory device 7, bits 7-2 store the lower 6 bits of the 10-bit subsecond data included in the time data TM, bit 1 stores data corresponding to the logic level of the third event signal EVIN3, and bit 0 stores data corresponding to the logic level of the second event signal EVIN2.

[0058] Furthermore, at address 0x1 of memory device 7, bits 7-4 store the lower 4 bits of the 7-bit second data included in the time data TM, and bits 3-0 store the upper 4 bits of the 10-bit subsecond data.

[0059] Furthermore, at address 0x2 of memory device 7, bits 7-3 store the 5-bit minute data included in the time data TM, and bits 2-0 store the upper 3 bits of the 7-bit second data.

[0060] Furthermore, at address 0x3 of memory device 7, bits 7-2 store the 6-bit time data included in the time data TM, and bits 1-0 store the upper 2 bits of the 7-bit minute data.

[0061] Furthermore, at address 0x4 of memory device 7, bits 7 to 6 store the lower two bits of the five-bit month data included in the time data TM, and bits 5 to 0 store the six-bit day data included in the time data TM.

[0062] Furthermore, at address 0x5 of memory device 7, bits 7-3 store the lower 5 bits of the 8-bit year data included in the time data TM, and bits 2-0 store the upper 3 bits of the 5-bit month data.

[0063] Furthermore, at address 0x6 of memory device 7, bit 7 stores data corresponding to the logic level of the second power supply voltage drop signal VBATLOW, bit 6 stores data corresponding to the logic level of the third power supply voltage drop signal VTMPLOW, bit 5 stores data corresponding to the logic level of the first power supply voltage drop signal VDDLOW, bit 4 stores data corresponding to the logic level of the oscillation stop signal FST, bit 3 stores data corresponding to the logic level of the first event signal EVIN1, and bits 2 to 0 store the upper 3 bits of the 8-bit year data.

[0064] Furthermore, the memory device 7 at address 0x7 stores data indicating the trigger for the timestamp processing. Specifically, if the third event signal EVIN3 is the trigger, bit 7 is set to 1; if the second event signal EVIN2 is the trigger, bit 6 is set to 1; if the first event signal EVIN1 is the trigger, bit 5 is set to 1; if the second power supply voltage drop signal VBATLOW is the trigger, bit 4 is set to 1; if the third power supply voltage drop signal VTMPLOW is the trigger, bit 3 is set to 1; if the first power supply voltage drop signal VDDLOW is the trigger, bit 2 is set to 1; if the oscillation stop signal FST is the trigger, bit 1 is set to 1; and if the event command detection signal WRCom is the trigger, bit 0 is set to 1.

[0065] In the example shown in Figure 5, the sub-second data, second data, minute data, hour data, day data, month data, and year data are the target time data, while all other data are the target event data.

[0066] Returning to the explanation in Figure 2, when the processor 51 finishes timestamp processing based on the event trigger signal EVTRG, it outputs a timestamp completion signal TSEND to the interrupt generation circuit 140.

[0067] The interrupt generation circuit 140 generates an interrupt signal INT based on the timestamp end signal TSEND and outputs the interrupt signal INT to the host device 6 via terminal P13 of the real-time clock circuit 3. Upon receiving the interrupt signal INT, the host device 6 performs predetermined interrupt processing. For example, the host device 6 sends a command to the real-time clock module 1 requesting the reading of timestamp data and receives the captured data CPDT stored in the memory device 7 from the real-time clock module 1.

[0068] Furthermore, in order to reduce the overall power consumption of the system, the host device 6 enters a sleep state when not performing any processing. When it receives an interrupt signal INT while in the sleep state, it wakes up from the sleep state, reads the timestamp data, and then returns to the sleep state once the necessary processing is complete.

[0069] The register group 70 includes various registers. For example, the register group 70 includes an event control register, a flag register, a command trigger register, etc. The event control register holds, for example, 2 bits of data for specifying whether the edges of the first event signal EVIN1, the second event signal EVIN2, and the third event signal EVIN3 that generate the event trigger signal EVTRG are rising edges, falling edges, or both. The flag register holds a first power supply voltage drop flag, which is set to 1 when the rising edge of the first power supply voltage drop signal VDDLOW occurs; a second power supply voltage drop flag, which is set to 1 when the rising edge of the second power supply voltage drop signal VBATLOW occurs; a third power supply voltage drop flag, which is set to 1 when the rising edge of the third power supply voltage drop signal VTMPLOW occurs; and an oscillation stop flag, which is set to 1 when the rising edge of the oscillation stop signal FST occurs. The command trigger register is a register for generating an event command detection signal WRCom in response to an event generation command.

[0070] The second interface circuit 80 is an interface circuit for communication between the real-time clock module 1 and the host device 6. In communication via the second interface circuit 80, the host device 6 is the master and the real-time clock module 1 is the slave. That is, the second interface circuit 80 functions as a slave interface to the host device 6. In this embodiment, the second interface circuit 80 is I 2 This is a C-bus compatible interface circuit that communicates with the host device 6 based on the serial clock signal SCL2 input via terminal P8 of the real-time clock circuit 3 and the serial data signal SDA2 input and output via terminal P9 of the real-time clock circuit 3. However, the second interface circuit 80 may be another serial bus compatible interface circuit such as SPI, or a parallel bus compatible interface circuit. SPI stands for Serial Peripheral Interface.

[0071] The second interface circuit 80 receives commands from the host device 6 via terminals P8 and P9 and performs various processes according to the received commands.

[0072] Specifically, when the second interface circuit 80 receives a command from the host device 6 requesting time setting, it updates the time data TM generated by the timing circuit 30 with the time data included in the command.

[0073] Furthermore, when the second interface circuit 80 receives a command from the host device 6 requesting time reading, it acquires the time data TM generated by the timing circuit 30 and transmits it to the host device 6.

[0074] Furthermore, when the second interface circuit 80 receives a command from the host device 6 requesting the reading of timestamp data, it outputs a control signal to the first interface circuit 60 requesting the reading of the captured data CPDT. The second interface circuit 80 then receives the captured data CPDT read from the memory device 7 by the first interface circuit 60 and transmits it to the host device 6. Alternatively, the real-time clock circuit 3 may have a through mode in which terminals P6 and P8 are electrically connected and terminals P7 and P9 are electrically connected. The host device 6 may then set the real-time clock circuit 3 to through mode, send a command to the memory device 7 requesting the reading of the captured data CPDT, and receive the captured data CPDT read from the memory device 7.

[0075] Furthermore, when the second interface circuit 80 receives a command from the host device 6 requesting the writing or reading of data to or from various registers included in the register group 70, it performs the writing or reading of data to or from the target register. For example, when the second interface circuit 80 receives an event occurrence command, which is a command requesting the writing of arbitrary data to a command trigger register, it generates an event command detection signal WRCom.

[0076] Furthermore, when the second interface circuit 80 receives a command from the host device 6 requesting to write or read data to or from the non-volatile memory 52, it performs the writing or reading of data to or from the non-volatile memory 52. ​​For example, in the pre-shipment inspection process of the real-time clock module 1, the inspection device, which functions as the host device 6, sends a command requesting to write the instruction set 521 to the non-volatile memory 52, and the second interface circuit 80 receives the command and writes the instruction set 521 to the non-volatile memory 52.

[0077] As described above, in the real-time clock module 1 of the first embodiment, the control circuit 50 starts supplying the power supply voltage MVDD to the memory device 7, then writes the captured data CPDT to the memory device 7 via the first interface circuit 60, and stops supplying the power supply voltage MVDD to the memory device 7 after writing the captured data CPDT to the memory device 7. In other words, according to the real-time clock module 1 of the first embodiment, the supply of the power supply voltage MVDD to the memory device 7 is started before writing the captured data CPDT to the memory device 7, and the supply of the power supply voltage MVDD to the memory device 7 is stopped after writing the captured data CPDT to the memory device 7, so the power consumption of the memory device 7 can be reduced. Furthermore, because the real-time clock module 1 writes the captured data CPDT to the memory device 7, the sleep period of the host device 6, which has a higher power consumption than the real-time clock module 1, can be extended, so the power consumption of the entire system can be reduced.

[0078] Furthermore, in the real-time clock module 1 of the first embodiment, the control circuit 50 selects at least one of several types of event data as target event data to be stored in response to the occurrence of an event, and also selects data corresponding to at least a portion of the time digits of the time data TM as target time data to be stored, and stores the capture data CPDT, which includes the target time data and target event data, in the memory device 7. Specifically, in the control circuit 50, the processor 51 selects the target time data and target event data based on the instruction set 521 stored in the non-volatile memory 52. ​​Therefore, according to the real-time clock module 1 of the first embodiment, it is possible to prevent unnecessary event data for each application from being stored in the memory device 7 in the timestamp.

[0079] 1-2. Second Embodiment Regarding the real-time clock module 1 of the second embodiment, the same reference numerals are used for components similar to those in the first embodiment, and descriptions that overlap with those of the first embodiment are omitted or simplified. The main focus of this explanation will be on the differences from the first embodiment.

[0080] Figure 6 shows an example of the system configuration including the real-time clock module 1 of the second embodiment.

[0081] As shown in Figure 6, the real-time clock module 1 of the second embodiment is connected to a main power supply 4, a backup power supply 5, a host device 6, a memory device 7, and M sensor devices 8-1 to 8-M, where M is an integer greater than or equal to 1.

[0082] Similar to the first embodiment, the real-time clock module 1 is supplied with a power supply voltage VDD from the main power supply 4 and a power supply voltage VBAT from the backup power supply 5. The real-time clock module 1 operates with the power supply voltage VDD when it is supplied from the main power supply 4, and operates with the power supply voltage VBAT when the supply of power supply voltage VDD from the main power supply 4 is cut off. Therefore, the real-time clock module 1 can continue its timing operation even when the supply of power supply voltage VDD from the main power supply 4 is cut off.

[0083] Similar to the first embodiment, the host device 6 operates with the power supply voltage VDD supplied from the main power supply 4, and the host device 6 and the real-time clock module 1 are configured with the host device 6 as the master and the real-time clock module 1 as the slave. 2 Communication is conducted via the C bus.

[0084] Memory device 7 is a non-volatile memory such as an EEPROM, and operates on power supply voltage MVDD supplied from the real-time clock module 1. Sensor devices 8-1 to 8-M are, for example, temperature sensors, position information sensors, inertial sensors, etc. The real-time clock module 1, memory device 7, and sensor devices 8-1 to 8-M are configured with the real-time clock module 1 as the master and memory device 7 and sensor devices 8-1 to 8-M as slaves, sharing a common I 2 Communication is conducted via the C bus.

[0085] Figure 7 is a functional block diagram of the real-time clock module 1 of the second embodiment. As shown in Figure 7, the real-time clock module 1 of the second embodiment differs from the real-time clock module 1 of the first embodiment in that sensor devices 8-1 to 8-M are connected and the real-time clock circuit 3 includes a timer trigger circuit 150.

[0086] In the second embodiment, the first interface circuit 60 is an interface circuit for communication between the real-time clock module 1 and the memory device 7 and sensor devices 8-1 to 8-M. In communication via the first interface circuit 60, the real-time clock module 1 is the master, and the memory device 7 and sensor devices 8-1 to 8-M are slaves. That is, the first interface circuit 60 functions as a master interface for the memory device 7 and sensor devices 8-1 to 8-M. The first interface circuit 60 is I 2 This is a C-bus compatible interface circuit that communicates with the memory device 7 and sensor devices 8-1 to 8-M based on the serial clock signal SCL1 output via terminal P6 of the real-time clock circuit 3 and the serial data signal SDA1 input and output via terminal P7 of the real-time clock circuit 3.

[0087] Similar to the first embodiment, the first interface circuit 60 transmits commands to the memory device 7 via terminals P6 and P7 in response to instructions from the processor 51, and the memory device 7 receives the commands and performs various processing in accordance with the commands. For example, the first interface circuit 60 sequentially acquires each of the 8 bits that constitute the capture data CPDT output from the control circuit 50 and writes each of the data to the memory device 7.

[0088] Furthermore, in the second embodiment, the first interface circuit 60 transmits commands corresponding to the instructions of the processor 51 to the sensor devices 8-1 to 8-M via terminals P6 and P7, and the sensor devices 8-1 to 8-M receive the commands and perform various processes corresponding to the commands.

[0089] In particular, in this embodiment, the first interface circuit 60 sends a command to the sensor device 8-i requesting it to transmit the detected data in response to an instruction from the processor 51, and the sensor device 8-i receives the command and transmits the detected data to the first interface circuit 60. The first interface circuit 60 receives the data detected by the sensor device 8-i and transmits the received data to the processor 51. i is an integer between 1 and M.

[0090] The timer trigger circuit 150 is supplied with the power supply voltage VLOGIC. Based on the time data TM, the timer trigger circuit 150 outputs a high-pulse timer trigger signal TMTRG every time the time determined by the control time data set in the timer setting register included in the register group 70 has elapsed. In other words, the timer trigger circuit 150 repeatedly outputs a high-pulse timer trigger signal TMTRG at the timing determined by the control time data.

[0091] The control time data is pre-set in the timer setting register by the host device 6. Specifically, the second interface circuit 80 receives the control time data transmitted from the host device 6 and sets the received control time data in the timer setting register.

[0092] The control circuit 50 controls the power supply circuit 130 to start supplying the power supply voltage MVDD to the memory device 7 at a timing determined by the control time data set in the timer setting register. Specifically, in order to reduce power consumption, the processor 51 wakes up from sleep mode at a timing determined by the control time data and starts supplying the power supply voltage MVDD to the memory device 7.

[0093] After the control circuit 50 starts supplying the power supply voltage MVDD to the memory device 7, it writes target time data corresponding to at least some of the time digits of the time data TM to the memory device 7 via the first interface circuit 60. In the second embodiment, after the control circuit 50 starts supplying the power supply voltage MVDD to the memory device 7, it acquires data detected by sensor devices 8-1 to 8-M via the first interface circuit 60, and writes the sensor data, including the acquired data, to the memory device 7 via the first interface circuit 60. That is, the control circuit 50 writes capture data CPDT, including the target time data and sensor data, to the memory device 7.

[0094] For example, one of the sensor devices 8-1 to 8-M may be a temperature sensor, and the sensor data may include temperature data. In this case, the temperature compensation circuit included in the oscillation circuit 10 may use the data detected by the temperature sensor, which is one of the sensor devices 8-1 to 8-M, instead of the temperature signal VTMP output from the temperature sensor 90. Also, for example, one of the sensor devices 8-1 to 8-M may be a position information sensor, and the sensor data may include position data. The position information sensor may be, for example, a GPS sensor. GPS stands for Global Positioning System or Global Positioning Satellite. Also, for example, one of the sensor devices 8-1 to 8-M may be an inertial sensor, and the sensor data may include inertial data. For example, the inertial sensor may be an acceleration sensor, and the inertial data may be acceleration data. Also, for example, the inertial sensor may be an angular velocity sensor, and the inertial data may be angular velocity data. Also, for example, the inertial sensor may be an IMU, and the inertial data may include acceleration data and angular velocity data. IMU stands for Inertial Measurement Unit.

[0095] Then, the control circuit 50 performs a timestamp process to write the capture data CPDT, which includes the target time data and sensor data, to the memory device 7, and then controls the power supply circuit 130 to stop supplying the power supply voltage MVDD to the memory device 7.

[0096] Figure 8 is a timing chart diagram showing an example of timestamp processing based on the timer trigger signal TMTRG by the control circuit 50. In the example in Figure 8, at time t11, the timer trigger signal TMTRG changes from a low level to a high level, and at time t12, the control circuit 50 starts supplying the power supply voltage MVDD from the power supply circuit 130 to the memory device 7. Next, during the period from time t12 to t13, the control circuit 50 continues to supply the power supply voltage MVDD from the power supply circuit 130 to the memory device 7 and writes the capture data CPDT, which includes the target time data and sensor data, to the memory device 7 via the first interface circuit 60. Then, at time t13, after the writing of the capture data CPDT to the memory device 7 is completed, the control circuit 50 stops supplying the power supply voltage MVDD from the power supply circuit 130 to the memory device 7.

[0097] Next, at time t14, after a time has elapsed from time t11 based on the control time data, the timer trigger signal TMTRG changes from a low level to a high level, and at time t15, the control circuit 50 starts supplying the power supply voltage MVDD from the power supply circuit 130 to the memory device 7. Next, during the period from time t15 to t16, the control circuit 50 continues to supply the power supply voltage MVDD from the power supply circuit 130 to the memory device 7 and writes the capture data CPDT, which includes the target time data and sensor data, to the memory device 7 via the first interface circuit 60. Then, at time t16, after the writing of the capture data CPDT to the memory device 7 is completed, the control circuit 50 stops supplying the power supply voltage MVDD from the power supply circuit 130 to the memory device 7.

[0098] Next, at time t17, after a time has elapsed from time t14 based on the control time data, the timer trigger signal TMTRG changes from a low level to a high level, and at time t18, the control circuit 50 starts supplying the power supply voltage MVDD from the power supply circuit 130 to the memory device 7. Next, during the period from time t18 to t19, the control circuit 50 continues to supply the power supply voltage MVDD from the power supply circuit 130 to the memory device 7 and writes the capture data CPDT, which includes the target time data and sensor data, to the memory device 7 via the first interface circuit 60. Then, at time t19, after the writing of the capture data CPDT to the memory device 7 is completed, the control circuit 50 stops supplying the power supply voltage MVDD from the power supply circuit 130 to the memory device 7.

[0099] Returning to the explanation of Figure 7, in the second embodiment, as in the first embodiment, the control circuit 50 starts supplying the power supply voltage MVDD to the memory device 7 in response to the occurrence of an event, selects at least one of several types of event data as the target event data, and selects the target time data corresponding to at least some of the time digits of the time data TM generated by the timing circuit 30, and stores the capture data CPDT, which includes the target time data and the target event data, in the memory device 7 via the first interface circuit 60. Then, after writing the capture data CPDT to the memory device 7, the control circuit 50 stops supplying the power supply voltage MVDD to the memory device 7.

[0100] A timing chart showing an example of timestamp processing based on the event trigger signal EVTRG by the control circuit 50 may be the same as that in Figure 3, so its illustration and explanation are omitted.

[0101] Similar to the first embodiment, the multiple types of event data may include a first power supply voltage drop signal VDDLOW, a second power supply voltage drop signal VBATLOW, a third power supply voltage drop signal VTMPLOW, an oscillation stop signal FST, a first event signal EVIN1, a second event signal EVIN2, a third event signal EVIN3, and an event command detection signal WRCom. Furthermore, in the second embodiment, the multiple types of event data may further include sensor data based on data detected by sensor devices 8-1 to 8-M.

[0102] Figure 9 shows an example of capture data CPDT stored in the memory device 7 in the second embodiment. In the example in Figure 9, the capture data CPDT is 64 bits of data and is stored, for example, at addresses 0x0 to 0x07 of the memory device 7.

[0103] Specifically, at address 0x0 of memory device 7, bit 7 is stored as 0, and bits 6 to 0 store the 7 bits of seconds data included in the time data TM.

[0104] Furthermore, at address 0x1 of memory device 7, bit 7 is stored as 0, and bits 6 to 0 store the 7 bits of minute data included in the time data TM.

[0105] Furthermore, at address 0x2 of memory device 7, bits 7 and 6 are stored as 0, and bits 5 to 0 store the 6 bits of time data included in the time data TM.

[0106] Furthermore, at address 0x3 of memory device 7, bits 7 and 6 are stored as 0, and bits 5 to 0 store the 6 bits of day data included in the time data TM.

[0107] Furthermore, at address 0x4 of memory device 7, bit 7 stores data corresponding to the logic level of the third event signal EVIN3, bit 6 stores data corresponding to the logic level of the second event signal EVIN2, bit 5 stores data corresponding to the logic level of the first event signal EVIN1, and bits 4 to 0 store 5 bits of month data included in the time data TM.

[0108] Furthermore, at address 0x5 of memory device 7, bits 7-3 store the 8-bit year data included in the time data TM.

[0109] Furthermore, at address 0x6 of memory device 7, bits 7 to 0 store the upper 8 bits of the sensor data.

[0110] Furthermore, at address 0x7 of memory device 7, bits 7 to 0 store the lower 8 bits of the sensor data.

[0111] In the example shown in Figure 9, the second data, minute data, hour data, day data, month data, and year data are the target time data, while all other data are the target event data.

[0112] Returning to the explanation in Figure 7, when the processor 51 has finished timestamp processing based on the timer trigger signal TMTRG or the event trigger signal EVTRG, it outputs a timestamp completion signal TSEND to the interrupt generation circuit 140.

[0113] The interrupt generation circuit 140 generates an interrupt signal INT based on the timestamp end signal TSEND and outputs the interrupt signal INT to the host device 6 via terminal P13 of the real-time clock circuit 3. Upon receiving the interrupt signal INT, the host device 6 performs predetermined interrupt processing. For example, the host device 6 sends a command to the real-time clock module 1 requesting the reading of timestamp data and receives the captured data CPDT stored in the memory device 7 from the real-time clock module 1.

[0114] Furthermore, in order to reduce the overall power consumption of the system, the host device 6 enters a sleep state when not performing any processing. When it receives an interrupt signal INT while in the sleep state, it wakes up from the sleep state, reads the timestamp data, and then returns to the sleep state once the necessary processing is complete.

[0115] The real-time clock module 1 of the second embodiment described above can achieve the same effects as the real-time clock module 1 of the first embodiment.

[0116] Furthermore, according to the real-time clock module 1 of the second embodiment, the control circuit 50 starts supplying the power supply voltage MVDD to the memory device 7 at a timing determined by the control time data, so the timing of writing the capture data CPDT to the memory device 7 can be controlled by the control time data. In addition, the host device 6 can set the control time data via the second interface circuit 80, so the timing of writing the capture data CPDT to the memory device 7 can be changed.

[0117] Furthermore, in the real-time clock module 1 of the second embodiment, the processor 51 of the control circuit 50 wakes up from sleep mode at a timing determined by the control time data and starts supplying the power supply voltage MVDD to the memory device 7. In other words, according to the real-time clock module 1 of the second embodiment, power consumption is reduced because the processor 51 is in sleep mode before the capture data CPDT is written to the memory device 7.

[0118] Furthermore, in the real-time clock module 1 of the second embodiment, the control circuit 50 can acquire data detected by sensor devices 8-1 to 8-M and store the capture data CPDT, which includes the target time data and sensor data based on the acquired data, in the memory device 7.

[0119] 1-3. Variations For example, in each of the above embodiments, the target time data and target event data selected by the control circuit 50 were the same regardless of the cause of the event trigger signal EVTRG, but they may be different for each cause of the event trigger signal EVTRG.

[0120] Furthermore, in each of the above embodiments, for example, the processor 51 could arbitrarily select target time data and target event data by performing software processing based on the instruction set 521 in the control circuit 50. However, the control circuit 50 may be configured as hardware that selects target time data and target event data based on selection data arbitrarily set in a predetermined register included in the non-volatile memory 52 or the register group 70.

[0121] Furthermore, in each of the embodiments described above, for example, the instruction set 521 specifies the target time data and the target event data, but the target event data may be specified without specifying the target time data. That is, the target time data selected by the control circuit 50 may be of a fixed type and cannot be selected by the instruction set 521, while the target event data may be arbitrarily selected by the instruction set 521.

[0122] Furthermore, for example, in the second embodiment described above, the control circuit 50 performs timestamp processing based on the timer trigger signal TMTRG and timestamp processing based on the event trigger signal EVTRG, but it is not necessary to perform either one of these processes. Also, in the second embodiment described above, the control circuit 50 is connected to the sensor devices 8-1 to 8-M, but it is not necessary to connect it to the sensor devices 8-1 to 8-M.

[0123] 2.Electronic equipment Figure 10 is a functional block diagram of an electronic device using a real-time clock module 1 and a memory device 7 according to one of the embodiments described above.

[0124] As shown in Figure 10, the electronic device 300 of this embodiment includes a real-time clock module 1, a main power supply 4, a backup power supply 5, a host device 6, a memory device 7, sensor devices 8-1 to 8-M, an operation unit 330, a storage unit 340, a communication unit 350, a display unit 360, and an audio output unit 370. Note that the electronic device 300 of this embodiment may have some of the components shown in Figure 10 omitted or modified, or other components added.

[0125] The real-time clock module 1, main power supply 4, backup power supply 5, host device 6, memory device 7, and sensor devices 8-1 to 8-M are each given the same reference numerals because they have the same configuration and function as those of the embodiments described above.

[0126] The real-time clock module 1 is supplied with power voltage VDD from the main power supply 4 and power voltage VBAT from the backup power supply 5. The real-time clock module 1 operates with power voltage VDD when power voltage VDD is supplied from the main power supply 4, and operates with power voltage VBAT when the supply of power voltage VDD from the main power supply 4 is cut off. Therefore, the real-time clock module 1 can continue its timing operation even when the supply of power voltage VDD from the main power supply 4 is cut off.

[0127] The host device 6 operates using the power supply voltage VDD supplied from the main power supply 4, and the host device 6 and the real-time clock module 1 communicate with each other, with the host device 6 acting as the master and the real-time clock module 1 as the slave. The host device 6 can be implemented, for example, by an MCU or MPU.

[0128] Memory device 7 is a non-volatile memory such as an EEPROM, and operates on power supply voltage MVDD supplied from the real-time clock module 1. Sensor devices 8-1 to 8-M are, for example, temperature sensors, position sensors, inertial sensors, etc. The real-time clock module 1 and memory devices 7 and sensor devices 8-1 to 8-M communicate with each other, with the real-time clock module 1 acting as the master and memory devices 7 and sensor devices 8-1 to 8-M acting as slaves.

[0129] As mentioned above, the real-time clock module 1 performs processes such as generating time data TM, acquiring data detected by sensor devices 8-1 to 8-M, and timestamp processing to store captured data CPDT in the memory device 7.

[0130] The host device 6 performs various calculation and control processes according to the program stored in the memory unit 340, etc. Specifically, the host device 6 performs various processes in response to operation signals from the operation unit 330, processes to control the communication unit 350 for data communication with other devices, processes to send display signals to display various information on the display unit 360, and processes to send sound signals to output various sounds from the sound output unit 370.

[0131] Furthermore, the host device 6 communicates with the real-time clock module 1, reads time data TM from the real-time clock module 1, and performs various calculation and control processing. The host device 6 also rewrites the time data TM on the real-time clock module 1. In addition, the host device 6 reads the capture data CPDT stored in the memory device 7 via the real-time clock module 1 and performs various calculation and control processing.

[0132] The operation unit 330 is an input device consisting of operation keys, button switches, etc., and outputs operation signals to the host device 6 in response to user operations. The host device 6 can, for example, set time information in the real-time clock module 1 in response to signals input from the operation unit 330.

[0133] The memory unit 340 stores programs and data for the host device 6 to perform various calculation and control processes. The memory unit 340 is also used as a workspace for the host device 6, temporarily storing programs and data read from the memory unit 340, data input from the operation unit 330, and calculation results performed by the host device 6 according to various programs. The memory unit 340 is comprised of ROM and RAM, and can be implemented using, for example, a hard disk, flexible disk, MO, MT, various types of memory, CD-ROM, or DVD-ROM. ROM stands for Read Only Memory, and RAM stands for Random Access Memory.

[0134] The communication unit 350 performs various controls to establish data communication between the host device 6 and the external device. The data communication may be wireless or wired.

[0135] The display unit 360 is a display device composed of an LCD or the like, and displays various information based on display signals input from the host device 6. The display unit 360 may also be provided with a touch panel that functions as an operation unit 330. LCD stands for Liquid Crystal Display.

[0136] The sound output unit 370 is composed of a speaker or the like, and outputs various information as sound or voice based on the sound signal input from the host device 6.

[0137] The electronic device 300 of this embodiment can achieve low power consumption by including the real-time clock module 1 of any of the embodiments described above.

[0138] Such electronic devices 300 can include a variety of electronic devices, such as data loggers, wireless devices for IoT applications, electronic clocks, personal computers such as mobile, laptop, and tablet types, mobile terminals such as smartphones and mobile phones, digital cameras, inkjet printers and other inkjet ejection devices, storage area network equipment such as routers and switches, local area network equipment, equipment for mobile terminal base stations, televisions, video cameras, video recorders, car navigation systems, real-time clock devices, pagers, electronic organizers, electronic dictionaries, calculators, electronic game devices, game controllers, word processors, workstations, video phones, security television monitors, electronic binoculars, POS terminals, electronic thermometers, blood pressure monitors, blood glucose meters, electrocardiogram measuring devices, ultrasound diagnostic equipment, medical devices such as electronic endoscopes, fish finders, various measuring instruments, instruments for vehicles, aircraft, ships, etc., flight simulators, head-mounted displays, motion trace, motion tracking, motion controllers, pedestrian autonomous navigation systems, etc.

[0139] The present invention is not limited to this embodiment, and various modifications can be implemented within the scope of the gist of the present invention.

[0140] The embodiments and variations described above are examples only and are not limited thereto. For example, each embodiment and each variation can be combined as appropriate.

[0141] The present invention includes configurations that are substantially identical to those described in the embodiments (for example, configurations with the same function, method, and result, or configurations with the same purpose and effect). Furthermore, the present invention includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. Furthermore, the present invention includes configurations that produce the same effects or achieve the same purpose as those described in the embodiments. Furthermore, the present invention includes configurations that add known technology to the configurations described in the embodiments.

[0142] The following can be derived from the embodiments and modifications described above.

[0143] One embodiment of a real-time clock module is: A real-time clock module connected to a memory device, A timing circuit that performs timing and generates time data, A first interface circuit that functions as a master interface to the memory device, A power supply circuit that supplies power supply voltage to the memory device, A control circuit that, after starting to supply the power supply voltage to the memory device, writes target time data corresponding to at least some of the time digits of the time data to the memory device via the first interface circuit, and stops supplying the power supply voltage to the memory device after writing the target time data to the memory device, It is equipped with.

[0144] This real-time clock module starts supplying power voltage to the memory device before writing the target time data to the memory device, and stops supplying power voltage to the memory device after writing the target time data to the memory device, thereby reducing the power consumption of the memory device.

[0145] One embodiment of the real-time clock module is: It is equipped with a register for storing control time data, The control circuit may start supplying the power supply voltage to the memory device at a timing determined by the control time data.

[0146] This real-time clock module allows the timing of writing target time data to the memory device to be controlled by control time data.

[0147] In one embodiment of the real-time clock module, The control circuit includes a processor, The processor may wake from sleep mode at the aforementioned timing and begin supplying the power supply voltage to the memory device.

[0148] This real-time clock module reduces power consumption because the processor is in a sleep state before writing the target time data to the memory device.

[0149] One embodiment of the real-time clock module is: A second interface circuit for receiving the control time data may be provided as a slave interface.

[0150] This real-time clock module allows the timing of writing target time data to the memory device to be changed externally.

[0151] In one embodiment of the real-time clock module, The control circuit may, in response to the occurrence of an event, select at least one of several types of event data as the target event data to be stored, and write the target event data to the memory device.

[0152] This real-time clock module stores the target event data selected from multiple types of event data in the memory device along with the target time data in response to an event, thus preventing the storage of unnecessary event data for each application in the timestamp.

[0153] One embodiment of the real-time clock module is: Connected to a sensor device, The control circuit may write sensor data based on the data detected by the sensor device to the memory device.

[0154] This real-time clock module allows sensor data to be stored in a memory device along with the target time data.

[0155] One embodiment of the real-time clock module is: The oscillator and, The system comprises an oscillator circuit that generates a clock signal by causing the oscillator to oscillate, The timing circuit may perform the timing based on the clock signal.

[0156] This real-time clock module allows for timekeeping based on a highly accurate clock signal obtained by oscillating an oscillator.

[0157] One aspect of electronic equipment is, One embodiment of the real-time clock module, The memory device and the above-mentioned memory device are included.

[0158] This electronic device can reduce overall power consumption by incorporating a real-time clock module that can reduce the power consumption of the memory device that writes time data. [Explanation of Symbols]

[0159] 1…Real-time clock module, 2…Oscillator, 3…Real-time clock circuit, 4…Main power supply, 5…Backup power supply, 6…Host device, 7…Memory device, 8-1~8-M…Sensor device, 10…Oscillator circuit, 20…Frequency divider circuit, 30…Timer circuit, 40…Event trigger circuit, 50…Control circuit, 51…Processor, 52…Non-volatile memory, 60…First interface circuit, 70…Register group, 80…Second interface Circuit, 90...Temperature sensor, 100...Oscillation monitoring circuit, 110...Power supply voltage monitoring circuit, 120...Power supply voltage selection circuit, 130...Power supply circuit, 140...Interrupt generation circuit, 150...Timer trigger circuit, 300...Electronic equipment, 330...Operation unit, 340...Memory unit, 350...Communication unit, 360...Display unit, 370...Sound output unit, 511...Fetch circuit, 512...Decode circuit, 513...Logic operation circuit, 514...Data buffer, 515...Capture circuit, 521...Instruction set

Claims

1. A real-time clock module that operates on a first power supply voltage and is connected to a memory device, A timing circuit that performs timing and generates time data, A first interface circuit that functions as a master interface to the memory device, A power supply circuit that generates a second power supply voltage based on the first power supply voltage and supplies the second power supply voltage to the memory device, In the state in which the real-time clock module is operating due to the first power supply voltage, After starting to supply the second power supply voltage to the memory device, the first interface circuit is used to write target time data corresponding to at least some of the time digits of the time data to the memory device, A control circuit that writes the target time data to the memory device and then stops supplying the second power supply voltage to the memory device, A real-time clock module equipped with the following features.

2. Equipped with an external terminal, The real-time clock module according to claim 1, which is connected to the memory device via the external terminal.

3. Includes an event trigger circuit that outputs an event trigger signal to the control circuit, The real-time clock module according to claim 1, wherein the control circuit starts supplying the second power supply voltage to the memory device in response to the event trigger signal.

4. The real-time clock module according to claim 3, wherein the event trigger circuit outputs the event trigger signal in response to at least one of the signals: an external input event signal, a power supply voltage drop signal, and an oscillation stop signal.

5. A real-time clock module connected to a memory device, A timing circuit that performs timing and generates time data, A first interface circuit that functions as a master interface to the memory device, A power supply circuit that supplies power supply voltage to the memory device, A control circuit that, after starting to supply the power supply voltage to the memory device, writes target time data corresponding to at least some of the time digits of the time data to the memory device via the first interface circuit, and stops supplying the power supply voltage to the memory device after writing the target time data to the memory device, A register for storing control time data, Equipped with, The control circuit is a real-time clock module that starts supplying the power supply voltage to the memory device at a timing determined by the control time data.

6. The control circuit includes a processor, The real-time clock module according to claim 5, wherein the processor wakes up from sleep state at the timing and starts supplying the power supply voltage to the memory device.

7. The real-time clock module according to claim 5, further comprising a second interface circuit that receives the control time data as a slave interface.

8. The real-time clock module according to claim 1 or 5, wherein the control circuit, in response to the occurrence of an event, selects at least one of a plurality of event data as the target event data to be stored, and writes the target event data to the memory device.

9. Connected to a sensor device, The real-time clock module according to claim 1 or 5, wherein the control circuit writes sensor data based on data detected by the sensor device to the memory device.

10. The oscillator and, The system comprises an oscillator circuit that generates a clock signal by causing the oscillator to oscillate, The real-time clock module according to claim 1 or 5, wherein the timing circuit performs timing based on the clock signal.

11. A real-time clock module according to any one of claims 1 to 7, An electronic device comprising the aforementioned memory device.

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