Method for manufacturing a semiconductor device, semiconductor device, integrated circuit element, and method for manufacturing an integrated circuit element.

Abstract

Provided is a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device comprises: a step for providing a first integrated circuit element comprising a first semiconductor substrate and a first wiring layer; a step for providing a second integrated circuit element comprising a second semiconductor substrate and a second wiring layer; a step for bonding a first insulating layer of the first integrated circuit element and a second insulating layer of the second integrated circuit element to each other; and a step for bonding a first electrode of the first integrated circuit element and a second electrode of the second integrated circuit element to each other. The first insulating layer includes an inorganic insulating material. At positions of the first insulating layer of the first wiring layer different from the location where the first electrode is disposed, a plurality of first openings are provided that are recessed from a bonding surface bonded with the second insulating layer toward the first semiconductor substrate, the plurality of first openings surrounding the first electrode discontinuously.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor device, a semiconductor device, an integrated circuit element, and a method for manufacturing an integrated circuit element.

Background Art

[0002] Patent Document 1 discloses a hybrid bonding method, which is a three-dimensional integration technology for semiconductors. In this bonding method, an insulating film is formed around an electrode on each bonding surface of a pair of integrated circuit elements (for example, a pair of semiconductor wafers), and the electrodes are bonded together, and the insulating films are bonded together. Also, Patent Document 2 discloses a similar technology.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the bonding method described in Patent Document 1, copper (Cu) is used as an electrode of an integrated circuit element, and an inorganic insulating film such as silicon dioxide (SiO2) is used as an insulating film. When performing such bonding between electrodes and between insulating films, each integrated circuit element is heated to, for example, 400°C for bonding, and then the bonded integrated circuit elements are cooled to 100°C to fabricate a semiconductor device. Due to this cooling process after heating, internal stress is accumulated in the integrated circuit element. If this accumulated internal stress is large, cracks may occur in the integrated circuit element (such as a semiconductor wafer) during cooling. In particular, as the integrated circuit element becomes larger or thinner, the occurrence of cracks during cooling becomes more likely.

[0005] The present disclosure aims to provide a method for manufacturing a semiconductor device, a semiconductor device, an integrated circuit element, and a method for manufacturing an integrated circuit element, which can suppress the occurrence of cracks when joining integrated circuit elements together. [Means for solving the problem]

[0006] This disclosure relates, in one aspect, to a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device comprises the steps of: providing a first integrated circuit element comprising a first semiconductor substrate having a semiconductor element and a first wiring layer having a first insulating layer and a first electrode and provided on one surface of the first semiconductor substrate; providing a second integrated circuit element comprising a second semiconductor substrate having a semiconductor element and a second wiring layer having a second insulating layer and a second electrode and provided on one surface of the second semiconductor substrate; joining the first insulating layer of the first integrated circuit element and the second insulating layer of the second integrated circuit element to each other; and joining the first electrode of the first integrated circuit element and the second electrode of the second integrated circuit element to each other. The first insulating layer includes an inorganic insulating material. At positions different from the arrangement of the first electrode of the first insulating layer, a plurality of first openings are provided that are recessed toward the first semiconductor substrate from the first bonding surface that bonds with the second insulating layer, and the plurality of first openings discontinuously surround the first electrode.

[0007] In this semiconductor device manufacturing method, a plurality of first openings are provided in the first integrated circuit element at positions different from the placement of the first electrode in the first insulating layer, and the plurality of first openings discontinuously surround the first electrode. In this case, even if internal stress accumulates in the first integrated circuit element or the second integrated circuit element due to heating when the first integrated circuit element is joined to the second integrated circuit element, such internal stress is released by the plurality of first openings during cooling. Such accumulation of internal stress is particularly likely to occur between the first insulating layer and the first electrode, which have different coefficients of thermal expansion, but the plurality of first openings discontinuously surrounding the first electrode can efficiently release the internal stress. In other words, this manufacturing method makes it possible to create stress-free areas within the manufactured semiconductor device and reduce internal stress. As a result, this semiconductor device manufacturing method can suppress the occurrence of cracks associated with cooling.

[0008] In the above-described method for manufacturing a semiconductor device, the plurality of first openings may be arranged so that the first electrode is not exposed on each side of the plurality of first openings. In this case, the first electrode is covered by the first insulating layer without any part other than the connection end on the surface side being exposed to the outside. This reduces the influence of the external environment on the first electrode and improves the reliability of the first electrode.

[0009] In the semiconductor device manufacturing method described above, the plurality of first openings may be provided so that the first semiconductor substrate is not exposed to the bottom surface of each of the plurality of first openings. In this case, the connection surface of the first semiconductor substrate with the first electrode is covered by the first insulating layer without being exposed to the outside. This reduces the influence of the external environment on the connection area between the first semiconductor substrate and the first electrode, and improves the reliability of the connection between the first semiconductor substrate and the first electrode.

[0010] In the above-described method for manufacturing a semiconductor device, each of the multiple first openings may have a closed opening shape in the planar direction of the first insulating layer. In this case, factors that affect the semiconductor device are less likely to penetrate the multiple first openings in the semiconductor device after manufacturing, i.e., into the interior of the semiconductor device. This reduces the influence of the external environment on the semiconductor device, making it possible to manufacture a highly reliable semiconductor device.

[0011] In the above-described method for manufacturing a semiconductor device, the width or diameter in the short-side direction of each of the multiple first openings may be narrower than the width or diameter in the short-side direction of the first electrode. In this case, the area of ​​the multiple first openings formed in the first insulating layer can be reduced, and the area used for bonding with the second insulating layer in the first insulating layer can be increased. This makes the bonding between the first integrated circuit element and the second integrated circuit element more reliable. Furthermore, in the above-described method for manufacturing a semiconductor device, the ratio of the total area of ​​the multiple first openings to the total area of ​​the first insulating layer in the planar direction may be 65% or less. In this case, the bonding between the first integrated circuit element and the second integrated circuit element can be made more reliable.

[0012] In the above-described method for manufacturing a semiconductor device, the multiple first openings may be formed by dry etching the first insulating layer of the first integrated circuit element. In this case, fine first openings can be formed quickly.

[0013] In the above-described method for manufacturing a semiconductor device, the second insulating layer may include an inorganic insulating material, and a plurality of second openings may be provided at positions different from the placement of the second electrode of the second insulating layer, recessed toward the second semiconductor substrate from the second bonding surface that bonds with the first insulating layer, and the plurality of second openings may discontinuously surround the second electrode. In this case, when bonding the first integrated circuit element to the second integrated circuit element, even if internal stress accumulates in the first integrated circuit element or the second integrated circuit element due to heating, such internal stress is released not only by the first opening but also by the second opening. As a result, this method for manufacturing a semiconductor device can further suppress the occurrence of cracks associated with cooling.

[0014] In the above-described method for manufacturing a semiconductor device, the inorganic insulating material included in at least one of the first insulating layer and the second insulating layer may be silicon dioxide, silicon nitride, or silicon oxynitride. In this case, a wiring layer having a finer first electrode can be formed. Furthermore, a finer opening can also be formed.

[0015] This disclosure relates, in another aspect, to a semiconductor device. This semiconductor device comprises a first integrated circuit element comprising a first semiconductor substrate having semiconductor elements, a first wiring layer having a first insulating layer and a first electrode and provided on one surface of the first semiconductor substrate, and a second integrated circuit element comprising a second semiconductor substrate having semiconductor elements, and a second wiring layer having a second insulating layer and a second electrode and provided on one surface of the second semiconductor substrate. The first insulating layer of the first integrated circuit element and the second insulating layer of the second integrated circuit element are joined to each other. The first electrode of the first integrated circuit element and the second electrode of the second integrated circuit element are joined to each other. The first insulating layer includes an inorganic insulating material. At positions different from the placement of the first electrode of the first insulating layer, a plurality of first openings are provided that are recessed toward the first semiconductor substrate from the first bonding surface that bonds with the second insulating layer, and the plurality of first openings discontinuously surround the first electrode.

[0016] In the semiconductor device described above, multiple first openings are provided in the first integrated circuit element at positions different from those of the first electrode in the first insulating layer. In this case, as described above, internal stress is released by the first openings. This suppresses the occurrence of cracks in the semiconductor device.

[0017] This disclosure, in yet another aspect, relates to an integrated circuit element for manufacturing a semiconductor device by joining it with other integrated circuit elements. This integrated circuit element comprises a semiconductor substrate having a first surface and a second surface, with semiconductor elements formed on at least one of the first surface and its interior, and a wiring layer provided on the second surface of the semiconductor substrate. The wiring layer has an inorganic insulating layer provided on the second surface of the semiconductor substrate and electrodes that are electrically connected to the semiconductor elements of the semiconductor substrate and penetrate the inorganic insulating layer to be exposed to the outside. Multiple openings are provided in the inorganic insulating layer at positions different from the location of the electrodes, recessed toward the semiconductor substrate, and the multiple openings discontinuously surround the electrodes.

[0018] In the above-described integrated circuit element, multiple openings are provided at locations different from those where the electrodes of the inorganic insulating layer are positioned. In this case, by manufacturing a semiconductor device using this integrated circuit element, the internal stress of the semiconductor device is released by the openings, as described above. This suppresses the occurrence of cracks in the semiconductor device.

[0019] This disclosure, in yet another aspect, relates to a method for manufacturing an integrated circuit element for joining with other integrated circuit elements to manufacture a semiconductor device. This method for manufacturing an integrated circuit element comprises the steps of: providing a semiconductor substrate having a first surface and a second surface, with a semiconductor element formed on at least one of the first surface and / or inside the first surface; and forming a wiring layer on the second surface of the semiconductor substrate. The step of forming the wiring layer comprises the steps of: forming an inorganic insulating layer on the second surface of the semiconductor substrate; forming electrodes that penetrate the inorganic insulating layer so as to be electrically connected to the semiconductor element; and forming a plurality of openings in the inorganic insulating layer at positions different from the locations where the electrodes are placed, recessed toward the semiconductor substrate, wherein the plurality of openings discontinuously surround the electrodes.

[0020] According to the above-described method for manufacturing integrated circuit elements, multiple openings are formed at locations different from the placement locations of the electrodes in the inorganic insulating layer. In this case, by using integrated circuit elements manufactured by this method, the internal stress of the semiconductor device is released by the multiple openings, as described above. This suppresses the occurrence of cracks in the semiconductor device.

[0021] In the above-described method for manufacturing integrated circuit elements, in the step of forming openings, multiple openings may be formed by dry etching the inorganic insulating layer. In this case, fine openings can be formed quickly.

[0022] In the above-described method for manufacturing integrated circuit elements, a step of forming openings may be performed after the step of forming electrodes. In this case, it becomes possible to form multiple openings at different heights from the electrodes.

[0023] In the method for manufacturing the above integrated circuit element, a step of forming an electrode may be performed after the step of forming an opening.

Advantages of the Invention

[0024] According to one aspect of the present disclosure, it is possible to suppress the occurrence of cracks when bonding integrated circuit elements to each other.

Brief Description of the Drawings

[0025] [Figure 1] FIG. 1 is a cross-sectional view showing an example of a semiconductor device manufactured by a method according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a cross-sectional view showing a part (upper part) of the semiconductor device shown in FIG. 1. [Figure 3] FIGS. 3(a) to (c) are plan views showing modified examples of the shape of the opening. [Figure 4] FIGS. 4(a) to (d) are cross-sectional views sequentially showing the steps of a method for manufacturing an integrated circuit element according to an embodiment. [Figure 5] FIGS. 5(a) to (d) are cross-sectional views sequentially showing the steps of a method for manufacturing an integrated circuit element according to another embodiment. [Figure 6] FIG. 6 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1.

Modes for Carrying Out the Invention

[0026] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the drawings as necessary. In the following description, the same or corresponding parts are denoted by the same reference numerals, and redundant descriptions are omitted. Also, the positional relationships such as up, down, left, and right are based on the positional relationships shown in the drawings unless otherwise specified. In the description and claims of this specification, when terms such as "left", "right", "front", "back", "up", "down", "above", "below", etc. are used, these are for the purpose of explanation and do not necessarily mean that this relative position is permanent. Furthermore, the dimensional ratios in the drawings are not limited to the ratios shown.

[0027] In this specification, the term "layer" includes not only structures formed on the entire surface when observed in a plan view, but also structures formed on only a part of the surface. Furthermore, in this specification, the term "process" includes not only independent processes, but also processes that are not clearly distinguishable from other processes, as long as their intended function is achieved. Also, numerical ranges indicated using "~" represent a range that includes the numbers before and after "~" as the minimum and maximum values, respectively. In numerical ranges described stepwise in this specification, the upper or lower limit of one numerical range may be replaced with the upper or lower limit of another stepwise numerical range. Furthermore, in numerical ranges described in this specification, the upper or lower limit of that range may be replaced with the values ​​shown in the examples.

[0028] (Configuration of a semiconductor device) Figure 1 is a schematic cross-sectional view showing an example of a semiconductor device manufactured by the manufacturing method according to this embodiment. As shown in Figure 1, the semiconductor device 1 comprises a first integrated circuit element 10 and a second integrated circuit element 20. The first integrated circuit element 10 comprises a first semiconductor substrate 11 and a first wiring layer 12 provided on the first semiconductor substrate 11. The second integrated circuit element 20 comprises a second semiconductor substrate 21 and a second wiring layer 22 provided on the second semiconductor substrate 21. In the semiconductor device 1, the first wiring layer 12 of the first integrated circuit element 10 and the second wiring layer 22 of the second integrated circuit element 20 are joined via a bonding surface 10a (first bonding surface) and a bonding surface 20a (second bonding surface), thereby forming the semiconductor device 1.

[0029] The first semiconductor substrate 11 and the second semiconductor substrate 21 are semiconductor wafers on which a plurality of semiconductor elements S1 and S2 constituting a functional circuit corresponding to a semiconductor chip such as an LSI (Large scale Integrated Circuit) chip or a CMOS (Complementary Metal Oxide Semiconductor) sensor are provided. The first semiconductor substrate 11 has a first surface 11a and a second surface 11b (one surface) on the opposite side, and is configured to provide the plurality of semiconductor elements S1 on the first surface 11a or inside the substrate. The second semiconductor substrate 21 has a first surface 21a and a second surface 21b on the opposite side, and is configured to provide the plurality of semiconductor elements S2 on the first surface 21a or inside the substrate.

[0030] The first wiring layer 12 and the second wiring layer 22 are layers that provide multiple electrodes within an insulating film that are electrically connected to multiple semiconductor elements S1 and S2 contained in adjacent first semiconductor substrates 11 and second semiconductor substrates 21, with one end of each electrode exposed to the outside. The first wiring layer 12 comprises an inorganic insulating layer 13 (first insulating layer), multiple electrodes 14 (first electrodes), and multiple openings 15 (multiple first openings). The second wiring layer 22 comprises an inorganic insulating layer 23 (second insulating layer) and multiple electrodes 24 (second electrodes). In the example shown in Figure 1, the second wiring layer 22 does not have the openings 15 provided in the first wiring layer 12, but the second wiring layer 22 may also have a similar number of openings. In the semiconductor device 1, the inorganic insulating layer 13 of the first wiring layer 12 and the inorganic insulating layer 23 of the second wiring layer 22 are joined, and each electrode 14 of the first wiring layer 12 and each electrode 24 of the second wiring layer 22 are joined.

[0031] The inorganic insulating layer 13 is an insulating layer provided on the second surface 11b of the first semiconductor substrate 11. The inorganic insulating layer 13 is composed of an inorganic material such as silicon dioxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON). The inorganic insulating layer 13 may be composed of multiple insulating layers (for example, three or more inorganic insulating layers).

[0032] Each of the electrodes 14 is electrically connected to the semiconductor element S1 of the first semiconductor substrate 11 and is an electrode that penetrates the inorganic insulating layer 13. The electrodes 14 are formed from a conductive metal such as copper (Cu) and penetrate the inorganic insulating layer 13. The electrodes 14 may be configured such that their diameter increases in steps from the first semiconductor substrate 11 toward the junction surface 10a. The diameter of the electrodes 14 may be, for example, 0.005 μm or more and 20 μm or less.

[0033] Each of the multiple openings 15 is a recess in the inorganic insulating layer 13 that extends from the bonding surface 10a toward the first semiconductor substrate 11, forming a void within the semiconductor device 1. The presence of this void within the semiconductor device 1 releases internal stress accumulated in the semiconductor device 1 during the bonding of the first integrated circuit element 10 and the second integrated circuit element 20, as described later. The openings 15 may also have the function of releasing external forces applied from the outside after the semiconductor device 1 has been manufactured. Each of the openings 15 is provided between or outside the electrodes 14, and is formed along the arrangement of the electrodes 14, for example, as shown in Figure 2, and is provided to discontinuously surround the electrodes 14. Furthermore, the openings 15 are provided at positions different from the placement of each electrode 14 in the inorganic insulating layer 13 and are spaced apart from the electrodes 14. As a result, the electrodes 14 are not exposed on the side surface 15a of the opening 15. In addition, the bottom surface 15b of the opening 15 is formed to be spaced apart from the first semiconductor substrate 11. As a result, the second surface 11b of the first semiconductor substrate 11 is not exposed on the bottom surface 15b of the opening 15.

[0034] As shown in Figure 2, the opening 15 has a closed opening shape in the planar direction of the inorganic insulating layer 13, for example, a rectangular shape. The shape of the opening 15 in the planar direction is not limited to the rectangular shape shown in Figure 2, and may be, for example, a star-shaped (e.g., quadragram) opening 15A as shown in Figure 3(a), a cross-shaped opening 15B as shown in Figure 3(b), or a circular or elliptical opening 15C as shown in Figure 3(c). The width or diameter in the short-side direction of the openings 15, 15A to 15C may be smaller than the width or diameter in the short-side direction of each electrode 14. Furthermore, it is preferable that the ratio of the total area of ​​the openings 15 to the total area of ​​the inorganic insulating layer 13 in the planar direction is 65% or less. In this case, the joining of the first integrated circuit element 10 and the second integrated circuit element 20 is not hindered by the provision of the opening 15, and a reliable joining can be achieved.

[0035] As shown in Figure 1, the inorganic insulating layer 23 is an insulating layer provided on the second surface 21b of the second semiconductor substrate 21. Similar to the inorganic insulating layer 13, the inorganic insulating layer 23 is composed of an inorganic material such as silicon dioxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON). It is preferable that the inorganic insulating layer 23 is formed from the same inorganic insulating material as the inorganic insulating layer 13. The inorganic insulating layer 23 may be composed of multiple insulating layers (for example, three or more inorganic insulating layers).

[0036] Electrode 24 is electrically connected to the semiconductor element S2 of the second semiconductor substrate 21 and penetrates the inorganic insulating layer 23. Electrode 24 is formed from a conductive metal such as copper (Cu) and penetrates the inorganic insulating layer 23. Electrode 24 may be configured such that its diameter gradually increases from the second semiconductor substrate 21 toward the bonding surface 20a. The diameter of electrode 24 may be, for example, 0.005 μm or more and 20 μm or less. Electrode 24 is bonded to electrode 14 and is electrically and mechanically connected to it.

[0037] (Method of manufacturing semiconductor devices) Next, the method for manufacturing the semiconductor device 1 will be described with reference to Figures 4 to 6. Figures 4(a) to 4(d) are cross-sectional views showing a method for manufacturing the first integrated circuit element 10 used in manufacturing the semiconductor device 1. Figures 5(a) to 5(c) are cross-sectional views showing another method for manufacturing the first integrated circuit element 10. Figure 6 is a cross-sectional view showing a method for manufacturing the semiconductor device 1 from the first integrated circuit element 10 and the second integrated circuit element 20.

[0038] The semiconductor device 1 can be manufactured, for example, through the following steps (a) to (d). (a) A step of preparing (providing) the first integrated circuit element 10 (see Figures 4 and 5). (b) A step of preparing (providing) the second integrated circuit element 20 (see Figure 6). (c) A step of joining the inorganic insulating layer 13 of the first integrated circuit element 10 and the inorganic insulating layer 23 of the second integrated circuit element 20 (see Figure 6). (d) A step of joining the electrode 14 of the first integrated circuit element 10 and the electrode 24 of the second integrated circuit element 20 (see Figure 6).

[0039] [Process (a)] Step (a) is a step of preparing a first integrated circuit element 10 comprising a first semiconductor substrate 11 having a plurality of semiconductor elements and a first wiring layer 12 provided on the second surface 11b of the first semiconductor substrate 11. In step (a), as shown in Figure 4(a), first an inorganic insulating layer 113 is formed on the second surface 11b of the first semiconductor substrate 11, which is made of silicon or the like and has a functional circuit formed inside. A plurality of semiconductor elements S1 (not shown in Figure 4) have already been formed on the first surface 11a and inside the first semiconductor substrate 11. The inorganic insulating layer 113 is made of an inorganic material such as silicon dioxide (SiO2), and has a thickness of 0.01 μm or more and 10 μm or less. Then, as shown in Figure 4(b), a plurality of grooves or holes 113a are made in the inorganic insulating layer 113 by, for example, the damascene method, and a metal 114 such as copper is filled into each groove or hole 113a by electroplating, sputtering, or chemical vapor deposition (CVD). When forming multiple grooves or holes 113a, predetermined locations on the inorganic insulating layer 113 are processed by dry etching. Then, as shown in Figure 4(c), the metal 114 is polished by chemical mechanical polishing (CMP) to form multiple electrodes 14. The width or diameter of the electrodes 14 is, for example, 0.01 μm or more and 10 μm or less. Subsequently, a resist (not shown) is formed on the wiring layer consisting of the inorganic insulating layer 113 and the electrodes 14, except for the locations where the openings 15 are formed, and as shown in Figure 4(d), multiple openings 15 are formed by dry etching. Then, the resist is peeled off to obtain the first integrated circuit element 10.

[0040] The first integrated circuit element 10 may be formed by another method as shown in Figure 5. As shown in Figure 5(a), first an inorganic insulating layer 113 is formed on the second surface 11b of a first semiconductor substrate 11 made of silicon or the like, on which a functional circuit is formed internally. Multiple semiconductor elements S1 (not shown in Figure 5) are already formed on the first surface 11a and internally of the first semiconductor substrate 11. The inorganic insulating layer 113 is made of an inorganic material such as silicon dioxide (SiO2), and has a thickness of 0.01 μm to 10 μm. Then, as shown in Figure 5(b), an opening 15 is formed in the inorganic insulating layer 113 by dry etching, and a resist 115 is provided on the opening 15. A groove or hole 113a for forming an electrode 14 is formed by sputtering, and the resist 115 is removed. After that, as shown in Figure 5(c), an electrode 114 is formed in the groove or hole 113a by electrolytic copper plating. Then, as shown in Figure 5(d), the electrodes 114 and the like are polished using a chemical mechanical polishing (CMP) method to form multiple electrodes 14 and obtain the first integrated circuit element 10.

[0041] [Step (b)] Step (b) is a step of preparing (providing) a second integrated circuit element 20 comprising a second semiconductor substrate 21 having a plurality of semiconductor elements and a second wiring layer 22 provided on the second surface of the second semiconductor substrate 21. In step (b), similar to step (a), an inorganic insulating layer 23 is formed on the second surface 21b of the second semiconductor substrate 21 made of silicon or the like, a plurality of grooves or holes are made in the inorganic insulating layer 23 by, for example, the damascene method, and electrodes 24 are formed by filling each groove or hole with a metal such as copper by electroplating, sputtering, or chemical vapor deposition (CVD) (see, for example, Figures 4(a) to (c)). The inorganic insulating layer 23 may be provided after the electrodes 24 are provided. In the manufacturing of the semiconductor device 1 shown in Figure 1, no openings are provided in the second integrated circuit element 20, but if an opening corresponding to the opening 15 is to be provided, the method shown in Figures 4 or 5 described above can be used.

[0042] [Process (c)] Step (c) is a step of joining the inorganic insulating layer 13 of the first integrated circuit element 10 to the inorganic insulating layer 23 of the second integrated circuit element 20. In step (c), after removing organic matter or metal oxides adhering to the surfaces of the bonding surface 10a of the first integrated circuit element 10 and the bonding surface 20a of the second integrated circuit element 20, as shown in Figure 6, the bonding surface 10a of the first integrated circuit element 10 and the bonding surface 20a of the second integrated circuit element 20 are brought into contact, and the electrodes 14 of the first integrated circuit element 10 and the electrodes 24 of the second integrated circuit element 20 are aligned. At this alignment stage, the inorganic insulating layer 13 of the first integrated circuit element 10 and the inorganic insulating layer 23 of the second integrated circuit element 20 are separated from each other and not joined (however, the electrodes 14 and 24 are aligned). Once the alignment is complete, the inorganic insulating layer 13 of the first integrated circuit element 10 and the inorganic insulating layer 23 of the second integrated circuit element 20 are joined. In this case, the inorganic insulating layer 13 of the first integrated circuit element 10 and the inorganic insulating layer 23 of the second integrated circuit element 20 may be uniformly heated before joining. The heating temperature when joining the inorganic insulating layer 13 and the inorganic insulating layer 23 may be, for example, 25°C to 800°C, and the pressure may be 0.1 MPa to 10 MPa. Furthermore, the temperature difference between the inorganic insulating layer 13 and the inorganic insulating layer 23 during joining is preferably, for example, 10°C or less. By heating and joining at such a uniform temperature, the inorganic insulating layer 13 and the inorganic insulating layer 23 are joined to form an insulating joint, and the first integrated circuit element 10 and the second integrated circuit element 20 are mechanically firmly attached to each other. In addition, because the heating and joining is performed at a uniform temperature, misalignment at the joint is less likely to occur, and high-precision joining can be achieved.

[0043] [Step (d)] Step (d) is a step of joining the electrode 14 of the first integrated circuit element 10 to the electrode 24 of the second integrated circuit element 20. In step (d), once the joining of the inorganic insulating layer 13 and the inorganic insulating layer 23 in step (c) is completed, a predetermined heat and / or pressure is applied to join the electrode 14 of the first integrated circuit element 10 to the electrode 24 of the second integrated circuit element 20. If electrodes 14 and 24 are made of copper, the heating temperature in step (d) is 150°C to 400°C, and may be 200°C to 300°C, and the pressure may be 0.1 MPa to 10 MPa. Through this joining process, electrode 14 and its corresponding electrode 24 are joined to form an electrode joint, and electrode 14 and electrode 24 are firmly joined mechanically and electrically. Note that the electrode joining in step (d) is performed, for example, after the joining in step (c), but may be performed simultaneously with the joining in step (c).

[0044] Once the bonding of the first integrated circuit element 10 and the second integrated circuit element 20 by steps (c) and (d) is completed, a semiconductor device 1 can be obtained. Individual semiconductor devices can be obtained by separating this semiconductor device 1 into individual pieces using a cutting means such as dicing. As a method for separating the semiconductor device 1 into individual pieces, for example, plasma dicing, stealth dicing, or laser dicing can be used.

[0045] As described above, according to the semiconductor device manufacturing method of this embodiment, in the first integrated circuit element 10, an opening 15 is provided at a position different from the location where the electrode 14 of the inorganic insulating layer 13 is placed, and multiple openings 15 discontinuously surround the electrode 14. In this case, even if internal stress accumulates in the first integrated circuit element 10 or the second integrated circuit element 20 due to heating when the first integrated circuit element 10 is joined to the second integrated circuit element 20, such internal stress is released by the multiple openings 15 during cooling. In particular, such accumulation of internal stress is likely to occur between the inorganic insulating layer 13 and the electrode 14, which have different coefficients of thermal expansion, but the multiple openings 15 discontinuously surrounding the electrode 14 can efficiently release the internal stress. That is, according to this manufacturing method, stress-free areas can be formed within the manufactured semiconductor device 1, thereby reducing internal stress. As a result, according to this semiconductor device manufacturing method, the occurrence of cracks associated with cooling can be suppressed.

[0046] Furthermore, in the semiconductor device manufacturing method according to this embodiment, the multiple openings 15 are provided so that the electrodes 14 are not exposed to each side surface 15a of the multiple openings 15. As a result, the electrodes 14 are covered by the inorganic insulating layer 13 without any external exposure except for the connection ends on the surface side. This reduces the influence of the external environment on the electrodes 14 and improves the reliability of the electrodes 14.

[0047] Furthermore, in the semiconductor device manufacturing method according to this embodiment, the multiple openings 15 are provided so that the first semiconductor substrate 11 is not exposed to the bottom surface 15b of each of the multiple openings 15. As a result, the connection surface of the first semiconductor substrate 11 with the electrode 14 is covered by the inorganic insulating layer 13 without being exposed to the outside. This reduces the influence of the external environment on the connection area between the first semiconductor substrate 11 and the electrode 14, and improves the reliability of the connection between the first semiconductor substrate 11 and the electrode 14.

[0048] Furthermore, in the semiconductor device manufacturing method according to this embodiment, each of the multiple openings 15 has an opening shape that is closed in the planar direction of the inorganic insulating layer 13. Therefore, factors that affect the semiconductor device 1 are less likely to penetrate the openings 15 inside the semiconductor device 1 after manufacturing, i.e., into the interior of the semiconductor device 1. As a result, the influence of the external environment on the semiconductor device 1 is reduced, and a highly reliable semiconductor device can be manufactured.

[0049] Furthermore, in the semiconductor device manufacturing method according to this embodiment, the width or diameter in the short-side direction of each of the multiple openings 15 is narrower than the width or diameter in the short-side direction of the electrode 14. Therefore, the area of ​​the multiple openings 15 formed in the inorganic insulating layer 13 can be reduced, and the area used for bonding with the inorganic insulating layer 23 in the inorganic insulating layer 13 can be widened. This makes the bonding between the first integrated circuit element 10 and the second integrated circuit element 20 more reliable.

[0050] Furthermore, in the semiconductor device manufacturing method according to this embodiment, the multiple openings 15 are formed by dry etching the inorganic insulating layer 13 of the first integrated circuit element 10. This method allows for the rapid formation of fine openings 15.

[0051] Furthermore, in the semiconductor device manufacturing method according to this embodiment, the inorganic insulating material constituting the inorganic insulating layer 13 and the inorganic insulating layer 23 is silicon dioxide, silicon nitride, or silicon oxynitride. This makes it possible to form wiring layers having finer electrodes 14 and 24, and also to form finer openings 15, etc.

[0052] Furthermore, in the semiconductor device manufacturing method according to this embodiment, a plurality of other openings (a plurality of second openings) that are recessed toward the second semiconductor substrate 21 from the bonding surface 20a may be provided at positions different from the arrangement of the electrodes 24 of the inorganic insulating layer 23. In this case, even if internal stress accumulates in the first integrated circuit element 10 or the second integrated circuit element 20 due to heating when bonding the first integrated circuit element 10 to the second integrated circuit element 20, such internal stress is released not only by the opening 15 but also by the other openings. As a result, this semiconductor device manufacturing method can further suppress the occurrence of cracks associated with cooling.

[0053] Although embodiments of the present invention have been described in detail above, the present invention is not limited to the above embodiments. For example, in the above embodiments, the application of the present invention to W2W (Wafer to Wafer) hybrid bonding was illustrated, but the present invention may also be applied to C2C (Chip to Chip) or C2W (Chip to Wafer). [Explanation of symbols]

[0054] 1... Semiconductor device, 10... First integrated circuit element, 10a... Bonding surface (first bonding surface), 11... First semiconductor substrate, 11a... First surface, 11b... Second surface, 12... First wiring layer, 13... Inorganic insulating layer (first insulating layer), 14... Electrode (first electrode), 15, 15A~15C... Opening (first opening), 15a... Side surface, 15b... Bottom surface, 20... Second integrated circuit element, 20a... Bonding surface (second bonding surface), 21... Second semiconductor substrate, 22... Second wiring layer, 23... Inorganic insulating layer (second insulating layer), 24... Electrode (second electrode).

Claims

1. A step of providing a first integrated circuit element comprising a first semiconductor substrate having a semiconductor element, and a first wiring layer having a first insulating layer and a first electrode and provided on one surface of the first semiconductor substrate, A step of providing a second integrated circuit element comprising a second semiconductor substrate having a semiconductor element, and a second wiring layer having a second insulating layer and a second electrode and provided on one surface of the second semiconductor substrate, A step of joining the first insulating layer of the first integrated circuit element and the second insulating layer of the second integrated circuit element to each other, The process includes a step of joining the first electrode of the first integrated circuit element and the second electrode of the second integrated circuit element to each other, The first insulating layer comprises an inorganic insulating material, Multiple first openings are provided in the first insulating layer at positions different from the placement of the first electrode, recessed toward the first semiconductor substrate from the first bonding surface that bonds with the second insulating layer, and these multiple first openings discontinuously surround the first electrode. A method for manufacturing a semiconductor device, wherein the plurality of first openings are provided such that the first electrodes are not exposed on each side surface of the plurality of first openings.

2. The plurality of first openings are provided so that the first semiconductor substrate is not exposed to the bottom surface of each of the plurality of first openings. A method for manufacturing a semiconductor device according to claim 1.

3. The depth of each of the plurality of first openings is shallower than the height of the first electrode. A method for manufacturing a semiconductor device according to claim 1 or 2.

4. The plurality of first openings discontinuously surround the first electrode in at least three directions, A method for manufacturing a semiconductor device according to any one of claims 1 to 3.

5. Each of the plurality of first openings has an opening shape that is closed in the planar direction of the first insulating layer. A method for manufacturing a semiconductor device according to any one of claims 1 to 4.

6. In the step of joining the first insulating layer and the second insulating layer to each other, each of the plurality of first openings is joined so as to face the planar portion of the second insulating layer. A method for manufacturing a semiconductor device according to any one of claims 1 to 5.

7. The aforementioned second insulating layer comprises an inorganic insulating material, In the second insulating layer, at positions different from the placement of the second electrode, a plurality of second openings are provided that are recessed toward the second semiconductor substrate from the second bonding surface that bonds with the first insulating layer, and the plurality of second openings discontinuously surround the second electrode. A method for manufacturing a semiconductor device according to any one of claims 1 to 6.

8. The inorganic insulating material included in at least one of the first insulating layer and the second insulating layer is silicon dioxide, silicon nitride, or silicon oxynitride. A method for manufacturing a semiconductor device according to any one of claims 1 to 7.

9. A first integrated circuit element comprising a first semiconductor substrate having a semiconductor element, and a first wiring layer having a first insulating layer and a first electrode and provided on one surface of the first semiconductor substrate, The second integrated circuit element comprises a second semiconductor substrate having a semiconductor element, and a second wiring layer having a second insulating layer and a second electrode, which is provided on one surface of the second semiconductor substrate. The first insulating layer of the first integrated circuit element and the second insulating layer of the second integrated circuit element are joined to each other. The first electrode of the first integrated circuit element and the second electrode of the second integrated circuit element are joined to each other. The first insulating layer comprises an inorganic insulating material, Multiple first openings are provided in the first insulating layer at positions different from the placement of the first electrode, recessed toward the first semiconductor substrate from the first bonding surface that bonds with the second insulating layer, and these multiple first openings discontinuously surround the first electrode. A semiconductor device in which the plurality of first openings are provided such that the first electrodes are not exposed on each side surface of the plurality of first openings.

10. The depth of each of the plurality of first openings is shallower than the height of the first electrode. The semiconductor device according to claim 9.

11. Each of the plurality of first openings is joined to face the planar portion of the second insulating layer, The semiconductor device according to claim 9 or 10.

12. An integrated circuit element for manufacturing a semiconductor device by joining it with other integrated circuit elements, A semiconductor substrate having a first surface and a second surface, wherein a semiconductor element is formed on at least one of the first surface and inside the substrate, The semiconductor substrate comprises a wiring layer provided on the second surface of the semiconductor substrate, The aforementioned wiring layer is An inorganic insulating layer provided on the second surface of the semiconductor substrate, The semiconductor substrate has an electrode that is electrically connected to the semiconductor element and penetrates the inorganic insulating layer, exposing it to the outside of the inorganic insulating layer, Multiple openings are provided in the inorganic insulating layer at positions different from the location where the electrodes are positioned, recessing toward the semiconductor substrate, and these multiple openings discontinuously surround the electrodes. An integrated circuit element in which the plurality of openings are provided such that the electrodes are not exposed on each side of the plurality of openings.

13. The depth of each of the plurality of openings is shallower than the height of the electrode. The integrated circuit element according to claim 12.

14. A method for manufacturing an integrated circuit element for manufacturing a semiconductor device by joining it with other integrated circuit elements, A step of providing a semiconductor substrate having a first surface and a second surface, wherein a semiconductor element is formed on at least one of the first surface and inside the substrate, The process includes forming a wiring layer on the second surface of the semiconductor substrate, The step of forming the wiring layer is, A step of forming an inorganic insulating layer on the second surface of the semiconductor substrate, A step of forming an electrode that penetrates the inorganic insulating layer so as to be electrically connected to the semiconductor element, The process includes forming a plurality of openings in the inorganic insulating layer at positions different from the locations where the electrodes are placed, the openings being recessed toward the semiconductor substrate, wherein the plurality of openings discontinuously surround the electrodes. A method for manufacturing an integrated circuit element, wherein the plurality of openings are provided so that the electrodes are not exposed on each side surface of the plurality of openings.

15. The depth of each of the plurality of openings is shallower than the height of the electrode. A method for manufacturing an integrated circuit element according to claim 14.

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