Optical receiver

Abstract

An optical receiver comprising a light-receiving element, a capacitor, a transimpedance, and a base. The light-receiving element comprises: a semiconductor layer; a first electrically conductive film electrically connected to a cathode electrode provided on a major surface of the semiconductor layer; a second electrically conductive film provided on the reverse side of the semiconductor layer from the major surface and electrically connected to the first electrically conductive film via an electrical conductor; and an anode pattern electrically connected to an anode electrode provided on the major surface of the semiconductor layer. The transimpedance includes a first pad electrically connected to the first electrically conductive film via a first wire, and a second pad electrically connected to the anode pattern via a second wire. The base has a major surface on which the light-receiving element and the transimpedance are mounted. A capacitance between the second electrically conductive film and the major surface of the base is greater than a parasitic capacitance between the first electrically conductive film and the second electrically conductive film, and an inductance of the electrical conductor is smaller than an inductance of the first wire.

Description

Technical Field

[0001] The present disclosure relates to a photoreceiver. This application claims priority based on Japanese Application No. 2021-134907 filed on August 20, 2021, and incorporates all the descriptions described in the Japanese application.

Background Art

[0002] Patent Document 1 discloses a photoreceiver including a light-receiving element and a transimpedance amplifier (TIA). In this photoreceiver, the electrical signal output from the light-receiving element is amplified by the TIA and then output to the outside of the photoreceiver. after being amplified by the TIA, it is output to the outside of the photoreceiver.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] A photoreceiver according to an embodiment includes a semiconductor layer provided with a light-receiving region, a first conductive film electrically connected to a cathode electrode provided on a main surface of the semiconductor layer, a second conductive film provided on the side opposite to the main surface of the semiconductor layer and electrically connected to the first conductive film through a conductor, and a light-receiving element having an anode pattern electrically connected to an anode electrode provided on the main surface of the semiconductor layer, a dielectric layer, and a capacitor composed of a first metal film and a second metal film provided sandwiching the dielectric layer therebetween, a first pad electrically connected to the first conductive film through a first wire, and a second pad electrically connected to the anode pattern through a second wire. A transimpedance amplifier and, on the main surface, the light-receiving element and the transimpedance amplifierIt comprises a base on which the second conductive film is mounted, and the capacitance between the second conductive film and the main surface of the base is greater than the parasitic capacitance between the first conductive film and the second conductive film. The inductance of the conductor is less than the inductance of the first wire. [Brief explanation of the drawing]

[0005] [Figure 1] Figure 1 is a plan view showing the internal structure of an optical receiver according to one embodiment. [Figure 2] Figure 2 is a cross-sectional view showing the optical receiver in Figure 1. [Figure 3] Figure 3 is a plan view showing an enlarged view of the surrounding structure of the photodetector and transimpedance amplifier in the optical receiver shown in Figure 1. [Figure 4] Figure 4 is a cross-sectional view along the line B1-B1 in Figure 3. [Figure 5] Figure 5 is a cross-sectional view along the line B2-B2 in Figure 3. [Figure 6] Figure 6 is an equivalent circuit diagram between the photodetector and the transimpedance amplifier in the optical receiver shown in Figure 1. [Figure 7] Figure 7 is an equivalent circuit diagram extracted from a portion of Figure 6. [Figure 8] Figure 8 is a graph showing the simulation results of the relationship between insertion loss and signal frequency in the optical receiver shown in Figure 1. [Figure 9] Figure 9 is a cross-sectional view showing an optical receiver according to Modification 1. [Figure 10] Figure 10 is a cross-sectional view showing an optical receiver according to a modified example 2. [Figure 11] Figure 11 is a cross-sectional view showing an optical receiver according to modified example 3. [Figure 12] Figure 12 is a plan view showing the photodetector in the optical receiver according to Modification 4. [Figure 13] Figure 13 is a graph showing the simulation results of the relationship between insertion loss and signal frequency in the optical receiver shown in Figure 12. [Figure 14] Figure 14 is a cross-sectional view showing an optical receiver according to Comparative Example 1. [Figure 15] Figure 15 is an equivalent circuit diagram between the photodetector and the transimpedance amplifier in the optical receiver shown in Figure 14. [Figure 16] Figure 16 is an equivalent circuit diagram extracted from a portion of Figure 15. [Figure 17] Figure 17 is a graph showing the simulation results of the relationship between insertion loss and signal frequency in the optical receiver shown in Figure 14. [Figure 18] Figure 18 is a cross-sectional view showing an optical receiver according to Comparative Example 2. [Figure 19] Figure 19 is an equivalent circuit diagram between the photodetector and the transimpedance amplifier in the optical receiver shown in Figure 18. [Figure 20] Figure 20 is a graph showing the simulation results of the relationship between insertion loss and signal frequency in the optical receiver shown in Figure 18. [Figure 21] Figure 21 is a cross-sectional view showing an optical receiver according to Comparative Example 3. [Figure 22] Figure 22 is an equivalent circuit diagram between the photodetector and the transimpedance amplifier in the optical receiver shown in Figure 21. [Figure 23] Figure 23 is a graph showing the simulation results of the relationship between insertion loss and signal frequency in the optical receiver shown in Figure 21. [Modes for carrying out the invention]

[0006] [Issues this disclosure aims to address] In the optical receiver described in Patent Document 1, the photodetector and the TIA are sometimes connected via a wire. However, in such a configuration, the existence of a resonant frequency due to the parasitic capacitance between the photodetector and the TIA and the inductance of the wire can be a problem. Due to the recent increase in the speed of optical communication, the frequency of optical signals is constantly increasing, and high-frequency bands of several tens of GHz or more are being used. Furthermore, it is even anticipated that high-frequency bands of 100 GHz or more will be used. If a resonant frequency exists in such a high-frequency band, an opaque band of the signal may be created, potentially leading to degradation of the signal waveform and a decrease in communication quality, such as inter-channel crosstalk. To reduce the inductance between the photodetector and the TIA, it is conceivable to connect the photodetector and the TIA using a flip-chip connection. However, in that case, a TIA with pads specifically for flip-chip connections is required, and a general-purpose TIA cannot be used, which may increase manufacturing costs.

[0007] [Effects of this disclosure] According to the optical receiver of this disclosure, a photodetector and a transimpedance are connected via a wire. amplifier By connecting these devices while shifting the opaque bandwidth caused by resonance, the degradation of communication quality can be suppressed.

[0008] [Description of Embodiments in this Disclosure] First, the contents of the embodiments of this disclosure will be listed and described. An optical receiver according to one embodiment includes a light-receiving element having a semiconductor layer on which a light-receiving region is provided, a first conductive film electrically connected to a cathode electrode provided on the main surface of the semiconductor layer, a second conductive film provided on the opposite side of the main surface of the semiconductor layer and electrically connected to the first conductive film via a conductor, and an anode pattern electrically connected to an anode electrode provided on the main surface of the semiconductor layer; a dielectric layer, and a capacitor consisting of a first metal film and a second metal film provided above and below the dielectric layer; and a transimpedance having a first pad electrically connected to the first conductive film via a first wire, and a second pad electrically connected to the anode pattern via a second wire. amplifier And, on the main surface, there is a light-receiving element and a transimpedance amplifier It comprises a base on which the second conductive film is mounted, and the capacitance between the second conductive film and the main surface of the base is greater than the parasitic capacitance between the first conductive film and the second conductive film. The inductance of the conductor is less than the inductance of the first wire.

[0009] In the optical receiver described above, a conductor is provided that is electrically connected to the first conductive film and the second conductive film, and the conductor inductance The capacitance between the first and second conductive films is connected in parallel with the parasitic capacitance between the first and second conductive films. The capacitance between the second conductive film and the main surface of the base is connected in series with the parasitic capacitance between the first and second conductive films. The inductance of the conductor is smaller than the inductance of the first wire, and the capacitance between the second conductive film and the main surface of the base is larger than the parasitic capacitance. In this configuration, the resonant frequency determined by this capacitance and the inductance of the first wire becomes dominant, and the resonant frequency can be set low. This allows the resonant frequency to be shifted to a lower frequency side than the high frequency band of tens of GHz or 100 GHz. In other words, the opaque band due to resonance can be removed from the signal frequency band. As a result, degradation of the signal waveform and the deterioration of communication quality such as inter-channel crosstalk can be suppressed.

[0010] In the optical receiver described above, the first conductive film may have an anode pad electrically connected to the anode electrode of the photodetector, and a first cathode pad and a second cathode pad electrically connected to the cathode electrode of the photodetector. The first cathode pad and the second cathode pad may be arranged with the anode pad in between. When the first cathode pad and the second cathode pad, both electrically connected to the cathode electrode of the photodetector, are arranged with the anode pad, both electrically connected to the anode electrode of the photodetector, in between, the magnetic fields created by the current flowing through the photodetector cancel each other out, making it difficult for the magnetic field to leak outside the first cathode pad and the second cathode pad. This can reduce crosstalk caused by electromagnetic coupling to other wiring patterns.

[0011] In the optical receiver described above, the dielectric layer may have a surface facing the second conductive film and a back surface facing the main surface of the base. A first metal film electrically connected to the second conductive film may be provided on the surface of the dielectric layer. A second metal film electrically connected to the main surface of the base may be provided on the back surface of the dielectric layer. In this case, bonding of the dielectric layer to the first metal film and the second metal film becomes easier.

[0012] In the optical receiver described above, the first metal film, the dielectric layer, and the second metal film may constitute a chip capacitor. In this case, a dielectric layer having a capacitance greater than the parasitic capacitance between the first conductive film and the second conductive film can be easily realized.

[0013] In the optical receiver described above, the first metal film, the dielectric layer, and the second metal film may constitute a MIM capacitor. In this case, a dielectric layer having a capacitance greater than the parasitic capacitance between the first conductive film and the second conductive film can be easily realized.

[0014] In the optical receiver described above, the dielectric layer may be an insulating film. In this case, the dielectric layer constituting the MIM capacitor can be suitably realized.

[0015] In the optical receiver described above, the dielectric layer may include at least one of silicon nitride, silicon oxide, and silicon nitride oxide. In this case, the dielectric layer constituting the MIM capacitor can be easily formed.

[0016] In the optical receiver described above, the conductor may extend between the first conductive film and the second conductive film, penetrating the photodetector, and may have vias connected to the first and second conductive films. The conductor may have multiple vias. The multiple vias may be spaced apart from each other in a plan view of the photodetector. In this case, a conductor can be easily realized that is connected in parallel with the parasitic capacitance between the first and second conductive films and has an inductance smaller than the inductance of the first wire. Furthermore, by configuring the first and second conductive films to be connected by vias, the degree of freedom in wiring design is increased.

[0017] The above-described optical receiver may further include a metal substrate provided between the dielectric layer and the base, and electrically connected to the main surface of the base. In this case, even if the dielectric layer is formed thinly to increase capacitance, the presence of the metal substrate allows the height of the dielectric layer and the photodetector on the metal substrate to be maintained high, thus reducing the transimpedance between the photodetector and the metal substrate. amplifier The height difference between them can be kept small. As a result, the first conductive film and the transimpedance amplifier This prevents the first wire connecting to the upper first pad from becoming too long, and also prevents the photodetector from having to use transimpedance. amplifier Connection loss between Loss It can be suppressed.

[0018] The optical receiver described above may further include an insulating substrate provided between the dielectric layer and the base. The insulating substrate may have a surface facing the dielectric layer and a back surface facing the main surface of the base. Back side It is electrically connected to the main surface of the base. Back side A metal film may be provided on the insulating substrate. surface This is via vias that penetrate the interior of the insulating substrate. Back side A metal film and an electrically connected surface A metal film may be provided. In this case, even if the dielectric layer is formed thinly to increase capacitance, the presence of an insulating substrate allows the height of the dielectric layer and the photodetector on the insulating substrate to be maintained high, thus ensuring that the photodetector and transimpedance are maintained. amplifier The height difference between them can be kept small. As a result, the first conductive film and the transimpedance amplifier This prevents the first wire connecting to the upper first pad from becoming too long, and also prevents the photodetector from having to use transimpedance. amplifier Connection loss between Loss It can be suppressed.

[0019] [Details of the embodiments of this disclosure] A specific example of an optical receiver according to one embodiment will be described below with reference to the drawings. This disclosure is not limited to these examples, but is as defined by the claims, and all modifications within the meaning and scope of the claims are intended to be included. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant descriptions are omitted where appropriate.

[0020] Figure 1 is a plan view showing the internal structure of the optical receiver 1 according to this embodiment. Figure 2 is a cross-sectional view showing the optical receiver 1. In Figure 1, the optical receiver 1 is shown with the lid of the package 11 removed. The optical receiver 1 is used as a ROSA (Receiver Optical Sub Assembly) of an optical transceiver. As shown in Figure 1, the optical receiver 1 comprises a package 11. Package 11 is a hollow container that is roughly rectangular in shape. Package 11 has metal side walls 12 and a metal bottom plate 13.

[0021] The bottom plate 13 is a rectangular flat plate. The bottom plate 13 extends along direction A1 and direction A2 intersecting direction A1. The bottom plate 13 includes a bottom surface 13a facing inward into the package 11. At least the bottom surface 13a of the bottom plate 13 is conductive, and the bottom surface 13a is set to a reference potential. The bottom plate 13 may be made of a metal such as copper molybdenum or copper tungsten. If the bottom plate 13 is made of a material with good thermal conductivity, it is possible to improve the heat dissipation of the bottom plate 13.

[0022] The side wall 12 has a rectangular frame shape and is positioned along the periphery of the bottom plate 13. The opening on the side wall 12 opposite to the bottom plate 13 is sealed by a lid. The side wall 12 includes side wall portions 12a and 12b aligned along direction A1. An opening is formed in side wall portion 12a, and a bush 14 is provided in this opening. The receptacle of the optical receiver 1 is fixed to side wall portion 12a via the bush 14. Inside the bush 14, for example, an optical window 15 (see Figure 2) is positioned. As shown in Figure 2, signal light L emitted from the optical fiber connected to the receptacle passes through the optical window 15 and is taken into the package 11. The signal light L is, for example, a multiplexed signal light having multiple signal light components.

[0023] As shown in Figures 1 and 2, the optical receiver 1 further comprises an optical axis converter 21, an optical demultiplexer 22, multiple lenses 23, multiple photodetectors 16, a TIA 25 (transimpedance amplifier), and a feedthrough 26. The optical axis converter 21, optical demultiplexer 22, multiple lenses 23, multiple photodetectors 16, and TIA 25 are housed inside the package 11 and are arranged in this order from the side wall 12a side in direction A1. As shown in Figure 2, the optical receiver 1 further comprises a capacitor 32 on which multiple photodetectors 16 are mounted.

[0024] The feedthrough 26 is provided in the side wall 12b and makes an electrical connection to the external circuit. The feedthrough 26 is, for example, constructed by laminating multiple ceramic substrates and is assembled to fit into an opening formed in the side wall 12b. Multiple terminals 26a for making an electrical connection to the external circuit are provided on the outer portion of the feedthrough 26 located outside the side wall 12b. Multiple terminals for making an electrical connection to the TIA 25 are provided on the inner portion of the feedthrough 26 located inside the side wall 12b. The multiple terminals on the inner portion of the side wall 12b and the multiple terminals 26a on the outer portion of the side wall 12b are short-circuited to each other by wiring embedded inside the feedthrough 26.

[0025] As shown in Figure 2, the optical axis converter 21 converts the optical axis of the signal light L input from the optical window 15 into the inside of the package 11. The optical axis converter 21 has a pair of mirrors 21a and 21b. The pair of mirrors 21a and 21b are arranged to face each other in direction A3, which intersects directions A1 and A2. One of the pair of mirrors 21a, 21b, is positioned opposite the optical window 15 in direction A1. Mirror 21a reflects the signal light L input from the optical window 15 in direction A1 towards the bottom plate 13 in direction A3. The other mirror 21b of the pair of mirrors 21a, 21b is installed on the bottom plate 13 and reflects the signal light L input from mirror 21a in direction A3 towards the side wall 12b in direction A1. In the following description, viewing from direction A3 may be referred to as a "plan view".

[0026] The signal light L reflected by the mirror 21b enters the optical demultiplexer 22 in direction A1. The optical demultiplexer 22 separates the signal light L, which is a multiplexed signal light, into multiple signal light components with different wavelengths. Multiple lenses 23 are positioned between the optical demultiplexer 22 and the multiple photodetectors 16 in direction A1 and are aligned along direction A2 (see Figure 1). Each lens 23 is incident on each signal light component separated by the optical demultiplexer 22. Each lens 23 focuses each separated signal light component and guides it to each photodetector 16.

[0027] Multiple photodetectors 16 are mounted on a capacitor 32 and are arranged along direction A2 so as to face direction A1 with respect to multiple lenses 23. Each photodetector 16 is, for example, a waveguide-type photodetector. Each photodetector 16 is optically coupled to an optical demultiplexer 22 via each lens 23. Signal light components from each lens 23 are incident on, for example, the side of each photodetector 16. Each photodetector 16 converts the corresponding signal light components into electrical signals. In the example shown in Figure 1, four photodetectors 16 are shown, but the number of photodetectors 16 is not particularly limited. The number of photodetectors 16 may be any number of one or more.

[0028] The TIA25 is mounted on the bottom surface 13a of the package 11 and positioned between the multiple photodetectors 16 and the feedthrough 26 in direction A1. The TIA25 is electrically connected to each photodetector 16. The TIA25 converts the current signals from each photodetector 16 into voltage signals. The TIA25 is electrically connected to the wiring of the feedthrough 26 via wires. The voltage signal output from the TIA25 is output to the outside of the optical receiver 1 via the feedthrough 26.

[0029] Figure 3 is a plan view showing an enlarged view of the peripheral structure of the photodetector 16 and TIA25. Figure 4 is a cross-sectional view along the line B1-B1 in Figure 3. Figure 5 is a cross-sectional view along the line B2-B2 in Figure 3.

[0030] The light-receiving element 16 has a semiconductor layer 24, a first conductive film 28, and a second conductive film 37. The semiconductor layer 24 has a light-receiving region 24R (see Figures 3 and 5). The semiconductor layer 24 is, for example, rectangular and has a surface 24a, a back surface 24b, and a side surface 24c. The surface 24a and the back surface 24b are aligned along direction A3. The surface 24a faces away from the bottom plate 13 in direction A3. The back surface 24b faces the capacitor 32 in direction A3. The side surface 24c faces the TIA 25 in direction A1. The side surface 24c connects the surface 24a and the back surface 24b in direction A3. The surface 24a is provided with the first conductive film 28. The first conductive film 28 is a metal film fixed to the surface 24a of the semiconductor layer 24. The first conductive film 28 is electrically connected to the cathode electrode and anode electrode of the photodetector 16. A second conductive film 37 is provided on the back surface 24b. The second conductive film 37 is a metal film fixed to the back surface 24b of the semiconductor layer 24. A parasitic capacitance C exists between the first conductive film 28 and the second conductive film 37. cq (See Figure 4) is occurring. Parasitic capacity C cq For example, this range is between 10 fF and 100 fF.

[0031] As shown in Figure 3, the first conductive film 28 has a first cathode pad 28b and a second cathode pad 28c. The first cathode pad 28b and the second cathode pad 28c are spaced apart along direction A2. An anode pad 28a is positioned between the first cathode pad 28b and the second cathode pad 28c. Therefore, the first cathode pad 28b and the second cathode pad 28c are positioned on both sides of the anode pad 28a in direction A2.

[0032] An anode pattern 28h extending linearly along direction A1 is connected to the anode pad 28a. The tip of the anode pattern 28h facing the anode pad 28a is the anode electrode of the photodetector 16, and the light-receiving region 24R of the photodetector 16 is electrically connected to the anode electrode (i.e., the tip of the anode pattern 28h). A cathode pattern 28f extending linearly along direction A1 is connected to the first cathode pad 28b. In other words, one end of the cathode pattern 28f in direction A1 is connected to the first cathode pad 28b. The other end of the cathode pattern 28f in direction A1 is connected to a cathode pattern 28j extending linearly along direction A2 toward the anode pattern 28h.

[0033] A cathode pattern 28g extending linearly along direction A1 is connected to the second cathode pad 28c. That is, one end of the cathode pattern 28g in direction A1 is connected to the second cathode pad 28c. The other end of the cathode pattern 28g in direction A1 is connected to a cathode pattern 28k extending linearly along direction A2 toward the anode pattern 28h. The cathode patterns 28f and 28g are arranged on both sides of the anode pattern 28h in direction A2.

[0034] The first cathode pad 28b is electrically connected to the cathode pattern 28j (cathode electrode) of the photodetector 16 via the cathode pattern 28f. The second cathode pad 28c is electrically connected to the cathode pattern 28k (cathode electrode) of the photodetector 16 via the cathode pattern 28g. The width of the anode pattern 28h is smaller than the width of each cathode pattern 28f, 28g, 28j, 28k. The cathode wiring pattern 28A, composed of the first cathode pad 28b, the second cathode pad 28c, and the cathode patterns 28f, 28g, 28j, 28k, has a U-shape that opens to one side in direction A1. The anode pad 28a and anode pattern 28h are positioned in the opening of the cathode wiring pattern 28A and are surrounded by the cathode wiring pattern 28A. The first conductive film 28 may have a configuration that includes a first cathode pad 28b, a second cathode pad 28c, a cathode pattern 28f, a cathode pattern 28g, a cathode pattern 28j, and a cathode pattern 28k.

[0035] As shown in Figures 3 and 4, the semiconductor layer 24 further has a plurality of vias 38. The plurality of vias 38 are provided inside the semiconductor layer 24 and are made of a conductive material. The plurality of vias 38 penetrate the semiconductor layer 24 in direction A3 and are connected to the first conductive film 28 and the second conductive film 37 that sandwich the semiconductor layer 24. Thus, the first conductive film 28 and the second conductive film 37 are electrically connected to each other via the plurality of vias 38. In this case, the inductance L of each via 38 via The inductance L of each wire 72, 73 is wire It is connected in parallel to it.

[0036] As shown in Figure 3, the multiple vias 38 are formed only in the region that overlaps with the cathode wiring pattern 28A in a plan view. That is, the multiple vias 38 are formed only in the region between the cathode wiring pattern 28A and the second conductive film 37 in direction A3. Therefore, the multiple vias 38 are not formed in the region that overlaps with the anode pad 28a and anode pattern 28h in a plan view, i.e., the region between the anode pad 28a and anode pattern 28h and the second conductive film 37 in direction A3. In the example shown in Figure 3, the multiple vias 38 are formed only in the region that overlaps with the cathode patterns 28f and 28g in a plan view.

[0037] As shown in Figure 3, the multiple vias 38 are spaced apart from each other and arranged at equal intervals in a plan view. The inner diameter of each of the multiple vias 38 may be set to be the same, for example. The combined inductance L of the multiple vias 38 via The combined inductance L of wires 72 and 73 is wire It is sufficiently small compared to the combined inductance L of wires 72 and 73. wire For example, while the combined inductance L of multiple vias 38 is between 0.1 nH and 0.5 nH, via For example, it is 0.05 nH or less. In the example shown in Figure 3, four vias 38 are shown, but the number of vias 38 is not limited to four and can be any number. The number of vias 38 may be one, two, three, or five or more. In the example shown in Figure 3, the multiple vias 38 are positioned so as not to overlap with the anode pad 28a, the first cathode pad 28b, and the second cathode pad 28c, but they may be positioned so as to overlap with these pads.

[0038] Referring again to FIG. 4, the capacitor 32 is a rectangular parallelepiped member on which the light receiving element 16 is mounted. The capacitor 32 is mounted on the bottom surface 13a of the bottom plate 13. Therefore, the capacitor 32 is disposed between the light receiving element 16 and the bottom surface 13a in the direction A3. The light receiving element 16 is mounted on the bottom surface 13a of the bottom plate 13 via the capacitor 32. The light receiving element 16 may be mounted on the bottom surface 13a via another member other than the capacitor 32 as long as a capacitance is generated between the second conductive film 37 and the bottom surface 13a. The capacitor 32 is a capacitive element such as a chip capacitor, for example. The capacitor 32 has a dielectric layer 41, a first metal film 42, and a second metal film 43. The dielectric layer 41 is sandwiched between the first metal film 42 and the second metal film 43 in the direction A3. The dielectric layer 41 functions as an insulating layer that electrically insulates between the first metal film 42 and the second metal film 43. The thickness of the dielectric layer 41 is, for example, thicker than each of the thicknesses of the first metal film 42 and the second metal film 43. The dielectric layer 41 has a front surface 41a and a back surface 41b arranged along the direction A3. The front surface 41a faces the back surface 24b of the semiconductor layer 24. The first metal film 42 is provided on the front surface 41a. Therefore, the first metal film 42 is disposed between the second conductive film 37 provided on the back surface 24b of the semiconductor layer 24 and the dielectric layer 41. The first metal film 42 is electrically joined to the second conductive film 37 via a conductive adhesive such as solder.

[0039] The back surface 41b of the dielectric layer 41 faces the bottom surface 13a of the bottom plate 13. The second metal film 43 is provided on the back surface 41b. Therefore, the second metal film 43 is disposed between the dielectric layer 41 and the bottom surface 13a. The second metal film 43 is electrically joined to the bottom surface 13a via a conductive adhesive such as solder. The capacitance C of the capacitor 32 c is generated between the first metal film 42 and the second metal film 43 sandwiching the dielectric layer 41. The capacitance C of the capacitor 32 c is the parasitic capacitance C generated between the first conductive film 28 and the second conductive film 37 cq and is connected in series thereto. The capacitance C of the capacitor 32 c is the parasitic capacitance C generated between the first conductive film 28 and the second conductive film 37 cqIt is considerably larger than that. Parasitic capacity C cq For example, while the capacitance of capacitor C is between 10fF and 100fF, c For example, this is 10pf or higher.

[0040] TIA25 is mounted on the bottom surface 13a of the base plate 13 and is electrically connected to the bottom surface 13a. Therefore, the ground potential (reference potential) of TIA25 matches the potential of the bottom surface 13a. TIA25 is positioned alongside the photodetector 16 in direction A1. TIA25 has, for example, a rectangular parallelepiped shape and has a front surface 25a and a back surface 25b. The front surface 25a and the back surface 25b are aligned along direction A3. The back surface 25b is electrically bonded to the bottom surface 13a via a conductive adhesive such as solder. The front surface 25a is positioned on the opposite side from the bottom surface 13a in direction A3.

[0041] The TIA25 further includes a signal pad 25c, a first bias pad 25d, and a second bias pad 25e. The signal pad 25c, the first bias pad 25d, and the second bias pad 25e are provided on the surface 25a of the TIA25. The first bias pad 25d and the second bias pad 25e are arranged on either side of the signal pad 25c in direction A2. The signal pad 25c is connected to the anode pad 28a via a wire 71 (see Figure 3). That is, one end of the wire 71 is connected to the signal pad 25c, and the other end of the wire 71 is connected to the anode pad 28a.

[0042] The first bias pad 25d is connected to the second cathode pad 28c of the first conductive film 28 via wire 72 (see Figure 3). That is, one end of wire 72 is connected to the first bias pad 25d, and the other end of wire 72 is connected to the second cathode pad 28c. The second bias pad 25e is connected to the first cathode pad 28b of the first conductive film 28 via wire 73. That is, one end of wire 73 is connected to the second bias pad 25e, and the other end of wire 73 is connected to the first cathode pad 28b.

[0043] A ground layer 27 is provided inside the TIA25. The ground layer 27 extends along directions A1 and A2 inside the TIA25. The ground layer 27 is located between the surface 25a and the back surface 25b, closer to the surface 25a. The ground layer 27 is connected to the back surface 25b via a via 29. The via 29 penetrates the TIA25 between the ground layer 27 and the back surface 25b in direction A3. The ground layer 27 is electrically connected to the bottom surface 13a of the bottom plate 13 via the via 29. Therefore, the ground potential is supplied to the ground layer 27.

[0044] <Effects and Effects> The effects obtained by the optical receiver 1 according to this embodiment, as described above, will be explained along with the problems of the comparative example. Figure 6 is an equivalent circuit diagram between the photodetector 16 and the TIA 25 in the optical receiver 1 according to this embodiment. Figure 7 is an equivalent circuit diagram extracted from a part of Figure 6. In Figure 6, "Port 1" indicates a portion set between the anode (A) and cathode (C) of the photodetector 16, and "Port 2" indicates a portion set between the signal pad 25c and the ground layer 27 of the TIA 25.

[0045] As shown in Figure 6, in the optical receiver 1, the cathode (C) of the photodetector 16 is connected to the first bias pad 25d and the second bias pad 25e of the TIA25 via wires 72 and 73. The anode (A) of the photodetector 16 is connected to the signal pad 25c of the TIA25 via wire 71. The ground layer 27 of the TIA25 is electrically connected to the bottom surface 13a of the bottom plate 13. There is a parasitic capacitance C between the cathode pads 28b, 28c and the second conductive film 37. cq Furthermore, in this embodiment, a capacitor 32 is provided between the second conductive film 37 and the bottom plate 13, and a plurality of vias 38 are formed between the cathode pads 28b, 28c and the second conductive film 37. Therefore, as shown in Figure 7, the capacitance C of the capacitor 32 c Parasitic capacity C cqConnected in series with respect to the inductance of each via 38 L via Parasitic capacity C cq It is connected in parallel to it.

[0046] The cathode pads 28b and 28c receive a power supply (bias) voltage from the first bias pad 25d and second bias pad 25e of the TIA25 via wires 72 and 73. When signal light L is incident on the photodetector 16, the photodetector 16 outputs a current signal (high-frequency current) of a magnitude corresponding to the amount of light. This current signal is input from the anode (A) of the photodetector 16 to the signal pad 25c of the TIA25 via the anode pad 28a and wire 71. The TIA25 converts the input current signal into a voltage signal. This voltage signal is supplied to an external source of the optical receiver 1 or to other electronic components within the optical receiver 1.

[0047] Figure 14 is a cross-sectional view showing an optical receiver 101 according to Comparative Example 1. Unlike the optical receiver 1 according to this embodiment, the optical receiver 101 does not have multiple vias formed on the photodetector 124, and there is no capacitor between the photodetector 124 and the base plate 13. Therefore, the optical receiver 101 has a configuration in which the photodetector 124 is directly mounted on the base plate 13. Figure 15 is an equivalent circuit diagram between the photodetector 124 and the TIA 25 in the optical receiver 101. Figure 16 is an equivalent circuit diagram extracted from a part of Figure 15. In the equivalent circuit diagram shown in Figure 15, the current signal from the photodetector 124 travels, for example, from the anode (A) of the photodetector 124 through the wire 71 and signal pad 25c to the ground layer 27 of the TIA 25, and then capacitively couples to the first bias pad 25d and the second bias pad 25e of the TIA 25. The current signal then flows through a path that returns to the cathode (C) of the photodetector 124 via wires 72 and 73.

[0048] Here, between the first conductive film 28 and the second conductive film 37, there is a parasitic capacitance C cq Because this is occurring, this parasitic capacity C cq The combined inductance L of wires 72 and 73 wireThis constitutes a parallel resonant circuit where components are connected in parallel. Figure 16 shows the inductance L wire and parasitic capacity C cq This shows a parallel resonant circuit composed of the following. The resonant frequency f1 of this parallel resonant circuit is expressed by the following equation (1). The resonant frequency f1 is the frequency bandwidth of the transmission signal (for example, several tens of G As the frequency approaches Hz or higher, the return current from TIA25 to the photodetector 124 decreases. At this time, the flow of the current signal from the photodetector 124 to TIA25 is obstructed, resulting in signal opacity.

number

[0049] Figure 17 is a graph showing the simulation results of the relationship between insertion loss (unit: dB) and signal frequency (unit: GHz) in the optical receiver 101. In optical communication systems, 100G transmission is the mainstream within branch lines and data centers, and between branch lines and data centers, and higher speeds such as 800G transmission are planned for the future. At such transmission speeds, the frequency bandwidth of the transmitted signal is several tens of G The frequency range is from Hz to around 100 GHz. In contrast, in the optical receiver 101, as shown in Figure 17, the insertion loss drops significantly around 30 GHz, indicating that the resonant frequency f1 is located around 30 GHz. In this case, the resonant frequency f1 overlaps with the frequency band of the transmitted signal, resulting in an opaque band of the transmitted signal as described above. As a result, there is a risk of degradation of the signal waveform and a decrease in communication quality, such as inter-channel crosstalk.

[0050] Figure 18 is a cross-sectional view showing the optical receiver 102 according to Comparative Example 2. Figure 19 is an equivalent circuit diagram between the photodetector 124 and the TIA25 in the optical receiver 102. Figure 20 is a graph showing the simulation results of the relationship between insertion loss (unit: dB) and signal frequency (unit: GHz) in the optical receiver 102.

[0051] The optical receiver 102 has a configuration in which a ceramic substrate 150 is further added between the light-receiving element 124 and the bottom plate 13 in the optical receiver 101 according to Comparative Example 1. The ceramic substrate 150 has a capacitance C of, for example, 10 fF or more and 100 fF or less. s This configuration has the following characteristics. Thus, by placing the ceramic substrate 150 under the photodetector 124, it is conceivable that the capacitance between the first conductive film 28 on the photodetector 124 and the bottom plate 13 can be reduced, and the resonant frequency can be shifted to the high-frequency side. In this configuration, as shown in Figure 19, the capacitance C of the ceramic substrate 150 s This is the parasitic capacitance C between the first conductive film 28 and the second conductive film 37. cq It is connected in series with respect to the parallel resonant circuit shown in Figure 19, and the resonant frequency f2 is expressed by the following equation (2).

number

[0052] However, in the optical receiver 102, parasitic capacitance C cq Capacitance C s If the noise cannot be sufficiently reduced, the resonant frequency f2 cannot be sufficiently shifted to the high-frequency side. As shown in Figure 20, the resonant frequency f2 of the parallel resonant circuit in the optical receiver 102 is only slightly shifted to the high-frequency side compared to the resonant frequency f1 in Comparative Example 1, and is located around 40 GHz. This resonant frequency f2 overlaps with the frequency band of the transmitted signal. Therefore, the measure of placing the ceramic substrate 150 under the photodetector 124, as in Comparative Example 2, does not sufficiently shift the resonant frequency f2.

[0053] Figure 21 is a cross-sectional view showing the optical receiver 103 according to Comparative Example 3. Figure 22 is an equivalent circuit diagram between the photodetector 224 and the TIA 25 in the optical receiver 103. Figure 23 is a graph showing the simulation results of the relationship between insertion loss (unit: dB) and signal frequency (unit: GHz) in the optical receiver 103.

[0054] The optical receiver 103 in Comparative Example 3 is the same as the photodetector element of the optical receiver 102 in Comparative Example 2.124 The optical receiver has a configuration in which multiple vias 138 are formed. In other words, the optical receiver 103 has an optical receiver 224 in which multiple vias 138 are formed, instead of the optical receiver 124 of the optical receiver 102. In this configuration, the multiple vias 138 penetrate the interior of the optical receiver 224 and are connected to the first conductive film 28 and the second conductive film 37 that sandwich the optical receiver 224. In this case, as shown in the parallel resonant circuit of Figure 22, the combined inductance L of the multiple vias 138 is via This is the parasitic capacitance C between the first conductive film 28 and the second conductive film 37. cq It is connected in parallel to it.

[0055] Here, the inductance L via is the inductance L wire Sufficiently smaller than, parasitic capacity C cq The capacitance C of the ceramic substrate 150 s Because it is sufficiently smaller than, the inductance L via and parasitic capacity C cq Approximating this to zero, the resonant frequency f3 of the parallel resonant circuit shown in Figure 22 is expressed by the following equation (3). Therefore, in the optical receiver 103, the inductance L wire and capacitance C s These two factors dominate the resonant frequency f3.

number

[0056] In contrast, the optical receiver 1 according to this embodiment includes a light-receiving element 16 on which a plurality of vias 38 are formed, and a capacitor 32 provided between the light-receiving element 16 and the bottom plate 13. The combined inductance L via This is the parasitic capacitance C between the first conductive film 28 and the second conductive film 37. cq It is connected in parallel with the capacitance C of capacitor 32. c Parasitic capacity C cqIt is connected in series with via 38. The combined inductance L via is the inductance L wire Sufficiently smaller than, parasitic capacity C cq capacitance C c Because it is sufficiently smaller than, the inductance L via and parasitic capacity C cq Approximating L to be zero, the resonant frequency f of the parallel resonant circuit shown in Figure 7 is expressed by the following equation (4). Therefore, in this embodiment, the inductance L wire and capacitance C c These two factors dominate the resonant frequency f.

number

[0057] Here, capacitance C c This is the capacitance C related to Comparative Example 3. s It is sufficiently larger than . Therefore, the resonant frequency f becomes lower than the resonant frequency f3 in Comparative Example 3, and shifts significantly to the lower frequency side. Figure 8 is a graph showing the simulation results of the relationship between insertion loss (unit: dB) and signal frequency (unit: GHz) in the optical receiver 1 according to this embodiment. As shown in Figure 8, the resonant frequency f has shifted to the extremely low frequency side, for example, below 5 GHz, and it can be seen that it does not exist in the frequency band of the transmission signal, such as tens of GHz or 100 GHz. In this way, in this embodiment, the resonant frequency f can be sufficiently shifted to the lower frequency side than the frequency band of the transmission signal. In other words, the opaque band due to resonance can be removed from the frequency band of the transmission signal. As a result, degradation of the signal waveform and the deterioration of communication quality such as inter-channel crosstalk can be suppressed. Furthermore, in this embodiment, unlike when the photodetector and TIA are connected with a flip-chip connection, there is no need to use a TIA with a pad dedicated to flip-chip connection, so there is a high degree of freedom in the combination of the photodetector and TIA.

[0058] On the higher frequency side of the transmission signal's frequency band, the inductance L via and parasitic capacity C cqIt is thought that a resonant frequency exists. This resonant frequency is thought to shift to the higher frequency side as the number of vias 38 increases, and does not exist in the frequency band of the transmitted signal. In the optical receiver 1 according to this embodiment, the capacitance C of capacitor 32 c Since it is sufficiently large and can be considered to short-circuit with respect to high frequencies, it can be considered that wires 72 and 73 and via 38 are connected in parallel to ground. In this case, the more vias 38 there are, the greater the combined inductance L via Because it appears to decrease, the inductance L via and parasitic capacity C cq The resonant frequency is thought to shift to the higher frequency side. On the other hand, in the optical receiver 103 according to Comparative Example 3, the capacitance C of capacitor 32 c Compared to the capacitance C of ceramic substrate 150 s Because it is small, it cannot be considered that wires 72 and 73 and via 138 are connected in parallel with respect to ground, resulting in a combined inductance L via It is thought that the signal is lowered and therefore not visible. For this reason, unlike the optical receiver 1 according to this embodiment, it is thought that the optical receiver 103 has a resonance point (see Figure 23) around 100 GHz on the high-frequency side.

[0059] In this embodiment, the first cathode pad 28b and the second cathode pad 28c are arranged on either side of the anode pad 28a, respectively. In this case, the magnetic fields created by the current flowing through the photodetector 16 cancel each other out, making it less likely for current to leak outside the cathode pads 28b and 28c. This reduces crosstalk caused by electromagnetic coupling to other wiring patterns.

[0060] In this embodiment, a first metal film 42 electrically connected to a second conductive film 37 is provided on the surface 41a of the dielectric layer 41, and a second metal film 43 electrically connected to the bottom surface 13a of the bottom plate 13 is provided on the back surface 41b of the dielectric layer 41. This facilitates bonding of the dielectric layer 41 to the first metal film 42 and the second metal film 43.

[0061] In this embodiment, the first metal film 42, the dielectric layer 41, and the second metal film 43 constitute a chip capacitor. This results in parasitic capacitance C cq Capacitance C is larger than c A capacitor 32 having the above characteristics can be easily realized.

[0062] In this embodiment, a plurality of vias 38 penetrate the semiconductor layer 24 and are connected to the first conductive film 28 and the second conductive film 37. The plurality of vias 38 are arranged at positions spaced apart from each other in a plan view. In this case, the parasitic capacitance C cq It is connected in parallel with respect to and has an inductance L wire A configuration with a smaller inductance can be easily realized. Furthermore, by connecting the first conductive film 28 and the second conductive film 37 by via 38, the degree of freedom in wiring design can be increased.

[0063] The optical receiver 1 relating to this disclosure is not limited to the embodiments described above. The optical receiver 1 relating to this disclosure may be modified in any way that does not depart from the spirit of the claims.

[0064] <Example 1> Figure 9 is a cross-sectional view showing the optical receiver 1A according to Modification 1. In the embodiment described above, the case in which capacitor 32 is a chip capacitor was illustrated. In Modification 1, the case in which capacitor 32A is an MIM (Metal-Insulator-Metal) capacitor is illustrated. Capacitor 3 2A has a dielectric layer 41A, a first metal film 42, and a second metal film 43, with the dielectric layer 41A sandwiched between the first metal film 42 and the second metal film 43. The dielectric layer 41A is formed thinner than the dielectric layer 41 according to the above-described embodiment. For example, the thickness of the dielectric layer 41A may be the same as the thickness of the first metal film 42 or the thickness of the second metal film 43. The dielectric layer 41A is configured as an insulating film that electrically insulates the first metal film 42 and the second metal film 43. The dielectric layer 41A may be composed of at least one of SiN (silicon nitride), SiO (silicon oxide), and SiON (silicon nitride oxide).

[0065] In the optical receiver 1A, the capacitor 32A is mounted on the back surface 24b of the semiconductor layer 24. In this case, the first metal film 42 of the capacitor 32A is integrally formed with the second conductive film 37 provided on the back surface 24b of the semiconductor layer 24. Therefore, when manufacturing the optical receiver 1A, the dielectric layer 41A and the second metal film 43 are formed on the back surface 24b of the semiconductor layer 24, and then the semiconductor layer 24 on which the dielectric layer 41A and the second metal film 43 are formed is mounted on a metal substrate 81, which will be described later. Capacitance C of capacitor 32A c This is the parasitic capacitance C between the first conductive film 28 and the second conductive film 37. cq It is significantly larger than that. Capacitance C of capacitor 32A c It is 10pF or more. Capacitance C of capacitor 32A c This may, for example, be the same as the capacitance of the chip capacitor.

[0066] The optical receiver 1A further includes a metal substrate 81 provided between the capacitor 32A and the base plate 13. The metal substrate 81 is a substrate made of a metallic material and is conductive. The metal substrate 81 has a surface 81a that is conductively bonded to the second metal film 43 of the capacitor 32A, and a back surface 81b that is conductively bonded to the bottom surface 13a of the base plate 13. Therefore, the second metal film 43 is electrically connected to the base plate 13 via the metal substrate 81. Depending on the thickness of the metal substrate 81, the height of the capacitor 32A on the metal substrate 81 and the height of the photodetector 16 on the capacitor 32A vary. Therefore, the thickness of the metal substrate 81 may be set so that the height of the photodetector 16 matches the height of the TIA 25.

[0067] Even with this configuration, the same effects as in the above-described embodiment can be obtained. Furthermore, in the optical receiver 1A, the capacitor 32A is composed of the first metal film 42, the dielectric layer 41A, and the second metal film 43, which makes it possible to reduce the thickness of the capacitor 32A and parasitic capacitance C cq A capacitor 32A having a larger capacitance than can be easily realized. The dielectric layer 41A is composed of at least one of silicon nitride, silicon oxide, and silicon nitride oxide, and insulates between the first metal film 42 and the second metal film 43. This makes it easy to form the dielectric layer 41A and to achieve the desired capacitance C between the first metal film 42 and the second metal film 43. c We can be sure to secure it.

[0068] Furthermore, in the optical receiver 1A, a metal substrate 81 is provided between the capacitor 32A and the bottom plate 13. As a result, even if the dielectric layer 41A is formed thinly to increase capacitance, the presence of the metal substrate 81 allows the height of the capacitor 32A and the photodetector 16 on the metal substrate 81 to be maintained high, thus keeping the height difference between the photodetector 16 and the TIA 25 small. Consequently, the situation in which the wires 71, 72, and 73 between the photodetector 16 and the TIA 25 become long can be suppressed, and connection loss between the photodetector 16 and the TIA 25 can be reduced. Loss It can be suppressed.

[0069] <Modification 2> Figure 10 is a cross-sectional view showing an optical receiver 1B according to Modification 2. The optical receiver 1B has a configuration in which the metal substrate 81 is replaced with an insulating substrate 82 in the optical receiver 1A according to Modification 1. In other words, the optical receiver 1B is equipped with a capacitor 32A instead of a capacitor 32, and an insulating substrate 82 instead of a metal substrate 81. The insulating substrate 82 is a substrate made of an insulating material and has electrical insulating properties. The insulating substrate 82 is provided between the capacitor 32A and the bottom plate 13. The insulating substrate 82 has a surface surface 82a facing the capacitor 32A and a back surface 82b facing the bottom plate 13. The surface surface 82a is provided with a surface metal film 83 which is conductively bonded to the second metal film 43 of the capacitor 32A. The back surface 82b is provided with a back surface metal film 84 which is conductively bonded to the bottom surface 13a of the bottom plate 13. The surface metal film 83 and the back surface metal film 84 are connected by a plurality of vias 85 that penetrate the insulating substrate 82 in direction A3.

[0070] Therefore, the surface metal film 83 and the back metal film 84 are electrically connected to each other via a plurality of vias 85. In other words, the second metal film 43 of the capacitor 32A is electrically connected to the bottom surface 13a of the bottom plate 13 via the surface metal film 83, the back metal film 84, and the plurality of vias 85. Depending on the thickness of the insulating substrate 82, insulation The height of the capacitor 32A on the substrate and the height of the photodetector 16 on the capacitor 32A vary. Therefore, the thickness of the insulating substrate 82 may be set so that the height of the photodetector 16 matches the height of the TIA 25. The configuration for electrically connecting the surface metal film 83 and the back metal film 84 does not have to be multiple vias 85; any conductor capable of electrically connecting the surface metal film 83 and the back metal film 84 may be used. For example, the surface metal film 83 and the back metal film 84 may be electrically connected by a metal film provided on the side surface of the insulating substrate 82.

[0071] Even in this configuration, the same effects as in the above-described embodiment can be obtained. Furthermore, in the optical receiver 1B, the dielectric layer 41 A Because an insulating substrate 82 is provided between the bottom plate 13 and the dielectric layer 41 to increase capacitance AEven if the substrate is formed thinly, the presence of the insulating substrate 82 allows the height of the capacitor 32A and the photodetector 16 to be maintained at a high level. This keeps the height difference between the photodetector 16 and the TIA 25 small. As a result, the situation in which the wires 71, 72, and 73 between the photodetector 16 and the TIA 25 become long can be suppressed, and connection loss between the photodetector 16 and the TIA 25 can be reduced. Loss It can be suppressed.

[0072] <Variation 3> Figure 11 is a cross-sectional view showing the optical receiver 1C according to Modification 3. Similar to the optical receiver 1A according to Modification 1, the optical receiver 1C is equipped with a capacitor 32A instead of capacitor 32. However, in the optical receiver 1C, the capacitor 32A is mounted on the metal substrate 81 instead of the back surface 24b of the semiconductor layer 24. In this case, the second metal film 43 of the capacitor 32A is formed integrally with the metal substrate 81. Therefore, when manufacturing the optical receiver 1C, the dielectric layer 41A and the first metal film 42 are formed on the surface 81a of the metal substrate 81, and then the photodetector 16 is mounted on the first metal film 42. Even with this configuration, the same effects as the embodiments described above are achieved. Furthermore, in the optical receiver 1C, the step of mounting the capacitor 32A on the metal substrate 81 can be easily incorporated into the manufacturing process of the optical receiver 1C, thus suppressing the complexity of the manufacturing process of the optical receiver 1C.

[0073] <Torture> 4 > Figure 12 shows a modified example. 4 This shows the optical receiver 1D related to this. plane This is a diagram. Figure 13 is a graph showing the simulation results of the relationship between insertion loss (unit: dB) and signal frequency (unit: GHz) in the optical receiver 1D shown in Figure 12. In the optical receiver 1D, the semiconductor layer 24A has more vias 38A than the semiconductor layer 24 according to the embodiment described above. Although six vias 38A are shown in Figure 12, the number of vias 38A is not limited to the example shown in Figure 12. The number of vias 38A may be other numbers, such as two or four.

[0074] Multiple vias 38A are arranged, for example, in a region that overlaps with the cathode wiring pattern 28A of the first conductive film 28 in a plan view. In the example shown in Figure 12, multiple vias 38A are arranged so that, in a plan view, one via each overlaps with the first cathode pad 28b, the second cathode pad 28c, and the cathode patterns 28f, 28g, 28j, and 28k. Multiple vias 38A are arranged, for example, symmetrically with respect to the anode pattern 28h in direction A2. Multiple vias 38A may be arranged only in positions that overlap one via each with the first cathode pad 28b, the second cathode pad 28c, and the cathode patterns 28f, 28g in a plan view, or they may be arranged only in positions that overlap one via each with the cathode patterns 28f, 28g.

[0075] Even when the number of vias 38A is increased in this way, as shown in Figure 13, it can be seen that there is no resonant frequency in the high-frequency band of several tens of GHz or 100 GHz. Therefore, even in this configuration, the same effects as the embodiment described above are achieved. Furthermore, as described above, the parasitic capacitance C increases as the number of vias 38A increases. cq and inductance L v ia Since the resonant frequency is expected to increase, increasing the number of vias 38A will more reliably remove the opaque band caused by resonance from the signal frequency band.

[0076] The optical receiver according to this disclosure is not limited to the embodiments and their respective modifications described above, and various other modifications are possible. For example, the embodiments and their respective modifications described above may be combined with each other according to the necessary purpose and effect. The configuration of the optical receiver is not limited to the embodiments and their respective modifications described above, and can be changed as appropriate. For example, the first conductive film may have a configuration other than one in which a first cathode pad and a second cathode pad are provided on both sides of the anode pad. Multiple vias do not need to be arranged at equal intervals, and may be arranged at unequal intervals. The conductor that electrically connects the first conductive film and the second conductive film does not need to be multiple vias, and may be any other configuration as long as it is possible to electrically connect the first conductive film and the second conductive film. The photodetector may have a side metal film provided on the side surface of the semiconductor layer instead of multiple vias. In this case, the first conductive film and the second conductive film are electrically connected by the side metal film on the side surface of the semiconductor layer. [Explanation of Symbols]

[0077] 1, 1A, 1B, 1C, 1D… Optical receivers 11…Package 12…Side wall 12a, 12b...Side wall part 13...Bottom plate 13a…Bottom surface 14…Bush 15…Optical window 16…Photodetector 21…Optical axis converter 21a, 21b…Mirror 22...Optical demultiplexer 23... Lens 24,24A… Semiconductor layer 24R…Receiving area 24a…Surface 24b…Back side 24c...side 25…TIA 25a…Surface 25b…Back side 25c... Signal pad 25d…1st bias pad 25e...2nd bias pad 26…Feedthrough 26a... Terminal 27... Ground Layer 28…First conductive film 28A... Cathode wiring pattern 28a... Anode pad 28b...First cathode pad 28c...Second cathode pad 28f, 28g, 28j, 28k… Cathode patterns 28h... Anode pattern 29... Beer 32,32A…Capacitor 37…Second conductive film 38,38A… Via 41,41A...Dielectric layer 41a…Surface 41b…Back side 42...first metal film 43…Second metal film 71, 72, 73… wire 81…Metal substrate 81a... Surface 81b…Reverse side 82...Insulating substrate 82a…Surface 82b…Back side 83…Surface metal film 84…Metal film on the back 85... Beer C c ...capacitance C cq ...parasitic capacitance L via ,L wire ...inductance L…Signal light

Claims

1. A light-receiving element having a semiconductor layer in which a light-receiving region is provided, a first conductive film electrically connected to a cathode electrode provided on the main surface of the semiconductor layer, a second conductive film provided on the side of the semiconductor layer opposite to the main surface and electrically connected to the first conductive film via a conductor, and an anode pattern electrically connected to an anode electrode provided on the main surface of the semiconductor layer, A capacitor comprising a dielectric layer, and a first metal film and a second metal film provided sandwiched above and below the dielectric layer, A transimpedance having a first pad electrically connected to the first conductive film via a first wire, and a second pad electrically connected to the anode pattern via a second wire, A base plate on which the light-receiving element and the transimpedance are mounted on the main surface, Equipped with, The capacitance between the second conductive film and the main surface of the bottom plate is greater than the parasitic capacitance between the first conductive film and the second conductive film. An optical receiver wherein the inductance of the conductor is smaller than the inductance of the first wire.

2. The first conductive film is The anode pad is electrically connected to the anode electrode of the light-receiving element, The photodetector has a first cathode pad and a second cathode pad that are electrically connected to the cathode electrode of the photodetector, The optical receiver according to claim 1, wherein the first cathode pad and the second cathode pad are arranged on either side of the anode pad, respectively.

3. The dielectric layer has a surface facing the second conductive film and a back surface facing the main surface of the bottom plate, The surface of the dielectric layer is provided with the first metal film which is electrically connected to the second conductive film. The optical receiver according to claim 1, wherein the back surface of the dielectric layer is provided with the second metal film electrically connected to the main surface of the bottom plate.

4. The optical receiver according to claim 1, wherein the conductor extends between the first conductive film and the second conductive film so as to penetrate the light-receiving element and has vias connected to the first conductive film and the second conductive film.

5. The conductor has a plurality of the aforementioned euros, The optical receiver according to claim 4, wherein the plurality of vias are arranged at positions spaced apart from each other in a plan view of the light-receiving element.

6. The optical receiver according to any one of claims 1 to 5, further comprising a metal substrate provided between the dielectric layer and the bottom plate and electrically connected to the main surface of the bottom plate.

7. The dielectric layer and the bottom plate are further provided with an insulating substrate, The insulating substrate has a surface facing the dielectric layer and a back surface facing the main surface of the bottom plate, The surface of the insulating substrate is provided with a surface metal film that is electrically connected to the main surface of the bottom plate. The optical receiver according to any one of claims 1 to 5, wherein a back metal film is provided on the back surface of the insulating substrate, which is electrically connected to the front metal film via vias that penetrate the interior of the insulating substrate.

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