Power module circuit board

Abstract

To provide a substrate for a power module capable of further reducing damage applied to a power semiconductor element at the time of wire bonding.SOLUTION: A substrate for a power module comprises: an insulation board; a plurality of surface patterns disposed on a surface of the insulation board; a power semiconductor element connected to one surface pattern out of the plurality of surface patterns; an electrode part disposed on an upper surface of the power semiconductor element; and bonding wires that connect the other surface patterns different from the one surface pattern out of the plurality of surface patterns to the electrode part. The electrode part has a contact layer formed of a metal and disposed on an upper surface, a protective layer laminated on the contact layer, and a connection layer formed of a metal and laminated on the protective layer in a state of being connected to the bonding wires. The protective layer contains a conductive ceramic with a hardness higher than that of the contact layer and the connection layer.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] This disclosure relates to a substrate for a power module.

Background Art

[0002] For example, Patent Document 1 discloses a power semiconductor device in which the surface electrode of a power semiconductor element is composed of a plurality of different metal layers. The layer structure composed of a plurality of metal layers is formed from an Al layer, a Cu layer formed on this Al layer and having a Vickers hardness of 200 to 350 Hv, and a Cu layer formed on this Cu layer and having a Vickers hardness of 70 to 150 Hv. By adopting such a layer structure, the damage applied to the power semiconductor element when bonding with a Cu wire is reduced.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in recent years, in the field of power semiconductor elements, there has been an increasing trend towards higher voltage, larger current, higher frequency, and faster switching of power semiconductor elements in order to improve added value. Along with this, for example, the number of bonding wires connected to the electrodes of a power semiconductor element by wire bonding may increase. Therefore, there is a need for a technology that further reduces the damage applied to the power semiconductor element during wire bonding.

[0005] This disclosure has been made to solve the above problems, and an object thereof is to provide a substrate for a power module that can further reduce the damage applied to a power semiconductor element during wire bonding.

Means for Solving the Problems

発明が解決しようとする課題

Problems to be Solved by the Invention

[0006] To solve the above problems, the power module substrate according to the present disclosure comprises an insulating board, a plurality of surface patterns arranged on the surface of the insulating board, a power semiconductor element connected to one of the plurality of surface patterns, an electrode portion arranged on the upper surface of the power semiconductor element, another surface pattern from the plurality of surface patterns different from the one surface pattern, and a bonding wire connecting the electrode portion, wherein the electrode portion is made of metal and has a contact layer arranged on the upper surface, a protective layer laminated on the contact layer, and a connecting layer made of metal and laminated on the protective layer while connected to the bonding wire, and the protective layer includes a conductive ceramic having a hardness higher than that of the contact layer and the connecting layer. [Effects of the Invention]

[0007] According to this disclosure, it is possible to provide a power module substrate that can further reduce the damage applied to power semiconductor elements during wire bonding. [Brief explanation of the drawing]

[0008] [Figure 1] This is a perspective view showing the schematic configuration of a power conversion device according to the first embodiment of this disclosure. [Figure 2] This figure shows the power module according to the first embodiment of this disclosure as viewed from the direction of line II-II shown in Figure 1. [Figure 3] This is a cross-sectional view taken along the line III-III shown in Figure 2. [Figure 4] Figure 3 is an enlarged view of the main part, showing the layer structure of the electrode section. [Figure 5] This figure shows the layer structure of the electrode portion when the main part of the cross-sectional view of the power module according to the second embodiment of this disclosure is magnified, and corresponds to the portion shown in Figure 4. [Figure 6]This figure shows the layer structure of the electrode portion when the main part of the cross-sectional view of the power module according to the third embodiment of this disclosure is magnified, and corresponds to the portion shown in Figure 4. [Figure 7A] The results of Example 1 are shown. [Figure 7B] The results of Example 1 are shown. [Figure 8] The results of Example 2 are shown. [Figure 9] The results of Example 3 are shown. [Modes for carrying out the invention]

[0009] The following describes embodiments for implementing a power conversion device equipped with a power module substrate according to this disclosure, with reference to the attached drawings.

[0010] <First Embodiment> A power converter is a device that converts direct current power into three-phase alternating current power, etc. Examples of power converters in this embodiment include inverters used in power grids such as those in power plants, and inverters used to drive electric motors in electric vehicles, etc.

[0011] As shown in Figure 1, the power converter 100 comprises a casing 1, an external input conductor 2, a capacitor 3, a power conversion unit 4, and a cooler 5. In Figure 1, the casing 1 and the cooler 5 are indicated by dashed lines.

[0012] [Casing] The casing 1 forms the outer shell of the power converter 100. In this embodiment, the casing 1 is made of a metal such as aluminum (Al) or a synthetic resin. In this embodiment, the casing 1 is made of aluminum and has a rectangular parallelepiped shape. The outer surface of the casing 1 has two sides that are arranged back to back.

[0013] Hereinafter, for convenience of explanation, among these two sides, the side facing one side is referred to as the "input-side surface 1a", and the side facing the other side is referred to as the "output-side surface 1b". An external input conductor 2 for inputting DC power is drawn out from the input-side surface 1a.

[0014] [External input conductor] The external input conductor 2 is a pair of electrical conductors (bus bars) that supply the DC power supplied from an external power system of the power conversion device 100 or a DC power source such as a battery to the capacitor 3. The external input conductor 2 in the present embodiment is formed of a metal containing copper (Cu) or the like. One end of the external input conductor 2 is connected to the capacitor 3, and the other end of the external input conductor 2 extends in a direction intersecting the input-side surface 1a of the casing 1, for example.

[0015] [Capacitor] The capacitor 3 is a smoothing capacitor that stores the charges input from the external input conductor 2 and suppresses voltage fluctuations accompanying power conversion. The DC voltage that has been ripple-suppressed and smoothed by passing through the capacitor 3 is supplied (applied) to the power conversion unit 4.

[0016] [Power conversion unit] The power conversion unit 4 converts the voltage input from the capacitor 3. The power conversion unit 4 is housed in the casing 1. The power conversion unit 4 in the present embodiment has three power modules 10 that are respectively in charge of the outputs for the U phase, V phase, and W phase in order to output three-phase AC power. Therefore, the power conversion device 100 in the present embodiment is a three-phase inverter including three power modules 10.

[0017] [Power module] The power module 10 is a device that converts and outputs the input power. As shown in FIGS. 2 and 3, the power module 10 includes a base plate 11, a substrate for power module 12, a main terminal portion 13, an output terminal portion 14, a reinforcing portion 15, and a sealing portion 16. <000009​​​ The base plate 11 is a flat plate-shaped member. The base plate 11 has a first surface 11a and a second surface 11b located on the back side of the first surface 11a. That is, the first surface 11a and the second surface 11b of the base plate 11 are parallel to each other and are back to back. The second surface 11b of the base plate 11 is fixed to the cooler 5 via a bonding material or the like (not shown). In this embodiment, copper is used for the base plate 11, for example. However, a metal such as aluminum may be used for the base plate 11.

[0019] (Power module circuit board) The power module substrate 12 includes an insulating board 20, a surface pattern 21, a power semiconductor element 22, an electrode portion 23, bonding wires 27, and a back surface pattern 28.

[0020] (Insulating board) The insulating plate 20 is flat. The insulating plate 20 has a surface 20a and a back surface 20b located on the back side of the surface 20a. The surface 20a and the back surface 20b of the insulating plate 20 are parallel to each other and are back to back.

[0021] In this embodiment, the insulating plate 20 is formed of an insulating material such as ceramic. In addition to ceramic, other materials such as paper phenol, paper epoxy, glass composite, glass epoxy, glass polyimide, and fluororesin can be used as the insulating material for forming the insulating plate 20.

[0022] (Surface pattern) The surface pattern 21 is a planar pattern of copper foil (Cu) or the like formed on the surface 20a of the insulating plate 20. The surface pattern 21 is formed, for example, by fixing it to the surface 20a of the insulating plate 20 by bonding or the like, and then etching or the like.

[0023] Multiple surface patterns 21 are arranged on the surface 20a of the insulating plate 20. These multiple surface patterns 21 are arranged adjacent to each other with gaps in between in the direction in which the insulating plate 20 expands. In this embodiment, the case in which three surface patterns 21 are arranged on the surface 20a of the insulating plate 20 will be described as an example. Hereinafter, for the sake of explanation, these three surface patterns 21 will be referred to as the first surface pattern 21a, the second surface pattern 21b, and the third surface pattern 21c.

[0024] The first surface pattern 21a and the second surface pattern 21b are patterns for exchanging DC power input and output with the capacitor 3, and correspond to the inlet or outlet portion of the loop between P and N formed on the surface pattern 21.

[0025] In this embodiment, the first surface pattern 21a and the second surface pattern 21b are connected to a main terminal section 13 that connects to the capacitor 3. The third surface pattern 21c is connected to an output terminal section 14 for outputting the alternating current converted by the power semiconductor element 22 to a load (not shown) located outside the power converter 100.

[0026] (Power semiconductor element) The power semiconductor element 22 is a circuit element that converts power by switching voltage and current on and off. The power semiconductor element 22 is, for example, a switching element such as an IGBT or a MOSFET. The power semiconductor element 22 is formed from, for example, a Si-based single crystal or a SiC-based single crystal which has higher hardness than a Si-based single crystal.

[0027] In this embodiment, as an example, a case is shown in which MOSFETs are used as power semiconductors, and four power semiconductor elements 22 are connected to the surface pattern 21 of the power module substrate 12. Note that if IGBTs are used as power semiconductor elements 22, it is necessary to arrange diodes in parallel that allow current to flow in the opposite direction to the IGBTs.

[0028] In this embodiment, the four power semiconductor elements 22 are composed of two first power semiconductor elements 22a and two second power semiconductor elements 22b. The first power semiconductor elements 22a are connected to the first surface pattern 21a. The second power semiconductor elements 22b are connected to the third surface pattern 21c.

[0029] When the power semiconductor element 22 is a MOSFET, the power semiconductor element 22 has a lower surface 22d (see Figure 3) on which an input terminal corresponding to the drain (not shown) is formed, an upper surface 22u on which an output terminal corresponding to the source (not shown) is formed, and a gate (not shown) corresponding to a control signal input terminal for controlling the switching of the power semiconductor element 22.

[0030] The lower surface 22d of the power semiconductor element 22 is electrically connected to the surface pattern 21 via a bonding material S. The lower surface 22d of the first power semiconductor element 22a is connected to the first surface pattern 21a. The lower surface 22d of the second power semiconductor element 22b is connected to the third surface pattern 21c. In this specification, the bonding material S can be, for example, solder or sintered material (metal powder, etc.).

[0031] A control signal generated by a gate drive substrate (not shown) located outside the power module substrate 12 is input to the power semiconductor element 22 through the gate. The power semiconductor element 22 switches according to this control signal. If the power semiconductor element 22 is an IGBT, it has a lower surface 22d corresponding to the collector, an upper surface 22u corresponding to the emitter, and a gate corresponding to the control signal input terminal.

[0032] (electrode part) The electrode portion 23 is located on the upper surface 22u of the power semiconductor element 22. The electrode portion 23 corresponds to the electrode portion of the power semiconductor element 22. In this embodiment, the electrode portion 23 has a three-layer structure. As shown in Figure 4, the electrode portion 23 has a contact layer 24, a protective layer 25, and a connecting layer 26.

[0033] The contact layer 24 is located on the upper surface 22u and is connected to the output terminal formed on the upper surface 22u in an integrated manner. The contact layer 24 is made of metal. In this embodiment, any one of Ni, Al, or Cr can be used as the metal forming the contact layer 24. The thickness L1 of the contact layer 24 is 0.05 to 0.5 μm. The contact layer 24 is formed on the upper surface 22u of the power semiconductor element 22, for example, by sputtering.

[0034] The protective layer 25 is a conductive material laminated on the contact layer 24. That is, the protective layer 25 is formed on the contact layer 24 in an integral state with the contact layer 24. The protective layer 25 is made of a conductive ceramic. In this embodiment, the conductive ceramic forming the protective layer 25 can be any one of the following: TiB2 (titanium diboride), ZrB2 (zirconium diboride), HfB2 (hafnium diboride), TiSi2 (titanium disilicate), and WSi2 (tungsten disilicate). The thickness L2 of the protective layer 25 is set to 0.5 to 2 μm. The protective layer 25 is formed on the contact layer 24, for example, by a sputtering method.

[0035] The connecting layer 26 is laminated on the protective layer 25. That is, the connecting layer 26 is formed on the protective layer 25 in an integral state with the protective layer 25. The connecting layer 26 is made of metal. In this embodiment, copper or an alloy containing copper can be used as the metal forming the connecting layer 26. The thickness L3 of the connecting layer 26 is 10 to 20 μm. The connecting layer 26 is formed on the protective layer 25 by, for example, a sputtering method.

[0036] Here, the hardness of the conductive ceramic forming the protective layer 25 is higher than the hardness of the metal forming the contact layer 24 and the connecting layer 26. Specifically, the conductive ceramic forming the protective layer 25 has a Vickers hardness more than 10 times greater than the metal forming the contact layer 24 and the connecting layer 26. Furthermore, the thermal conductivity of the conductive ceramic forming the protective layer 25 is lower than the thermal conductivity of the metal forming the contact layer 24 and the connecting layer 26.

[0037] The Vickers hardness of TiB2 is, for example, 32-34 GPa. ZrB2 has a Vickers hardness of, for example, 21-23 GPa. HfB2 has a Vickers hardness of, for example, 27-29 GPa. TiSi2 has a Vickers hardness of, for example, 9-11 GPa. WSi2 also has a Vickers hardness of, for example, 9-11 GPa.

[0038] (Bonding wire) As shown in Figures 2 to 4, the bonding wire 27 is a conductor that connects the surface pattern 21 and the electrode portion 23 located on the upper surface 22u of the power semiconductor element 22. In this embodiment, the bonding wire 27 is made of a metal including copper, and has a diameter of, for example, 200 to 400 μm.

[0039] One end of the bonding wire 27 is connected to the connecting layer 26 in the electrode portion 23. The other end of the bonding wire 27 is connected to the surface pattern 21. In this embodiment, multiple bonding wires 27 connect the connecting layer 26 and the surface pattern 21.

[0040] Specifically, as shown in Figure 2, six bonding wires 27 connect the connection layer 26 of the electrode portion 23 located on the upper surface 22u of the first power semiconductor element 22a to the third surface pattern 21c. Also, as shown in Figures 2 to 4, six bonding wires 27 connect the connection layer 26 of the electrode portion 23 located on the upper surface 22u of the second power semiconductor element 22b to the second surface pattern 21b. In other words, the surface patterns 21 located on the surface 20a of the insulating plate 20 are electrically connected to each other by the bonding wires 27.

[0041] One end and the other end of the bonding wire 27 are integrally connected to the connecting layer 26 and the surface pattern 21 of the electrode portion 23 by wire bonding, which involves applying ultrasonic waves or the like from the outside.

[0042] DC power is input to the first power semiconductor element 22a through the first surface pattern 21a, and DC power is input to the second power semiconductor element 22b through the second surface pattern 21b and the bonding wire 27 connecting the second surface pattern 21b and the second power semiconductor element 22b. As the first power semiconductor element 22a and the second power semiconductor element 22b perform switching operations, the above DC power is converted to AC power and output to the third surface pattern 21c through the electrode portion 23 and the bonding wire 27.

[0043] (Reverse side pattern) The back surface pattern 28 is a planar pattern of copper foil or the like formed on the back surface 20b of the insulating plate 20. The back surface pattern 28 is fixed to the center of the first surface 11a of the base plate 11 via a bonding material S. The back surface pattern 28 is formed, for example, by fixing it to the back surface 20b of the insulating plate 20 by bonding or the like, and then etching or the like.

[0044] (Main terminal part) The main terminal section 13 is an electrical conductor (busbar) that exchanges DC power between the capacitor 3 and the power module substrate 12. The main terminal section 13 is made of a metal including copper. The main terminal section 13 has a P terminal 13p as the positive electrode and an N terminal 13n as the negative electrode.

[0045] These P terminals 13p and N terminals 13n are arranged side by side with a gap G representing a spatial distance (insulation distance). The P terminal 13p connects the positive electrode (not shown) of the capacitor 3 to the first surface pattern 21a of the power module substrate 12. The N terminal 13n connects the negative electrode (not shown) of the capacitor 3 to the second surface pattern 21b of the power module substrate 12.

[0046] (Output terminal section) The output terminal section 14 is an electrical conductor (busbar) for outputting AC power, which has been converted by the power semiconductor element 22, to the outside of the power converter 100. The output terminal section 14 is made of a metal including copper. One end of the output terminal section 14 is connected to the third surface pattern 21c on the power module substrate 12. As shown in Figure 1, the other end of the output terminal section 14 extends outward, for example, beyond the output side surface 1b of the casing 1. Power output wiring (not shown) connected to a load (AC rotating electric machine) such as a motor is connected to the other end of the output terminal section 14.

[0047] (Reinforcement section) As shown in Figures 2 and 3, the reinforcing portion 15 is a member that mechanically reinforces the main terminal portion 13 and the output terminal portion 14 while being fixed to the first surface 11a of the base plate 11. The reinforcing portion 15 is formed of, for example, a synthetic resin material (insulating material). In this embodiment, for example, PPS (polyphenylene sulfide) can be used as the material forming the reinforcing portion 15. However, synthetic resin materials other than PPS may also be used for the reinforcing portion 15. The reinforcing portion 15 is fixed to the first surface 11a of the base plate 11 by, for example, an adhesive.

[0048] The reinforcing portion 15 surrounds the power module substrate 12 from the outside, covering the P terminal 13p and N terminal 13n of the main terminal portion 13, as well as the output terminal portion 14. The reinforcing portion 15 forms a case that surrounds the power module substrate 12 from all sides in a direction along the surface 20a of the base plate 11. Therefore, the reinforcing portion 15 defines a space in which the power module substrate 12 is housed together with the base plate 11. In this embodiment, for the sake of explanation, this space in which the power module substrate 12 is housed is referred to as the "potting space Rp".

[0049] (Sealing part) The sealing portion 16 is a sealing member located within the potting space Rp. In the drawing, the sealing portion 16 is shown with hatching for space limitations. Liquid potting material is filled into the potting space Rp from the outside (potting) to seal the components exposed within the potting space Rp. The sealing portion 16 is formed when the potting material filled into the potting space Rp is subjected to a predetermined temperature and time, causing the potting material to harden. The sealing portion 16 formed by the hardening of the potting material electrically insulates the components within the potting space Rp, and the components from the space outside the power module 10.

[0050] In this embodiment, the potting material can be, for example, silicone gel or epoxy resin. Note that synthetic resins other than silicone gel or epoxy resin may also be used as the potting material. The sealing portion 16 within the potting space Rp is arranged to cover the surfaces of the power module substrate 12, the main terminal portion 13, and the output terminal portion 14, respectively.

[0051] [Cooler] As shown in Figure 1, the cooler 5 is a device that primarily cools the power module 10 of the power conversion unit 4. The cooler 5 is installed stacked on the casing 1 and is fixed and integrated with the casing 1. As shown in Figure 3, the cooler 5 has a base 51 and heat dissipation fins 52. In Figure 3, the base 51 and heat dissipation fins 52 are shown by dotted lines.

[0052] The base portion 51 is plate-shaped. The base portion 51 has a bonding surface 51a that is bonded to the second surface 11b of the base plate 11 of the power module 10 via a bonding material S, and a heat dissipation surface 51b that faces the opposite side from the bonding surface 51a.

[0053] The joint surface 51a and the heat dissipation surface 51b are facing each other, parallel to one another. The heat dissipation fins 52 are columnar members arranged in multiple locations on the heat dissipation surface 51b of the base 51. Each heat dissipation fin 52 protrudes from the heat dissipation surface 51b toward the side opposite to the power module 10, with the base 51 as the center.

[0054] A liquid coolant W, such as water, is introduced into the cooler 5 from an external source. The heat dissipation surface 51b of the base 51 and the heat dissipation fins 52 are cooled by contact with the liquid coolant W introduced from the external source. The liquid coolant W is heated by heat exchange with the heat conducted from the power module 10 to the base 51 and heat dissipation fins 52, and at the same time cools the power module 10.

[0055] (Effects and Benefits) When the bonding wire 27 is connected to the electrode portion 23 by ultrasonic wire bonding, the heat and pressure generated by the ultrasonic waves are directed from the electrode portion 23 to the power semiconductor element 22.

[0056] In the configuration of the above embodiment, a protective layer 25 made of conductive ceramic, whose hardness is higher than that of the metal forming the contact layer 24 and the connecting layer 26, is interposed between the contact layer 24 and the connecting layer 26. As a result, when pressure generated by ultrasound is applied to the connecting layer 26 of the electrode portion 23, this pressure is absorbed by the protective layer 25. In other words, the protective layer 25 suppresses the transmission of pressure to the contact layer 24 during wire bonding.

[0057] Furthermore, since the thermal conductivity of the protective layer 25 is lower than that of the contact layer 24 and the connecting layer 26, heat conduction from the connecting layer 26 to the contact layer 24 can be suppressed more effectively compared to, for example, the case where the protective layer 25 is made of metal.

[0058] Therefore, the damage inflicted on the power semiconductor element 22 during wire bonding is reduced. As a result, it is possible to suppress the occurrence of abnormalities such as cracks and fissures in the power semiconductor element 22.

[0059] Furthermore, in the above configuration, the contact layer 24 is formed with a thickness L1 of 0.05 to 0.5 μm, and the protective layer 25 is formed with a thickness L2 of 0.5 to 2 μm. This ensures conductivity between the power semiconductor element 22 and the bonding wire 27 while suppressing deformation such as strain and bending in each layer.

[0060] <Second Embodiment> Next, a second embodiment of the power converter 100 according to this disclosure will be described with reference to Figure 5. In the second embodiment described below, components common to the first embodiment described above are denoted by the same reference numerals in the figure and their descriptions are omitted. In the second embodiment, the configuration of the electrode portion 23 on the power module substrate 12 differs from the configuration of the electrode portion 23 described in the first embodiment.

[0061] (electrode part) The electrode portion 23 in this embodiment has a five-layer structure. The electrode portion 23 has a contact layer 24, a protective layer 25a formed in three layers, and a connecting layer 26. The protective layer 25a has a first metal layer 251, a main body layer 252, and a second metal layer 253.

[0062] The first metal layer 251 is formed on the contact layer 24 in an integral state with the contact layer 24. The first metal layer 251 is made of a metal containing Ti (titanium). The thickness L2a of the first metal layer 251 is set to 0.1 to 0.5 μm. The first metal layer 251 is formed on the contact layer 24 by, for example, a sputtering method.

[0063] Here, since the first metal layer 251 is formed of metal, the bonding force between this first metal layer 251 and the contact layer 24 is greater than the bonding force between the main layer 252 and the contact layer 24 when the first metal layer 251 is not present. Furthermore, since the first metal layer 251 is formed of a metal containing Ti, the bonding force between this first metal layer 251 and the main layer 252 is greater than the bonding force between, for example, a metal other than Ti and the main layer 252. In other words, the combination of the first metal layer 251 and the main layer 252 has a higher affinity than the combination of a metal other than Ti and the main layer 252.

[0064] The main body layer 252 is laminated on the first metal layer 251. That is, the main body layer 252 is formed on the first metal layer 251 in an integral state with the first metal layer 251. The main body layer 252 is made of conductive ceramic. In this embodiment, any one of TiB2, ZrB2, HfB2, TiSi2, and WSi2 can be used as the conductive ceramic forming the main body layer 252. The thickness L2b of the main body layer 252 is set to 0.5 to 2 μm. The main body layer 252 is formed on the first metal layer 251 by, for example, a sputtering method.

[0065] The second metal layer 253 is laminated on the main layer 252. That is, the second metal layer 253 is formed on the main layer 252 in an integral state with the main layer 252. The second metal layer 253 is made of a metal containing Ti. The thickness L2c of the second metal layer 253 is set to 0.1 to 0.5 μm. The second metal layer 253 is formed on the main layer 252 by, for example, a sputtering method.

[0066] Here, since the second metal layer 253 is formed of metal, the bonding force between this second metal layer 253 and the connecting layer 26 is greater than the bonding force between the main layer 252 and the connecting layer 26 when the second metal layer 253 is not present. Furthermore, since the second metal layer 253 is formed of a metal containing Ti, the bonding force between this second metal layer 253 and the main layer 252 is greater than the bonding force between, for example, a metal other than Ti and the main layer 252. In other words, the combination of the second metal layer 253 and the main layer 252 has a higher affinity than the combination of a metal other than Ti and the main layer 252.

[0067] The connecting layer 26 is laminated on the second metal layer 253. That is, the connecting layer 26 is formed on the second metal layer 253 in an integral state with the second metal layer 253.

[0068] (Effects and Benefits) In the configuration of the second embodiment, when pressure generated by ultrasound is applied to the connecting layer 26 of the electrode portion 23, this pressure is absorbed by the second metal layer 253. That is, the second metal layer 253 suppresses the transmission of pressure to the main body layer 252 during wire bonding. Furthermore, the pressure transmitted from the main body layer 252 toward the power semiconductor element 22 is absorbed by the first metal layer 251. That is, the first metal layer 251 suppresses the transmission of pressure to the power semiconductor element 22 via the contact layer 24 during wire bonding.

[0069] Therefore, damage to the main body layer 252 and the power semiconductor element 22 during wire bonding can be further reduced. As a result, abnormalities such as peeling and cracking in the electrode portion 23 can be suppressed, and abnormalities such as cracks and fissures in the power semiconductor element 22 can be suppressed.

[0070] Furthermore, in the configuration of the second embodiment, the first metal layer 251 and the second metal layer 253 are formed with thicknesses L2a and L2c of 0.1 to 0.5 μm, and the main body layer 252 is formed with a thickness L2b of 0.5 to 2 μm. This makes it possible to ensure conductivity between the power semiconductor element 22 and the bonding wire 27 while suppressing deformation such as strain and bending in each layer.

[0071] <Third Embodiment> Next, a third embodiment of the power converter 100 according to this disclosure will be described with reference to Figure 6. In the third embodiment described below, components common to the first embodiment described above are denoted by the same reference numerals in the figure and their descriptions are omitted. In the third embodiment, the configuration of the electrode portion 23 on the power module substrate 12 differs from the configuration of the electrode portion 23 described in the first embodiment.

[0072] (electrode part) The electrode portion 23 in this embodiment has a five-layer structure. The electrode portion 23 has a contact layer 24, a protective layer 25b formed in three layers, and a connecting layer 26. The protective layer 25b has a first protective layer 254, a metal layer 255, and a second protective layer 256.

[0073] The first protective layer 254 is a conductive material laminated on the contact layer 24. That is, the first protective layer 254 is formed on the contact layer 24 in an integral state with the contact layer 24. The first protective layer 254 is made of a conductive ceramic. In this embodiment, any one of TiB2, ZrB2, HfB2, TiSi2, and WSi2 can be used as the conductive ceramic forming the first protective layer 254. The thickness L2d of the first protective layer 254 is set to 0.5 to 2 μm. The first protective layer 254 is formed on the contact layer 24 by, for example, a sputtering method.

[0074] The metal layer 255 is laminated on the first protective layer 254. That is, the metal layer 255 is formed on the first protective layer 254 in an integral state with the first protective layer 254. The metal layer 255 is made of a metal containing Ti. The thickness L2e of the metal layer 255 is set to 0.1 to 0.5 μm. The metal layer 255 is formed on the first protective layer 254 by, for example, a sputtering method.

[0075] The second protective layer 256 is a conductive material laminated on the metal layer 255. That is, the second protective layer 256 is formed on the metal layer 255 in an integral state with the metal layer 255. The second protective layer 256 is made of a conductive ceramic. In this embodiment, any one of TiB2, ZrB2, HfB2, TiSi2, and WSi2 can be used as the conductive ceramic forming the second protective layer 256. The thickness L2f of the second protective layer 256 is set to 0.5 to 2 μm. The second protective layer 256 is formed on the metal layer 255 by, for example, a sputtering method.

[0076] The connecting layer 26 is laminated on the second protective layer 256. That is, the connecting layer 26 is formed on the second protective layer 256 in an integral state with the second protective layer 256.

[0077] (Effects and Benefits) According to the configuration of the third embodiment, when pressure generated by ultrasound is applied to the connecting layer 26 of the electrode portion 23, this pressure is absorbed by the second protective layer 256 and the metal layer 255. In other words, the second protective layer 256 and the metal layer 255 suppress the transmission of pressure to the first protective layer 254 during wire bonding.

[0078] Furthermore, the first protective layer 254 and the second protective layer 256, both made of conductive ceramic, are laminated with a metal layer 255, made of a metal containing Ti, interposed between them. This allows for a greater increase in the thickness of the protective layer 25b while suppressing deformation such as strain and bending in the protective layer 25b, compared to, for example, a single layer. Therefore, damage to the power semiconductor element 22 during wire bonding can be further reduced.

[0079] (Other embodiments) Although embodiments of this disclosure have been described in detail above with reference to the drawings, the specific configuration is not limited to that of the embodiments, and additions, omissions, substitutions, and other modifications to the configuration are possible without departing from the gist of this disclosure.

[0080] The results of evaluation experiments (Examples 1-3) to facilitate understanding of the effects described in each embodiment are shown as examples in Figures 7A to 9. Figures 7A to 9 show whether or not cracks or fissures (microcracks) occur on the surface of the power semiconductor element 22 when the output intensity of the ultrasonic used during wire bonding is changed in eight steps from 10 to 100. "10" in the ultrasonic output intensity indicates a predetermined output intensity. In the manufacturing of the power module 10 in the above embodiment, for example, "30" is used for the ultrasonic output intensity. The presence or absence of cracks or fissures on the surface of the power semiconductor element 22 is determined by observing the surface of the power semiconductor element 22 using, for example, a scanning electron microscope (SEM), and by comparing it with, for example, a limit sample.

[0081] In this evaluation experiment, the bonding wire 27 is made of copper and has a diameter of 300 μm. The contact layer 24 is made of aluminum and has a thickness L1 of 0.1 μm. The connecting layer 26 is made of copper and has a thickness L3 of 15 μm. Note that the diameter of the bonding wire 27, the thickness L1 of the contact layer 24, and the thickness L3 of the connecting layer 26 shown here are actual values, and slight manufacturing errors and design tolerances are acceptable.

[0082] "Example 1" Figure 7A shows the case where the power semiconductor element 22 is formed from a Si-based single crystal. Rows (i) to (v) in "The Invention" in Figure 7A show the results after wire bonding with the configuration described in the first embodiment, while the rows in "Comparative Example" in Figure 7A show the results after wire bonding with a configuration in which conductive ceramic is not used for the protective layer 25. In "The Invention" in Figure 7A, the protective layer 25 is formed from TiB2, ZrB2, HfB2, TiSi2, and WSi2, respectively, and in all cases is formed with a thickness L2 of 1.0 μm. In "Comparative Example" in Figure 7A, the protective layer 25 is formed from a metal containing Ta (tantalum) and is formed with a thickness of 1.0 μm. Note that the thickness L2 of the protective layer 25 shown here refers to an actual value, and slight manufacturing errors and design tolerances are permissible.

[0083] Figure 7B shows the case where the power semiconductor element 22 is formed from a SiC-based single crystal. The row labeled "Invention" in Figure 7B shows the result after wire bonding with the configuration described in the first embodiment, and the row labeled "Comparative Example" in Figure 7B shows the result after wire bonding with a configuration in which conductive ceramic is not used for the protective layer 25. In "Invention" in Figure 7B, the protective layer 25 is formed from TiB2 and has a thickness L2 of 1.0 μm. In "Comparative Example" in Figure 7B, the protective layer 25 is formed from a metal containing Ta (tantalum) and has a thickness of 1.0 μm. Note that the thickness L2 of the protective layer 25 shown here refers to an actual value, and slight manufacturing errors and design tolerances are acceptable.

[0084] Figures 7A and 7B, which show the effects of the configuration of the first embodiment, demonstrate that the occurrence of cracks and fissures in the power semiconductor element 22 is suppressed compared to the "comparative example".

[0085] Example 2 Figure 8 shows the case where the power semiconductor element 22 is formed from a Si-based single crystal. Rows (i) and (iii) in "The Invention" in Figure 8 show the results after wire bonding with the configuration described in the second embodiment. The first metal layer 251 and the second metal layer 253 in "The Invention" (i) and (iii) in Figure 8 are formed from Ti and are both formed with thicknesses L2a and L2c of 0.2 μm, respectively. The main body layer 252 in "The Invention" (i) in Figure 8 is formed from HfB2 and has a thickness L2b of 1.0 μm. The main body layer 252 in "The Invention" (iii) in Figure 8 is formed from TiSi2 and has a thickness L2b of 1.0 μm. Note that the thicknesses L2a of the first metal layer 251, L2c of the second metal layer 253, and L2b of the main body layer 252 shown here refer to actual values, and slight manufacturing errors and design tolerances are permissible. Row (ii) in "The Invention" in Figure 8 corresponds to the result shown in row (iii) in "The Invention" in Figure 7A. Row (iv) in "The Invention" in Figure 8 corresponds to the result shown in row (iv) in "The Invention" in Figure 7A. In this case, "Main body layer" in Figure 8 should be read as "Protective layer" in Figure 7A.

[0086] Figure 8, which shows the effects of the configuration of the second embodiment, shows that the occurrence of cracks and fissures in the power semiconductor element 22 is suppressed compared to the "comparative example".

[0087] "Example 3" Figure 9 shows the case where the power semiconductor element 22 is formed from a Si-based single crystal. Rows (i) and (iii) in "The Invention" in Figure 9 show the results after wire bonding with the configuration described in the third embodiment. In "The Invention" (i) in Figure 9, the first protective layer 254 and the second protective layer 256 are formed from TiB2 and are both formed with thicknesses L2d and L2f of 1.0 μm. In "The Invention" (iii) in Figure 9, the first protective layer 254 and the second protective layer 256 are formed from ZrB2 and are both formed with thicknesses L2d and L2f of 1.0 μm. In "The Invention" (i) and (iii) in Figure 9, the metal layer 255 is formed from Ti and is formed with a thickness L2e of 0.2 μm. Note that the thickness L2d of the first protective layer 254, the thickness L2f of the second protective layer 256, and the thickness L2e of the metal layer 255 shown here refer to actual values, and slight manufacturing errors and design tolerances are permitted. Row (ii) in "The Invention" in Figure 9 corresponds to the result shown in row (i) in "The Invention" in Figure 7A. Row (iv) in "The Invention" in Figure 9 corresponds to the result shown in row (ii) in "The Invention" in Figure 7A. In this case, "First protective layer" in Figure 9 should be read as "Protective layer" in Figure 7A.

[0088] Figure 9, which shows the effects of the configuration of the third embodiment, shows that the occurrence of cracks and fissures in the power semiconductor element 22 is suppressed compared to the "comparative example".

[0089] Furthermore, although an inverter was used as an example of the power conversion device 100 in the embodiment, the power conversion device 100 is not limited to an inverter. The power conversion device 100 may be a device that performs power conversion using a power semiconductor element 22, such as a converter or a combination of an inverter and a converter. If the power conversion device 100 is a converter, it is sufficient that an AC voltage is input to the output terminal 14 from an external input power source (not shown), the power semiconductor element 22 converts this AC voltage to a DC voltage, and the DC voltage from the power semiconductor element 22 is output from the input terminal.

[0090] <Note> The power module substrate described in the embodiment can be understood, for example, as follows:

[0091] (1) The power module substrate 12 according to the first embodiment comprises an insulating board 20, a plurality of surface patterns 21 arranged on the surface 20a of the insulating board 20, a power semiconductor element 22 connected to one of the plurality of surface patterns 21, an electrode portion 23 arranged on the upper surface 22u of the power semiconductor element 22, another surface pattern 21 from the plurality of surface patterns 21 that is different from the one surface pattern 21, and a bonding wire 27 connecting the electrode portion 23, wherein the electrode portion 23 is made of metal and has a contact layer 24 arranged on the upper surface 22u, protective layers 25, 25a, 25b laminated on the contact layer 24, and a connecting layer 26 made of metal and laminated on the protective layers 25, 25a, 25b in a state connected to the bonding wire 27, wherein the protective layers 25, 25a, 25b include conductive ceramic having a hardness higher than that of the contact layer 24 and the connecting layer 26.

[0092] As a result, when ultrasonic waves are applied to the electrode portion 23 during wire bonding, and the pressure associated with the ultrasonic waves is applied to the connecting layer 26 of the electrode portion 23, this pressure is absorbed by the protective layers 25, 25a, and 25b of the electrode portion 23. Furthermore, compared to the case where the protective layers 25, 25a, and 25b are formed of, for example, metal, heat conduction from the connecting layer 26 to the contact layer 24 can be suppressed.

[0093] (2) The power module substrate 12 according to the second embodiment is the power module substrate 12 of (1), wherein the protective layer 25a may have a first metal layer 251 formed of a metal containing Ti and integrally laminated on the contact layer 24, a main body layer 252 formed of a conductive ceramic and integrally laminated on the first metal layer 251, and a second metal layer 253 formed of a metal containing Ti and integrally arranged with the main body layer 252 and the connection layer 26 between the main body layer 252 and the connection layer 26.

[0094] As a result, the pressure generated by the ultrasonic waves during wire bonding is absorbed by the second metal layer 253 in the protective layer 25a. In addition, the pressure transmitted from the main layer 252 toward the power semiconductor element 22 is absorbed by the first metal layer 251 in the protective layer 25a.

[0095] (3) The power module substrate 12 according to the third embodiment is the power module substrate 12 according to (1), wherein the protective layer 25b may have a first protective layer 254 made of conductive ceramic and integrally laminated on the contact layer 24, a metal layer 255 made of a metal containing Ti and integrally laminated on the first protective layer 254, and a second protective layer 256 made of conductive ceramic and integrally disposed between the metal layer 255 and the connection layer 26.

[0096] As a result, when the pressure generated by the ultrasonic waves during wire bonding is applied to the connecting layer 26 of the electrode section 23, this pressure is absorbed by the second protective layer 256 and the metal layer 255. Furthermore, compared to, for example, the case where the protective layer 25b is a single layer, the thickness of the protective layer 25b can be increased while suppressing deformation such as strain and bending in the protective layer 25b.

[0097] (4) The power module substrate 12 according to the fourth embodiment is the power module substrate 12 of (1), wherein the contact layer 24 is formed with a thickness L1 of 0.05 to 0.5 μm, and the protective layer 25 is formed with a thickness L2 of 0.5 to 2 μm.

[0098] This ensures conductivity between the power semiconductor element 22 and the bonding wire 27 while suppressing deformation such as strain and bending in the contact layer 24 and the protective layer 25.

[0099] (5) The power module substrate 12 according to the fifth embodiment is the power module substrate 12 of (2), wherein the contact layer 24 is formed with a thickness L1 of 0.05 to 0.5 μm, the first metal layer 251 and the second metal layer 253 are formed with thicknesses L2a and L2c of 0.1 to 0.5 μm, and the main body layer 252 may be formed with a thickness L2b of 0.5 to 2 μm.

[0100] This makes it possible to ensure conductivity between the power semiconductor element 22 and the bonding wire 27 while suppressing deformation such as strain in each layer.

[0101] (6) The power module substrate 12 according to the sixth embodiment is the power module substrate 12 of (3), wherein the first protective layer 254 and the second protective layer 256 are formed with thicknesses L2d and L2f of 0.5 to 2 μm, and the metal layer 255 may be formed with a thickness L2e of 0.1 to 0.5 μm.

[0102] This makes it possible to ensure conductivity between the power semiconductor element 22 and the bonding wire 27 while suppressing deformation such as strain in each layer.

[0103] (7) The power module substrate 12 according to the seventh embodiment is any of the power module substrates 12 of (1) to (6), wherein the conductive ceramic may be formed of any one of TiB2, ZrB2, HfB2, TiSi2, and WSi2.

[0104] This allows the above effects to be achieved with greater precision.

[0105] (8) The power module substrate 12 according to the eighth embodiment is any of the power module substrates 12 of (1) to (7), wherein a plurality of the bonding wires 27 may connect the other surface patterns 21 and the connecting layer 26. [Explanation of symbols]

[0106] 1…Casing 1a…Input side 1b…Output side 2…External input conductor 3…Capacitor 4…Power conversion section 5…Cooler 10…Power module 11…Base plate 11a…First side 11b…Second side 12…Power module substrate 13…Main terminal section 13p…P terminal 13n…N terminal 14…Output terminal section 15…Reinforcement section 16…Sealing section 20…Insulating plate 20a…Front surface 20b…Back surface 21…Front surface pattern 21a…First surface pattern 21b…Second surface pattern 21c…Third surface pattern 22…Power semiconductor element 22a…First power semiconductor element 22b…Second power semiconductor element 22d…Bottom surface 22u…Top surface 23…Electrode section 24…Contact layer 25,25a,25b…Protective layer 26…Connection layer 27…Bonding wire 28…Back surface pattern 51…Base 51a…Bonding surface 51b…Heat dissipation surface 52…Heat dissipation fins 100…Power conversion device 251…First metal layer 252…Main body layer 253…Second metal layer 254…First protective layer 255…Metal layer 256…Second protective layer G…Gap Rp…Potting space S…Bonding material W…Liquid refrigerant

Claims

1. Insulating board and, A plurality of surface patterns arranged on the surface of the insulating plate, A power semiconductor element connected to one of the multiple surface patterns, An electrode portion arranged on the upper surface of the power semiconductor element, A bonding wire connecting one of the multiple surface patterns, which is different from the first surface pattern, to the electrode portion, Equipped with, The electrode portion is A contact layer formed of metal and positioned on the upper surface, A protective layer laminated on the contact layer, A connecting layer formed of metal and laminated on the protective layer, connected to the bonding wire, It has, The protective layer is a power module substrate containing a conductive ceramic having a harder hardness than the contact layer and the connecting layer.

2. The aforementioned protective layer is A first metal layer formed of a metal containing Ti and integrally laminated to the contact layer, A main body layer formed of conductive ceramic and integrally laminated on the first metal layer, A second metal layer is formed from a metal containing Ti and is integrally disposed between the main body layer and the connecting layer, A power module substrate according to claim 1, having the following features.

3. The aforementioned protective layer is A first protective layer formed of conductive ceramic and integrally laminated to the contact layer, A metal layer formed from a metal containing Ti and integrally laminated to the first protective layer, A second protective layer formed of conductive ceramic, disposed integrally with the metal layer and the connecting layer between the metal layer and the connecting layer, A power module substrate according to claim 1, having the following features.

4. The contact layer is formed with a thickness of 0.05 to 0.5 μm. The power module substrate according to claim 1, wherein the protective layer is formed with a thickness of 0.5 to 2 μm.

5. The contact layer is formed with a thickness of 0.05 to 0.5 μm. The first metal layer and the second metal layer are formed with a thickness of 0.1 to 0.5 μm. The power module substrate according to claim 2, wherein the main body layer is formed with a thickness of 0.5 to 2 μm.

6. The first protective layer and the second protective layer are formed with a thickness of 0.5 to 2 μm. The power module substrate according to claim 3, wherein the metal layer is formed with a thickness of 0.1 to 0.5 μm.

7. The conductive ceramic is TiB ２ , ZrB ２ HfB ２ , TiSi ２ and WSi ２ A power module substrate according to any one of claims 1 to 6, which is formed by any one of the following.

8. The power module substrate according to any one of claims 1 to 6, wherein a plurality of bonding wires connect the other surface patterns and the connecting layer.

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