Semiconductor memory

Abstract

To provide a semiconductor memory device that operates suitably.SOLUTION: A semiconductor storage device includes: a conductive layer including a first range and a second range; a first semiconductor layer facing the conductive layer in the first range; a second semiconductor layer facing the conductive layer in the second range; a first bit line electrically connected to one end of the first semiconductor layer; and a second bit line electrically connected to one end of the second semiconductor layer. If the sense time of the first bit line when executing a predetermined operation on a first memory cell including a first charge storage unit is used as a first operation parameter and the sense time of the second bit line when executing a predetermined operation on a second memory cell including a second charge storage unit is used as a second operation parameter, the second operation parameter is different from the first operation parameter.SELECTED DRAWING: Figure 28A

Description

[Technical Field]

[0001] This embodiment relates to a semiconductor memory device. [Background technology]

[0002] A semiconductor memory device is known that comprises a substrate, a plurality of conductive layers stacked in a direction intersecting the surface of the substrate, semiconductor layers facing these plurality of conductive layers, and a gate insulating layer provided between the conductive layers and the semiconductor layers. The gate insulating layer includes a memory portion capable of storing data, such as an insulating charge storage layer made of silicon nitride (Si3N4) or a conductive charge storage layer such as a floating gate. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2017-157260 [Overview of the project] [Problems that the invention aims to solve]

[0004] To provide a semiconductor memory device that operates optimally. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a substrate; a conductive layer spaced apart from the substrate in a first direction intersecting the surface of the substrate, extending in a second direction intersecting the first direction, and having a first range and a second range aligned in the second direction; a first semiconductor layer extending in the first direction and facing the conductive layer in the first range; a second semiconductor layer extending in the first direction and facing the conductive layer in the second range; a first charge storage unit provided between the conductive layer and the first semiconductor layer; a second charge storage unit provided between the conductive layer and the second semiconductor layer; a first bit line electrically connected to one end of the first semiconductor layer; and a second bit line electrically connected to one end of the second semiconductor layer. When performing a predetermined operation on a first memory cell including a first charge storage unit, the magnitude and supply time of one or more voltages supplied to the first bit line, the stable waiting time until sensing of the first bit line begins, and the sensing time of the first bit line are defined as first operation parameters. When performing a predetermined operation on a second memory cell including a second charge storage unit, the magnitude and supply time of one or more voltages supplied to the second bit line, the stable waiting time until sensing of the second bit line begins, and the sensing time of the second bit line are defined as second operation parameters. At least a portion of the second operation parameters differs from at least a portion of the first operation parameters. [Brief explanation of the drawing]

[0006] [Figure 1] This is a schematic block diagram showing the configuration of the memory system 10 according to the first embodiment. [Figure 2] This is a schematic block diagram showing the configuration of the memory die MD according to the first embodiment. [Figure 3] This is a schematic circuit diagram showing a part of the configuration of the memory die MD. [Figure 4] Figure 3 is a schematic circuit diagram showing the configuration of the string unit SU. [Figure 5] This is a schematic circuit diagram showing the configuration of the voltage generation circuit VG, the CG driver circuit DRV, and the raw decoder RD. [Figure 6] This is a schematic circuit diagram showing the configuration of the charge pump circuit 32 in the voltage generation circuit VG. [Figure 7] This is a schematic circuit diagram showing the configuration of the voltage output circuit 32a. [Figure 8] This is a schematic circuit diagram showing the configuration of the variable resistor element 32b4. [Figure 9] This is a schematic block diagram showing the configuration of the Row control circuit (RowC) and the block decoder (BLKD). [Figure 10] This is a schematic block diagram showing the configuration of the sense amplifier module SAM. [Figure 11] This is a schematic circuit diagram showing the configuration of the sense amplifier unit SAU. [Figure 12] This is a schematic plan view of a memory die (MD). [Figure 13] This is a schematic cross-sectional view of a memory die (MD). [Figure 14] This is a schematic enlarged view of the area indicated by A in Figure 12. [Figure 15] This is a schematic plan view showing a portion of the structure shown in Figure 14, with some details omitted. [Figure 16] This is a schematic plan view showing a portion of the structure shown in Figure 14, with some details omitted. [Figure 17] This is a schematic plan view showing a portion of the structure shown in Figure 14, with some details omitted. [Figure 18] This is a schematic plan view showing a portion of the structure shown in Figure 14, with some details omitted. [Figure 19] This is a schematic enlarged view of the area indicated by B in Figure 12. [Figure 20] This is a schematic enlarged view of the area indicated by C in Figure 19. [Figure 21] This is a schematic enlarged view of the area indicated by D in Figure 13. [Figure 22] This is a schematic enlarged view of Figure 14. [Figure 23] Figure 22 is a schematic cross-sectional view taken along the line EE' of the structure shown, viewed in the direction of the arrow. [Figure 24] This is a schematic diagram illustrating the threshold voltage of a memory cell (MC). [Figure 25]This is a schematic cross-sectional view illustrating the read operation. [Figure 26] This is a timing chart to explain the read operation. [Figure 27] This is a schematic diagram illustrating the adjustment of the operating parameters of the selected word line WLS according to the first embodiment. [Figure 28A] This is a schematic diagram illustrating the adjustment of the operating parameters of the bit line BL and source lines SL1 and SL2 according to the first embodiment. [Figure 28B] This diagram shows the signal lines for the control signals SGL1 and SGL2 between the SQC sequencer and the sense amplifier modules SAM(1) and SAM(2). [Figure 29] This is a timing chart for illustrating the read operation of the semiconductor memory device according to the second embodiment. [Figure 30] This is a flowchart illustrating the writing operation of the semiconductor memory device according to the third embodiment. [Figure 31] This is a schematic cross-sectional view illustrating the program operations involved in a write operation. [Figure 32] This is a schematic cross-sectional view illustrating the verification operation included in the write operation. [Figure 33] This is a timing chart to explain the writing operation. [Figure 34] This is a timing chart to explain the writing operation. [Figure 35] This is a timing chart for illustrating the writing operation of the semiconductor memory device according to the fourth embodiment. [Figure 36] This is a schematic exploded perspective view showing an example configuration of a semiconductor memory device according to the fifth embodiment. [Figure 37] This is a schematic bottom view showing an example of the configuration of a chip CM. [Figure 38] This is a schematic cross-sectional view showing a part of the configuration of the memory die MD according to the fifth embodiment. [Figure 39]This is a schematic cross-sectional view showing a part of the configuration of the memory die MD according to the fifth embodiment. [Figure 40] This is a schematic plan view showing an example of the configuration of a chip CP. [Figure 41] Figure 40 is a schematic cross-sectional view taken by cutting the structure along the FF' line and viewing it in the direction of the arrow. [Figure 42] Figure 40 is a schematic cross-sectional view taken by cutting the structure along the GG' line and viewing it along the direction of the arrow. [Figure 43] This is a schematic diagram illustrating the adjustment of the operating parameters of the selected word line WLS according to the fifth embodiment. [Figure 44] This is a schematic diagram illustrating the adjustment of the operating parameters of the bit line BL and source lines SL1 and SL2 according to the fifth embodiment. [Figure 45] This is a schematic diagram illustrating the adjustment of the operating parameters of the selected word line WLS according to the sixth embodiment. [Figure 46] This is a schematic diagram illustrating the adjustment of the operating parameters of the bit line BL and source lines SL1 and SL2 according to the sixth embodiment. [Figure 47] This is a schematic circuit diagram showing an example configuration of a three-dimensional NOR flash memory. [Figure 48] This is a schematic block diagram showing an example configuration of the semiconductor memory device 900 according to the seventh embodiment. [Figure 49] This is a schematic circuit diagram showing another example configuration of a three-dimensional NOR flash memory. [Figure 50] This is a schematic circuit diagram showing an example configuration of a three-dimensional DRAM. [Figure 51] This is a schematic circuit diagram showing another example configuration of a three-dimensional DRAM. [Figure 52] This is a schematic block diagram showing an example configuration of the semiconductor memory device 1000 according to the ninth embodiment. [Figure 53] This is a circuit diagram showing an example configuration of a sense amplifier sa, which includes a sense amplifier circuit sac. [Figure 54]This is a schematic XY cross-sectional view showing the configuration of a DRAM. [Figure 55] Figure 54 is a schematic cross-sectional view taken along the CC' line of the structure shown, viewed in the direction of the arrow. [Modes for carrying out the invention]

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. Furthermore, the following drawings are schematic, and some components may be omitted for illustrative purposes. Also, common parts in multiple embodiments are denoted by the same reference numerals, and their descriptions may be omitted.

[0008] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die, or to a memory system including a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). It may also refer to a configuration including a host computer, such as a smartphone, tablet device, or personal computer.

[0009] Furthermore, in this specification, the term "control circuit" may refer to peripheral circuits such as sequencers provided on the memory die, or it may refer to a controller die or controller chip connected to the memory die, or it may refer to a configuration that includes both of these.

[0010] Furthermore, in this specification, when we say that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or it may be connected to the second configuration via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0011] Furthermore, in this specification, when it is said that the first configuration is "connected between" the second and third configurations, it may mean that the first, second, and third configurations are connected in series, and that the second configuration is connected to the third configuration via the first configuration.

[0012] Furthermore, in this specification, when it is said that a circuit "conducts" two wires, it may mean, for example, that the circuit includes a transistor, that this transistor is located in the current path between the two wires, and that this transistor is in the ON state.

[0013] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0014] Furthermore, in this specification, the direction along a predetermined plane may be referred to as the first direction, the direction intersecting the first direction along this predetermined plane may be referred to as the second direction, and the direction intersecting this predetermined plane may be referred to as the third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0015] Furthermore, in this specification, expressions such as "top" and "bottom" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "top," and the direction approaching the substrate along the Z direction is called "bottom." Also, when referring to the bottom surface or bottom end of a configuration, it means the surface or end of that configuration that is on the substrate side, and when referring to the top surface or top end, it means the surface or end of that configuration that is on the opposite side from the substrate. In addition, surfaces that intersect with the X direction or Y direction are called sides, etc.

[0016] [First Embodiment] [Memory System 10] Figure 1 is a schematic block diagram showing the configuration of the memory system 10 according to the first embodiment.

[0017] The memory system 10 reads, writes, erases, and otherwise performs operations on user data in response to signals transmitted from the host computer 20. The memory system 10 is, for example, a memory chip, memory card, SSD, or other system capable of storing user data. The memory system 10 comprises a plurality of memory dies MD and a controller die CD.

[0018] The memory die MD stores user data. The memory die MD comprises multiple memory blocks BLK. Each memory block BLK comprises multiple page units PG. Each memory block BLK may also be a unit for performing erase operations. Each page unit may also be a unit for performing read and write operations.

[0019] As shown in Figure 1, the controller die CD is connected to multiple memory dies MD and a host computer 20. The controller die CD includes, for example, a data conversion table 21, a FAT (File Allocation Table) 22, an erase count retention unit 23, an ECC circuit 24, and an MPU (Micro Processor Unit) 25.

[0020] The logical-to-physical address conversion table 21 stores the correspondence between the logical address received from the host computer 20 and the physical address assigned to the page PG in the memory die MD. The logical-to-physical address conversion table 21 is implemented, for example, by RAM (Random Access Memory), which is not shown in the diagram.

[0021] FAT22 maintains FAT information indicating the status of each page PG. This FAT information includes, for example, information indicating "enabled," "invalid," and "erased." For example, a page PG that is "enabled" stores valid data that is read in response to commands from the host computer 20. A page PG that is "invalid" stores invalid data that is not read in response to commands from the host computer 20. A page PG that is "erased" has no data stored in it since the erasure process was performed. FAT22 is implemented by, for example, RAM (not shown).

[0022] The erase count retention unit 23 stores the physical address corresponding to the memory block BLK and the number of erase operations performed on the memory block BLK in association with each other. The erase count retention unit 23 is implemented, for example, by RAM (not shown).

[0023] The ECC circuit 24 detects errors in the data read from the memory die MD and corrects the data if possible.

[0024] The MPU25 performs processing such as logical-to-physical address conversion, bit error detection / correction, garbage collection (compaction), and wear leveling by referring to the logical-to-physical address conversion table 21, FAT 22, erase count retention unit 23, and ECC circuit 24.

[0025] [Circuit configuration of the memory die MD] Figure 2 is a schematic block diagram showing the configuration of the memory die MD according to the first embodiment. Figure 3 is a schematic circuit diagram showing a part of the configuration of the memory die MD. Figure 4 is a schematic circuit diagram showing the configuration of the string unit SU in Figure 3. Figure 5 is a schematic circuit diagram showing the configuration of the voltage generation circuit VG, the CG driver circuit DRV, and the row decoder RD. Figure 6 is a schematic circuit diagram showing the configuration of the charge pump circuit 32 in the voltage generation circuit VG. Figure 7 is a schematic circuit diagram showing the configuration of the voltage output circuit 32a. Figure 8 is a schematic circuit diagram showing the configuration of the variable resistor element 32b4. Figure 9 is a schematic block diagram showing the configuration of the row control circuit RowC and the block decoder BLKD. Figure 10 is a schematic block diagram showing the configuration of the sense amplifier module SAM. Figure 11 is a schematic circuit diagram showing the configuration of the sense amplifier unit SAU.

[0026] Figure 2 illustrates multiple control terminals. These control terminals may be represented as control terminals corresponding to high-active signals (positive logic signals). They may also be represented as control terminals corresponding to low-active signals (negative logic signals). Furthermore, they may be represented as control terminals corresponding to both high-active and low-active signals. In Figure 2, the symbols for control terminals corresponding to low-active signals include an overline. In this specification, the symbols for control terminals corresponding to low-active signals include a slash (" / "). Note that the description in Figure 2 is illustrative, and the specific configuration can be adjusted as appropriate. For example, some or all high-active signals may be treated as low-active signals, or some or all low-active signals may be treated as high-active signals.

[0027] As shown in Figure 2, the memory die MD comprises a memory cell array MCA and a peripheral circuit PC. The peripheral circuit PC comprises a voltage generation circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequencer SQC. The peripheral circuit PC also comprises a cache memory CM, an address register ADR, a command register CMR, and a status register STR. Furthermore, the peripheral circuit PC comprises an input / output control circuit I / O and a logic circuit CTR. The peripheral circuit PC also comprises a source line driver circuit SDRV (Figure 28A).

[0028] [Circuit configuration of memory cell array MCA] As shown in Figure 3, the memory cell array MCA comprises the aforementioned multiple memory block BLK. Each of these multiple memory block BLK comprises a multiple string unit SU. Each of these multiple string unit SU comprises a multiple memory string MS. One end of each of these multiple memory string MS is connected to the peripheral circuit PC via a bit line BL. The other end of each of these multiple memory string MS is connected to the peripheral circuit PC via a common source line SL (common source line SL1 in the division range DU1 described later, and common source line SL2 in the division range DU2 described later; see Figure 4).

[0029] The memory string MS comprises a drain-side selection transistor STD, multiple memory cells MC (memory transistors), a source-side selection transistor STS, and a source-side selection transistor STSb. The drain-side selection transistor STD, the multiple memory cells MC, the source-side selection transistor STS, and the source-side selection transistor STSb are connected in series between the bit line BL and the source line SL. Hereinafter, the drain-side selection transistor STD, the source-side selection transistor STS, and the source-side selection transistor STSb may simply be referred to as selection transistors (STD, STS, STSb).

[0030] A memory cell MC is a field-effect transistor. A memory cell MC comprises a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge storage film. A memory cell MC stores one or more bits of data. Word lines WL are connected to the gate electrodes of multiple memory cell MCs corresponding to one memory string MS. These word lines WL are commonly connected to all memory string MS in one memory block BLK.

[0031] Selection transistors (STD, STS, STSb) are field-effect transistors. Each selection transistor (STD, STS, STSb) comprises a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. Each gate electrode of a selection transistor (STD, STS, STSb) is connected to a selection gate line (SGD, SGS, SGSb), respectively. One drain-side selection gate line SGD is commonly connected to all memory strings MS in one string unit SU. One source-side selection gate line SGS is commonly connected to all memory strings MS in one memory block BLK. One source-side selection gate line SGSb is commonly connected to all memory strings MS in one memory block BLK.

[0032] [Division range of word line WL: DU1, DU2] As shown in Figure 4, each of the multiple word lines WL corresponds to a hookup region R, which will be described later. HU1 ,R HU2 (Figure 12, etc.) The system is physically or virtually divided into two division ranges DU1 and DU2. Then, for example, half of the multiple memory cells MC connected to one word line WL (e.g., word line WL0) are connected to division ranges DU1 and DU2 of the multiple word line WL.

[0033] In the example in Figure 4, the string unit SU has n word lines WL0 to WLn-1 and 2m bit lines BL0 to BL2m-1. Additionally, 2m memory strings MS0 to MS2m-1 are connected to the 2m bit lines BL0 to BL2m-1. n and m are integers greater than or equal to 1. In this case, m memory cells MC are connected to each of the division ranges DU1 of the n word lines WL0 to WLn-1. Similarly, m memory cells MC are connected to each of the division ranges DU2 of the n word lines WL0 to WLn-1. Note that the 2m memory cells MC connected to the n word lines WL0 to WLn-1 are sometimes referred to as memory cells MC0 to MCn-1.

[0034] As shown in Figure 4, of the 2m memory strings MS0 to MS2m-1, one end of m memory strings MS0 to MSm-1 in the division range DU1 is connected to the peripheral circuit PC via m bit lines BL0 to BLm-1 in the division range DU1. Also, of the 2m memory strings MS0 to MS2m-1, one end of m memory strings MSm to MS2m-1 in the division range DU2 is connected to the peripheral circuit PC via m bit lines BLm to BL2m-1 in the division range DU2.

[0035] Source lines SL1 and SL2 are provided corresponding to division ranges DU1 and DU2, as shown in Figure 4. Of the 2m memory strings MS0 to MS2m-1, the other ends of m memory strings MS0 to MSm-1 in division range DU1 are connected to the peripheral circuit PC via the common source line SL1 in division range DU1. Similarly, of the 2m memory strings MS0 to MS2m-1, the other ends of m memory strings MSm to MS2m-1 in division range DU2 are connected to the peripheral circuit PC via the common source line SL2 in division range DU2.

[0036] As mentioned above, the multiple word lines WL0 to WLn-1 are physically or virtually divided into two division ranges DU1 and DU2. However, as will be described later, one word line WL (divided range DU1, DU2) is connected to the word line switch WLSW via the corresponding wiring and contact CC. Therefore, one word line WL (divided range DU1, DU2) is supplied with the same voltage at the same time.

[0037] On the other hand, multiple bit lines BL included in division range DU1 and multiple bit lines BL included in division range DU2 can be supplied with different voltages at different timings. Also, source line SL1 corresponding to division range DU1 and source line SL2 corresponding to division range DU2 can be supplied with different voltages at different timings.

[0038] Furthermore, the select gate lines (SGD, SGS, SGSb), like the word line WL, are physically or virtually divided into two division ranges DU1 and DU2. The select gate lines (SGD, SGS, SGSb) are connected to the word line switch WLSW via wiring and contact CC. Therefore, the select gate lines (SGD, SGS, SGSb) are each supplied with the same voltage at the same timing.

[0039] [Circuit configuration of the voltage generation circuit VG] The voltage generation circuit VG (Figure 2) comprises multiple voltage generation units vg1 to vg3, as shown in Figure 5, for example. The voltage generation units vg1 to vg3 generate a voltage of a predetermined magnitude during read, write, and erase operations, and supply voltage to the voltage supply line L VG It outputs via the following. For example, the voltage generation unit vg1 outputs the program voltage V described later during the writing operation. PGM It outputs the following. In addition, the voltage generation unit vg2 outputs the read path voltage V described later during the read operation. READ It outputs the following. In addition, the voltage generation unit vg2 outputs the write path voltage V during the writing operation, which will be described later. PASSOutputs it. Also, the voltage generation unit vg3 outputs a read voltage, which will be described later, during the read operation. Also, the voltage generation unit vg3 outputs a verify voltage, which will be described later, during the write operation. The voltage generation units vg1 to vg3 may be, for example, a boost circuit such as a charge pump circuit or a buck circuit such as a regulator. These buck circuits and boost circuits are each connected to the voltage supply line L P is connected. The voltage supply line L P is supplied with the power supply voltage V CC or the ground voltage V SS (FIG. 2). These voltage supply lines L P are connected to, for example, the pad electrode P. The operating voltage output from the voltage generation circuit VG is appropriately adjusted according to the control signal from the sequencer SQC.

[0040] The charge pump circuit 32 in the voltage generation circuit VG includes, for example, as shown in FIG. 6, a voltage output circuit 32a, a voltage dividing circuit 32b, and a comparator 32c. The voltage output circuit 32a outputs the voltage V VG to the voltage supply line L. The voltage dividing circuit 32b is connected to the voltage supply line L VG . The comparator 32c outputs a feedback signal FB to the voltage output circuit 32a according to the magnitude relationship between the voltage V OUT ' output from the voltage dividing circuit 32b and the reference voltage V REF .

[0041] The voltage output circuit 32a includes, as shown in FIG. 7, a plurality of transistors 32a2a, 32a2b. The plurality of transistors 32a2a, 32a2b are alternately connected between the voltage supply line L VG and the voltage supply line L P . The illustrated voltage supply line L P is supplied with the power supply voltage V CC ​​A voltage is supplied. The gate electrodes of multiple transistors 32a2a and 32a2b connected in series are connected to their respective drain electrodes and capacitors 32a3. The voltage output circuit 32a also includes an AND circuit 32a4, level shifters 32a5a and 32a5b. The AND circuit 32a4 outputs the logical OR of the clock signal CLK and the feedback signal FB. The level shifter 32a5a boosts the output signal of the AND circuit 32a4 and outputs it. The output terminal of the level shifter 32a5a is connected to the gate electrode of transistor 32a2a via capacitor 32a3. The level shifter 32a5b boosts the inverted signal of the output signal of the AND circuit 32a4 and outputs it. The output terminal of the level shifter 32a5b is connected to the gate electrode of transistor 32a2b via capacitor 32a3.

[0042] When the feedback signal FB is in the "H" state, the AND circuit 32a4 outputs the clock signal CLK. Consequently, the voltage supply line L VG From voltage supply line L P Electrons are transferred to the voltage supply line L VG The voltage increases. On the other hand, when the feedback signal FB is in the "L" state, the AND circuit 32a4 does not output the clock signal CLK. Therefore, the voltage supply line L VG The voltage does not increase.

[0043] As shown in Figure 6, the voltage divider circuit 32b comprises a resistive element 32b2 and a variable resistive element 32b4. The resistive element 32b2 is connected to the voltage supply line L VG The variable resistor element 32b4 is connected between the voltage divider terminal 32b1 and the voltage supply line L. P It is connected in series between these two voltage supply lines L. P The ground voltage V SS The following is supplied. The resistance value of the variable resistor element 32b4 is the operating voltage control signal V CTRL It is adjustable accordingly. Therefore, the voltage V at the voltage divider terminal 32b1 OUT The magnitude of ' is the operating voltage control signal V CTRL It can be adjusted accordingly.

[0044] As shown in Figure 8, the variable resistor element 32b4 has multiple current paths 32b5. The multiple current paths 32b5 are connected to the voltage divider terminal 32b1 and the voltage supply line L P They are connected in parallel between them. Each of the multiple current paths 32b5 comprises a resistor 32b6 and a transistor 32b7 connected in series. The resistance values ​​of the resistors 32b6 provided in each current path 32b5 may be different from each other. The gate electrodes of the transistors 32b7 are connected to the operating voltage control signals V CTRL Different bits are input. Additionally, the variable resistor element 32b4 may have a current path 32b8 that does not include the transistor 32b7.

[0045] Comparator 32c outputs a feedback signal FB, as shown in Figure 6. The feedback signal FB is, for example, the voltage V at the voltage divider terminal 32b1. OUT ' is the reference voltage V REF The "L" state is reached when it is greater than the specified value. The feedback signal FB is, for example, a voltage V. OUT ' is the reference voltage V REF The "H" state occurs when the value is smaller.

[0046] Furthermore, the voltage generation circuit VG (Figure 2), as explained with reference to Figures 5 to 8 above, is a programmed voltage V applied to the word line WL (wiring CG). PGM , read path voltage V READ , write path voltage V PASS The configuration generated the read voltage and verify voltage. However, the voltage generation circuit VG can generate not only the operating voltage applied to the word line WL, but also multiple operating voltages applied to the bit line BL, source line SL, and selection gate lines (SGD, SGS, SGSb) during read, write, and erase operations on the memory cell array MCA, and output them to multiple voltage supply lines. These operating voltages are adjusted as appropriate according to the control signals from the sequencer SQC.

[0047] [Circuit configuration of the Low Decoder RD] The row decoder RD comprises, for example, a row control circuit RowC, a word line decoder WLD, a CG driver circuit DRV, and an address decoder (not shown), as shown in Figure 5. The row control circuit RowC comprises, for example, a plurality of block decoder units blkd and a block decoder BLKD, as shown in Figure 9.

[0048] Multiple block decoder units (blkd) correspond to multiple memory blocks (BLK) in the memory cell array (MCA). Each block decoder unit (blkd) includes multiple word line switches (WLSW). Each word line switch (WLSW) corresponds to multiple word lines (WL) in the memory block (BLK). The word line switch (WLSW) is, for example, a field-effect NMOS transistor. The drain electrode of the word line switch (WLSW) is connected to the word line (WL). The source electrode of the word line switch (WLSW) is connected to wiring (CG). Wiring (CG) is connected to all block decoder units (blkd) in the row control circuit (RowC). The gate electrode of the word line switch (WLSW) is connected to the signal supply line (BLKSEL). Multiple signal supply lines (BLKSEL) are provided, corresponding to all block decoder units (blkd). The signal supply lines (BLKSEL) are also connected to all word line switches (WLSW) in the block decoder unit (blkd).

[0049] The block decoder BLKD decodes the block address during read and write operations. During read and write operations, for example, one signal line BLKSEL corresponding to the block address in the address register ADR (Figure 2) becomes "H" and the other signal lines BLKSEL become "L". For example, a predetermined drive voltage with a positive magnitude is supplied to one signal line BLKSEL, and a ground voltage V is supplied to the other signal lines BLKSEL. SS These are supplied. As a result, all word lines WL in one memory block BLK corresponding to this block address become conductive with all wiring CG. Also, all word lines WL in other memory blocks BLK become floating.

[0050] The word line decoder WLD comprises multiple word line decoding units wld. These multiple word line decoding units wld correspond to multiple memory cells MC in the memory string MS. In the illustrated example, the word line decoding unit wld comprises two transistors T WLS ,T WLU It is equipped with a transistor T WLS ,T WLU For example, a field-effect NMOS transistor. Transistor T WLS ,T WLU The drain electrode of the transistor T is connected to the wiring CG. WLS The source electrode is the wiring CG S It is connected to transistor T. WLU The source electrode is the wiring CG U It is connected to transistor T. WLS The gate electrode is the signal line WLSEL S It is connected to transistor T. WLU The gate electrode is the signal line WLSEL U It is connected to the signal line WLSEL. S This is one of the transistors T included in all word line decoding units (wld). WLS Multiple units are provided to accommodate this. Signal line WLSEL U This is the other transistor T included in all word line decoding units wld. WLU Multiple versions are provided to accommodate this.

[0051] In read and write operations, for example, the signal line WLSEL corresponds to a word line decode unit wld that corresponds to a page address in the address register ADR (Figure 2). S This enters the "H" state, and the corresponding WLSEL U This enters the "L" state. In addition, the signal line WLSEL corresponds to the other word line decoding unit wld. S This enters the "L" state, and the corresponding WLSEL U This will result in an "H" state. Also, wiring CG S A voltage corresponding to the selected word line WL is supplied to it. Also, wiring CG UA voltage corresponding to the unselected word line WL is supplied to this. As a result, the voltage corresponding to the selected word line WL is supplied to one word line WL corresponding to the above page address. In addition, the voltage corresponding to the unselected word line WL is supplied to the other word lines WL.

[0052] The CG driver circuit DRV is, for example, a six-transistor T DRV1 ~T DRV6 It is equipped with a transistor T DRV1 ~T DRV6 For example, a field-effect NMOS transistor. Transistor T DRV1 ~T DRV4 The drain electrode is connected to the wiring CG. S It is connected to transistor T. DRV5 ,T DRV6 The drain electrode is connected to the wiring CG. U It is connected to transistor T. DRV1 The source electrode is connected to the voltage supply line L. VG1 It is connected to the output terminal of the voltage generation unit vg1 via transistor T. DRV2 ,T DRV5 The source electrode is connected to the voltage supply line L. VG2 It is connected to the output terminal of the voltage generation unit vg2 via transistor T. DRV3 The source electrode is connected to the voltage supply line L. VG3 It is connected to the output terminal of the voltage generation unit vg3 via transistor T. DRV4 ,T DRV6 The source electrode is connected to the voltage supply line L. P It is connected to the pad electrode P via the transistor T. DRV1 ~T DRV6 Signal lines VSEL1 to VSEL6 are connected to the gate electrodes of each device.

[0053] In read operations, write operations, etc., for example, wiring CG S One of the multiple signal lines VSEL1 to VSEL4 corresponding to this will be in the "H" state, and the others will be in the "L" state. Also, wiring CG U Of the two corresponding signal lines VSEL5 and VSEL6, one will be in the "H" state and the other in the "L" state.

[0054] The address decoder not shown, for example, sequentially refers to the row address RA of the address register ADR (FIG. 2) according to the control signal from the sequencer SQC (FIG. 2). The row address RA includes the block address and page address described above. The address decoder controls the voltages of the signal lines BLKSEL and WLSEL S ,WLSEL U to the "H" state or the "L" state.

[0055] In the example of FIG. 5, one block decoder unit blkd is provided for each memory block BL in the row decoder RD. However, this configuration can be changed as appropriate. For example, one block decoder unit blkd may be provided for each of two or more memory blocks BL.

[0056] [Circuit Configuration of Sense Amplifier Module SAM] The sense amplifier module SAM (FIG. 2) includes a plurality of sense amplifier units SAU, as shown in FIG. 10 for example. The plurality of sense amplifier units SAU correspond to a plurality of bit lines BL. Each sense amplifier unit SAU includes a sense amplifier SA, a wiring LBUS, and latch circuits SDL, DL0 to DLn L (n L is a natural number), and. A charging transistor 55 (FIG. 11) for precharge is provided in the sense amplifier module SAM (FIG. 2). The gate of the charging transistor 55 is connected to the signal line LBP, one end of the charging transistor 55 is connected to the wiring LBUS, and a voltage VHLB is supplied to the other end of the charging transistor 55. The signal line LBP is connected to the sequencer SQC. The wiring LBUS is connected to the wiring DBUS via a switch transistor DSW.

[0057] The sense amplifier SA includes a sense transistor 41, as shown in FIG. 11. The sense transistor 41 discharges the charge of the wiring LBUS according to the current flowing through the bit line BL. The source electrode of the sense transistor 41 is grounded to the voltage VSS It is connected to a voltage supply line to which voltage is supplied. The drain electrode is connected to the wiring LBUS via the switch transistor 42. The gate electrode is connected to the bit line BL via the sense node SEN, the discharge transistor 43, the node COM, the clamp transistor 44, and the withstand voltage transistor 45. Incidentally, the sense node SEN is connected to the internal control signal line CLKSA via the capacitor 48.

[0058] Also, the sense amplifier SA includes a voltage transfer circuit. The voltage transfer circuit selectively conducts the node COM and the sense node SEN to the voltage supply line to which voltage V DD is supplied or the voltage supply line to which voltage V SRC is supplied according to the data latched in the latch circuit SDL. The voltage transfer circuit includes a node N1, a charge transistor 46, a charge transistor 49, a charge transistor 47, and a discharge transistor 50. The charge transistor 46 is connected between the node N1 and the sense node SEN. The charge transistor 49 is connected between the node N1 and the node COM. The charge transistor 47 is connected between the node N1 and the voltage supply line to which voltage V DD is supplied. The discharge transistor 50 is connected between the node N1 and the voltage supply line to which voltage V SRC is supplied. Incidentally, the gate electrodes of the charge transistor 47 and the discharge transistor 50 are commonly connected to the node INV_S of the latch circuit SDL.

[0059] Incidentally, the sense transistor 41, the switch transistor 42, the discharge transistor 43, the clamp transistor 44, the charge transistor 46, the charge transistor 49, and the discharge transistor 50 are, for example, enhancement-type NMOS transistors. The withstand voltage transistor 45 is, for example, a depletion-type NMOS transistor. The charge transistor 47 is, for example, a PMOS transistor.

[0060] Furthermore, the gate electrode of the switch transistor 42 is connected to the signal line STB. The gate electrode of the discharge transistor 43 is connected to the signal line XXL. The gate electrode of the clamp transistor 44 is connected to the signal line BLC. The gate electrode of the breakdown transistor 45 is connected to the signal line BLS. The gate electrode of the charge transistor 46 is connected to the signal line HLL. The gate electrode of the charge transistor 49 is connected to the signal line BLX. These signal lines STB, XXL, BLC, BLS, HLL, and BLX are connected to the sequencer SQC.

[0061] The latch circuit SDL comprises nodes LAT_S and INV_S, inverter 51, inverter 52, switch transistor 53, and switch transistor 54. Inverter 51 has an output terminal connected to node LAT_S and an input terminal connected to node INV_S. Inverter 52 has an input terminal connected to node LAT_S and an output terminal connected to node INV_S. Switch transistor 53 is located in the current path between node LAT_S and wiring LBUS. Switch transistor 54 is located in the current path between node INV_S and wiring LBUS. Switch transistors 53 and 54 are, for example, NMOS transistors. The gate electrode of switch transistor 53 is connected to sequencer SQC via signal line STL. The gate electrode of switch transistor 54 is connected to sequencer SQC via signal line STI.

[0062] Latch circuits DL0~DLn L It is configured in much the same way as the latch circuit SDL. However, as mentioned above, node INV_S of the latch circuit SDL is in conduction with the gate electrodes of the charging transistor 47 and the discharging transistor 50 in the sense amplifier SA. Latch circuits DL0~DLn L In this respect, it differs from the latch circuit SDL.

[0063] The switch transistor DSW is, for example, an NMOS transistor. The switch transistor DSW is connected between wiring LBUS and wiring DBUS. The gate electrode of the switch transistor DSW is connected to the sequencer SQC via signal line DBS.

[0064] Furthermore, as illustrated in Figure 10, the aforementioned signal lines STB, HLL, XXL, BLX, BLC, and BLS are all commonly connected among all sense amplifier units SAU included in the sense amplifier module SAM. Also, the aforementioned internal control signal line CLKSA is commonly connected among all sense amplifier units SAU included in the sense amplifier module SAM. Additionally, the aforementioned voltage V DD The voltage supply line and voltage V that are supplied SRC The voltage supply lines that provide the signal are connected in common among all sense amplifier units SAU included in the sense amplifier module SAM. Similarly, the signal lines STI and STL of the latch circuit SDL are connected in common among all sense amplifier units SAU included in the sense amplifier module SAM. In the same manner, latch circuits DL0 to DLn... L Signal lines TI0 to TIn correspond to the signal lines STI and STL inside. L TL0~TLn L These are connected in common among all sense amplifier units SAU included in the sense amplifier module SAM. On the other hand, multiple signal lines DBS are provided, each corresponding to all sense amplifier units SAU included in the sense amplifier module SAM.

[0065] Furthermore, the sense amplifier module SAM is provided with two sense amplifier modules SAM(1) and SAM(2) corresponding to the division ranges DU1 and DU2 of the word line WL (as shown in Figure 30, which will be described later). The configuration of the two sense amplifier modules SAM(1) and SAM(2) is the same as that of the sense amplifier module SAM described with reference to Figures 10 and 11.

[0066] [Source Line Driver Circuit SDRV Configuration] The source line driver circuit SDRV (Figure 28A, described later) is a circuit that supplies voltage from the voltage generation circuit VG to the source lines SL1 and SL2. The source line driver circuit SDRV is connected to the voltage generation circuit VG via a voltage supply line, and is also connected to the source lines SL1 and SL2.

[0067] [Circuit configuration of cache memory CM] The cache memory CM (Figure 2) comprises multiple latch circuits. These multiple latch circuits are connected to the latch circuits in the sense amplifier module SAM via wiring DBUS. The data DAT contained in these multiple latch circuits is sequentially transferred to the sense amplifier module SAM or the input / output control circuit I / O.

[0068] Furthermore, a decode circuit and a switch circuit (not shown) are connected to the cache memory CM. The decode circuit decodes the column address CA held in the address register ADR. The switch circuit connects the latch circuit corresponding to the column address CA to the bus DB (Figure 2) in response to the output signal of the decode circuit.

[0069] [Circuit configuration of the SQC sequencer] The sequencer SQC (Figure 2) holds command data D in the command register CMR. CMD Accordingly, internal control signals are output to the low decoder RD, sense amplifier module SAM, and voltage generation circuit VG. In addition, the sequencer SQC outputs status data D indicating its own status as appropriate. ST Output this to the status register STR.

[0070] The SQC sequencer also generates a ready / busy signal and outputs it to the RY / / BY terminal. During the period when the RY / / BY terminal is in the "L" state (busy period), access to the memory die MD is basically prohibited. Conversely, during the period when the RY / / BY terminal is in the "H" state (ready period), access to the memory die MD is permitted.

[0071] [Circuit configuration of input / output control circuit I / O] The input / output control circuit I / O comprises data signal input / output terminals DQ0 to DQ7, toggle signal input / output terminals DQS, / DQS, multiple input circuits, multiple output circuits, a shift register, and a buffer circuit. The multiple input circuits, multiple output circuits, shift register, and buffer circuit are each connected to the power supply voltage V CCQ and ground voltage V SS It is connected to the terminal to which the power is supplied.

[0072] Data input via data signal input / output terminals DQ0 to DQ7 is output from the buffer circuit to the cache memory CM, address register ADR, or command register CMR, according to an internal control signal from the logic circuit CTR. Conversely, data output via data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or status register STR to the buffer circuit, according to an internal control signal from the logic circuit CTR.

[0073] Multiple input circuits include, for example, comparators connected to any of the data signal input / output terminals DQ0 to DQ7, or to both of the toggle signal input / output terminals DQS and DQS. Multiple output circuits include, for example, OCD (Off Chip Driver) circuits connected to any of the data signal input / output terminals DQ0 to DQ7, or to either of the toggle signal input / output terminals DQS and DQS.

[0074] [Circuit configuration of the logic circuit CTR] The logic circuit CTR (Figure 2) receives external control signals from the controller die CD via the external control terminals / CEn, CLE, ALE, / WE, RE, and / RE, and outputs internal control signals to the input / output control circuit I / O accordingly.

[0075] [Memory die MD structure] Figure 12 is a schematic plan view of the memory die MD. Figure 13 is a schematic cross-sectional view of the memory die MD. Note that Figure 13 is a diagram to explain the schematic configuration of the memory die MD and does not show the specific number, shape, arrangement, etc. of the components. Figure 14 is a schematic enlarged view of the part indicated by A in Figure 12. However, in Figure 14, only a part of the configuration of Figure 12 (the first hookup region R described later) is shown. HU1 ) is omitted. Figures 15 to 18 are schematic plan views showing a part of the structure shown in Figure 14 with some parts omitted. Figure 19 is a schematic enlarged view of the part shown in B of Figure 12. Figure 20 is a schematic enlarged view of the part shown in C of Figure 19. Figure 21 is a schematic enlarged view of the part shown in D of Figure 13. Figure 22 is a schematic enlarged view of Figure 14. Figure 23 is a schematic cross-sectional view of the structure shown in Figure 22, cut along line EE' and viewed in the direction of the arrow.

[0076] Figures 15 to 18 illustrate the conductive layers 110 described in Figure 14 that are provided at predetermined height positions (conductive layer 200, conductive layer 210, conductive layer 220, or conductive layer 230). In addition, Figures 15 to 18 omit the configurations included in the second and fourth memory block BLKs, counting from the negative side in the Y direction, among the multiple memory block BLKs arranged in the Y direction.

[0077] The memory die MD comprises a semiconductor substrate 100, as shown in Figure 12, for example. In the illustrated example, the semiconductor substrate 100 has four memory cell array regions R arranged in the X and Y directions. MCA A memory cell array region R is provided. MCA These are two memory hole regions R aligned in the X direction. MH And between these, two first hookup regions R aligned in the X direction HU1 And a second hookup region R is provided between these. HU2 It is equipped with the following.

[0078] Furthermore, the division range DU1 of the above word line WL is, for example, two memory hole regions R aligned in the X direction. MH Of these, the memory hole region R on the negative side in the X directionMH This is the range of the word line WL that corresponds to it. Furthermore, the division range DU2 of the above word line WL is, for example, two memory hole regions R aligned in the X direction. MH Of these, the memory hole region R on the positive side in the X direction MH This is the range of the corresponding word line WL.

[0079] The memory die MD, as shown in Figure 13, for example, consists of a semiconductor substrate 100 and a transistor layer L provided on the semiconductor substrate 100. TR And the transistor layer L TR A wiring layer D0 is provided above it, a wiring layer D1 is provided above wiring layer D0, a wiring layer D2 is provided above wiring layer D1, and a memory cell array layer L is provided above wiring layer D2. MCA1 and memory cell array layer L MCA1 Memory cell array layer L located above MCA2 and memory cell array layer L MCA2 It comprises a wiring layer M0 provided above and a wiring layer (not shown) provided above the wiring layer M0.

[0080] [Structure of semiconductor substrate 100] The semiconductor substrate 100 is a semiconductor substrate made of p-type silicon (Si) containing p-type impurities such as boron (B). The surface of the semiconductor substrate 100 is provided with an N-type well region containing an N-type impurity such as phosphorus (P), a p-type well region containing a p-type impurity such as boron (B), a semiconductor substrate region without an N-type well region or a p-type well region, and an insulating region 100I.

[0081] [Transistor layer L TR [Structure] For example, as shown in Figure 13, a wiring layer GC is provided on the upper surface of the semiconductor substrate 100 via an insulating layer (not shown). The wiring layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 100. Furthermore, each region of the semiconductor substrate 100 and the plurality of electrodes gc included in the wiring layer GC are connected to a contact CS.

[0082] The N-type well region, P-type well region, and semiconductor substrate region of the semiconductor substrate 100 function as the channel region of multiple transistors Tr that constitute the peripheral circuit PC, and as one electrode of multiple capacitors, respectively.

[0083] The multiple electrodes gc contained in the wiring layer GC each function as the gate electrodes of multiple transistors Tr that constitute the peripheral circuit PC, and as the other electrodes of multiple capacitors, etc.

[0084] The contact CS extends in the Z direction and is connected at its lower end to the upper surface of the semiconductor substrate 100 or electrode gc. An impurity region containing N-type or P-type impurities is provided at the connection point between the contact CS and the semiconductor substrate 100. The contact CS may also include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0085] [Structure of wiring layers D0, D1, and D2] For example, as shown in Figure 13, multiple wirings included in wiring layers D0, D1, and D2 are electrically connected to at least one of the configurations in the memory cell array MCA and the configurations in the peripheral circuit PC.

[0086] Each wiring layer D0, D1, and D2 contains multiple wirings d0, d1, and d2, respectively. These multiple wirings d0, d1, and d2 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0087] [Memory cell array layer L MCA1 ,L MCA2 Memory hole region R MH [Structure in] For example, as shown in Figure 14, the memory cell array layer L MCA1 ,L MCA2The memory block BLK is provided with multiple memory blocks BLK arranged in the Y direction. Each memory block BLK comprises multiple string units SU arranged in the Y direction, as shown in Figure 19, for example. Between two adjacent memory blocks BLK in the Y direction, an interblock insulating layer ST made of silicon oxide (SiO2) or the like is provided. Between two adjacent string units SU in the Y direction, an interstring insulating layer SHE made of silicon oxide (SiO2) or the like is provided, as shown in Figure 20, for example.

[0088] The memory block BLK comprises, for example, a plurality of conductive layers 110 arranged in the Z direction and a plurality of semiconductor layers 120 extending in the Z direction, as shown in Figure 13. The memory block BLK also comprises, for example, a plurality of gate insulating films 130 provided between the plurality of conductive layers 110 and the plurality of semiconductor layers 120, as shown in Figure 21.

[0089] The conductive layer 110 is a substantially plate-shaped conductive layer stretched in the X direction. The conductive layer 110 may contain a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W) or molybdenum (Mo). The conductive layer 110 may also contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 (Figure 21) made of silicon oxide (SiO2) or the like is provided between a plurality of conductive layers 110 arranged in the Z direction.

[0090] Below the conductive layer 110, a conductive layer 111 is provided, for example, as shown in Figure 13. The conductive layer 111 may contain, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer, such as silicon oxide (SiO2), is provided between the conductive layer 111 and the conductive layer 110.

[0091] A conductive layer 112 is provided below the conductive layer 111. The conductive layer 112 may contain, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). The conductive layer 112 may also contain, for example, a metal such as tungsten (W), a conductive layer such as tungsten silicide, or other conductive layers. An insulating layer such as silicon oxide (SiO2) is provided between the conductive layer 112 and the conductive layer 111.

[0092] The conductive layer 112 functions as the source line SL (Figure 3). The conductive layer 112 is the memory cell array layer L MCA1 It is provided in the memory cell array region R. The conductive layer 112 is, for example, in the memory cell array region R. MCA Two memory hole regions R included MH Of these, the memory hole region R corresponding to the division range DU1 MH A common feature is provided for the memory hole area R corresponding to the division range DU2. MH These are commonly provided (Figure 12).

[0093] The conductive layer 111 functions as the gate electrode of the source-side selection gate line SGSb (Figure 3) and the multiple source-side selection transistors STSb connected thereto. The conductive layer 111 is located in the memory cell array layer L MCA1 Two memory hole regions R are provided, aligned in the X direction. MH , two first hookup regions R provided between these HU1 , and a second hookup region R provided between them HU2 It extends in the X direction over the entire length. The conductive layer 111 is electrically independent for each memory block BLK.

[0094] Furthermore, one or more of the conductive layers 110 located at the bottom of the multiple conductive layers 110 function as the gate electrodes of the source-side selection gate line SGS (Figure 3) and the multiple source-side selection transistors STS connected thereto. These conductive layers 110 are located in the memory cell array layer L MCA1 Two memory hole regions R are provided, aligned in the X direction. MH, two first hookup regions R provided between these HU1 , and a second hookup region R provided between them HU2 They extend in the X direction over the entire length. These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0095] Furthermore, the multiple conductive layers 110 located above this function as part of the word line WL (Figure 3) and the gate electrodes of the multiple memory cells MC (Figure 3) connected thereto. These multiple conductive layers 110 function as memory cell array layer L, for example, as illustrated in Figure 15. MCA1 Two memory hole regions R are provided, aligned in the X direction. MH , two first hookup regions R provided between these HU1 (Omitted in Figure 15; see Figure 12), and the second hookup region R provided between them. HU2 They extend in the X direction over two memory hole regions R. MH It comprises two portions 201 and a portion 202 connected to both of these portions 201. The two portions 201 are electrically connected via the portion 202. Furthermore, these multiple conductive layers 110 are electrically independent for each memory block BLK. In the following description, such conductive layers 110 may be referred to as conductive layers 200.

[0096] Furthermore, above this, pairs of conductive layers 110 aligned in the X direction are stacked in the Z direction. These sets of conductive layers 110 function as part of the word line WL (Figure 3) and the gate electrodes of the multiple memory cells MC (Figure 3) connected thereto. These sets of conductive layers 110 form the memory cell array layer L MCA1 These two conductive layers 110 are provided in, for example, one or the other memory hole region R, as illustrated in Figure 16. MH , one or the other first hookup region R HU1 (Omitted in Figure 16; see Figure 12), and the second hookup region R HU2It extends in the X direction over a portion of the structure. These two conductive layers 110 are electrically connected via contact CC and wiring. Furthermore, these multiple conductive layers 110 are electrically independent for each memory block BLK. In the following description, such conductive layers 110 may be referred to as conductive layers 210.

[0097] Furthermore, the multiple conductive layers 110 located above this function as part of the word line WL (Figure 3) and the gate electrodes of the multiple memory cells MC (Figure 3) connected thereto. These multiple conductive layers 110 function as memory cell array layer L, for example, as illustrated in Figure 17. MCA2 Two memory hole regions R are provided, aligned in the X direction. MH , two first hookup regions R provided between these HU1 (Omitted in Figure 17; see Figure 12), and the second hookup region R provided between them. HU2 They extend in the X direction over two memory hole regions R. MH It comprises two portions 221 and a portion 222 connected to both of these portions 221. The two portions 221 are electrically connected via the portion 222. Furthermore, these multiple conductive layers 110 are electrically independent for each memory block BLK. In the following description, such conductive layers 110 may be referred to as conductive layers 220.

[0098] Furthermore, above this, pairs of conductive layers 110 aligned in the X direction are stacked in the Z direction. These sets of conductive layers 110 function as part of the word line WL (Figure 3) and the gate electrodes of the multiple memory cells MC (Figure 3) connected thereto. These sets of conductive layers 110 form the memory cell array layer L MCA2 These two conductive layers 110 are provided in, for example, one or the other memory hole region R, as illustrated in Figure 18. MH , one or the other first hookup region R HU1 (Omitted in Figure 18; see Figure 12), and the second hookup region R HU2It extends in the X direction over a portion of the structure. These two conductive layers 110 are electrically connected via contact CC and wiring. Furthermore, these multiple conductive layers 110 are electrically independent for each memory block BLK. In the following description, such conductive layers 110 may be referred to as conductive layers 230.

[0099] Furthermore, one or more conductive layers 110 located above this are memory cell array layers L MCA2 These conductive layers 110 are provided and function as gate electrodes for the drain-side selection gate wire SGD and the multiple drain-side selection transistors STD (Figure 3) connected thereto. These multiple conductive layers 110 have a smaller width in the Y direction than the other conductive layers 110, as illustrated in Figure 19, for example. In addition, between two adjacent conductive layers 110 in the Y direction, an inter-string unit insulating layer SHE is provided, as illustrated in Figure 20, for example. Each of these multiple conductive layers 110 is electrically independent for each string unit SU.

[0100] The semiconductor layer 120 is arranged in a predetermined pattern in the X and Y directions, as shown in Figure 20, for example. The semiconductor layer 120 functions as the channel region of multiple memory cells MC and selection transistors (STD, STS, STSb) included in one memory string MS (Figure 3). The semiconductor layer 120 is, for example, a semiconductor layer made of polycrystalline silicon (Si). The semiconductor layer 120 has, for example, a substantially cylindrical shape, and an insulating layer 125 (Figure 21) made of silicon oxide or the like is provided in the central part.

[0101] The semiconductor layer 120 is, for example, as shown in Figure 13, the memory cell array layer L MCA1 Semiconductor region 120 included L and memory cell array layer L MCA2 Semiconductor region 120 included U The semiconductor layer 120 is connected to the conductive layer 112 at its lower end, and to the bit line BL via contacts Ch and Vy at its upper end.

[0102] Semiconductor field 120 LThis is a roughly cylindrical region extending in the Z direction. Semiconductor region 120 L The outer surfaces are each the memory cell array layer L MCA1 It is surrounded by multiple conductive layers 110 and conductive layers 111, and is facing these multiple conductive layers 110 and conductive layers 111. L The lower end (for example, memory cell array layer L) MCA1 The diameter of the multiple conductive layers 110 and the portion located below conductive layer 111 (included in the semiconductor region 120) is L The upper end (for example, the memory cell array layer L) MCA1 It is smaller than the diameter of the portion located above the multiple conductive layers 110 contained within it.

[0103] Semiconductor field 120 U This is a roughly cylindrical region extending in the Z direction. Semiconductor region 120 U The outer surfaces are each the memory cell array layer L MCA2 It is surrounded by multiple conductive layers 110 and faces these multiple conductive layers 110. U The lower end (for example, memory cell array layer L) MCA2 The diameter of the portion located below the multiple conductive layers 110 included in the semiconductor region 120 U The upper end (for example, the memory cell array layer L) MCA2 The diameter of the portion located above the multiple conductive layers 110 included in and the semiconductor region 120 L It is smaller than the diameter of the upper end.

[0104] The gate insulating film 130 (Figure 21) has a substantially cylindrical shape that covers the outer surface of the semiconductor layer 120. The gate insulating film 130 comprises a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 laminated between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the block insulating film 133 are insulating films such as silicon oxide (SiO2) and silicon nitrate (SiON). The charge storage film 132 is a charge-storing film such as silicon nitride (Si3N4). The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer surface of the semiconductor layer 120, excluding the contact area between the semiconductor layer 120 and the conductive layer 112.

[0105] Figure 21 shows an example in which the gate insulating film 130 includes a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may also include a floating gate such as polycrystalline silicon containing N-type or P-type impurities.

[0106] [Memory cell array layer L MCA1 ,L MCA2 First hookup region R HU1 [Structure in] As shown in Figure 19, the first hookup region R HU1 Each of these has a small contact connection region r corresponding to the memory block BLK. CC1 A contact connection area R is provided in the area corresponding to some memory blocks BLK. C4T A system is in place.

[0107] Contact connection small area r CC1 The X-direction ends of multiple conductive layers 110, which function as drain-side selected gate lines SGD, are provided. Furthermore, the contact connection small region r CC1The device is provided with multiple contact CCs arranged in a matrix when viewed from the Z direction. These multiple contact CCs extend in the Z direction and are connected to the conductive layer 110 at their lower ends. The contact CCs may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0108] Among the multiple contacts CC aligned in the X direction, the memory hole region R MH The closest one is connected to the first conductive layer 110 from the top. Also, the memory hole region R MH The second closest is connected to the second conductive layer 110 from the top. Similarly, the memory hole region R MH The contact closest to the a-th (where a is a natural number)-th contact is connected to the a-th conductive layer 110, counting from the top. These multiple contacts CC are connected to the drain electrode of the transistor Tr via wiring m0 in wiring layer M0, contact C4, wiring d0, d1, d2 in wiring layers D0, D1, D2, and contact CS.

[0109] Furthermore, the first hookup region R HU1 A support structure HR is provided near the contact CC. The support structure HR extends, for example, in the Z direction and is connected to the conductive layer 112 at its lower end. The support structure HR contains, for example, silicon oxide (SiO2).

[0110] Contact connection area R C4T In this, between the two block-inter-insulating layers ST aligned in the Y direction, there are two insulating layers ST aligned in the Y direction. O A insulating layer ST is provided. O Between them is the small contact area r C4T A block-to-block insulating layer ST and insulating layer ST are provided. O Between them is a small conductive layer connection region r 110 These regions are provided. These regions extend in the X direction along the interblock insulating layer ST.

[0111] Insulating layer STO It extends in the Z direction and is connected to the conductive layer 112 (Figure 13) at its lower end. Insulating layer ST O This includes, for example, silicon oxide (SiO2).

[0112] Contact connection small area r C4T As shown in Figure 13, for example, it comprises a plurality of insulating layers 110A arranged in the Z direction and a plurality of contacts C4 extending in the Z direction.

[0113] The insulating layer 110A is a roughly plate-shaped insulating layer that extends in the X direction. The insulating layer 110A may also contain an insulating layer of silicon nitride (SiN) or the like. An insulating layer of silicon oxide (SiO2) or the like is provided between multiple insulating layers 110A arranged in the Z direction.

[0114] Multiple contacts C4 are arranged in the X direction. Contacts C4 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). For example, as shown in Figure 13, the outer surfaces of contacts C4 are surrounded by insulating layers 110A and 101, respectively, and are connected to these insulating layers 110A and 101. Contacts C4 extend in the Z direction, are connected to wiring m0 in wiring layer M0 at the upper end, and to wiring d2 in wiring layer D2 at the lower end.

[0115] small area r connected to conductive layer 110 For example, as shown in Figure 19, the narrow portion 110 of a plurality of conductive layers 110 arranged in the Z direction C4T It is equipped with.

[0116] [Memory cell array layer L MCA1 ,L MCA2 Second hookup region R HU2 [Structure in] As shown in Figure 14, the second hookup region R HU2 It corresponds to multiple memory block BLKs and multiple contact-connected small regions r CC2 And multiple contact connection areas R C4T And, is provided.

[0117] Contact connection small area r CC2 A portion of multiple conductive layers 110, which function as word lines WL or source-side selected gate lines SGS, is provided. Furthermore, a small contact connection region r CC2 Multiple contacts CC are provided, arranged in the X direction when viewed from the Z direction. As shown in Figure 23, each of these contacts CC is connected to the conductive layer 110. Also, as shown in Figure 22, these contacts CC are connected to the drain electrode of the transistor Tr via wiring m0 in the wiring layer M0, contact C4, wiring d0, d1, d2 in the wiring layers D0, D1, D2, and contact CS.

[0118] Furthermore, as shown in Figure 15, portion 202 of the conductive layer 200 is a small contact connection region r CC2 A narrow section 110 provided there CC2 It is equipped with this narrow part 110 CC2 In the region adjacent to it in the Y direction, there is an opening 102 CC2 A narrow section 110 is provided. CC2 This is the contact connection area R C4T The narrowest part inside is 110 C4T In addition, two adjacent portions 201 in the X direction are made electrically connected. Furthermore, only one contact CC is connected to the conductive layer 200. Aperture 102 CC2 A contact CC is provided, which is connected to a conductive layer 110 located further down.

[0119] Furthermore, as shown in Figure 16, between the two conductive layers 210 aligned in the X direction, there is a narrow section 110 as illustrated in Figure 15. CC2 There is no such feature. Furthermore, contact CCs are connected to each of these two conductive layers 210. Also, there is an opening 102 between these two conductive layers 210. CC2 An opening 102 is provided. CC2 A contact CC is provided, which is connected to a conductive layer 110 located further down.

[0120] Furthermore, as shown in Figure 17, portion 222 of the conductive layer 220 is a contact connection small region r CC2 A narrow section 110 provided there CC2 It is equipped with this narrow part 110 CC2 In the region adjacent to it in the Y direction, there is an opening 102 CC2 A narrow section 110 is provided. CC2 This is the contact connection area R C4T The narrowest part inside is 110 C4T In addition, two adjacent portions 221 in the X direction are made electrically connected. Furthermore, only one contact CC is connected to the conductive layer 220. Aperture 102 CC2 A contact CC is provided, which is connected to a conductive layer 110 located further down.

[0121] Furthermore, as shown in Figure 18, between the two conductive layers 230 aligned in the X direction, there is a narrow section 110 as illustrated in Figure 17. CC2 There is no such feature. Furthermore, contact CCs are connected to each of these two conductive layers 230. Also, there is an opening 102 between these two conductive layers 230. CC2 An opening 102 is provided. CC2 A contact CC is provided, which is connected to a conductive layer 110 located further down.

[0122] [Structure of wiring layer M0, etc.] As shown in Figure 13, the multiple wirings included in the wiring layer M0 are, for example, in the memory cell array layer L MCA1 ,L MCA2 Internal structure and transistor layer L TR It is electrically connected to at least one of the internal components.

[0123] The wiring layer M0 includes multiple wirings m0. These multiple wirings m0 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu).

[0124] Some of the multiple wirings m0 function as bit lines BL (Figure 3). The bit lines BL are aligned in the X direction and extend in the Y direction, as shown in Figure 20, for example. Each of these multiple bit lines BL is connected to one semiconductor layer 120 contained in each string unit SU.

[0125] Furthermore, some of the multiple wirings m0 function as wirings m0a, as illustrated in Figures 15 to 18. Wirings m0a are provided in the current path between contact CC and contact C4 as described above, and extend in the Y direction.

[0126] Furthermore, as described above, another wiring layer is provided above the wiring layer M0. Each of these wiring layers contains multiple wirings. These multiple wirings may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) or tantalum nitride (TaN) and a metal film such as copper (Cu).

[0127] Some of these multiple wires function as wire m1a, as illustrated in Figures 16 and 18. Wiring m1a is a wire provided in the current path between contact CC and contact C4 as described above, and extends in the X direction.

[0128] [Threshold voltage of memory cell MC] Next, with reference to Figure 24, the threshold voltage of the memory cell MC will be explained.

[0129] Figure 24(a) is a schematic histogram illustrating the threshold voltage of a memory cell MC that records 3 bits of data. The horizontal axis shows the voltage of the word line WL, and the vertical axis shows the number of memory cell MCs. Figure 24(b) is a table showing an example of the relationship between the threshold voltage of a memory cell MC that records 3 bits of data and the data recorded. Figure 24(c) is a table showing another example of the relationship between the threshold voltage of a memory cell MC that records 3 bits of data and the data recorded.

[0130] In the example shown in Figure 24(a), the threshold voltage of the memory cell MC is controlled to eight different states. The threshold voltage of the memory cell MC controlled to the Er state is the erase verify voltage V VFYEr It is smaller. Also, for example, the threshold voltage of a memory cell MC controlled to state A is the verify voltage V VFYA Larger verify voltage V VFYB It is smaller. Also, for example, the threshold voltage of a memory cell MC controlled to the B state is the verify voltage V VFYB Larger verify voltage V VFYC Smaller. Similarly, the threshold voltages of memory cells MC controlled to C state ~ F state are, respectively, the verify voltage V VFYC ~Verify voltage V VFYF Larger verify voltage V VFYD ~Verify voltage V VFYG It is smaller. Also, for example, the threshold voltage of a G-state controlled memory cell MC is the verify voltage V VFYG Larger, read path voltage V READ Smaller.

[0131] Furthermore, in the example in Figure 24(a), there is a readout voltage V between the threshold distribution corresponding to the Er state and the threshold distribution corresponding to the A state. CGAR The following is set. Also, between the threshold distribution corresponding to state A and the threshold distribution corresponding to state B, the read voltage V CGBR The following is set. Similarly, between the threshold distribution corresponding to state B and the threshold distribution corresponding to state C, and between the threshold distribution corresponding to state F and the threshold distribution corresponding to state G, the readout voltage V CGBR ~Read voltage V CGGR It is set.

[0132] For example, the Er state corresponds to the lowest threshold voltage. A memory cell MC in the Er state is, for example, a memory cell MC in the erase state. A memory cell MC in the Er state is assigned the data "111", for example.

[0133] Furthermore, the A state corresponds to a threshold voltage higher than the threshold voltage corresponding to the Er state described above. For example, the memory cell MC in the A state is assigned the data "101".

[0134] Furthermore, the B state corresponds to a threshold voltage higher than the threshold voltage corresponding to the A state described above. For example, the memory cell MC in the B state is assigned the data "001".

[0135] Similarly, in the diagram, states C through G correspond to threshold voltages higher than those corresponding to states B through F. The memory cells MC in these states are assigned data such as "011", "010", "110", "100", and "000".

[0136] In the case of the allocation shown in Figure 24(b), the lower bits of data are read at a single read voltage V CGDR This can be determined by the three read voltages V. CGAR ,V CGCR ,V CGFR This can be determined by the three read voltages V. CGBR ,V CGER ,V CGGR This can be determined by [the method used].

[0137] Furthermore, the number of bits of data recorded in the memory cell MC, the number of states, and the data assignment to each state can be changed as appropriate.

[0138] For example, in the case of an assignment as illustrated in Figure 24(c), the lower bits of data are read at one read voltage V CGDR This can be determined by the two read voltages V. CGBR ,V CGFR This can be determined by the four read voltages V. CGAR ,V CGCR ,V CGER ,V CGGRThis can be determined by [the method used].

[0139] [Read operation] Next, the read operation of the semiconductor memory device according to this embodiment will be described.

[0140] Figure 25 is a schematic cross-sectional view illustrating the read operation. Figure 26 is a timing chart illustrating the read operation.

[0141] In the following explanation, the word line WL that is the target of the operation is selected. S This is called a non-selected word line WL, and other word lines WL are called non-selected word lines WL. U It is sometimes referred to as such. Furthermore, in the following explanation, among the multiple memory cells MC included in the string unit SU that is the target of the operation, the selected word line WL is used. S This section describes an example of performing a read operation on a connected memory cell (hereinafter sometimes referred to as a "selected memory cell MC"). In the following description, a configuration including multiple such selected memory cell MCs may be referred to as a selected page PG.

[0142] Furthermore, in Figure 25, the word line WL is divided into division ranges DU1 and DU2. In the example in Figure 25, division range DU1 is the negative X-direction range of the word line WL, and division range DU2 is the positive X-direction range of the word line WL. The source line SL is also divided into source lines SL1 and SL2, corresponding to division ranges DU1 and DU2.

[0143] At the timing t101 of the read operation, for example, as shown in Figures 25 and 26, the unselected word line WL U Read path voltage V READ This supplies power to turn on the non-selected memory cell MC. Also, the selected word line WL is used. S The read voltage used for reading (read voltage V as explained in Figure 24) CGAR ~V CGGRIt supplies a voltage of either (or greater than) or greater than that. Also, it supplies voltage V to the selected gate lines (SGD, SGS, SGSb). SG It supplies voltage V. SG This is large enough to form an electron channel in the channel region of the selection transistor (STD, STS, STSb), thereby turning the selection transistor (STD, STS, STSb) ON.

[0144] A waiting time Ta is provided between the timings t101 and t102 of the read operation. The waiting time Ta is, for example, related to the selection word line WL. S This is the waiting time for charging.

[0145] At the timing t102 of the read operation, the selected word line WL S The read voltage used for reading (read voltage V as explained in Figure 24) CGAR ~V CGGR This supplies either of the following: As a result, some of the selected memory cells MCs become ON, and the remaining selected memory cells MCs become OFF, as shown in Figure 25, for example.

[0146] At the timing t103 of the read operation, for example, a voltage V is applied to source lines SL1 and SL2. S Supply power to begin charging source lines SL1 and SL2.

[0147] At the timing t104 of the read operation, for example, the bit line BL is charged. For example, the latch circuit SDL in Figure 11 is latched to "H", and the state of the signal lines STB, XXL, BLC, BLS, HLL, BLX is set to "L,L,H,H,H,H". As a result, a voltage V is applied to the bit line BL and the sense node SEN. DD The battery is supplied, and charging begins.

[0148] A waiting time Ts is provided between the timings t103 and t105 of the read operation. The waiting time Ts is, for example, a waiting time to converge the current in the source line SL.

[0149] A waiting time Tb is provided between timings t104 and t105 of the read operation. The waiting time Tb is, for example, a waiting time to converge the current of the bit line BL.

[0150] At the timing t105 of the read operation, for example, the voltage on the signal line BLC is reduced, and a voltage V is applied to the bit line BL. DD This supplies the signal. At this time, the voltage of the signal line BLC is adjusted to a voltage that keeps the clamp transistor 44 (Figure 11) connected to the signal line BLC in the ON state.

[0151] Furthermore, at the timing t105 of the read operation, for example, the voltages on source lines SL1 and SL2 are reduced, and a voltage V is applied to source lines SL1 and SL2. SRC It supplies voltage V. SRC For example, the ground voltage V SS It has a similar size. Voltage V SRC For example, the ground voltage V SS Slightly larger, and voltage V DD A sufficiently lower voltage is also acceptable.

[0152] A waiting time Tc is provided between timings t105 and t106 of the read operation. The waiting time Tc is, for example, a waiting time to stabilize the current of the bit line BL. Hereafter, the waiting time Tc may be referred to as the "stabilization waiting time".

[0153] At the timing t106 of the read operation, the sense amplifier module SAM (Figure 2) detects the ON / OFF state of the memory cell MC and acquires data indicating the state of this memory cell MC. Hereafter, this type of operation may be referred to as a sense operation. In a sense operation, for example, the state of the signal lines STB, XXL, BLC, BLS, HLL, BLX (Figure 11) is set to "L, H, H, H, L, L". As a result, the charge of the sense node SEN connected to the selected memory cell MC in the ON state is released via the bit line BL, and the voltage of this sense node decreases. On the other hand, the charge of the sense node SEN connected to the selected memory cell MC in the OFF state is maintained, and the voltage of this sense node is maintained.

[0154] A waiting time Td is provided between timings t106 and t107 (Figure 26) of the read operation. The waiting time Td is, for example, a waiting time to detect the state of the memory cell MC. Hereafter, the waiting time Td may be referred to as the "sense time".

[0155] At timing t107 of the read operation, the sense operation is terminated. For example, the state of the signal lines STB,XXL,BLC,BLS,HLL,BLX (Figure 11) is set to "L,L,L,L,L,L". This electrically disconnects the sense node SEN from the bit line BL. Also, the supply of current to the bit line BL is terminated.

[0156] Although not shown in the diagram, at a predetermined timing after the readout timing t106, the wiring LBUS is charged by the charging transistor 55 (Figure 11), and then the signal line STB is temporarily set to the "H" state. Here, the sense transistor 41 is either ON or OFF depending on the charge of the sense node SEN. Therefore, the voltage of the wiring LBUS is either "H" or "L" depending on the charge of the sense node SEN. After that, the latch circuit SDL or latch circuits DL0~DLn L The data from the wiring LBUS is latched by one of the following methods.

[0157] At the timing t108 of the read operation, the selected word line WL S , non-selected word line WL U And ground voltage V is applied to the selected gate lines (SGD, SGS, SGSb) SS To supply.

[0158] Furthermore, in Figure 26, during the reading operation, the selected word line WL S One read voltage V CGDR An example was described in which only the data is supplied and the sense operation is performed once in this state. Such an operation is performed, for example, when the data is allocated in the manner shown in Figure 24(b) and the data of the lower bits is to be determined.

[0159] For example, when determining the data of the middle bit, the selection word line WL S Read voltage V CGAR The signal is supplied, and in this state, the sense operation is performed once. Also, the selected word line WL S Read voltage V CGCR The signal is supplied, and in this state, the sense operation is performed once. Also, the selected word line WL S Read voltage V CGFR The signal is supplied, and in this state, the sense operation is performed once.

[0160] For example, when determining the data of the higher bits, the selection word line WL is used. S Read voltage V CGBR The signal is supplied, and in this state, the sense operation is performed once. Also, the selected word line WL S Read voltage V CGER The signal is supplied, and in this state, the sense operation is performed once. Also, the selected word line WL S Read voltage V CGGR The signal is supplied, and in this state, the sense operation is performed once.

[0161] [Variations in wiring resistance during readout operations] As explained with reference to Figures 15 and 17, the conductive layers 200 and 220 have two memory hole regions R MHIt comprises two parts 201 and 221 provided therein, and parts 202 and 222 connected to both of these two parts 201 and 221. Furthermore, the two parts 201 and 221 are electrically connected via parts 202 and 222.

[0162] Furthermore, as explained with reference to Figures 16 and 18, the two conductive layers 210 or two conductive layers 230 aligned in the X direction are spaced apart in the X direction and are electrically connected via contact CC and wiring m0a, m1a.

[0163] Here, the multiple conductive layers 110 contain heat-resistant materials such as tungsten (W) and molybdenum (Mo) for manufacturing purposes. On the other hand, the wirings m0a and m1a contain highly conductive materials such as copper (Cu). In such a configuration, for example, the wiring resistance between two portions 201 of the conductive layer 200, and the wiring resistance between two portions 221 of the conductive layer 220, is greater than the wiring resistance between two conductive layers 210 aligned in the X direction, and the wiring resistance between two conductive layers 230 aligned in the X direction.

[0164] Furthermore, due to differences in connection structure and wiring materials as described above, unusual differences may occur between the wiring resistance between the division range DU1 of the word line WL and the word line switch WLSW, and between the wiring resistance between the division range DU2 of the word line WL and the word line switch WLSW.

[0165] For example, the third conductive layer 200 from the negative side in the Y direction, as shown in Figure 15, is in the hookup region R HU2 It is connected to contact CC at the positive X-direction position. Also, the narrow portion 110 of the conductive layer 200 C4T This is the hookup region R HU2 It is provided on the negative side in the X direction. Also, the narrow portion 110 of the conductive layer 200 CC2 This is the hookup region R HU2 It is located on the positive side in the X direction. In this case, the wiring resistance between the divided area (e.g., divided area DU1) on the negative side in the X direction of the conductive layer 200 (word line WL) and the word line switch WLSW is defined as the wiring resistance RW (1) The wiring resistance between the divided area on the positive X side of the conductive layer 200 (word line WL) (e.g., divided area DU2) and the word line switch WLSW is defined as the wiring resistance R W (2) If so, the wiring resistance R W (1) and wiring resistance R W The resistance values ​​in (2) will be approximately the same. For example, the wiring resistance R W (1), R W (2) The wiring resistance R of the word line WL135 in Figures 27 and 28A, which will be described later. W135(1) ,R W135(2) It corresponds to.

[0166] Furthermore, for example, the first conductive layer 220 counting from the negative side in the Y direction shown in Figure 17 is in the hook-up region R HU2 It is connected to contact CC at the central position in the X direction. Also, the narrow portion 110 of the conductive layer 220 CC2 This is the hookup region R HU2 It is provided on the negative side in the X direction. Also, the narrow portion 110 of the conductive layer 220 C4T This is the hookup region R HU2 It is located on the positive side in the X direction. The width of the conductive layer 220 is the narrow portion 110 C4T Narrower part 110 CC2 It is narrower. Also, the narrow part is 110 C4T Narrower part 110 CC2 This is longer. In this case, the wiring resistance between the divided area on the negative X side of the conductive layer 220 (word line WL) (e.g., divided area DU1) and the word line switch WLSW is the wiring resistance R. W (11) The wiring resistance between the divided area on the positive X side of the conductive layer 220 (word line WL) (e.g., divided area DU2) and the word line switch WLSW is defined as the wiring resistance R W (12) If so, the wiring resistance R W (11) The resistance value is the wiring resistance R W (12) is greater than the resistance value. Note that the wiring resistance R W (11), R W The difference in resistance values ​​in (12) is large. For example, the wiring resistance R W (11), R W(12) The wiring resistance R of the word line WL156 in Figures 27 and 28A, which will be described later. W156(1) ,R W156(2) It corresponds to.

[0167] Note that the narrow section 110 in Figure 17 CC2 This is called the third range, and the narrow part 110 in Figure 17 C4T This is sometimes referred to as the fourth range.

[0168] Furthermore, for example, the fourth conductive layer 230 from the positive side in the Y direction shown in Figure 18 is in the hook-up region R HU2 It is connected to two contacts CC at the negative X-direction position and the central position. Furthermore, the two contacts CC are connected to contact C4 via wiring m0a of wiring layer M0. In this case, the wiring resistance between the divided area (e.g., divided area DU1) on the negative X-direction side of the conductive layer 230 (word line WL) and the word line switch WLSW is defined as wiring resistance R. W (21) The wiring resistance between the divided area on the positive X side of the conductive layer 230 (word line WL) (for example, divided area DU2) and the word line switch WLSW is defined as the wiring resistance R W (22) If so, the wiring resistance R W (21) The resistance value is the wiring resistance R W (22) is smaller than the resistance value. Note that the wiring resistance R W (21), R W The difference in resistance values ​​in (22) is large. For example, the wiring resistance R W (21), R W (22) The wiring resistance R of the word line WL157 in Figures 27 and 28A, which will be described later. W157(1) ,R W157(2) It corresponds to.

[0169] In this way, the wiring resistance R between the divided ranges DU1 and DU2 and the word line switch WLSW is W If a difference occurs, during the read operation, a selected memory cell MC that should be determined to be in the OFF state may be determined to be in the ON state, for example.

[0170] [Adjusting operating parameters] [Select word line WL]S [Adjusting the operating parameters] Selection word line WL in read operation S The operating parameters are the waiting time Ta in Figure 26 and the selected word line WL between timings t101 and t102 in Figure 26. S This includes the voltage Va supplied to it. The voltage Va is the read voltage (in the example in Figure 26, the read voltage V CGDR It has a size greater than or equal to ).

[0171] Figure 27 shows the selection word line WL according to the first embodiment. S This is a schematic diagram illustrating the adjustment of the operating parameters. Word lines WL135, WL156, and WL157 in Figure 27 correspond to word line WLn-1 in Figure 4 when n is 136, 157, and 158. Also, "8k" in Figure 27 indicates that the storage capacity of the division ranges DU1 and DU2 of each word line WL135, WL156, and WL157 is 8k bytes each. Therefore, the number of memory cells MC corresponding to the storage capacity of 8k bytes to be read is connected to the division ranges DU1 and DU2 of each word line WL135, WL156, and WL157. From this, it can be seen that the number of memory cells MC corresponding to the storage capacity of 16k bytes to be read is connected to each word line WL135, WL156, and WL157. Note that the values ​​in Figure 27 are just examples and are not limited to these values.

[0172] As shown in Figure 27, each word line WL135, WL156, and WL157 is connected to the CG driver circuit DRV via the word line switch WLSW and wiring CG. A word line decoder WLD and the like are provided between the word line switch WLSW and the CG driver circuit DRV (Figure 5), but they are omitted in Figure 27. The CG driver circuit DRV performs voltage supply operations to the word lines WL (wiring CG) according to the control signal SGL0 from the sequencer SQC. The control signal SGL0 includes the signals of the signal lines VSEL1 to VSEL6 in Figure 5.

[0173] Wiring resistance R W135(1) ,R W156(1),R W157(1) These are the resistances of the various wirings and contact CC between the division range DU1 of the word lines WL135, WL156, and WL157 and the word line switch WLSW, respectively. Also, the wiring resistance R W135(2) ,R W156(2) ,R W157(2) These are the resistances of the various wires and contact CC between the division range DU2 of the word lines WL135, WL156, and WL157 and the word line switch WLSW, respectively. For example, the wiring resistance R W135(1) ,R W135(2) ,R W156(2) ,R W157(2) This is the resistance value of the medium (indicated as "Medium" in the diagram). Wiring resistance R W156(1) This represents the large resistance value (indicated as "Large" in the diagram). Wiring resistance R W157(1) This represents the small resistance value (indicated as "Small" in the diagram).

[0174] As described above, a single word line WL (divided range DU1, DU2) is supplied with the same voltage at the same time. In this case, the selected word line WL S The operating parameters (wait time Ta, voltage Va) are adjusted in units of word line WL.

[0175] For example, the selected word line WL S The wiring resistance R W For small word lines WL (for example, word line WL157 in Figure 27), select word line WL S The wiring resistance R W Compared to the case of a moderate word line WL (for example, word line WL135 in Figure 27), the waiting time Ta is shortened and the voltage Va is reduced. Also, the selected word line WL S The wiring resistance R W For large word lines WL (for example, word line WL156 in Figure 27), select word line WL S The wiring resistance R W Compared to the case of a medium-sized word line WL (for example, word line WL135 in Figure 27), the waiting time Ta is increased and the voltage Va is increased. Note that the selected word line WL SEither one of the operating parameters (wait time Ta, voltage Va) may be adjusted. By adjusting such operating parameters, the selected word line WL may be affected during the read operation. S Wiring resistance R W Depending on the selected word line WL S It is possible to perform proper charging. That is, the selected word line WL S In contrast, the wiring resistance R W This allows for the supply of an appropriate voltage, preventing overcharging or undercharging. As a result, the reliability of the read operation is improved.

[0176] Furthermore, in Figure 27, if one of the two division ranges DU1 and DU2 of the word line WL is not to be read, and only the other is to be read, then the selected word line WL S The wiring resistance R of the division range to be read out W Depending on the selected word line WL S You may also adjust the operating parameters (waiting time Ta, voltage Va).

[0177] [Adjustment of operating parameters for bit line BL and source lines SL1, SL2] The operating parameters of bit line BL in the read operation include the waiting time Tb in Figure 26, the voltage Vb supplied to bit line BL between timings t104 and t105 in Figure 26, the waiting time Tc in Figure 26, and the waiting time Td in Figure 26.

[0178] Furthermore, the operating parameters of source lines SL1 and SL2 during the readout operation are the waiting time Ts shown in Figure 26, and the voltage V supplied to source lines SL1 and SL2 between timings t103 and t105 shown in Figure 26. S It includes.

[0179] Figure 28A is a schematic diagram illustrating the adjustment of the operating parameters of the bit line BL and source lines SL1 and SL2 according to the first embodiment. The meanings of the word lines WL135, WL156, WL157 and "8k" in Figure 28A are the same as those explained in Figure 27. Also, the wiring resistance R of the word lines WL135, WL156, WL157 in Figure 28A. W Its size is the same as that explained in Figure 27.

[0180] As shown in Figure 28A, bit line BL in division range DU1 is connected to sense amplifier module SAM(1). Bit line BL in division range DU2 is connected to sense amplifier module SAM(2). Sense amplifier module SAM(1) performs voltage supply and sensing operations on bit line BL according to control signal SGL1 from sequencer SQC. Sense amplifier module SAM(2) performs voltage supply and sensing operations on bit line BL according to control signal SGL2 from sequencer SQC. Both control signals SGL1 and SGL2 include signals for signal lines STB, XXL, BLC, BLS, HLL, BLX, CLKSA, and LBP.

[0181] The sense time (waiting time Td in Figure 26) is controlled by the signal on signal line XXL. A typical method of separation control is as follows: There is a wire through which the XXL signal passes (signal line XXL1 in Figure 28B) connecting the sequencer SQC and the sense amplifier module SAM(1), and a wire through which the XXL signal passes (signal line XXL2 in Figure 28B) connecting the sequencer SQC and the sense amplifier module SAM(2). The sequencer SQC separates and controls the signal on signal line XXL1 included in the control signal SGL1 and the signal on signal line XXL2 included in the control signal SGL2.

[0182] Furthermore, as shown in Figure 28A, source line SL1 corresponding to division range DU1 is connected to source line driver circuit SDRV(1). Source line SL2 corresponding to division range DU2 is connected to source line driver circuit SDRV(2). Source line driver circuit SDRV(1) performs voltage supply operation to source line SL1 according to control signal SGL11 from sequencer SQC. Source line driver circuit SDRV(2) performs voltage supply operation to source line SL2 according to control signal SGL12 from sequencer SQC.

[0183] Waiting time Ts and voltage V S (Figure 26) is controlled by the source line driver circuit SDRV. The sequencer SQC controls the waiting time Ts and voltage Vs of the source line SL in division range DU1 and the waiting time Ts and voltage Vs of the source line SL in division range DU2 separately by separating and controlling the signals included in the control signal SGL11 and the signals included in the control signal SGL12. Alternatively, the operating parameters of the source line SL may be controlled in conjunction with the operating parameters of the bit line BL. Or, the operating parameters of the bit line BL may be controlled in conjunction with the operating parameters of the source line SL. In this case, the operating parameters of the bit line BL are controlled by controlling the signals of the signal lines BLC, BLX, etc.

[0184] As described above, multiple bit lines BL included in the division range DU1 can be supplied with different voltages at different timings. In this case, the operating parameters of the bit lines BL (wait time Tb, voltage Vb, wait time Tc, wait time Td) are adjusted in units of the division ranges DU1 and DU2 of the word line WL.

[0185] For example, the selected word line WL S If it is the word line WL157, then the division range DU1 of that word line WL157 is the wiring resistance R of the "small" range. W157(1)The operating parameters (wait time Tb, voltage Vb, wait time Tc, wait time Td) of the bit line BL in the division range of the word line WL157 are defined as the "intermediate" wiring resistance R W157(2) Compared to the operating parameters of the bit line BL (within the division range), the waiting time Tb is shortened, the voltage Vb is reduced, the waiting time Tc is increased, and the waiting time Td (sense time) is increased.

[0186] Also, the selected word line WL S If the word line is WL156, then the division range DU1("large" wiring resistance R of that word line WL156) W156(1) The operating parameters of bit line BL in the division range of word line WL156 are set to the wiring resistance R in the division range DU2 ("middle"). W156(2) Compared to the operating parameters of the bit line BL (within the division range), the waiting time Tb is increased, the voltage Vb is increased, the waiting time Tc is increased, and the waiting time Td (sense time) is decreased.

[0187] Furthermore, one or more of the operating parameters of the bit line BL (wait time Tb, voltage Vb, wait time Tc, wait time Td) may be adjusted. By adjusting such operating parameters, the selection word line WL may be affected during the read operation. S Wiring resistance R in the division range DU1, DU2 W Accordingly, it is possible to perform appropriate charging and sensing operations on the bit lines BL belonging to the division ranges DU1 and DU2. As a result, the reliability of the read operation is improved.

[0188] Furthermore, as described above, source line SL1 and source line SL2, which correspond to division range DU1, can supply different voltages at different timings. In this case, the operating parameters (wait time Ts, voltage Vs) of source lines SL1 and SL2 are adjusted in units of division ranges DU1 and DU2 of word line WL.

[0189] For example, the selected word line WL S If it is the word line WL157, then the division range DU1 of that word line WL157 is the wiring resistance R of the "small" range. W157(1)The operating parameters (wait time Ts, voltage Vs) of source line SL1 in the division range of word line WL157 are defined as the "intermediate" wiring resistance R W157(2) The operating parameters of source line SL2 (within the division range) are set to reduce the waiting time Ts and voltage Vs.

[0190] Also, the selected word line WL S If the word line is WL156, then the division range DU1("large" wiring resistance R of that word line WL156) W156(1) The operating parameters of source line SL1 (within the division range) and the wiring resistance R of word line WL156 (within the division range DU2) W156(2) The operating parameters of source line SL2 (within the division range) are increased by making the waiting time Ts longer and the voltage Vs larger.

[0191] Furthermore, it is also possible to adjust only one of the operating parameters (wait time Ts, voltage Vs) of source lines SL1 and SL2. By adjusting such operating parameters, the selected word line WL can be controlled during the read operation. S Wiring resistance R in the division range DU1, DU2 W Accordingly, it is possible to properly charge source lines SL1 and SL2 belonging to division ranges DU1 and DU2. As a result, the reliability of the read operation is improved.

[0192] [Second Embodiment] Next, a semiconductor memory device according to the second embodiment will be described with reference to Figure 29. Figure 29 is a timing chart for explaining the read operation of the semiconductor memory device.

[0193] In the first embodiment, the method for performing the read operation was illustrated with reference to Figures 26 to 28. However, this method is merely illustrative, and the method for performing the read operation can be adjusted as appropriate.

[0194] For example, the semiconductor memory device according to the second embodiment is basically configured in the same way as the semiconductor memory device according to the first embodiment. Also, the read operation according to the second embodiment is basically performed in the same way as the read operation according to the first embodiment.

[0195] However, in the read operation according to the second embodiment, at timing t101, the selected word line WL S Read path voltage V READ It will be supplied.

[0196] Furthermore, in the read operation according to the second embodiment, at timing t102, the selected word line WL S The read voltage (in the example in Figure 29, the read voltage V CGDR The following voltage Ve is supplied:

[0197] Furthermore, in the read operation according to the second embodiment, a waiting time Te is provided between timings t102 and t103. The waiting time Te is, for example, the selected word line WL S This is the waiting time for the charge to discharge.

[0198] Furthermore, in the reading operation according to the second embodiment, at timing t103, the selected word line WL S A read voltage is supplied to it.

[0199] Selection word line WL according to the second embodiment S The operating parameters include, for example, a waiting time Te. Also, the selected word line WL according to the second embodiment. S The operating parameters include, for example, the selection of the word line WL between timings t102 and t103. S This includes the voltage Ve supplied to it. The latency Te and voltage Ve are adjusted in units of word line WL.

[0200] For example, the selected word line WL S The wiring resistance R W For small word lines WL (for example, word line WL157 in Figure 27), select word line WLS The wiring resistance R W Compared to the case of a medium word line WL (for example, word line WL135 in Figure 27), the waiting time Te is shortened and the voltage Ve is increased. Also, the selected word line WL S The wiring resistance R W For large word lines WL (for example, word line WL156 in Figure 27), select word line WL S The wiring resistance R W Compared to the case of a medium-sized word line WL (for example, word line WL135 in Figure 27), the waiting time Te is increased and the voltage Ve is decreased. Note that the selected word line WL S Either one of the operating parameters (wait time Te, voltage Ve) may be adjusted. By adjusting such operating parameters, the selected word line WL may be affected during the read operation. S Wiring resistance R W Depending on the selected word line WL S This allows for proper discharge of the charge, resulting in improved reliability of the readout operation.

[0201] Furthermore, in Figure 27, if one of the two division ranges DU1 and DU2 of the word line WL is not to be read, and only the other is to be read, then the selected word line WL S The wiring resistance R of the division range to be read out W Depending on the selected word line WL S You may also adjust the operating parameters (wait time Te, voltage Ve).

[0202] [Third Embodiment] Next, a semiconductor memory device according to the third embodiment will be described with reference to Figures 30 to 34.

[0203] The first and second embodiments described examples of adjusting the operating parameters used for read operations. In contrast, the third embodiment describes an example of adjusting the operating parameters used for write operations.

[0204] The semiconductor memory device according to the third embodiment is basically configured the same as the semiconductor memory device according to the first or second embodiment. Furthermore, when performing a read operation of the semiconductor memory device according to the third embodiment, the operating parameters may be adjusted in the same manner as in the first or second embodiment, or they may not be adjusted.

[0205] [Writing operation] Next, the writing operation of the semiconductor memory device according to this embodiment will be described.

[0206] Figure 30 is a flowchart illustrating the write operation. Figure 31 is a schematic cross-sectional view illustrating the program operation included in the write operation. Figure 32 is a schematic cross-sectional view illustrating the verify operation included in the write operation. Figures 33 and 34 are timing charts illustrating the write operation.

[0207] In step S101, for example, as shown in Figure 30, the number of loops n W This is set to 1. Loop count n W This is a variable that indicates the number of write loops. Also, for example, the latch circuits DL0~DLn of the sense amplifier unit SAU (Figure 11) L The user data written to the memory cell MC is then latched.

[0208] In step S102, a program operation is executed. The program operation is performed by selecting the word line WL. S This operation involves supplying a program voltage to increase the threshold voltage of the memory cell MC. This operation is performed, for example, from timing t121 to timing t125 in Figure 33.

[0209] At the program operation timing t121, for example, the bit line BL connected to the memory cell MC that adjusts the threshold voltage among multiple selected memory cells is used. W Voltage V SRCThe bit line BL is connected to one of the multiple select memory cells MC that does not undergo threshold voltage adjustment, and supplies the current. P Voltage V DD It supplies bit lines BL. W The corresponding latch circuit SDL (Figure 11) latches "L", and the bit line BL P The corresponding latch circuit SDL (Figure 11) is latched to "H". Also, the state of the signal lines STB, XXL, BLC, BLS, HLL, and BLX is set to "L,L,H,H,L,H". Hereafter, among the multiple selectable memory cells MC, those that adjust the threshold voltage are sometimes called "write memory cells MC", and those that do not adjust the threshold voltage are sometimes called "prohibition memory cells MC".

[0210] At program execution timing t122, the selected word line WL S and non-selected word line WL U Write path voltage V PASS A voltage V is supplied. Also, a voltage V is applied to the drain-side selected gate line SGD. SGD The following is supplied: Write path voltage V PASS For example, the read path voltage V explained with reference to Figure 24. READ It has the above size. Voltage V SGD The voltage V is explained with reference to Figures 25 and 26. SG It is smaller than that, and has a size such that the drain-side selection transistor STD turns ON or OFF depending on the voltage of the bit line BL.

[0211] At program execution timing t123, the selected word line WL S Program voltage V PGM It supplies the program voltage V. PGM The write path voltage V PASS It is larger than that.

[0212] Here, for example, as shown in Figure 31, bit line BL W The channel of the semiconductor layer 120 connected to it has a voltage V SRC Such a semiconductor layer 120 and a selected word line WL are supplied. SA relatively large electric field is generated between the two. As a result, electrons in the channel of the semiconductor layer 120 tunnel through the tunnel insulating film 131 (Figure 21) into the charge storage film 132 (Figure 21). This increases the threshold voltage of the write memory cell MC.

[0213] Also, bit line BL P The channel of the semiconductor layer 120 connected to it is electrically floating, and the potential of this channel is the non-selected word line WL U Capacitive coupling with the write path voltage V PASS It has risen to this extent. Such a semiconductor layer 120 and selected word line WL S Only an electric field smaller than any of the above-mentioned electric fields is generated between them. Therefore, electrons in the channel of the semiconductor layer 120 do not tunnel into the charge storage film 132 (Figure 21). Consequently, the threshold voltage of the disabled memory cell MC does not increase.

[0214] A waiting time Tf is provided between timings t123 and t124 of the program operation. The waiting time Tf is, for example, a waiting time to increase the threshold voltage of the write memory cell MC.

[0215] At program execution timing t124, the selected word line WL S and non-selected word line WL U Write path voltage V PASS To supply.

[0216] At program operation timing t125, the selected word line WL S , non-selected word line WL U And ground voltage V is applied to the selected gate lines (SGD, SGS, SGSb) SS To supply.

[0217] In step S103 (Figure 30), a verification operation is performed.

[0218] At the verification timing t131, for example, as shown in Figure 33, the selected word line WLS and non-selected word line WL U Read path voltage V READ The voltage V is supplied to turn on all memory cells (MC). Additionally, the voltage V is applied to the selected gate lines (SGD, SGS, SGSb). SG The system supplies power to turn on the selector transistors (STD, STS, STSb).

[0219] At the verification timing t132, the selected word line WL S Then, a predetermined verification voltage (verification voltage V as explained in Figure 24) is used. VFYA ~V VFYG This supplies either of the following: As a result, some of the selected memory cells MCs become ON, and the remaining selected memory cells MCs become OFF, as shown in Figure 32, for example.

[0220] Furthermore, at timing t132, for example, the bit line BL is charged. In this case, for example, latch circuits DL0~DLn L Based on the data inside, the bit line BL connected to the memory cell MC (in the example of Figure 33, the bit line BL) corresponds to a specific state (in the example of Figure 33, state A). A ) with voltage V DD It supplies voltage V to the other bit lines BL. SRC To supply.

[0221] During the verification operation timing t133 to t134, a sense operation is performed, for example, as shown in Figure 33. At this time, latch circuits DL0 to DLn L The memory cell MC may also be latched with data indicating its ON / OFF state.

[0222] During the verification operation at timings t135 to t137, the same processing as at timings t132 to t134 is performed on memory cells MC in other states (state B in the example in Figure 33). Note that in Figure 33, the bit line BL connected to the memory cell MC corresponding to state B is referred to as bit line BL B It states that.

[0223] During the verification operation at timings t138 to t140, the same processing as at timings t132 to t134 is performed on memory cells MC of other states (C state in the example in Figure 33). Note that in Figure 33, the bit line BL connected to the memory cell MC corresponding to the C state is referred to as bit line BL C It states that.

[0224] At timing t141, the selected word line WL S and non-selected word line WL U Read path voltage V READ The voltage V is supplied to turn on all memory cells (MC). Additionally, the voltage V is applied to the selected gate lines (SGD, SGS, SGSb). SG The system supplies power to turn on the selector transistors (STD, STS, STSb).

[0225] At the verification timing t142, the selected word line WL S , non-selected word line WL U And ground voltage V is applied to the selected gate lines (SGD, SGS, SGSb) SS To supply.

[0226] Subsequently, the data latched by the latch circuit SDL is transferred to a counter circuit (not shown). The counter circuit counts the number of memory cells MC whose threshold voltage has reached the target value, or the number of memory cells MC whose threshold voltage has not reached the target value.

[0227] In the example shown in Figure 33, the selected word line WL is used during the verification operation. S Three different verification voltages V VFYA ,V VFYB ,V VFYC An example of supplying this was shown. However, in the verification operation, the selected word line WL S The number of verification voltages supplied may be two or fewer, or four or more, or, for example, as illustrated in Figure 34, the number of loops n W It may change accordingly.

[0228] In step S104 (Figure 30), the result of the verification operation is determined. For example, by referring to the counter circuit described above, if the number of memory cells MCs whose threshold voltage has not reached the target value is greater than or equal to a certain number, the verification is determined to be FAIL and the process proceeds to step S105. On the other hand, if the number of memory cells MCs whose threshold voltage has not reached the target value is less than or equal to a certain number, the verification is determined to be PASS and the process proceeds to step S107.

[0229] In step S105, the number of loop iterations is n. W a predetermined number of times N W Determine whether the condition has been met. If it has not been met, proceed to step S106. If it has been met, proceed to step S108.

[0230] In step S106, the number of loop iterations is n. W Add 1 to it and proceed to step S102. Also, in step S106, for example, the program voltage V PGM A predetermined voltage dV is added to it. Therefore, as shown in Figure 34, for example, the program voltage V PGM The number of loop iterations is n. W It increases along with the increase of [something].

[0231] In step S107, status data D, indicating that the write operation was completed successfully, is stored in the status register STR (Figure 2). ST Store the data and terminate the write operation. Note that status data D ST This is output to the controller die CD (Figure 1) in response to the status read operation.

[0232] In step S108, status data D is entered into the status register STR (Figure 2) indicating that the write operation did not complete successfully. ST Store the data and terminate the write operation.

[0233] [Variations in wiring resistance during writing operations] As described above, the wiring resistance between two portions 201 of the conductive layer 200 (Figure 15), and the wiring resistance between two portions 221 of the conductive layer 220 (Figure 17) are greater than the wiring resistance between two conductive layers 210 (Figure 16) aligned in the X direction, and the wiring resistance between two conductive layers 230 (Figure 18) aligned in the X direction.

[0234] Furthermore, due to differences in connection structure and wiring materials as described above, unusual differences may occur between the wiring resistance between the division range DU1 of the word line WL and the word line switch WLSW, and between the wiring resistance between the division range DU2 of the word line WL and the word line switch WLSW.

[0235] In this case, the threshold voltage of the selected memory cell MC may increase unnecessarily during the writing operation.

[0236] [Select word line WL] S [Adjusting the operating parameters] The selected word line WL during the writing operation. S The operating parameters are the waiting time Tf in Figure 33 and the program voltage V in Figure 34. PGM Initial voltage Vf (loop count n) W Program voltage V when is 1 PGM ) is included.

[0237] For example, the selected word line WL S The wiring resistance R W For small word lines WL (for example, word line WL157 in Figure 27), select word line WL S The wiring resistance R W Compared to the case of a moderate word line WL (for example, word line WL135 in Figure 27), the waiting time Tf is shortened and the voltage Vf is reduced. Also, the selected word line WL S The wiring resistance R W For large word lines WL (for example, word line WL156 in Figure 27), select word line WL S The wiring resistance R WCompared to the case of a medium word line WL (for example, word line WL135 in Figure 27), the waiting time Tf is made longer and the voltage Vf is made larger. Note that the selected word line WL in the writing operation S You may adjust only one of the operating parameters (wait time Tf, voltage Vf). By adjusting such operating parameters, the selected word line WL may be affected during the writing operation. S Wiring resistance R W Accordingly, it is possible to suppress the increase in the threshold voltage of the selected memory cell MC. As a result, the reliability of the write operation is improved.

[0238] Furthermore, in Figure 27, if one of the two divisional ranges DU1 and DU2 of the word line WL is not the target of writing, and only the other is the target of writing, then the wiring resistance R of the divisional range to be read in the selected word line WLS W Depending on the situation, the operating parameters of the selected word line WLS (wait time Tf, voltage Vf) may be adjusted.

[0239] [Fourth Embodiment] Next, with reference to Figure 35, a semiconductor memory device according to the fourth embodiment will be described. Figure 35 is a timing chart for illustrating the writing operation of the semiconductor memory device.

[0240] In the third embodiment, the method for performing the write operation is illustrated with reference to Figures 30 to 34. However, this method is merely illustrative, and the method for performing the write operation can be adjusted as appropriate.

[0241] For example, the semiconductor memory device according to the fourth embodiment is basically configured the same as the semiconductor memory device according to the third embodiment. However, the write operation according to the fourth embodiment is different from the write operation according to the third embodiment. The write operation according to the fourth embodiment is basically performed the same as the write operation according to the third embodiment.

[0242] However, in the writing operation according to the fourth embodiment, at timing t132, the selected word line WL SThe verification voltage used first in the verification operation (in the example in Figure 35, the verification voltage V) VFYA ) or a lower voltage is supplied.

[0243] Furthermore, in the writing operation according to the fourth embodiment, a waiting time Te' is provided between timings t132 and t231. The waiting time Te' is, for example, the selected word line WL S This is the waiting time for the charge to discharge.

[0244] Furthermore, in the writing operation according to the fourth embodiment, at timings t231, t233, and t235, the selected word line WL S The verification voltage (in the example in Figure 35, the verification voltage V) VFYA ,V VFYB ,V VFYC ) will be supplied.

[0245] Furthermore, in the writing operation according to the fourth embodiment, a waiting time Tb' is provided between timings t132 to t232, between timings t135 to t234, and between timings t138 to t236. The waiting time Tb' is, for example, a waiting time to converge the current of the bit line BL.

[0246] Furthermore, in the writing operation according to the fourth embodiment, the voltage of the signal line BLC (voltage of the bit line BL) is reduced at timings t232, t234, and t236. At this time, the voltage of the signal line BLC is adjusted to a voltage that keeps the clamp transistor 44 (Figure 11) connected to the signal line BLC in the ON state.

[0247] Furthermore, in the writing operation according to the fourth embodiment, a waiting time Tc' is provided between timings t232 to t133, between timings t234 to t136, and between timings t236 to t139. The waiting time Tc' is, for example, a waiting time to stabilize the current of the bit line BL. Hereinafter, the waiting time Tc' may be referred to as the "stabilization waiting time".

[0248] Furthermore, in the writing operation according to the fourth embodiment, a waiting time Td' is provided between timings t133 to t134, between timings t136 to t137, and between timings t139 to t140. The waiting time Td' is, for example, a waiting time for detecting the state of the memory cell MC. Hereinafter, the waiting time Td' may be referred to as the "sense time".

[0249] Furthermore, in the writing operation according to the fourth embodiment, at timings t135 and t138, the selected word line WL S In the verification operation, the verification voltage used next is (in the example in Figure 35, the verification voltage V) VFYB ,V VFYC ) or a higher voltage is supplied.

[0250] Furthermore, in the writing operation according to the fourth embodiment, a waiting time Ta' is provided between timings t135 to t233 and between timings t138 to t235. The waiting time Ta' is, for example, the selected word line WL S This is the waiting time for charging.

[0251] Furthermore, the selected word line WL in the writing operation according to the fourth embodiment. S The operating parameters are adjusted in units of word lines WL. In addition, the operating parameters of bit lines BL in the writing operation according to the fourth embodiment are adjusted in units of the division ranges DU1 and DU2 of the word lines WL.

[0252] Selection word line WL in the writing operation according to the fourth embodiment S The operating parameters include, for example, delay times Ta' and Te'. In addition, the operating parameters of bit line BL in the write operation according to the fourth embodiment include delay times Tb', Tc', and Td'.

[0253] By adjusting the waiting time Ta' in the operating parameters, the selected word line WL can be changed. S It is possible to suppress excessive charging. Also, by adjusting the waiting time Tb' in the operating parameters, the selected word line WL can be controlled. S It is possible to suppress the current in the bit line BL to the extent that the effects of excessive charging are canceled out. Furthermore, by adjusting the waiting time Tc' in the operating parameters, the selected word line WL can be controlled. S It is possible to stabilize the cell current to the extent that the effects of excessive charging are canceled out. Furthermore, by adjusting the waiting time Td' (sense time) in the operating parameters, the amount of charge reduction at the sense node SEN can be controlled by the selected word line WL. S It is possible to suppress the effects of excessive charging to the extent that they are negated. Furthermore, by adjusting the waiting time Te' in the operating parameters, the selected word line WL can be controlled. S It is possible to suppress excessive discharge.

[0254] Furthermore, the selected word line WL during the writing operation. S The operating parameters include, for example, the selection of the word line WL between timings t132 and t231. S This includes the voltage supplied to it. By adjusting this operating parameter, the selected word line WL S It is possible to suppress excessive discharge.

[0255] Furthermore, the operating parameters of the bit line BL during the write operation include, for example, the voltage supplied to the signal line BLC (the voltage of the bit line BL) between timings t132 and t232. By adjusting these operating parameters, the selected word line WL SIt is possible to increase the current in the bit line BL to the extent that the effects of excessive discharge are canceled out.

[0256] Furthermore, the operating parameters of the bit line BL during the write operation include, for example, the voltage supplied to the signal line BLC (the voltage of the bit line BL) between timings t135 to t234 and between timings t138 to t236. By adjusting these operating parameters, the selection word line WL S It is possible to suppress the current in the bit line BL to the extent that the effects of excessive charging are canceled out.

[0257] Furthermore, the selected word line WL during the writing operation. S The operating parameters include, for example, the selection word line WL between timing t135 and timing t233, and between timing t138 and timing t235. S This includes the voltage supplied to it. By adjusting this operating parameter, the selected word line WL S It is possible to prevent excessive charging.

[0258] [Fifth Embodiment] Next, a semiconductor memory device according to the fifth embodiment will be described.

[0259] [Memory die MD structure] Figure 36 is a schematic exploded perspective view showing an example configuration of a semiconductor memory device according to this embodiment. As shown in Figure 36, the memory die MD is located on the chip C on the memory cell array MCA side. M And, the peripheral circuit PC side chip C P It is equipped with the following.

[0260] Chip C M On the upper surface are multiple external pad electrodes P (not shown) that can be connected to bonding wires. X A chip C is provided. M On the lower surface, there are multiple bonded electrodes P I1 A chip C is provided. P On the upper surface, there are multiple bonded electrodes P I2A chip C is provided below. M Regarding this, multiple bonded electrodes P I1 The surface on which the multiple external pad electrodes P are provided is called the surface, and X The side on which this is provided is called the back side. Also, chip C P Regarding this, multiple bonded electrodes P I2 The surface on which the chip is provided is called the front surface, and the surface opposite the front surface is called the back surface. In the illustrated example, chip C P The surface is chip C P It is located above the back surface, and chip C M The back side is chip C M It is positioned above the surface.

[0261] Chip C M and chip C P This is chip C M Surface and chip C P Multiple bonded electrodes P are arranged so as to face each other on the surface. I1 This is a plurality of bonded electrodes P I2 Multiple adhesive electrodes P are provided, corresponding to each of them. I2 It is positioned in a location where it can be bonded. Bonding electrode P I1 and bonded electrode P I2 This refers to chip C M and chip C P It functions as a bonding electrode for bonding two materials together and for electrical conductivity.

[0262] Furthermore, in the example shown in Figure 36, chip C M The corners a1, a2, a3, and a4 are, respectively, chip C P These correspond to corners b1, b2, b3, and b4.

[0263] Figure 37 shows chip C M This is a schematic bottom view showing an example of the configuration. Figure 37 shows the bonded electrode P I1 Some components of the structure are omitted. Figures 38 and 39 are schematic cross-sectional views showing some components of the memory die MD. Figure 40 shows chip C P This is a schematic plan view showing an example of the configuration. Figure 40 shows the bonded electrode P I2 Some of the components have been omitted.

[0264] [Chip C M [Structure] In the example shown in Figure 37, chip C M It comprises four memory planes MP aligned in the X direction. Each of these four memory planes MP comprises multiple memory blocks BLK aligned in the Y direction. In the example in Figure 37, each of the multiple memory blocks BLK has a hookup region R provided at both ends in the X direction. HU3 And the memory hole region R provided between these MH3 It also includes the memory hole region R in the example shown in Figure 37. MH3 There are two regions R in the X direction MH3U It is divided into these two regions R MH3U The widths in the X direction can all be the same or they can not be the same. Note that there are two regions R MH3U One of them corresponds to division range DU1, and the other corresponds to division range DU2. Also, chip C M This is a peripheral region R located on one end in the Y direction, beyond the four memory planes MP. P It is equipped with.

[0265] Note that in the illustrated example, the hookup region R HU3 These are provided at both ends of the memory plane MP in the X direction. However, this configuration is merely illustrative, and the specific configuration can be adjusted as appropriate. For example, the hookup region R HU3 The hook-up region R may be located at one end of the memory plane MP in the X direction, rather than at both ends in the X direction. HU3 It may be located at the center or near the center of the memory plane MP in the X direction.

[0266] Chip C M For example, as shown in Figure 38, the substrate layer L SB and the base layer L SB Memory cell array layer L located below MCA and memory cell array layer L MCAIt comprises a contact layer CH provided below, a plurality of wiring layers M10, M11 provided below the contact layer CH, and a chip bonding electrode layer MB provided above the wiring layers M10, M11.

[0267] [Chip C M The base layer L SB [Structure] For example, as shown in Figure 38, the substrate layer L SB The memory cell array layer L MCA It comprises a conductive layer 500 provided on the upper surface, an insulating layer 501 provided on the upper surface of the conductive layer 500, a back surface wiring layer MA provided on the upper surface of the insulating layer 501, and an insulating layer 502 provided on the upper surface of the back surface wiring layer MA.

[0268] The conductive layer 500 may contain, for example, a semiconductor layer such as silicon (Si) implanted with N-type impurities such as phosphorus (P) or P-type impurities such as boron (B), or it may contain a metal such as tungsten (W), or it may contain a silicide such as tungsten silicide (WSi).

[0269] The conductive layer 500 functions as part of the source lines SL1 and SL2 (Figure 4). Four conductive layers 500 are provided, corresponding to the four memory planes MP (Figure 37). Regions VZ that do not include the conductive layer 500 are provided at the X and Y ends of the memory planes MP.

[0270] The insulating layer 501 includes, for example, silicon oxide (SiO2).

[0271] The back wiring layer MA includes multiple wirings ma. These multiple wirings ma may include, for example, aluminum (Al).

[0272] Some of the multiple wirings ma function as part of the source lines SL1 and SL2 (Figure 4). There are four of these wirings ma, corresponding to the four memory planes MP (Figure 37). Each of these wirings ma is electrically connected to the conductive layer 500.

[0273] Furthermore, some of the multiple wirings ma are external pad electrodes P X This function is achieved by this wiring ma in the surrounding region R. P It is provided in the region VZ that does not include the conductive layer 500, and the memory cell array layer L MCA It is connected to the internal contact CC. In addition, a portion of the wiring ma is exposed to the outside of the memory die MD through an opening TV provided in the insulating layer 502.

[0274] The insulating layer 502 is a passivation layer made of an insulating material such as polyimide.

[0275] [Chip C M Memory cell array layer L MCA Memory hole region R MH3 [Structure in] Memory hole region R of the fifth embodiment MH3 The structure in this is the memory cell array layer L of the first embodiment, as described with reference to Figures 13, 20, and 21, etc. MCA1 ,L MCA2 Memory hole region R MH Since the structure is similar to that in the previous example, redundant explanations will be omitted. In this case, the conductive layer 110 in Figure 13 is replaced with the conductive layer 510 in Figure 38, the insulating layer 101 in Figure 13 is replaced with the insulating layer 501 in Figure 38, and the semiconductor layer 120 in Figure 13 is replaced with the semiconductor layer 520 in Figure 38. In the first embodiment, the bit line BL is provided on the positive side in the Z direction and the source lines SL1 and SL2 are provided on the negative side in the Z direction, whereas in the fifth embodiment, the bit line BL is provided on the negative side in the Z direction and the source lines SL1 and SL2 are provided on the positive side in the Z direction.

[0276] [Chip C M Memory cell array layer L MCA Hookup region R HU3 [Structure in] As shown in Figure 39, the hookup region R HU3 Multiple contact CCs are provided in this structure. Each of these contact CCs extends in the Z direction and is connected to the conductive layer 510 at its upper end.

[0277] [Chip C M Memory cell array layer L MCA The surrounding region R P [Structure in] Surrounding region R P For example, as shown in Figure 38, the external pad electrode P X In response, multiple contact CCs are provided. These multiple contact CCs have an external pad electrode P at their upper end. X Connected.

[0278] [Structure of the contact layer CH] Multiple contacts ch contained in the contact layer CH are, for example, in the memory cell array layer L MCA Internal components and chip C P It is electrically connected to at least one of the internal components.

[0279] The contact layer CH includes multiple contacts ch as multiple wirings. These multiple contacts ch may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The contacts ch are provided corresponding to the multiple semiconductor layers 520 and are connected to the lower ends of the multiple semiconductor layers 520.

[0280] [Chip C M [Structure of wiring layers M10, M11] Multiple wirings included in wiring layers M10 and M11 are, for example, in the memory cell array layer L MCA Internal components and chip C P It is electrically connected to at least one of the internal components.

[0281] The wiring layer M10 includes a plurality of wirings m10. These plurality of wirings m10 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu). Some of the plurality of wirings m10 function as bit lines BL. The bit lines BL are aligned in the X direction and extend in the Y direction.

[0282] The wiring layer M11 includes multiple wirings m11, as shown in Figure 38, for example. These multiple wirings m11 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Alternatively, the multiple wirings m11 may be metal films such as copper (Cu). The wiring pattern in the wiring layer M11 will be described later.

[0283] [Structure of the chip-bonded electrode layer MB] Multiple wirings included in the chip bonding electrode layer MB are, for example, in the memory cell array layer L MCA Internal components and chip C P It is electrically connected to at least one of the internal components.

[0284] The chip-bonded electrode layer MB consists of multiple bonded electrodes P I1 This includes multiple bonded electrodes P. I1 For example, a barrier conductive film p such as titanium nitride (TiN) I1B and metal films such as copper (Cu) p I1M It may also contain a multilayer film, etc.

[0285] [Chip C P [Structure] Chip C P For example, as shown in Figure 40, there are four peripheral circuit regions R aligned in the X direction corresponding to the memory plane MP. PC It includes these four peripheral circuit regions R PC At both ends in the X direction, there are, respectively, a low control circuit region R RC A low control circuit region R is provided. RC Between them are two block decoder regions R aligned in the X direction. BD A block decoder region R is provided. BD Between them are four sense amplifier regions R aligned in the X and Y directions. SA A is provided. Also, although not shown in the diagram, the peripheral circuit region R PC Circuits are also located in other areas inside. P The surrounding region R PIn the region opposite to it, there is the circuit region R. C A system is in place.

[0286] Low control circuit region R RC This area is provided with multiple block decoder units blkd (word line switches WLSW that constitute the block decoder units blkd), as explained with reference to Figure 9. BD A block decoder BLKD, as explained with reference to Figure 9, is provided. Sense amplifier region R SA This includes a sense amplifier SA, etc., corresponding to the bit line BL as explained with reference to Figure 11. Circuit region R C An input / output circuit (not shown) is provided. This input / output circuit connects to an external pad electrode P via contact CC, etc., as explained with reference to Figure 38. X Connected.

[0287] Furthermore, Figure 40 shows the hookup region R when viewed from the Z direction. HU3 The area overlapping with (Figure 37) is shown with a dotted line. Also, as mentioned above, the memory hole area R MH3 There are two regions R in the X direction MH3U It is divided into (Figure 37).

[0288] In the example in Figure 40, the low control circuit region R RC A portion of it is the hookup region R when viewed from the Z direction. HU3 It is located in the region that overlaps with (Figure 37). Furthermore, the low control circuit region R RC A portion of this is the memory hole region R when viewed from the Z direction. MH3 It is located in the region that overlaps with (Figure 37). Also, in the example in Figure 40, the low control circuit region R RC The width in the X direction is the hookup region R HU3 It is larger than the width in the X direction in (Figure 37).

[0289] Also, chip C PAs shown in Figure 38, for example, the device comprises a semiconductor substrate 600, an electrode layer GC0 provided above the semiconductor substrate 600, wiring layers D10, D11, D12, D13, D14 provided above the electrode layer GC0, and a chip-bonded electrode layer DB provided above the wiring layers D10, D11, D12, D13, D14.

[0290] As shown in Figure 40, multiple general signal through-wiring (ISL) extending in the X direction are aligned in the X direction to form four peripheral circuit regions R corresponding to four memory planes MP. PC These multiple general signal through-wiring (ISLs) are provided over a wide area. For example, chip C P It is formed in the wiring layers D10 to D14.

[0291] [Chip C P [Structure of semiconductor substrate 600] The semiconductor substrate 600 contains, for example, p-type silicon (Si) containing p-type impurities such as boron (B). The surface of the semiconductor substrate 600 is provided with, for example, an N-type well region 600N containing an N-type impurity such as phosphorus (P), a p-type well region 600P containing a p-type impurity such as boron (B), a semiconductor substrate region 600S where the N-type well region 600N and the p-type well region 600P are not provided, and an insulating region 600I. A portion of the p-type well region 600P is provided in the semiconductor substrate region 600S, and a portion of the p-type well region 600P is provided in the N-type well region 600N. The N-type well region 600N, the p-type well region 600P provided in the N-type well region 600N and the semiconductor substrate region 600S, and the semiconductor substrate region 600S each function as part of a plurality of transistors Tr and a plurality of capacitors that constitute the peripheral circuit PC.

[0292] [Chip C P [Structure of the electrode layer GC0] An electrode layer GC0 is provided on the upper surface of the semiconductor substrate 600 via an insulating layer 600G. The electrode layer GC0 includes a plurality of electrodes gc facing the surface of the semiconductor substrate 600. Each region of the semiconductor substrate 600 and each of the electrodes gc included in the electrode layer GC0 are connected to a contact CS.

[0293] The N-type well region 600N of the semiconductor substrate 600, the P-type well region 600P provided in the N-type well region 600N and the semiconductor substrate region 600S, and the semiconductor substrate region 600S each function as the channel region of multiple transistors Tr constituting the peripheral circuit PC, and as one electrode of multiple capacitors, respectively.

[0294] The multiple electrodes gc contained in the electrode layer GC0 function as gate electrodes of multiple transistors Tr that constitute the peripheral circuit PC, and as the other electrodes of multiple capacitors, respectively.

[0295] The contact CS extends in the Z direction and is connected at its lower end to the upper surface of the semiconductor substrate 600 or electrode gc. An impurity region containing N-type or P-type impurities is provided at the connection point between the contact CS and the semiconductor substrate 600. The contact CS may also include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0296] [Chip C P [Structure of wiring layers D10, D11, D12, D13, D14] For example, as shown in Figure 38, the multiple wirings included in D10, D11, D12, D13, and D14 are, for example, memory cell array layer L MCA Internal components and chip C P It is electrically connected to at least one of the internal components.

[0297] Each wiring layer D10, D11, and D12 contains multiple wirings d10, d11, and d12, respectively. These multiple wirings d10, d11, and d12 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0298] Each wiring layer D13 and D14 contains multiple wirings d13 and d14, respectively. These multiple wirings d13 and d14 may include, for example, barrier conductive films such as titanium nitride (TiN), tantalum nitride (TaN), a laminated film of tantalum nitride (TaN) and tantalum (Ta), and a laminated film of a metal film such as copper (Cu).

[0299] [Structure of the chip-bonded electrode layer DB] Multiple wirings included in the chip bonding electrode layer DB are, for example, in the memory cell array layer L MCA Internal components and chip C P It is electrically connected to at least one of the internal components.

[0300] The chip-bonded electrode layer DB consists of multiple bonded electrodes P I2 This includes multiple bonded electrodes P. I2 Examples include barrier conductive films such as titanium nitride (TiN), tantalum nitride (TaN), and multilayer films of tantalum nitride (TaN) and tantalum (Ta). I2B and metal films such as copper (Cu) p I2M It may also contain a multilayer film, etc.

[0301] [Wiring pattern in wiring layer M11] As explained with reference to Figure 9, a word line switch WLSW is connected to each word line WL. Here, since a relatively large voltage may be supplied to the word line WL, a high-voltage transistor is used as the word line switch WLSW. However, high-voltage transistors can be relatively large. In relation to this, the low control circuit region R, as explained with reference to Figure 40, RC The area can sometimes become relatively large.

[0302] Here, the low control circuit region R RC The area of ​​the hookup region R HU3 If the area is larger than the area of ​​the low control circuit region R RC A portion of the hookup region R, viewed from the Z direction. HU3 It is also conceivable to place it in the overlapping region and the remaining portion in a region that does not overlap with the memory plane MP when viewed from the Z direction. However, in this case, the peripheral circuit region R PC In some cases, the total area may become larger than the area of ​​the memory plane MP, resulting in an increase in the circuit area of ​​the memory die MD.

[0303] Therefore, in the fifth embodiment, as described with reference to Figure 40, the low control circuit region R RC A portion of the hookup region R, viewed from the Z direction. HU3 It is placed in the overlapping area, and the remaining part is the memory hole region R when viewed from the Z direction. MH3 It is located in the area that overlaps with [another area].

[0304] When such a structure is adopted, some bit lines BL are in the sense amplifier region R when viewed from the Z direction. SA Rather, the low control circuit region R RC or block decoder region R BD It will be placed in a position that overlaps with it.

[0305] Therefore, in the fifth embodiment, a wiring m11a extending in the X direction is provided in the wiring layer M11, and a portion of the bit lines BL and the sense amplifier region R are connected via this wiring m11a. SA The internal components are electrically connected. With this configuration, the low control circuit region R RC This makes it possible to suppress the increase in the circuit area of ​​the memory die MD that accompanies the increase in area, thereby providing a semiconductor memory device that enables high integration.

[0306] [Variations in wiring resistance during readout operations] Figure 41 is a schematic cross-sectional view of the structure shown in Figure 40, cut along line FF' and viewed in the direction of the arrow. Figure 42 is a schematic cross-sectional view of the structure shown in Figure 40, cut along line GG' and viewed in the direction of the arrow. Figures 41 and 42 are simplified cross-sectional views. In Figures 41 and 42, components identical to those in Figures 37 to 40 are denoted by the same reference numerals, and redundant explanations are omitted.

[0307] As explained with reference to Figure 40, some bit lines BL are transmitted through wiring m11a in wiring layer M11 to the sense amplifier region R SA It is electrically connected to the sense amplifier SA inside. In this case, as shown in Figure 41, the sense amplifier region R SA The low control circuit region R is adjacent to the X direction. RC When electrically connecting the word line switch WLSW and the word line WL (hereinafter referred to as the specific word line WLt), the wiring m11a in wiring layer M11 cannot be used, and it is necessary to use the wirings d10, d11, and d12 in wiring layers D10, D11, and D12. On the other hand, as shown in Figure 42, the wiring m11a in wiring layer M11 is used as the wiring to electrically connect the word line WL other than the specific word line WLt to the word line switch WLSW.

[0308] Here, if either of the two division ranges DU1 or DU2 of the word line WL (either division range DU1 only or division range DU2 only) is faulty, a combination of faulty division ranges from other word lines WL may be used to secure the 16kbyte storage capacity to be read. In this case, the division range of a specific word line WLt may be combined with the division range of a word line WL other than the specific word line WLt. Consequently, a unique difference may occur between the wiring resistance between the division range of the specific word line WLt and the word line switch WLSW, and between the wiring resistance between the division range of a word line WL other than the specific word line WLt and the word line switch WLSW.

[0309] Furthermore, when the division range of a specific word line WLt is combined with the division range of a word line WL other than the specific word line WLt, the specific word line WLt or its division range may be referred to as the first conductive layer, and the word line WL other than the specific word line WLt or its division range may be referred to as the second conductive layer. The first conductive layer is the sense amplifier region R when viewed from the Z direction. SA The second conductive layer overlaps with the sense amplifier region R when viewed from the Z direction. SA It is a conductive layer that does not overlap with the other layers.

[0310] [Adjusting operating parameters] [Selection word line WL in read operation] S [Adjusting the operating parameters] Selection word line WL in the read operation according to the fifth embodiment S The operating parameters are the same as those described in the first embodiment (Figure 26) and the second embodiment (Figure 29). That is, the selected word line WL in the read operation. S The operating parameters include the waiting time Ta in Figure 26, and the selected word line WL between timings t101 and t102 in Figure 26. S This includes the voltage Va supplied to it. It also includes the selection word line WL in the read operation. S The operating parameters include the waiting time Te in Figure 29, and the selected word line WL between timings t102 and t103 in Figure 29. S This includes the voltage Ve supplied to it.

[0311] Figure 43 shows the selected word line WL according to the fifth embodiment. S This is a schematic diagram illustrating the adjustment of the operating parameters. Note that the meaning of "8k" in Figure 43 is the same as that explained in Figure 27.

[0312] In Figure 43, word lines WL135i and WL135o are different word lines, and the division ranges of these word lines WL135i and WL135o are combined to form a 16k byte read target. Similarly, the division ranges of word lines WL156i and WL156o are combined to form a 16k byte read target, and the division ranges of word lines WL157i and WL157o are combined to form a 16k byte read target. Note that the wiring resistance R of word lines WL135i, 135o, WL156i, WL156o, WL157i, and WL157o in Figure 43 W Its size is the same as that described in Figure 27.

[0313] As shown in Figure 43, each division range DU1 of the word lines WL135i, WL156i, and WL157i is connected to the CG driver circuit DRV(1) via the word line switch WLSW and wiring CG. Similarly, each division range DU2 of the word lines WL135o, WL156o, and WL157o is connected to the CG driver circuit DRV(2) via the word line switch WLSW and wiring CG. In this way, each division range DU1 and DU2 is connected to a word line switch WLSW. Note that a word line decoder WLD and the like are provided between the word line switch WLSW and the CG driver circuits DRV(1) and DRV(2) (Figure 5), but these are omitted in Figure 43.

[0314] The CG driver circuits DRV(1) and DRV(2) respectively perform voltage supply operations for the division ranges DU1 and DU2 of the word line WL (wiring CG) according to the control signals SGL31 and SGL32 from the sequencer SQC. The control signals SGL31 and SGL32 each include the signals of the signal lines VSEL1 to VSEL6 in Figure 5.

[0315] In the first embodiment (Figure 27) and the second embodiment (Figure 29), the selected word line WL S The operating parameters (wait time Ta, voltage Va, wait time Te, voltage Ve) were adjusted on a word line WL basis. In contrast, in the fifth embodiment (Figure 43), the selected word line WL SThe operating parameters (wait time Ta, voltage Va, wait time Te, voltage Ve) are adjusted in units of the word line WL division range DU1, DU2.

[0316] For example, the selected word line WL S If the word lines are WL157i and WL157o, then the division range DU1("small" wiring resistance R) of the word line WL157i is... W157(1) The operating parameters (wait time Ta, voltage Va, wait time Te, voltage Ve) of the division range of the word line WL157o are defined in the division range DU2 ("intermediate" wiring resistance R W157(2) Compared to the operating parameters of the division range, the waiting time Ta is shortened, the voltage Va is reduced, the waiting time Te is shortened, and the voltage Ve is increased. Also, the selected word line WL S If the word lines are WL156i and WL156o, then the division range DU1("large" wiring resistance R) of the word line WL156i is... W156(1) The operating parameters of the division range are set for the division range DU2 of word line WL156o ("medium" wiring resistance R W156(2) Compared to the operating parameters of the division range, the waiting time Ta is made longer, the voltage Va is made larger, the waiting time Te is made larger, and the voltage Ve is made smaller. Alternatively, one or more of the operating parameters (waiting time Ta, voltage Va, waiting time Te, voltage Ve) of the division ranges DU1 and DU2 may be adjusted. By adjusting these operating parameters, the selected word line WL may be affected during the read operation. S Wiring resistance R in the division range DU1, DU2 W Depending on the selected word line WL S It is possible to perform appropriate charging for each segmented range DU1 and DU2.

[0317] [Selection word line WL during writing operation] S [Adjusting the operating parameters] Selection word line WL in the writing operation according to the fifth embodiment S The operating parameters are the same as those described in the third embodiment (Figures 33 and 34) and the fourth embodiment (Figure 35). That is, the selected word line WL in the write operation. SThe operating parameters include the waiting time Tf in Figure 33 and the voltage Vf in Figure 34. Additionally, the selected word line WL is used during the writing operation. S The operating parameters include the waiting times Ta' and Te' shown in Figure 35.

[0318] For example, the selected word line WL S If the word lines are WL157i and WL157o, then the division range DU1("small" wiring resistance R) of the word line WL157i is... W157(1) The operating parameters (wait time Tf, voltage Vf, wait time Ta', wait time Te') of the division range of word line WL157o are defined as the "intermediate" wiring resistance R W157(2) Compared to the operating parameters of the division range, the waiting time Tf is shortened, the voltage Vf is reduced, the waiting time Ta' is shortened, and the waiting time Te' is shortened. Also, the selected word line WL S If the word lines are WL156i and WL156o, then the division range DU1("large" wiring resistance R) of the word line WL156i is... W156(1) The operating parameters of the division range are set for the division range DU2 of word line WL156o ("medium" wiring resistance R W156(2) The waiting time Tf is made longer, the voltage Vf is made larger, the waiting time Ta' is made longer, and the waiting time Te' is made longer than the operating parameters of the division range DU1 and DU2. Alternatively, one or more of the operating parameters (waiting time Tf, voltage Vf, waiting time Ta', waiting time Te') of the division range DU1 and DU2 may be adjusted. By adjusting these operating parameters, the selected word line WL may be affected during the writing operation. S Wiring resistance R in the division range DU1, DU2 W Depending on the selected word line WL S It is possible to perform appropriate charging for each segmented range DU1 and DU2.

[0319] [Adjustment of operating parameters for bit line BL and source lines SL1, SL2] The operating parameters of the bit line BL in the read operation according to the fifth embodiment are the same as those described in the first embodiment (Figure 26) and the second embodiment (Figure 29). That is, the operating parameters of the bit line BL in the read operation include the waiting time Tb in Figures 26 and 29, the voltage Vb supplied to the bit line BL between timings t104 and t105 in Figures 26 and 29, the waiting time Tc in Figures 26 and 29, and the waiting time Td in Figures 26 and 29.

[0320] Furthermore, the operating parameters of source lines SL1 and SL2 in the read operation according to the fifth embodiment are the same as those described in the first embodiment (Figure 26) and the second embodiment (Figure 29). That is, the operating parameters of source lines SL1 and SL2 in the read operation are the waiting time Ts in Figures 26 and 29, and the voltage V supplied to source lines SL1 and SL2 between timings t103 and t105 in Figures 26 and 29. S It includes.

[0321] Figure 44 is a schematic diagram illustrating the adjustment of the operating parameters of the bit line BL and source lines SL1 and SL2 according to the fifth embodiment. The meanings of the word lines WL135i, WL135o, WL156i, WL156o, WL157i, and WL157o in Figure 44 are the same as those explained in Figure 43. The meaning of "8k" in Figure 44 is the same as that explained in Figure 27. Furthermore, the wiring resistance R of the word lines WL135i, WL135o, WL156i, WL156o, WL157i, and WL157o in Figure 44 is also shown. W Its size is the same as that explained in Figure 27.

[0322] The configuration shown in Figure 44 is basically the same as the configuration shown in Figure 28. However, in the configuration shown in Figure 44, a word line switch WLSW is connected to each division range DU1 and DU2. Furthermore, the adjustment of the operating parameters of the bit line BL and source lines SL1 and SL2 according to the fifth embodiment is the same as the adjustment of the operating parameters of the bit line BL and source lines SL1 and SL2 according to the first and fourth embodiments.

[0323] For example, the selected word line WL S If the word lines are WL157i and WL157o, then the division range DU1("small" wiring resistance R) of the word line WL157i is... W157(1) The operating parameters (wait time Tb, voltage Vb, wait time Tc, wait time Td) of the bit line BL in the division range of the word line WL157o are defined as the "intermediate" wiring resistance R W157(2) Compared to the operating parameters of the bit line BL (within the division range), the waiting time Tb is shortened, the voltage Vb is reduced, the waiting time Tc is increased, and the waiting time Td (sense time) is increased.

[0324] Also, the selected word line WL S If the word lines are WL156i and WL156o, then the division range DU1("large" wiring resistance R) of the word line WL156i is... W156(1) The operating parameters of bit line BL in the division range of word line WL156o are set to the wiring resistance R in the division range DU2 ("middle"). W156(2) Compared to the operating parameters of the bit line BL (within the division range), the waiting time Tb is increased, the voltage Vb is increased, the waiting time Tc is increased, and the waiting time Td (sense time) is decreased.

[0325] Furthermore, one or more of the operating parameters of the bit line BL (wait time Tb, voltage Vb, wait time Tc, wait time Td) may be adjusted. By adjusting such operating parameters, the selection word line WL may be affected during the read operation. S Wiring resistance R in the division range DU1, DU2 W Accordingly, it is possible to perform appropriate charging and sensing operations on the bit lines BL belonging to the division ranges DU1 and DU2. As a result, the reliability of the read operation is improved.

[0326] For example, the selected word line WL S If the word lines are WL157i and WL157o, then the division range DU1("small" wiring resistance R) of the word line WL157i is... W157(1) The operating parameters (wait time Ts, voltage Vs) of source line SL1 in the division range of word line WL157 are defined as the "intermediate" wiring resistance R W157(2)The operating parameters of source line SL2 (within the division range) are set to reduce the waiting time Ts and voltage Vs.

[0327] Also, the selected word line WL S If the word lines are WL156i and WL156o, then the division range DU1("large" wiring resistance R) of the word line WL156i is... W156(1) The operating parameters of source line SL1 (in the division range) and the wiring resistance R of word line WL156o (in the division range DU2) W156(2) The operating parameters of source line SL2 (within the division range) are increased by making the waiting time Ts longer and the voltage Vs larger.

[0328] Furthermore, it is also possible to adjust only one of the operating parameters (wait time Ts, voltage Vs) of source lines SL1 and SL2. By adjusting such operating parameters, the selected word line WL can be controlled during the read operation. S Wiring resistance R in the division range DU1, DU2 W Accordingly, it is possible to properly charge source lines SL1 and SL2 belonging to division ranges DU1 and DU2. As a result, the reliability of the read operation is improved.

[0329] [Sixth Embodiment] In the first to fifth embodiments described above, each of the multiple word lines WL was physically or virtually divided into two division ranges DU1 and DU2. In contrast, in the sixth embodiment, each of the multiple word lines WL is physically or virtually divided into four division ranges DU21, DU22, DU23, and DU24.

[0330] Figure 45 shows the selected word line WL according to the sixth embodiment. S This is a schematic diagram illustrating the adjustment of the operating parameters. In Figure 45, the word lines WL156i, WL156o, WL156p, and WL156q combine the division ranges of four different word lines. Similarly, WL157i, WL157o, WL156p, and WL156q combine the division ranges of four different word lines.

[0331] Furthermore, the “4k” in Figure 45 indicates that the memory capacity of each division range DU21, DU22, DU23, and DU24 of each word line WL156i, WL156o, WL156p, WL156q, WL157i, WL157o, WL157p, and WL157q is 4k bytes. Therefore, for each combination of division ranges DU21, DU22, DU23, and DU24 of each word line WL156i, WL156o, WL156p, and WL156q, a number of memory cells MC corresponding to the memory capacity of 4k bytes to be read are connected. Similarly, for each word line WL157i, WL157o, WL157p, and WL157q, a number of memory cells MC corresponding to the memory capacity of 4k bytes to be read are connected to the division ranges DU21, DU22, DU23, and DU24. Therefore, each word line WL156i, WL156o, WL156p, and WL156q is connected to a number of memory cells MC corresponding to the storage capacity of 16k bytes to be read. In addition, each word line WL157i, WL157o, WL157p, and WL157q is connected to a number of memory cells MC corresponding to the storage capacity of 16k bytes to be read. Note that the values ​​in Figure 45 are just examples and are not limited to these values.

[0332] As shown in Figure 45, the division ranges DU21, DU22, DU23, and DU24 of each word line WL156i, WL156o, WL156p, and WL156q are connected to the CG driver circuits DRV(1), DRV(2), DRV(3), and DRV(4) respectively via the word line switch WLSW and wiring CG. Similarly, the division ranges DU21, DU22, DU23, and DU24 of each word line WL157i, WL157o, WL157p, and WL157q are connected to the CG driver circuits DRV(1), DRV(2), DRV(3), and DRV(4) respectively via the word line switch WLSW and wiring CG.

[0333] The CG driver circuits DRV(1), DRV(2), DRV(3), and DRV(4) respectively perform voltage supply operations to the division ranges DU21, DU22, DU23, and DU24 of the word line WL (wiring CG) according to the control signals SGL41, SGL42, SGL43, and SGL44 from the sequencer SQC. The control signals SGL41, SGL42, SGL43, and SGL44 each include the signals of the signal lines VSEL1 to VSEL6 in Figure 5.

[0334] In the sixth embodiment (Figure 45), the selected word line WL S The operating parameters (wait time Ta, voltage Va, wait time Te, voltage Ve) are adjusted in units of the word line WL division range DU21, DU22, DU23, DU24. S The adjustment of the operating parameters is as described above, and a detailed explanation will be omitted.

[0335] Figure 46 is a schematic diagram illustrating the adjustment of the operating parameters of the bit line BL and source lines SL1 and SL2 according to the sixth embodiment. As shown in Figure 46, the bit lines BL of division ranges DU21, DU22, DU23, and DU24 are connected to sense amplifier modules SAM(1), SAM(2), SAM(3), and SAM(4), respectively. Sense amplifier modules SAM(1), SAM(2), SAM(3), and SAM(4) perform voltage supply and sense operations for the bit lines BL of division ranges DU21, DU22, DU23, and DU24 according to control signals SGL51, SGL52, SGL53, and SGL54 from the sequencer SQC. Control signals SGL51, SGL52, SGL53, and SGL54 all include signals for signal lines STB, XXL, BLC, BLS, HLL, BLX, CLKSA, and LBP.

[0336] Note that in Figure 46, the source line driver circuit SDRV is omitted. However, the source lines SL (e.g., source lines SL1, SL2, SL3, SL4) corresponding to the division ranges DU21, DU22, DU23, and DU24 are connected to the source line driver circuits SDRV(1), SDRV(2), SDRV(3), and SDRV(4), respectively. The source line driver circuits SDRV(1), SDRV(2), SDRV(3), and SDRV(4) perform voltage supply operations to the source lines SL corresponding to the division ranges DU21, DU22, DU23, and DU24 according to the control signals for each division range DU21, DU22, DU23, and DU24 from the sequencer SQC.

[0337] In the sixth embodiment (Figure 46), the operating parameter (voltage Vs) of the source line SL is adjusted in units of the division range DU21, DU22, DU23, and DU24 of the word line WL. The adjustment of the operating parameter of the source line SL is as described above, and a detailed explanation is omitted.

[0338] [Seventh Embodiment] In the embodiments described above, examples of application to NAND flash memory have been explained. However, the technology described herein can also be applied to configurations other than NAND flash memory, such as three-dimensional NOR flash memory.

[0339] Figure 47 is a schematic circuit diagram showing an example configuration of a three-dimensional NOR flash memory. The NOR flash memory illustrated in Figure 47 has multiple memory layers (ML). NOR It includes these multiple memory layer MLs. NOR These are aligned perpendicular to the substrate. Furthermore, these multiple memory layers ML NOR These are, respectively, word lines (WL). NOR And, Word line WL NOR Multiple memory cells connected to MC NOR It is equipped with the following.

[0340] Memory Cell MC NOR This is a field-effect transistor, similar to the memory cell MC explained with reference to Figure 3.NOR The memory cell (MC) comprises a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cell (MC) changes depending on the amount of charge in the charge storage film.

[0341] Memory Cell MC NOR The gate electrode is the word line WL NOR It is connected to the memory cell MC. NOR The drain electrode is bit wire BL NOR It is connected to the memory cell MC. NOR The source electrode is the source wire SL NOR It is connected to bit line BL. NOR and source line SL NOR These are, respectively, memory layer ML NOR Multiple memory cells (MC) are located inside. NOR Multiple versions are provided to accommodate this. Also, bit line BL NOR and source line SL NOR Each of these is a multiple memory layer ML NOR The internal memory cell MC NOR Connected.

[0342] Furthermore, as shown in Figure 47, multiple memory layer MLs NOR Each of these is connected to multiple word line switches WLSW. Furthermore, these multiple word line switches WLSW are connected to multiple word lines WL NOR It is provided in response to the following: Multiple word lines (WL) NOR Wiring resistance R between the multiple word line switches WLSW W These are, for example, "large," "medium," and "small."

[0343] Multiple word lines (WL) NOR It is physically or virtually divided into two division ranges DU1 and DU2. For example, multiple word lines WL NOR Of these, the (k-1)th word line WL NOR(1) It contains a number of memory cells (MC) corresponding to the storage capacity of the Ak bytes to be read. NOR The word line WL is connected.NOR(2) It contains a number of memory cells (MC) corresponding to the storage capacity of the Bk bytes to be read. NOR The following are connected. Note that A and B are arbitrary numbers. Therefore, the k-1th word line WL NOR(1) WL NOR(2) It contains a number of memory cells (MC) corresponding to the storage capacity of the (A+B) KB to be read. NOR The k-th word line WL is connected. NOR(1) WL NOR(2) It contains a number of memory cells (MC) corresponding to the storage capacity of the (A+B) KB to be read. NOR The k+1th word line WL is connected. NOR(1) WL NOR(2) It contains a number of memory cells (MC) corresponding to the storage capacity of the (A+B) KB to be read. NOR It is connected.

[0344] [Operation of three-dimensional NOR flash memory] Figure 48 is a schematic block diagram showing an example configuration of the semiconductor memory device 900 according to the seventh embodiment. The semiconductor memory device 900 according to the seventh embodiment is a three-dimensional NOR flash memory.

[0345] As shown in Figure 48, the semiconductor memory device 900 includes a memory cell array 901, a row control circuit 902, a column control circuit 903, an address register 904, a data buffer 905, an input / output shift register 906, a voltage generation circuit 907, and a sequencer 908.

[0346] The memory cell array 901 consists of multiple memory cells MC NOR This includes, in the semiconductor memory device 900, each memory cell MC NOR The gate is a multiple word line WL NOR It is connected to one of the corresponding ones. NOR One end of the current path is connected to multiple bit lines BL NOR It is connected to one of the corresponding ones. NOR The other end of the current path is the source wire SL NORIt is connected to, for example, ground. Multiple memory cells MC NOR These are arranged in a two-dimensional array or a three-dimensional array.

[0347] Memory Cell MC NOR This is a field-effect transistor with a stacked gate structure having a charge storage layer. The charge storage layer may be a floating gate electrode or a charge trap film.

[0348] The low control circuit 902(1) controls multiple word lines WL belonging to the division range DU1 shown in Figure 47. NOR(1) Connected to this, the low control circuit 920(2) has multiple word lines WL belonging to the division range DU2 shown in Figure 47. NOR(2) It is connected to the following. The low control circuits 902(1) and 920(2) have multiple word lines WL NOR It is equipped with multiple word line switches WLSW corresponding to the multiple word line WL NOR From among these, a word line corresponding to the address information is selected. The row control circuits 902(1) and 902(2) apply a predetermined voltage to the selected word line (and the unselected word line) according to the write sequence, read sequence, erase sequence, etc.

[0349] The column control circuit 903(1) has multiple bit lines BL belonging to the division range DU1 shown in Figure 47. NOR Connected to this, the column control circuit 903(2) has multiple bit lines BL belonging to the division range DU2 shown in Figure 47. NOR It is connected to the following. The column control circuits 903(1) and 903(2) control multiple bit lines BL NOR From among these, a bit line corresponding to the address information is selected. The column control circuits 903(1) and 903(2) apply a predetermined voltage to the selected bit line (and the unselected bit line) according to the write sequence, read sequence, erase sequence, etc.

[0350] The address register 904 temporarily stores address information from the input / output shift register 906. The address register 904 sends the address information to the row control circuits 902(1) and 902(2) and the column control circuits 903(1) and 903(2).

[0351] The data buffer 905 temporarily stores data read from the memory cell array 901 and data written from the input / output shift register 906.

[0352] The input / output shift register 906 temporarily stores signals DQ that are transferred between the memory cell array 901 and the outside of the semiconductor memory device 900. Signals DQ may include read data, write data, and / or address information. The input / output shift register 906 transmits address information to the address register 904. The input / output shift register 906 transmits write data to the data buffer 905. The input / output shift register 906 transmits read data supplied from the memory cell array 901 to the host computer 20. The input / output shift register 906 can perform parallel-to-serial conversion of signals DQ.

[0353] The voltage generation circuit 907 generates multiple voltages used in the write sequence, read sequence, and erase sequence, respectively. The voltage generation circuit 907 supplies the generated voltages to the row control circuits 902(1), 902(2) and the column control circuits 903(1), 903(2), etc.

[0354] The sequencer 908 controls the operation of the entire semiconductor memory device 900 based on various control signals such as the reset signal RESETn, the hold signal HOLDn, and the write protect signal Wn. The sequencer 908 outputs control signals to the row control circuits 902(1), 902(2), the column control circuits 903(1), 903(2), and the voltage generation circuit 907, thereby controlling the word line WL. NOR and bit line BL NOR It is possible to control the voltage supplied, the supply time, and the waiting time.

[0355] Furthermore, the semiconductor memory device 900 may include other components such as a status register. The status register temporarily stores status signals that indicate the internal operating status of the semiconductor memory device 900 and the execution results of the operation sequence.

[0356] Even in this configuration, the word line WL NOR Wiring resistance R between the word line switch WLSW W Accordingly, the operating parameters for read and write operations are adjusted for each division range DU1 and DU2. This allows for the execution of appropriate read and write operations.

[0357] [Eighth Embodiment] The configuration of the three-dimensional NOR flash memory is not limited to the configuration described with reference to Figure 47. Figure 49 is a schematic circuit diagram showing another example configuration of the three-dimensional NOR flash memory. In the eighth embodiment, multiple memory cells MC are placed between horizontally extending bit lines BLk-2 to BLk+2 (where k is an integer of 2 or more) and source lines SLk-2 to SLk+2. NOR Multiple memory cells MC are connected in parallel and arranged vertically. NOR These are commonly driven by vertically extending word lines WL0 to WL4. Furthermore, the multiple word lines WL0 to WL4 are physically or virtually divided into two division ranges DU1 and DU2. Note that the word line switches are omitted in Figure 49. It is also possible to apply the configuration shown in Figure 48 to the three-dimensional NOR flash memory shown in Figure 49.

[0358] Even in this configuration, the wiring resistance R between the word line WL and the word line switch W Accordingly, the operating parameters for read and write operations are adjusted for each division range DU1 and DU2. This allows for the execution of appropriate read and write operations.

[0359] [Ninth Embodiment] The technologies described herein are applicable to configurations other than flash memory, such as three-dimensional DRAM.

[0360] Figure 50 is a schematic circuit diagram showing an example of a three-dimensional DRAM configuration. As shown in Figure 50, the memory cell array 1201 consists of multiple memory layers ML D It includes these multiple memory layer MLs. D These are aligned perpendicular to the substrate. Furthermore, these multiple memory layers ML D These are, respectively, bit line BL D And, bit line BL D Multiple transistors connected to each other D And these multiple transistors Tr D It comprises multiple capacitor Caps connected to a plate wire PL that is commonly connected to these multiple capacitor Caps. D The source electrode is bit line BL D It is connected to the transistor Tr D The drain electrode of the transistor is connected to the capacitor Cap. D The gate electrode is the word line WL D It is connected to the word line WL. D And the plate line PL is each a multiple memory layer ML D The transistor inside Tr D Connected.

[0361] Word line WL D When a low-level or high-level voltage is applied to the bit line BL, the transistor Tr D This can be either an ON state or an OFF state. As a result, charge is accumulated in the capacitor Cap, or the accumulated charge is discharged.

[0362] In DRAM, data is stored by associating it with the charge accumulated in the capacitor Cap. Furthermore, in DRAM, a refresh circuit periodically refreshes the charge in the capacitor Cap to maintain its integrity. For the sake of simplicity, the refresh circuit and other related components are omitted in this explanation.

[0363] The above word line WL D It is divided into multiple subdivisions. Note that the word line switch is omitted in Figure 50.

[0364] Figure 51 is a schematic circuit diagram showing another example of a three-dimensional DRAM configuration. As shown in Figure 51, the memory cell array 1201' consists of multiple memory layers ML D It is equipped with these multiple memory layers ML D The 's are aligned perpendicular to the substrate. Also, these multiple memory layers ML D ' represents the word line WL D ' and, Word line WL D Multiple transistors connected to ' Tr D ' and these multiple transistors Tr D It comprises multiple capacitors Cap connected to a terminal and a plate wire PL commonly connected to these multiple capacitors Cap. D The source electrode of ' is bit wire BL D It is connected to the transistor Tr D The drain electrode of the transistor ' is connected to the capacitor Cap. D The gate electrode of ' is the word line WL D It is connected. Also, bit line BL D ' and plate lines PL are, respectively, multiple memory layers ML D 'The transistor inside Tr D It is connected to '.

[0365] The above word line WL D The ' is also divided into multiple subdivisions. Note that the word line switch is omitted in Figure 51. Even in such a configuration, the word line WLD Wiring resistance R between ' and the word line switch W Accordingly, the operating parameters for read and write operations are adjusted for each of the multiple division ranges. This allows for the execution of appropriate read and write operations.

[0366] [Operation of three-dimensional DRAM] Figure 52 is a schematic block diagram showing an example configuration of the semiconductor memory device 1000 according to the ninth embodiment. The semiconductor memory device 1000 according to the ninth embodiment is a three-dimensional DRAM. In the following description, the memory cell array is assumed to be the memory cell array 1201 shown in Figure 50.

[0367] As shown in Figure 52, the semiconductor memory device 1000 of the ninth embodiment includes a memory cell array 1201, an input / output circuit 1210, word line drivers 1220(1) and 1220(2) (referred to as WLD(1) and WLD(2) in Figure 52), a row decoder 1222, a read / write amplifier 1233, a command decoder 1241, sense units 1250(1) and 1250(2), a column decoder 1251, a command address input circuit 1260, a clock input circuit 1271, an internal clock generation circuit 1272, and a voltage generation circuit 1280.

[0368] Furthermore, the semiconductor memory device 1000 is equipped with multiple external terminals, including clock terminals CK, / CK, command / address terminal CAT, data terminal DQT, data mask terminal DMT, and power terminals VPP, VDD, VSS, VDDQ, VSSQ.

[0369] In this embodiment, components of the semiconductor memory device 1000 other than the memory cell array 1201 may be referred to as peripheral circuits.

[0370] The memory cell array 1201 has the configuration described with reference to Figure 50. As described above, the word line WL D It is physically or virtually divided into multiple division ranges (for example, two division ranges DU1 and DU2).

[0371] As shown in Figure 53, the sense amplifier sa senses the data read from the memory cell MC. The sense amplifier sa connects to a pair of bit lines BL D (BL in Figure 53) D -T,BL D -It is positioned in accordance with C). The sense unit 1250 is equipped with multiple sense amplifiers sa.

[0372] Each of the multiple memory cells MC in the memory cell array 1201 is associated with a memory address. Of the multiple external terminals, the command / address terminal CAT receives the memory address from an external device such as a host computer. The memory address received by the command / address terminal CAT is transmitted to the command address input circuit 1260. Upon receiving the memory address, the command address input circuit 1260 sends the decoded row address XADD to the row decoder 1222 and the decoded column address YADD to the column decoder 1251.

[0373] Furthermore, the command / address terminal CAT receives commands from external devices such as a host computer. Commands received by the command / address terminal CAT are transmitted to the command address input circuit 1260. Upon receiving a command, the command address input circuit 1260 transmits the received command as an internal command ICMD to the command decoder 1241.

[0374] The command decoder 1241 includes circuitry that decodes the internal command ICMD and generates a signal for executing the internal command. The command decoder 1241 transmits, for example, the activated command ACT and the refresh command AREF to the row decoder 1222. The row decoder 1222 transmits the command ACT and the refresh command AREF received from the command decoder 1241 to the word line WL. D Select this. The Row Decoder 1222 will select the word line WL. D A signal indicating this is sent to the word line driver 1220.

[0375] The word line driver 1220(1) controls multiple word lines WL within a divided range (e.g., DU1). D It is connected to multiple word lines WL of a divided range (e.g., DU2). The word line driver 1220(1) is connected to multiple word lines WL of a divided range (e.g., DU2). D It is connected to the word line drivers 1220(1) and 1220(2). The word line drivers 1220 receive signals from the row decoder 1222 and the word line WL indicated by that signal. D A low-level or high-level voltage is applied to it. Note that the word line driver 1220 has a word line WL D A corresponding word line switch is provided.

[0376] Furthermore, the command decoder 1241 transmits, for example, a read / write command R / W to the column decoder 1251. The column decoder 1251 then processes the bit line BL according to the read / write command R / W received from the command decoder 1241. D Select this. Column decoder 1251 will select the bit line BL. D A signal indicating this is sent to the sense unit 1250.

[0377] The sense unit 1250(1) contains multiple bit lines BL of a divided range (e.g., DU1). D It is connected to multiple bit lines BL of a divided range (e.g., DU2). Sense unit 1250(2) D It is connected to the sense unit 1250(1) and 1250(2). The sense unit 1250 receives a signal from the column decoder 1251 and the bit line BL indicated by that signal. D A low-level or high-level voltage is applied to it.

[0378] When reading data, the command / address terminal CAT receives a memory address along with a read command. This allows data to be read from the memory cell MC within the memory cell array 1201 specified by the memory address. The read data is output externally via the sense unit 1250, read / write amplifier 1233, and input / output circuit 1210 through the data terminal DQT.

[0379] When writing data, the command / address terminal CAT receives the memory address along with the write command, and the data terminal DQT receives the data to be written. If necessary, the data mask terminal DMT also receives the data mask. The written data is transmitted to the memory cell array 1201 via the input / output circuit 1210, the read / write amplifier 1233, and the sense unit 1250. This writes the data to the memory cell MC specified by the memory address.

[0380] The read / write amplifier 1233 is equipped with various latch circuits for temporarily holding read and write data.

[0381] The voltage generation circuit 1280 is supplied with power supply voltage from the power supply terminals VPP, VDD, and VSS. Based on the power supply voltage, the voltage generation circuit 1280 generates various internal voltages VOD, VARY, and VPERI. The internal voltages VOD and VARY are mainly used in the sense amplifier sa, while the internal voltage VPERI is used in other peripheral circuits.

[0382] Furthermore, the input / output circuit 1210 is supplied with power voltage from power terminals VDDQ and VSSQ. Dedicated power voltages are supplied to power terminals VDDQ and VSSQ to prevent power noise generated in the input / output circuit 1210 from propagating to other circuit blocks. Note that the power voltage supplied to power terminals VDDQ and VSSQ may be the same as the power voltage supplied to power terminals VDD and VSS.

[0383] Complementary external clock signals are input to the clock terminals CK and / CK. The external clock signals are supplied to the clock input circuit 1271. The clock input circuit 1271 generates the internal clock signal ICLK. The internal clock signal ICLK is supplied to the internal clock generation circuit 1272 and the command decoder 1241.

[0384] The internal clock generation circuit 1272, when enabled by the clock enable from the command address input circuit 1260, generates various internal clock signals LCLK. The internal clock signals LCLK are used to measure the timing of various internal operations. For example, the internal clock signal LCLK is output to the input / output circuit 1210. The input / output circuit 1210 sends and receives data from the data terminal DQT based on the input internal clock signal LCLK.

[0385] [Sense amplifier configuration] Next, with reference to Figure 53, an example configuration of the sense amplifier sa will be described. Figure 53 is a circuit diagram showing an example configuration of the sense amplifier sa, including the sense amplifier circuit sac.

[0386] As shown in Figure 53, the bit line BL connected to the memory cell MC in the memory cell array 1201 D -T, and bit line BL D -T and the corresponding bit line BL D -C is connected to the sense amplifier circuit sac.

[0387] The sense amplifier circuit sac is a transistor TR 51 ~TR 54 It contains a transistor (TR). 51 ,TR 53 This is a low-voltage P-channel MOS transistor, and the transistor TR 52 ,TR 54 This is a low-voltage N-channel MOS transistor.

[0388] Transistor (TR) 51One terminal of the [transistor] is connected to a signal line to which a sense signal SAP is supplied, and the [transistor] 51 The other terminal of the [transistor] is connected to one terminal of the [transistor] 52 One terminal of the [transistor] 52 The other terminal is connected to a signal line to which a sense signal SAN is supplied. Also, between the [transistors] 51 , [transistor] 52 (at the connection point between the other terminal of the [transistor] 51 and one terminal of the [transistor] 52 ), a bit line BL D -T is connected.

[0389] One terminal of the [transistor] 53 is connected to a signal line to which a sense signal SAP is supplied, and the [transistor] 53 The other terminal of the [transistor] is connected to one terminal of the [transistor] 54 One terminal of the [transistor] 54 The other terminal is connected to a signal line to which a sense signal SAN is supplied. Also, between the [transistors] 53 , [transistor] 54 (at the connection point between the other terminal of the [transistor] 53 and one terminal of the [transistor] 54 ), a bit line BL D -C is connected.

[0390] Also, the gate terminals (gate electrodes) of the [transistors] 51 , [transistor] 52 are connected between the [transistors] 53 , [transistor] 54 and the gate terminals (gate electrodes) of the [transistors] 53 , [transistor] 54 are connected between the [transistors] 51 , [transistor] 52

[0391] Column switches YSW are connected to the bit lines BL D -T, BL D [[ID=6�]]-C on the downstream side of the sense amplifier circuit sac. The column switch YSW is the [transistor] 71,TR 72 includes transistor TR 71 ,TR 72 is a low-voltage N-channel MOS transistor.

[0392] One terminal of transistor TR 71 is connected to bit line BL D -T, and the other terminal of transistor TR 71 is connected to local input / output line LIOT. One terminal of transistor TR 72 is connected to bit line BL D -C, and the other terminal of transistor TR 72 is connected to local input / output line LIOB. The gate terminal (gate electrode) of transistor TR 71 ,TR 72 is connected to the signal line to which column selection signal YS is supplied.

[0393] Thus, the sense amplifier circuit sac is connected to local input / output lines LIOT and LIOB via column switch YSW. Transfer gate TG is connected to local input / output lines LIOT and LIOB and also to main input / output lines MIOT and MIOB. Transfer gate TG functions as a switch. Main input / output lines MIOT and MIOB are connected to read / write amplifier 1233.

[0394] Bit lines BL D -T, BL D -C on the downstream side of column switch YSW are connected to equalize circuit EQ. Equalize circuit EQ includes transistors TR 81 ~TR 83 . Transistors TR 81 ~TR 83 are low-voltage N-channel MOS transistors.

[0395] One terminal of transistor TR 81 is connected to bit line BL D -T, and the other terminal of transistor TR 81 is the other terminal of transistor TR 82It is connected to one of the terminals of the transistor TR. 82 The other terminal is bit wire BL D -Connected to C. Also, transistor TR 81 ,TR 82 A power line supplying an equalization voltage VBLEQ is connected between them. The magnitude of the equalization voltage VBLEQ is half the power supply voltage VDDSA for the sense amplifier sa.

[0396] Transistor (TR) 83 One of the terminals is bit wire BL D -T is connected to transistor TR 83 The other terminal is bit wire BL D -Connected to C. Transistor TR 81 ~TR 83 The gate terminal (gate electrode) is connected to the signal line to which the equalization signal BLEQ is supplied.

[0397] [SenseAmp operation] Next, we will explain the operation of the sense amplifier sa, which includes the sense amplifier circuit sac described above.

[0398] Normally, in a steady state, the equalizer signal BLEQ is driven to a high level. This causes the transistor TR of the equalizer circuit EQ to malfunction. 81 ~TR 83 When it turns on, the bit line BL D -T,BL D -C is equalized to the precharge potential.

[0399] When the active command ACT is issued, the equalization is released, and the corresponding word line WL is generated based on the entered row address XADD. D This is driven to the VPP level by the word line driver 1220. The equalization is deactivated, i.e., the equalization circuit EQ remains inactive, from the time the active command ACT is issued until the precharge command is issued.

[0400] Word line WL DThe transistor Tr of the corresponding memory cell MC is driven to the VPP level. D The capacitor Cap of the memory cell MC turns on the bit line BL. D -T and bit line BL D -Connected to C. As a result, depending on the charge of the capacitor Cap of the memory cell MC, the bit line BL D -T or bit line BL D -The potential of C changes slightly. In the example in Figure 53, the bit line BL D This shows a slight increase in the potential at -T.

[0401] Subsequently, at predetermined timings, the sense signals SAN and SAP change to low and high levels, respectively, activating the sense amplifier circuit sac. As a result, the bit line BL D -T,BL D -The potential difference across C is amplified. In the example in Figure 53, the bit line BL D -C is driven at a low level, bit line BL D -T indicates that it is driven to a high level.

[0402] Next, when a read command is issued, the corresponding column selection signal YS changes to a high level according to the column address YADD entered in synchronization with the read command. Prior to the activation of the column selection signal YS, the local input / output lines LIOT and LIOB are pre-charged to the power supply voltage VCC.

[0403] When the column selection signal YS is activated, the transistor TR of the column switch YSW is activated. 71 ,TR 72 Because it turns on, bit line BL D -T,BL D -C is connected to the corresponding local input / output lines LIOT and LIOB. As a result, local input / output line LIOT is maintained at the precharge level, and local input / output line LIOB is reduced from the precharge level to a low level.

[0404] When the transfer gate TG is turned ON, the local input / output lines LIOT and LIOB are connected to the main input / output lines MIOT and MIOB. As a result, the main input / output line MIOT is maintained at the precharge level, while the main input / output line MIOB drops from the precharge level to a low level.

[0405] Through the above steps, data is read from the memory cell MC.

[0406] Furthermore, in Figures 52 and 53, the memory cell array 1201' shown in Figure 51 may be used instead of the memory cell array 1201 shown in Figure 50.

[0407] [Adjusting operating parameters in DRAM read operations] Word line WL D (For example, word line WL) D(1) If the wiring resistance between the word line driver 1220 (word line switch) is high, the word line driver 1220 will cause the word line WL D(1) Because the voltage applied during charging rises slowly (Figure 53), bit line BL D The stabilization waiting time Tg is increased. On the other hand, the word line WL D (For example, word line WL) D(2) If the wiring resistance between the word line driver 1220 (word line switch) is small, the word line driver 1220 will control the word line WL D Because the voltage applied during charging rises faster (Figure 53), bit line BL D Reduce the stabilization wait time Tg.

[0408] [Example of a three-dimensional DRAM structure] Next, we will describe an example of a three-dimensional DRAM structure.

[0409] Figure 54 is a schematic XY cross-sectional view showing the configuration of a DRAM. Figure 55 is a schematic cross-sectional view of the structure shown in Figure 54, cut along the CC' line and viewed in the direction of the arrow.

[0410] For example, as shown in Figure 55, the memory cell array 1201 consists of multiple memory layers ML arranged alternately in the Z direction. D The memory also includes an insulating layer 701 made of silicon oxide (SiO2) or the like. D An insulating layer 705 made of silicon oxide (SiO2) or the like is provided above the insulating layer 701.

[0411] As shown in Figure 54, the memory layer ML D This is the memory cell region R MC The capacitor structure is provided with a plurality of capacitor structures 710 arranged alternately in the Y direction and an insulating layer 702 made of silicon oxide (SiO2) or the like. Each capacitor structure 710 comprises electrodes 711 and 712 and an insulating layer 713 provided between them.

[0412] Electrode 711 functions as one electrode of capacitor Cap. Electrode 711 is extended in the X direction. One end of electrode 711 in the X direction is connected to plate wire PL. Electrodes 711 and 712 may contain, for example, polysilicon (Poly-Si), tungsten (W), tungsten nitride (WN), tungsten silicide (WSi), tungsten silicide (WSiN), molybdenum (Mo), molybdenum nitride (MoN), iridium (Ir), iridium oxide (IrO), ruthenium (Ru), ruthenium oxide (RuO), tantalum nitride (TaN), titanium nitride (TiN), titanium silicide (TiSiN), titanium ruthenium nitride (RuTiN), etc., or other conductive materials, or a laminated film of multiple conductive materials.

[0413] Furthermore, the plate wire PL extends in the Y and Z directions, forming multiple memory layers ML. D It is divided in the X direction. One side and the other side of the plate line PL in the X direction are each multiple memory layers ML D It is connected to multiple electrodes 711 corresponding to multiple capacitor structures 710. The plate wire PL may contain, for example, the same material as the electrodes 711.

[0414] Electrode 712 functions as the other electrode of the capacitor Cap. Electrode 712 faces the outer circumferential surface (top and bottom surfaces and both sides in the Y direction) of electrode 711 and extends in the X direction along the outer circumferential surface of electrode 711. One end of electrode 712 in the X direction is connected to a semiconductor layer 721, which will be described later. Electrode 712 may contain, for example, the same material as electrode 711.

[0415] The insulating layer 713 is provided between electrodes 711 and 712. The insulating layer 713 insulates electrodes 711 and 712. The insulating layer 713 may contain, for example, aluminum oxide (AlO), zirconium oxide (ZrO), hafnium oxide (HfO), niobium oxide (NbO), tantalum oxide (TaO), barium strontium titanate (BST), lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), or other insulating metal oxides, or other insulating materials, or mixtures thereof such as ZrHfO, ZrAlO, ZrNbO, etc. Furthermore, the insulating layer 713 may contain a multilayer film of multiple insulating materials, such as a multilayer film of zirconium oxide, aluminum oxide, and zirconium oxide (ZAZ), or a multilayer film of ZrHfO, ZrAlO, and ZrNbO. Furthermore, the insulating layer 713 may be a ferroelectric material.

[0416] Furthermore, as shown in Figure 54, the memory layer ML D This is the word line connection region R WL It is provided with a plurality of transistor structures 720 arranged in the Y direction. Each transistor structure 720 includes a semiconductor layer 721. It also has a word line connection region R WL The structure includes a conductive layer 722 and an insulating layer 723 provided on the outer surface of the conductive layer 722.

[0417] Semiconductor layer 721 is a transistor Tr DIt functions as a channel region or the like. The semiconductor layer 721 extends in the X direction. The semiconductor layer 721 may contain, for example, silicon (Si), germanium (Ge), carbon (C), zinc tin oxide (ZnSnO: generally referred to as “ZTO”), indium zinc oxide (InZnO: generally referred to as “IZO”), indium gallium zinc oxide (InGaZnO: generally referred to as “IGZO”), indium gallium silicon oxide (InGaSiO: generally referred to as “IGSO”), indium tungsten oxide (InWO: generally referred to as “IWO”), or other semiconductor materials, or may contain a laminated film of a plurality of semiconductor materials.

[0418] The conductive layer 722 functions as gate electrodes of a plurality of transistors Tr arranged in the Z direction and word lines WL D and. D A plurality of conductive layers 722 are provided corresponding to a plurality of transistor structures 720 arranged in the Y direction. The conductive layer 722 may contain, for example, polysilicon (Poly-Si), tungsten (W), tungsten nitride (WN), tungsten silicide (WSi), tungsten silicon nitride (WSiN), molybdenum (Mo), molybdenum nitride (MoN), iridium (Ir), iridium oxide (IrO), ruthenium (Ru), ruthenium oxide (RuO), tantalum nitride (TaN), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium titanium nitride (RuTiN), etc., or may contain other conductive materials, or may contain a laminated film of a plurality of conductive materials.

[0419] The insulating layer 723 is a transistor Tr DIt functions as a gate insulating film. The insulating layer 723 comprises a portion that covers the outer circumferential surface of the conductive layer 722 and a portion provided between the semiconductor layer 721 and the conductive layer 722. The insulating layer 723 insulates the semiconductor layer 721 and the conductive layer 722. The insulating layer 723 may contain, for example, aluminum oxide (AlO), zirconium oxide (ZrO), hafnium oxide (HfO), niobium oxide (NbO), tantalum oxide (TaO), barium strontium titanate (BST), lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), or other insulating metal oxides, or other insulating materials, or mixtures thereof such as ZrHfO, ZrAlO, ZrNbO, etc. The insulating layer 723 may contain a laminated film of multiple insulating materials. The insulating layer 723 may contain, for example, the same material as the insulating layer 713.

[0420] Furthermore, as shown in Figure 54, the memory layer ML D This is the word line connection region R WL The device is provided with two conductive layers 730 that are aligned in the X direction and extend in the Y direction. An insulating layer 703 made of silicon oxide (SiO2) or the like is provided between the two conductive layers 730 that are aligned in the X direction.

[0421] The conductive layer 730 functions as a bit line BL. The conductive layer 730 may contain, for example, polysilicon (Poly-Si), tungsten (W), tungsten nitride (WN), tungsten silicide (WSi), tungsten silicide nitride (WSiN), molybdenum (Mo), molybdenum nitride (MoN), iridium (Ir), iridium oxide (IrO), ruthenium (Ru), ruthenium oxide (RuO), tantalum nitride (TaN), titanium nitride (TiN), titanium silicide nitride (TiSiN), titanium ruthenium nitride (RuTiN), etc., or it may contain other conductive materials, or it may contain a laminated film of multiple conductive materials, such as a laminated film of titanium nitride (TiN) and tungsten (W).

[0422] Furthermore, as shown in Figure 54, the memory layer ML D This is the bit line connection region RBL It is provided with a conductive layer 740 that extends in the X direction. In addition, an insulating layer 704 made of silicon oxide (SiO2) or the like is provided on the Y-direction side of the conductive layer 740.

[0423] In the example shown in Figure 54, the conductive layer 740 is connected to the Y-direction end of the conductive layer 730. The conductive layer 740 may contain, for example, the same material as the conductive layer 730. In the example shown in Figure 54, the multiple conductive layers 740 arranged in the X-direction form a memory cell region R MC Each is electrically independent.

[0424] Even in this configuration, the word line WL D Wiring resistance R between the word line switch and the word line switch W Accordingly, the operating parameters for read and write operations are adjusted for each of the multiple division ranges. This allows for the execution of appropriate read and write operations.

[0425] [Other embodiments] The semiconductor memory devices according to the first to ninth embodiments have been described above. However, the configurations and operations described above are merely examples, and the specific configurations and operations can be adjusted as appropriate.

[0426] For example, in the first to fifth embodiments and the seventh to ninth embodiments, the word line WL was divided into two division ranges DU1 and DU2, and in the sixth embodiment, the word line WL was divided into four division ranges DU1 to DU4. However, the word line WL may also be divided into three division ranges, five or more division ranges.

[0427] Furthermore, for example, in the first to ninth embodiments, the multiple division ranges were of the same size (number of memory cells MC), but the multiple division ranges may each be of different sizes.

[0428] Furthermore, in this embodiment, at least some of the wiring materials (including contact CC) between the word line WL (divided range DU1, DU2) and the word line switch WLSW, such as the wiring width, wiring length, wiring height, the difference in the charging direction of the word line WL, and the position of the plane, result in a wiring resistance R W The resistance values ​​are different.

[0429] In general, read and write operations are executed using page PG as the execution unit. In this case, for example, page PG may be composed of multiple division ranges of a single word line WL, or page PG may be composed of division ranges of multiple word lines (for example, word lines WLi, WLo) (for example, division range DU1 of word line WLi, division range DU2 of word line WLo). Also, page PG may be composed of division ranges of word lines from different blocks (for example, word line WLi of block (1), word line WLo of block (2)) (for example, division range DU1 of word line WLi, division range DU2 of word line WLo). Furthermore, page PG may be composed of division ranges of word lines from predetermined blocks on different planes (for example, word line WLi of block (11) of plane (1), word line WLo of block (21) of plane (2)) (for example, division range DU1 of word line WLi, division range DU2 of word line WLo). Even with this configuration, it is possible to adjust the operating parameters for each division range.

[0430] For example, the memory cell array MCA according to the first to fourth embodiments consists of two memory cell array layers L aligned in the Z direction, as described with reference to Figure 13. MCA1 ,L MCA2 It also had a memory cell array layer L MCA1 Among the multiple conductive layers 110 contained therein, some conductive layers 200 (Figure 15) consist of two portions 201 aligned in the X direction and portions 202 connected thereto, and above this there is a pair of conductive layers 210 aligned in the X direction (Figure 16). Also, the memory cell array layer L MCA2Among the multiple conductive layers 110 contained therein, some conductive layers 220 (Figure 17) consist of two portions 221 aligned in the X direction and portions 222 connected thereto, and above this, a pair of conductive layers 230 (Figure 18) aligned in the X direction are provided.

[0431] However, this configuration is merely an example, and the specific configuration can be adjusted as needed.

[0432] For example, in the memory cell array MCA according to the first to fourth embodiments, the memory cell array layer L MCA2 This can be omitted. In such cases, the memory cell array layer L MCA1 The device may also include multiple conductive layers 110 (Figure 19) that function as drain-side select gate wires SGDs, etc.

[0433] Furthermore, for example, in the memory cell array MCA according to the first to fourth embodiments, the memory cell array layer L MCA1 and memory cell array layer L MCA2 One or more memory cell array layers may be provided between them. Each of these memory cell array layers may contain multiple conductive layers 110. Furthermore, some of these multiple conductive layers 110 may have two parts aligned in the X direction and a part connected thereto. Above this, a pair of conductive layers 110 aligned in the X direction may be provided.

[0434] Furthermore, in the above examples, a memory transistor was shown with a configuration that includes an insulating or conductive charge storage portion in the gate insulating film. However, such configurations are merely illustrative, and the components included in the gate insulating film of a memory transistor can be adjusted as appropriate. For example, a memory transistor may be configured to include a ferroelectric material in the gate insulating film.

[0435] Furthermore, in the above example, a configuration with multiple memory transistors was illustrated as a memory cell array (MCA). However, such a configuration is merely illustrative, and the specific configuration can be adjusted as appropriate. For example, a configuration other than memory transistors may be adopted for the memory cell array (MCA).

[0436] Alternatively, for example, the memory cell array MCA may be SRAM (Static Random Access Memory). SRAM has two CMOS inverters. The input terminal of one is connected to the output terminal of the other, and the output terminal of one is connected to the input terminal of the other.

[0437] Furthermore, the memory cell array MCA may be a magnetoresistive random access memory (MRAM) or a spin-transfer torque MRAM (STT-MRAM). MRAM and STT-MRAM include a pair of ferromagnetic films and a tunnel insulating film. The pair of ferromagnetic films are arranged opposite each other. The tunnel insulating film is provided between the pair of ferromagnetic films. The magnetization direction of the ferromagnetic films changes in response to the write operation.

[0438] Furthermore, the memory cell array MCA may be a resistive random access memory such as ReRAM (Resistive Random Access Memory). ReRAM includes a pair of electrodes and a metal oxide, etc. The metal oxide, etc. is placed between the pair of electrodes. Filaments such as oxygen vacancies are formed in the metal oxide, etc. in response to the write operation. The pair of electrodes are electrically connected or disconnected through these filaments such as oxygen vacancies.

[0439] Furthermore, the memory cell array MCA may also be a phase-change memory such as PCRAM (Phase Change Random Access Memory) or PCM (Phase Change Memory). The phase-change memory may contain a chalcogenide film such as GeSbTe. The crystalline state of the chalcogenide film may change in accordance with the write operation.

[0440] [others] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0441] 110, 200, 210, 220, 230, 510, 722... Conductive layer (word line), 120, 520, 721... Semiconductor layer, 130... Gate insulating film, WL... Word line, BL... Bit line, DU1, DU2, DU3, DU4... Division range.

Claims

1. circuit board and A word line conductive layer having a first range and a second range aligned in the second range, which are spaced apart from the substrate in a first direction intersecting the surface of the substrate, extend in a second direction intersecting the first direction, and which are spaced apart from the substrate in a first range. A first semiconductor layer extending in the first direction and facing the word line conductive layer in the first range, A second semiconductor layer extending in the first direction and facing the word line conductive layer in the second range, A first charge storage unit is provided between the word wire conductive layer and the first semiconductor layer, A second charge storage unit is provided between the word wire conductive layer and the second semiconductor layer, A first bit line electrically connected to one end of the first semiconductor layer, A second bit line electrically connected to one end of the second semiconductor layer, A driver circuit that controls the voltage supplied to the word wire conductive layer, A first wiring includes a first contact electrically connected to the first range and a first circuit, The second range includes a second contact electrically connected to the second range, and a second wiring connecting the second range and the second circuit. Equipped with, The resistance of the first wiring is greater than the resistance of the second wiring. The first contact and the second contact are provided between the first semiconductor layer and the second semiconductor layer. When performing a predetermined operation on the first memory cell including the first charge storage unit, the magnitude and supply time of one or more voltages supplied to the first bit line, the stabilization waiting time until sensing of the first bit line begins, and the sensing time of the first bit line are defined as first operation parameters. When the predetermined operation is performed on the second memory cell including the second charge storage unit, the magnitude and supply time of one or more voltages supplied to the second bit line, the stabilization waiting time until sensing of the second bit line begins, and the sensing time of the second bit line are defined as the second operation parameters. At least a portion of the second operating parameters differs from at least a portion of the first operating parameters. Semiconductor memory device.

2. When the predetermined operation is performed on the first memory cell, at least one of the magnitude and supply time of one or more voltages supplied to the first bit line is greater than at least one of the magnitude and supply time of one or more voltages supplied to the second bit line when the predetermined operation is performed on the second memory cell. The semiconductor memory device according to claim 1.

3. When the predetermined operation is performed on the first memory cell, the stable waiting time until sensing of the first bit line is longer than when the predetermined operation is performed on the second memory cell, the stable waiting time until sensing of the second bit line is longer. The semiconductor memory device according to claim 1.

4. The sense time of the first bit line when performing the predetermined operation on the first memory cell is shorter than the sense time of the second bit line when performing the predetermined operation on the second memory cell. The semiconductor memory device according to claim 1.

5. A first source line electrically connected to the other end of the first semiconductor layer, A second source line electrically connected to the other end of the second semiconductor layer and Equipped with, When performing the predetermined operation on the first memory cell, at least one of the magnitude of the voltage supplied to the first source line and the supply time is greater than at least one of the magnitude of the voltage supplied to the second source line when performing the predetermined operation on the second memory cell. The semiconductor memory device according to claim 1.

6. The word wire conductive layer is A third range is provided between the first range and the first contact, A fourth range provided between the second range and the second contact and Equipped with, The third range is longer or shorter in width than the fourth range. The semiconductor memory device according to claim 1.

7. A conductive layer comprising multiple conductive layers arranged in a first direction, extending in a second direction intersecting the first direction, a first conductive layer that overlaps with the sense amplifier region when viewed from the first direction, and a second conductive layer that does not overlap with the sense amplifier region when viewed from the first direction, A first semiconductor layer stretched in the aforementioned first direction and facing the aforementioned first conductive layer, A second semiconductor layer stretched in the first direction and facing the second conductive layer, A first charge storage unit provided between the first conductive layer and the first semiconductor layer, A second charge storage unit is provided between the second conductive layer and the second semiconductor layer, A first bit line electrically connected to one end of the first semiconductor layer, A second bit line electrically connected to one end of the second semiconductor layer, A first driver circuit that controls the voltage supplied to the first conductive layer, A second driver circuit that controls the voltage supplied to the second conductive layer and Equipped with, When performing a predetermined operation on the first memory cell including the first charge storage unit, the magnitude and supply time of one or more voltages supplied to the first conductive layer are defined as the first operation parameters. When the predetermined operation is performed on the second memory cell including the second charge storage unit, the magnitude and supply time of one or more voltages supplied to the second conductive layer are defined as the second operation parameters. At least a portion of the second operating parameters differs from at least a portion of the first operating parameters. Semiconductor memory device.

8. The device comprises a first wiring that connects the first conductive layer and the first circuit, and a second wiring that connects the second conductive layer and the second circuit. The resistance of the first wiring is greater than the resistance of the second wiring. When performing the predetermined operation on the first memory cell, at least one of the magnitude of one or more voltages supplied to the first conductive layer and the supply time is greater than at least one of the magnitude of one or more voltages supplied to the second conductive layer when performing the predetermined operation on the second memory cell. The semiconductor memory device according to claim 7.

9. The first operation parameter includes the magnitude and supply time of one or more voltages supplied to the first bit line when performing the predetermined operation on the first memory cell, a stabilization waiting time until sensing of the first bit line begins, and the sensing time of the first bit line. The second operation parameter includes the magnitude and supply time of one or more voltages supplied to the second bit line when performing the predetermined operation on the second memory cell, a stabilization waiting time until sensing of the second bit line begins, and the sensing time of the second bit line. The semiconductor memory device according to claim 7.

10. The device comprises a first wiring that connects the first conductive layer and the first circuit, and a second wiring that connects the second conductive layer and the second circuit. The resistance of the first wiring is greater than the resistance of the second wiring. When performing the predetermined operation on the first memory cell, at least one of the magnitude and supply time of one or more voltages supplied to the first bit line is greater than at least one of the magnitude and supply time of one or more voltages supplied to the second bit line when performing the predetermined operation on the second memory cell. The semiconductor memory device according to claim 9.

11. The device comprises a first wiring that connects the first conductive layer and the first circuit, and a second wiring that connects the second conductive layer and the second circuit. The resistance of the first wiring is greater than the resistance of the second wiring. When the predetermined operation is performed on the first memory cell, the stable waiting time until sensing of the first bit line begins is longer than when the predetermined operation is performed on the second memory cell, the stable waiting time until sensing of the second bit line begins. The semiconductor memory device according to claim 9.

12. The device comprises a first wiring that connects the first conductive layer and the first circuit, and a second wiring that connects the second conductive layer and the second circuit. The resistance of the first wiring is greater than the resistance of the second wiring. When performing the predetermined operation on the first memory cell, the sense time of the first bit line is shorter than when performing the predetermined operation on the second memory cell. The semiconductor memory device according to claim 9.

13. A first source line electrically connected to the other end of the first semiconductor layer, A second source line electrically connected to the other end of the second semiconductor layer and A first wiring that connects the first conductive layer and the first circuit, A second wiring that connects the second conductive layer and the second circuit, Equipped with, The resistance of the first wiring is greater than the resistance of the second wiring. When performing the predetermined operation on the first memory cell, at least one of the magnitude of the voltage supplied to the first source line and the supply time is greater than at least one of the magnitude of the voltage supplied to the second source line when performing the predetermined operation on the second memory cell. The semiconductor memory device according to claim 7.

14. The first wiring has a shorter wiring length in the copper wiring layer than the second wiring. The semiconductor memory device according to claim 8.

15. A conductive layer comprising multiple conductive layers arranged in a first direction, extending in a second direction intersecting the first direction, a first conductive layer that overlaps with the sense amplifier region when viewed from the first direction, and a second conductive layer that does not overlap with the sense amplifier region when viewed from the first direction, A first semiconductor layer stretched in the aforementioned first direction and facing the aforementioned first conductive layer, A second semiconductor layer stretched in the first direction and facing the second conductive layer, A first charge storage unit provided between the first conductive layer and the first semiconductor layer, A second charge storage unit is provided between the second conductive layer and the second semiconductor layer, A first bit line electrically connected to one end of the first semiconductor layer, Electrically connected to one end of the second semiconductor layer The second bit line and, A first driver circuit that controls the voltage supplied to the first conductive layer, A second driver circuit that controls the voltage supplied to the second conductive layer, A first wiring that connects the first conductive layer and the first circuit, A second wiring that connects the second conductive layer and the second circuit, Equipped with, The resistance of the first wiring is greater than the resistance of the second wiring. The magnitude and supply time of one or more voltages supplied to the first bit line, the stabilization waiting time until sensing of the first bit line begins, and the sensing time of the first bit line are defined as the first operation parameters when performing a predetermined operation on the first memory cell including the first charge storage unit. When the predetermined operation is performed on the second memory cell including the second charge storage unit, the magnitude and supply time of one or more voltages supplied to the second bit line, the stabilization waiting time until sensing of the second bit line begins, and the sensing time of the second bit line are defined as the second operation parameters. At least a portion of the second operating parameters differs from at least a portion of the first operating parameters. Semiconductor memory device.

16. When performing the predetermined operation on the first memory cell, at least one of the magnitude and supply time of one or more voltages supplied to the first bit line is greater than at least one of the magnitude and supply time of one or more voltages supplied to the second bit line when performing the predetermined operation on the second memory cell. The semiconductor memory device according to claim 15.

17. When the predetermined operation is performed on the first memory cell, the stable waiting time until sensing of the first bit line begins is longer than when the predetermined operation is performed on the second memory cell, the stable waiting time until sensing of the second bit line begins. The semiconductor memory device according to claim 15.

18. When performing the predetermined operation on the first memory cell, the sense time of the first bit line is shorter than when performing the predetermined operation on the second memory cell. The semiconductor memory device according to claim 15.

19. A first source line electrically connected to the other end of the first semiconductor layer, A second source line electrically connected to the other end of the second semiconductor layer and Equipped with, When performing the predetermined operation on the first memory cell, at least one of the magnitude of the voltage supplied to the first source line and the supply time is greater than at least one of the magnitude of the voltage supplied to the second source line when performing the predetermined operation on the second memory cell. The semiconductor memory device according to claim 15.

20. The first and second wirings differ in at least one of the material, width, height, and length. A semiconductor memory device according to any one of claims 2, 8, and 15.

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