In-memory computing device and method

Abstract

To provide an in-memory computing device and method.SOLUTION: According to an embodiment, a multiply and accumulator (MAC) circuit includes: a field-effect transistor for applying a middle voltage Vmid to a node; a pair of resistance elements having respective determined resistance values on the basis of the middle voltage Vmid applied to one end connected to the node and a weighting value setting voltage applied to the other end; a plurality of multipliers including a capacitor for receiving a voltage that occurs at the node on the basis of an input voltage individually applied to each of the other ends of the pair of resistance elements and a combined resistance value of the pair of resistance elements in response to the case that individual resistance values of the pair of resistance elements are determined so as to charge / discharge electrical charge; and an output line for outputting a voltage based on the electrical charge charged / discharged to / from the plurality of multipliers.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an in-memory computing device and method. [Background technology]

[0002] Vector-matrix multiplication operations, also known as MAC (multiply and accumulate) operations, significantly impact application performance in various fields. For example, MAC operations may be performed in machine learning and authentication operations of neural networks involving multiple layers. The input signal is considered to form an input vector and may be data for an image, byte stream, or other dataset. The input signal is multiplied by a weighted value, and the output vector is obtained from the accumulated MAC operation results, which can then be provided as the input vector for the next layer. Since such MAC operations are repeated across multiple layers, the processing performance of the neural network is primarily determined by the performance of the MAC operations. [Overview of the project] [Problems that the invention aims to solve]

[0003] The object of the present invention is to provide an in-memory computing device and method. [Means for solving the problem]

[0004] A multiply and accumulator (MAC) circuit according to one embodiment has an intermediate voltage V at the node. mid A field-effect transistor to which the voltage is applied, and the intermediate voltage V applied to one end connected to the node. midThe device includes, and a plurality of multipliers, each including a pair of resistive elements having a resistance value determined based on a weighted value setting voltage applied to the other end, and a capacitor that receives a voltage generated at the node and charges / discharges a charge based on an input voltage individually applied to the other end of each pair of resistive elements and the combined resistance value of the pair of resistive elements in response to the determination of the individual resistance values ​​of the pair of resistive elements, and an output line that outputs a voltage based on the charge charged / discharged to the plurality of multipliers.

[0005] Each pair of resistive elements may be one of either a resistive random access memory (RRAM) or a magnetic random access memory (MRAM).

[0006] Each of the pairs of resistive elements may be a resistive element whose resistance value is variable.

[0007] The multiplier accumulator circuit can determine the resistance value of each pair of resistive elements by applying a voltage across each of the pairs of resistive elements to each of the plurality of multipliers, and can record the weighted value based on the combined resistance values ​​of the pairs of resistive elements in the corresponding multiplier.

[0008] The combined resistance of the pair of resistive elements can correspond to any one of the ternary values ​​representing the weighted connection lines between layers included in the neural network.

[0009] The multiplier accumulator circuit can precharge the capacitor to the preset voltage by applying a preset voltage to the input terminals connected to the other end of each pair of resistive elements and by applying the preset voltage to the output line, before applying the input voltage to each pair of resistive elements.

[0010] The multiplier accumulator circuit can, in response to the determination of the resistance values ​​of each pair of resistive elements, individually apply the input voltage to the input terminals connected to the other end of each pair of resistive elements, and apply the input value resulting from the combined input voltages to the multiplier.

[0011] The combined input voltages can correspond to any one of the ternary values ​​representing the output values ​​of the nodes included in the layers of the neural network.

[0012] The multiplier accumulator circuit can generate a voltage at the node that corresponds to a value calculated by multiplying the input value corresponding to the combination of input voltages individually applied to each pair of resistive elements by a weighting value corresponding to the combination of resistance values ​​of the pair of resistive elements.

[0013] The output line is connected to each of the capacitors included in each of the plurality of multipliers and can output a voltage based on the accumulation of charge charged / discharged to each of the plurality of multipliers' capacitors via capacitive coupling.

[0014] A computing method performed by a multiplier accumulator circuit according to one embodiment involves applying an intermediate voltage V to one end of each pair of resistive elements connected to a node. mid The operation includes, and, determining the resistance value of each of the pair of resistive elements based on a weighted value setting voltage applied to the other end of each of the pair of resistive elements; and, in response to the determination of the individual resistance values ​​of the pair of resistive elements, charging / discharging charges based on the voltage generated at the node based on the input voltage applied individually to the other end of each of the pair of resistive elements and the combined resistance value of the pair of resistive elements; and outputting a voltage based on the charges being charged / discharged.

[0015] Each pair of resistive elements may be one of either a resistive random access memory (RRAM) or a magnetic random access memory (MRAM).

[0016] The operation of determining the resistance value of each of the pair of resistive elements may include the operation of determining the resistance value of each of the pair of resistive elements by applying a voltage across each of the pair of resistive elements, and the operation of recording a weighted value based on the combined resistance values ​​of the pair of resistive elements in a multiplier that includes the pair of resistive elements.

[0017] The combined resistance of the pair of resistive elements can correspond to any one of the ternary values ​​representing the weighted connection lines between layers included in the neural network.

[0018] The charge / discharge operation may include precharging the capacitor to the preset voltage by applying a preset voltage to the input terminals connected to the other end of each pair of resistive elements and applying the preset voltage to the output line, before applying the input voltage to each pair of resistive elements.

[0019] The charging / discharging operation may include, in response to the determination of the resistance values ​​of each pair of resistive elements, applying the input voltage individually to the input terminals connected to the other end of each pair of resistive elements, and applying the input value resulting from the combined input voltages to a multiplier.

[0020] The combined input voltages can correspond to any one of the ternary values ​​representing the output values ​​of the nodes included in the layers of the neural network.

[0021] The charging / discharging operation may include generating a voltage at the node that corresponds to a value calculated by multiplying an input value corresponding to the combination of input voltages individually applied to each pair of resistive elements by a weighting value corresponding to the combination of resistance values ​​of the pair of resistive elements.

[0022] The multiplier constituting the multiplier accumulator circuit according to one embodiment has an intermediate voltage V at the node. mid A field-effect transistor to which the voltage is applied, and the intermediate voltage V applied to one end connected to the node mid The device includes, and a pair of resistive elements having resistance values ​​determined based on a weighted value setting voltage applied to the other end, and a capacitor that receives a voltage generated at the node and charges / discharges based on an input voltage individually applied to the other end of each of the pair of resistive elements and the combined resistance value of the pair of resistive elements in response to the determination of the individual resistance values ​​of the pair of resistive elements.

[0023] The multiplier can generate a voltage at the node that corresponds to a value calculated by multiplying the input value corresponding to the combination of input voltages individually applied to each pair of resistive elements by a weighting value corresponding to the combination of resistance values ​​of the pair of resistive elements.

[0024] A method performed by a multiplier accumulator (MAC) circuit according to one embodiment involves applying an intermediate voltage V to the node corresponding to one end of the first resistive element and the second resistive element of one multiplier. mid The operation includes: recording a weight value for one multiplier by applying a voltage, applying a first weight value setting voltage to the other end of the first resistive element, and applying a second weight value setting voltage to the other end of the second resistive element; applying an input value to one multiplier by applying a first input voltage to the other end of the first resistive element and applying a second input voltage to the other end of the second resistive element; and generating an output value for a neural network node by discharging a capacitor in response to the application of the input value.

[0025] The operation for recording the weighted value includes: an operation to record a first weighted value in response to the first weighted value setting voltage being greater than the second weighted value setting voltage; an operation to record a second weighted value in response to the first weighted value setting voltage being the same value as the second weighted value setting voltage; and an operation to record a third weighted value in response to the first weighted value setting voltage being less than the second weighted value setting voltage. The operation of applying the input values ​​may include: an operation of applying a first input value in response to the first input voltage being greater than the second input voltage; an operation of applying a second input value in response to the first input voltage being the same value as the second input voltage; and an operation of applying a third input value in response to the first input voltage being less than the second input voltage.

[0026] A method performed by a multiplier accumulator circuit according to one embodiment further includes applying a predetermined voltage to an output line connected to the other end of the first resistive element, the other end of the second resistive element, and one end of the capacitor in response to the recording of the weighted value, wherein the operation of applying the input value may include the operation of applying the input value in response to the application of the predetermined voltage. [Effects of the Invention]

[0027] According to the present invention, an in-memory computing device and method can be provided. [Brief explanation of the drawing]

[0028] [Figure 1] This figure shows one multiplier that constitutes a multiply-accumulator (MAC) circuit according to one embodiment. [Figure 2] This is a flowchart illustrating a computing method using a multiplier accumulator circuit according to one embodiment. [Figure 3A] This diagram illustrates the process by which a multiplier accumulator circuit according to one embodiment records weighted values ​​in a multiplier. [Figure 3B] This diagram illustrates the process by which a multiplier accumulator circuit according to one embodiment records weighted values ​​in a multiplier. [Figure 4] This figure illustrates the process by which a multiplier accumulator circuit according to one embodiment precharges the capacitor with a preset voltage before applying the input value to the multiplier. [Figure 5A] This diagram illustrates the process by which a multiplier accumulator circuit according to one embodiment applies an input value to a multiplier. [Figure 5B] This diagram illustrates the process by which a multiplier accumulator circuit according to one embodiment applies an input value to a multiplier. [Figure 6] This figure illustrates the structure of a multiplier accumulator circuit according to one embodiment. [Figure 7] This figure illustrates the weight values ​​that can be recorded in the multiplier of a multiplier accumulator circuit according to one embodiment. [Figure 8] This figure illustrates the input values ​​that can be applied to the multiplier in a multiplier accumulator circuit according to one embodiment. [Figure 9] This figure illustrates an example of a neural network operation implemented by a multiplier accumulator circuit according to one embodiment. [Modes for carrying out the invention]

[0029] The specific structural or functional descriptions of the embodiments are disclosed for illustrative purposes only and may be modified in various ways. Therefore, the embodiments are not limited to any particular disclosure, and the scope of this specification includes modifications, equivalents, or substitutions that are part of the technical concept.

[0030] Terms such as "first" or "second" may be used to describe multiple components, but such terms should be interpreted solely for the purpose of distinguishing one component from others. For example, the first component may be named the second component, and similarly, the second component may be named the first component.

[0031] Whenever one component is described as being “linked” or “connected” to another component, it should be understood that it is directly linked to or connected to the other component, but with other components potentially in between.

[0032] A singular expression includes plural expressions unless the context clearly indicates otherwise. In this specification, terms such as “includes” or “has” indicate the presence of features, figures, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood not to presuppose the presence or addition of one or more other features, figures, steps, actions, components, parts, or combinations thereof.

[0033] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as those generally understood by a person of ordinary skill in the art to which this embodiment belongs. Commonly used, predefined terms should be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as ideal or overly formal unless expressly defined herein.

[0034] The embodiments will be described in detail below with reference to the attached drawings. When describing with reference to the drawings, the same components will be given the same reference numerals regardless of the reference numerals used in the drawings, and redundant explanations will be omitted.

[0035] Figure 1 shows a multiplier that constitutes a multiply-accumulator (MAC) circuit according to one embodiment.

[0036] For the efficient implementation of artificial intelligence, accelerating neural network computations is necessary, and the processing performance of a neural network is primarily determined by the performance of MAC (Machine Access Computation) operations. When implementing neural network computations with conventional von Neumann-type hardware, bottlenecks caused by excessive memory access traffic and inefficiencies due to energy consumption during memory access become problematic, making it difficult to efficiently implement MAC operations. To overcome this, various forms of in-memory computing are being researched, one of which is a method of accelerating neural network computations using non-volatile memory elements. Conventional technologies have proposed methods for performing in-memory computing operations using resistive elements such as resistive random access memory (RRAM) and magnetic random access memory (MRAM). By implementing various neural network operations in memory using resistance changes of various non-volatile elements such as RRAM and MRAM, it is possible to reduce memory access and realize neural network computations with significantly improved computational efficiency. In particular, conventional multiplier accumulator circuits that perform neural network calculations and are composed of resistive elements such as RRAM and MRAM acquire the result of MAC calculation in the form of a current and output the calculation result via a current sense amplifier. However, this current sensing method suffers from the problem that the detection range overlaps when the MAC value, which is the result of MAC calculation, becomes large. To improve this problem, multiplier accumulator circuits that acquire the result of MAC calculation in the form of a voltage using a voltage sensing method have been devised. However, conventional multiplier accumulator circuits composed of resistive elements such as RRAM and MRAM that use the voltage sensing method have the problem that the linearity between the MAC calculation result and the output of the multiplier accumulator circuit is not guaranteed depending on the number of resistive elements used.For example, conventional multiplier accumulator circuits composed of resistive elements of RRAM have a problem in that the linearity between the MAC calculation result and the output of the multiplier accumulator circuit is difficult to guarantee depending on the number of resistive elements of the RRAM used in the turn-on state (e.g., low resistance state (LRS)). Conventional multiplier accumulator circuits used additional circuits to correct the linearity between the MAC calculation result and the output of the multiplier accumulator circuit, but they did not exhibit perfect linearity.

[0037] Furthermore, in-memory computing operations using resistive elements are sensitive to the problem of variable resistance values ​​of the resistive elements themselves. To solve this problem of variable resistance values ​​of resistive elements, the Write-Verify method is mainly used, which repeatedly reads and writes using the resistance value of the resistive element over various periods. This Write-Verify method corrects the problem of variable resistance values ​​of resistive elements and can guarantee the on / off ratio of the resistive element. Conventionally, in-memory computing operations using resistive elements could not be realized unless the on / off ratio of the resistive element was guaranteed. Here, the on / off ratio of the resistive element represents the ratio of the resistance value when the resistive element is on to the resistance value when the resistive element is off.

[0038] In other words, conventional multiplier accumulator circuits capable of performing in-memory computing operations have problems with linearity between the MAC operation result and the output of the multiplier accumulator circuit, the variability problem of resistive elements, and the additional temporal and spatial damage incurred to compensate for the on / off ratio of resistive elements. As will be described later, a multiplier accumulator circuit according to one embodiment can guarantee linearity between the MAC operation result and the output of the multiplier accumulator circuit, is highly resistant to the variability problem of resistive elements, and can perform MAC operations even if the on / off ratio of resistive elements is relatively small, as long as it is guaranteed to some extent. Below, a multiplier accumulator circuit according to one embodiment, which is composed of non-volatile elements and performs neural network operations, will be described.

[0039] The multiplier-accumulator circuit may be a circuit that outputs a value obtained by accumulating multiplication results. The multiplier-accumulator circuit according to one embodiment includes a plurality of multipliers and output lines respectively connected to the plurality of multipliers. First, in FIG. 1, one multiplier 100 constituting the multiplier-accumulator circuit according to one embodiment will be described.

[0040] The multiplier 100 according to one embodiment includes a field-effect transistor 110, a pair of resistive elements 121, 122, and a capacitor 130. The multiplier 100 is also connected to an output line 140. More specifically, the output line 140 is connected to one end of the capacitor 130 of the multiplier. As will be described later, the capacitor 130 multiplies an input value corresponding to a combination of a weighted value recorded in the multiplier 100 and an input voltage applied to the multiplier 100 by a combined resistance value of the pair of resistive elements 121, 122, receives a voltage corresponding to the calculated value, and can charge / discharge electric charges. Further, the output line 140 can output a voltage based on the accumulation of the electric charges charged / discharged to each of the capacitors of the plurality of multipliers included in the multiplier-accumulator circuit.

[0041] The field-effect transistor 110 applies an intermediate voltage V mid to a node 101 where the pair of resistive elements 121, 122 are connected to each other. The field-effect transistor 110 may be connected to the pair of resistive elements 121, 122 at the node 101 respectively. For example, the field-effect transistor 110 may be an NMOS transistor or a PMOS transistor. A word line (WL) may be connected to the gate terminal of the field-effect transistor 110. For example, the word line may be a line connected to the gate terminals of the field-effect transistors included in each of the plurality of multipliers. The reference voltage V DD is input to the word line, and here, the reference voltage V DD is applied to the gate terminal of the field-effect transistor connected to the word line. When the reference voltage is applied to the gate terminal, the field-effect transistor is turned on. <00002?6>

[0042] Each pair of resistive elements 121 and 122 may be resistive devices having various resistance values. The first resistive element 121 and the second resistive element 122 are connected via node 101. One end of the first resistive element 121 is connected to node 101, and the other end is connected to a positive input terminal 151. One end of the second resistive element 122 is connected to node 101, and the other end is connected to a negative input terminal 152. Hereinafter, in this specification, the positive input terminal will be described as the first input terminal, and the negative input terminal will be described as the second input terminal.

[0043] Each of the resistive element pairs 121 and 122 may be resistive elements having various resistance values. Each of the resistive element pairs 121 and 122 may be a variable resistor. According to one embodiment, each of the resistive element pairs 121 and 122 may be one of a resistive random access memory (RRAM) and a magnetic random access memory (MRAM). For example, a resistive random access memory is a type of non-volatile memory element with an insulating film between two metal plates, and its resistance can be changed by a voltage applied across the elements. For example, an RRAM may have a high resistance state (HRS) or a low resistance state (LRS) depending on the voltage applied externally. As a different example, an MRAM, also a non-volatile memory element, may have a parallel state with a high resistance or an anti-parallel state with a low resistance depending on the voltage applied externally. However, the type of resistive element is not necessarily limited to this, and other resistive elements with multiple resistance values ​​can also be used in the multiplier accumulator circuit according to one embodiment.

[0044] The multiplier accumulator circuit can determine the resistance values ​​of each pair of resistive elements 121 and 122 by applying a voltage across each of the resistive element pairs 121 and 122 for each multiplier. The resistance value of the first resistive element 121 may be determined based on the input voltage applied to node 101 and the weighted value setting voltage applied to the first input terminal 151. Similarly, the resistance value of the second resistive element 122 may be determined based on the input voltage applied to node 101 and the weighted value setting voltage applied to the negative input terminal 152. When the field-effect transistor 110 is turned on, in order to determine the resistance values ​​of each pair of resistive elements 121 and 122, the field-effect transistor 110 applies an intermediate voltage V to node 101. mid Apply the voltage. Here, the resistance value of the first resistive element 121 is the intermediate voltage V applied to one end connected to node 101. mid The resistance value of the second resistive element 122 is determined based on the weight value setting voltage applied to the other end, and the resistance value of the second resistive element 122 is determined based on the intermediate voltage V applied to one end connected to node 101. mid The weight value setting voltage may be determined based on the weight value setting voltage applied to the other end. Here, the weight value setting voltage applied to the first input terminal 151 connected to the other end of the first resistive element 121 and the weight value setting voltage applied to the second input terminal 152 connected to the other end of the second resistive element 122 may be the same or may be different from each other.

[0045] Capacitor C130 is connected to the resistive element pair 121, 122 and the field-effect transistor 110, respectively, and can be charged or discharged by receiving voltage. For example, capacitor 130 may receive the voltage generated at node 101 and charge or discharge. More specifically, after the individual resistance values ​​of resistive element pair 121, 122 are determined, capacitor 130 can receive the voltage generated at node 101 based on the input voltage individually applied to the other end of each resistive element pair and the combined resistance value of resistive element pair 121, 122, and charge / discharge.

[0046] Figure 2 is a flowchart illustrating a computing method using a multiplier accumulator circuit according to one embodiment.

[0047] First, in operation S210, the multiplier accumulator circuit determines the resistance value of each pair of resistive elements for each of the multiple multipliers, and records the weighted value corresponding to the combined resistance value of the pair of resistive elements.

[0048] The multiplier accumulator circuit applies an intermediate voltage V to one end of each pair of resistive elements contained in a particular multiplier among several multipliers. mid An intermediate voltage is applied to one end of each pair of resistive elements, and a weighting value setting voltage is applied to the other end. The multiplier accumulator circuit uses a field-effect transistor to apply an intermediate voltage to one end of each pair of resistive elements, and can apply a weighting value setting voltage to the other end of each pair of resistive elements via the input terminal included in the corresponding multiplier. As will be described later, the combined resistance value of a pair of resistive elements corresponds to one weighting value, and the multiplier accumulator circuit records the weighting value corresponding to the combined resistance value of each pair of resistive elements for each of the multiple multipliers.

[0049] Next, in operation S220, the multiplier accumulator circuit precharges the capacitors for each multiplier to a predetermined voltage.

[0050] The multiplier accumulator circuit can apply a preset voltage to the output line connected to each capacitor included in the multiple multipliers after the resistance values ​​of the pair of resistive elements have been determined. Here, the preset voltage may be applied to one end of the capacitor included in each of the multiple multipliers. Alternatively, the multiplier accumulator circuit may apply a preset voltage to the input terminal of each of the multiple multipliers. Here, the preset voltage may be applied to the other end of the capacitor included in the multiple multipliers. In summary, the multiplier accumulator circuit can apply a preset voltage across the capacitors of each of the multiple multipliers. Here, the preset voltage is the read voltage V read It may also be read voltage V readThis indicates the voltage used to read the resistance values ​​of a pair of resistive elements.

[0051] Then, in operation S230, the multiplier accumulator circuit applies an input value by applying an input voltage to the input terminal for each of the multiple multipliers.

[0052] A multiplier accumulator circuit applies an input voltage to the input terminal of each of its multiple multipliers. As will be described later, each combination of input voltages corresponds to a single input value, and the multiplier accumulator circuit can apply an input value corresponding to each combination of input voltages to each of its multiple multipliers.

[0053] The capacitor of the multiplier receives a voltage corresponding to the product of the input value corresponding to the combination of input voltages applied to the multiplier and the weighted value corresponding to the combination of resistance values ​​of the pair of resistive elements included in the multiplier, and can charge / discharge based on the received voltage. The output line then outputs a voltage based on the charge being charged or discharged to each of the multiple multipliers, thereby enabling MAC calculation.

[0054] Figure 3A illustrates the process by which a multiplier accumulator circuit according to one embodiment records weighted values ​​in the multiplier.

[0055] The multiplier accumulator circuit records a weighted value for one of several multipliers, the multiplier 300. The multiplier accumulator circuit can determine the resistance values ​​of the first resistive element 321 and the second resistive element 322. The resistance values ​​of the resistive elements can be changed by the voltage across the resistive elements.

[0056] According to one embodiment, a resistive element can enter an on state or an off state depending on the voltage applied across the resistive element. The resistive element may have a first resistance value, which is a low resistance value, in the on state, and a second resistance value, which is a high resistance value, in the off state. For example, if the resistive element is an RRAM, the on state may correspond to a low resistance state (LRS) with a low resistance value of the RRAM, and the off state may correspond to a high resistance state (HRS) with a high resistance value of the RRAM. As a different example, if the resistive element is an MRAM, the on state may correspond to an anti-parallel state with a low resistance value of the MRAM, and the off state may correspond to a parallel state with a high resistance value.

[0057] The multiplier accumulator circuit can record a weighted value in the multiplier 300 based on the combined resistance values ​​of the resistive element pair 321,322. For example, the weighted value may be any one of the ternary values ​​+1, 0, or -1. The weighted value recorded based on the combined resistance values ​​of the resistive element pair will be explained more specifically with reference to Figure 4.

[0058] The multiplier-accumulator circuit can determine the resistance values ​​of each pair of resistive elements 321 and 322 by applying a voltage across each of the resistive element pairs 321 and 322. First, the multiplier-accumulator circuit applies an intermediate voltage V using a field-effect transistor 310 to node 301 connected to one end of the first resistive element 321 and the second resistive element 322. mid Apply the voltage. As described above, the gate terminal of the field-effect transistor 310 is connected to the word line. A reference voltage V is applied to the word line. DD When a reference voltage V is input, a reference voltage V is applied to the gate terminal of the field-effect transistor 310 connected to the word line. DD A reference voltage V is applied. DD When a voltage is applied to the gate terminal of the field-effect transistor 310, the field-effect transistor 310 can be turned on.

[0059] The first terminal of the field-effect transistor 310 indicates the terminal connected to the source line, and the second terminal of the field-effect transistor indicates the terminal connected to node 301. The first terminal of the field-effect transistor may be either the drain terminal or the source terminal, and the second terminal may be the remaining terminal. An intermediate voltage V is applied to the source line. mid This may be entered.

[0060] The multiplier accumulator circuit connects the gate terminal of the field-effect transistor 310 to the reference voltage via a word line. VDD By applying the voltage, the field-effect transistor can be turned on. With the field-effect transistor 310 turned on, the multiplier / accumulator circuit applies the intermediate voltage V through the source line to the first terminal of the field-effect transistor 310. mid By applying this voltage, the voltage at the second terminal of the field-effect transistor 310 is changed to an intermediate voltage V. mid This can be changed. More specifically, a reference voltage V can be applied to the gate terminal of the field-effect transistor 310. DD When the intermediate voltage V is applied, the field-effect transistor 310 operates in the saturation region. When the field-effect transistor 310 operates in the saturation region, a low resistance path is provided between the first and second terminals within the field-effect transistor 310, which can act like a short circuit. As a result, the intermediate voltage V applied to the first terminal mid The voltage at the second terminal is changed, and the field-effect transistor 310 receives the intermediate voltage V at node 301 connected to the second terminal. mid It can be applied.

[0061] Then, by applying a weighting value setting voltage to the other end of the resistive element pair 321 and 322, the resistance values ​​of each resistive element pair 321 and 322 can be determined. More specifically, one end of the first resistive element 321 is connected to node 301 and the other end is connected to the first input terminal 351. The multiplier accumulator circuit applies a weighting value setting voltage to the first input terminal 351, and the weighting value setting voltage is applied to the other end of the first resistive element 321 from the first input terminal 351. Similarly, one end of the second resistive element 322 may be connected to node 301 and the other end to the second input terminal 352. The multiplier accumulator circuit applies a weighting value setting voltage to the second input terminal 352, and the weighting value setting voltage is applied to the other end of the second resistive element 322 from the second input terminal 352. For example, the magnitudes of the weight value setting voltage applied to the first input terminal 351 and the weight value setting voltage applied to the second input terminal 352 may be the same, or they may be different from each other.

[0062] In summary, the first resistive element 321 is connected to node 301 and has an intermediate voltage V applied to one end of it. mid The resistance value can be determined based on the first weight value setting voltage applied to the other end connected to the first input terminal 351. The second resistive element 322 is subjected to an intermediate voltage V applied to one end connected to node 301. mid The resistance value can be determined based on the second weight value setting voltage applied to the other end connected to the second input terminal 352.

[0063] Referring to Figure 3B, the multiplier accumulator circuit according to one embodiment can determine the resistance values ​​of each pair of resistive elements 321 and 322 by applying a voltage across each of the resistive element pairs 321 and 322, and record the weighted value based on the combined resistance values ​​of the resistive element pairs in the multiplier 300 which includes the resistive element pairs 321 and 322.

[0064] For example, the turn-on voltage V is the voltage applied to one end of a resistive element. onWhen a voltage higher than V is applied to the other end of the resistive element, the resistive element can enter a turn-on state and have a first resistance value. Also, the voltage applied to one end of the resistive element is the turn-off voltage V. off When a voltage lower than V is applied to the other end of the resistive element, the resistive element may enter a turn-off state and have a second resistance value. The first resistance value may be relatively lower than the second resistance value. According to one embodiment, the ratio of the first resistance value to the second resistance value may be greater than or equal to the threshold ratio. According to one embodiment, the first resistance value is smaller than the threshold resistance value, and the second resistance value is larger than the threshold resistance value. Turn-on voltage V on and turn-off voltage V off These may differ from each other depending on the type of resistive element.

[0065] As an example, let's assume the resistive element is an RRAM. The turn-on voltage V is the voltage applied to one end of the resistive element. on When a voltage significantly higher than V is applied to the other end, a conductive path is formed within the resistive element, causing the resistive element to enter a low resistance state (LRS), and the resistive element will have a relatively small resistance value. On the other hand, the voltage applied to one end of the resistive element is the turn-off voltage V. off When a voltage significantly lower is applied to the other end, a conductive path cannot be formed within the resistive element, causing the resistive element to enter a high-resistance state (HRS), resulting in a relatively high resistance value.

[0066] According to one embodiment, the multiplier-accumulator circuit can record a weighted value based on the combined resistance of a pair of resistive elements 321 and 322 in a multiplier 300 that includes the pair of resistive elements 321 and 322. According to one embodiment, the combined resistance of a pair of resistive elements corresponds to one of the ternary values ​​that represent the weighted values ​​of the connecting lines between layers included in the neural network, as described later with reference to Figure 9 below. If the resistive elements have one of the first and second resistance values, the multiplier-accumulator circuit can record a weighted value of one of the ternary values ​​"1", "0", or "-1" in the multiplier. However, the weighted values ​​that the multiplier can record are not necessarily limited to ternary values. As will be described later with reference to Figure 7, a resistive element can enter three or more states, and thereby may have three or more resistance values. In such cases, the multiplier-accumulator circuit can record various weighted values ​​based on the combined resistance values ​​in the multiplier.

[0067] According to one embodiment, the multiplier accumulator circuit may correspond to the case where the weighted value indicating "1" is determined to be the first resistance value and the second resistance value of the first resistive element 321 and the second resistive element 322, respectively. The multiplier accumulator circuit is entered with the first resistive element 321 in the turned-on state and the second resistive element 322 in the turned-off state, and the weighted value indicating "1" is recorded. More specifically, the multiplier accumulator circuit may also turn on the field-effect transistor 310, and an intermediate voltage V is supplied to node 301 via the source line. mid The multiplier accumulator circuit may also apply a weight value setting voltage to the first input terminal 351 connected to the other end of the first resistive element. Here, the weight value setting voltage applied to the first input terminal 351 is the intermediate voltage V mid So, the turn-on voltage V on Only a higher voltage (V on +V mid ) may also be the case. The multiplier accumulator circuit is connected to an intermediate voltage V applied to one end of the first resistive element 321. midBased on the first weighting value setting voltage applied to the other end of the first resistive element 321, the first resistive element 321 can be turned on, and the resistance value of the first resistive element can be determined as the first resistance value. Next, the multiplier accumulator circuit may apply a weighting value setting voltage to the second input terminal 352 connected to the other end of the second resistive element. Here, the weighting value setting voltage applied to the second input terminal 352 is the intermediate voltage V mid So, the turn-off voltage V off Only a lower voltage (V mid -V off ) may also be the case. The multiplier accumulator circuit is connected to an intermediate voltage V applied to one end of the second resistive element 322. mid Based on the weight value setting voltage applied to the other end of the second resistive element 322, the second resistive element 322 can be turned off, and the resistance value of the second resistive element can be determined as the second resistance value.

[0068] The multiplier accumulator circuit can correspond to the case where the weighted value indicating "0" is determined to be the second resistance value for both the first resistive element 321 and the second resistive element 322. Here, the multiplier accumulator circuit is the intermediate voltage V mid So, the turn-off voltage V off Only a lower voltage (V mid -V off ) is applied to the first input terminal 351 as the weighted value setting voltage, and the intermediate voltage V mid So, the turn-off voltage V off Only a lower voltage (V mid -V off ) may be applied to the second input terminal 352 as the weighted value setting voltage.

[0069] Furthermore, the multiplier accumulator circuit can correspond to the case where the weighting value indicating "-1" is determined to be the second resistance value and the first resistance value of the first resistive element 321 and the second resistive element 322, respectively. Here, the multiplier accumulator circuit uses the intermediate voltage V mid So, the turn-off voltage V off Only a lower voltage (V mid -V off ) is applied to the first input terminal 351 as the weighted value setting voltage, and the intermediate voltage V mid So, the turn-on voltage V onOnly a higher voltage (V on +V mid ) may be applied to the second input terminal 352 as the weighted value setting voltage.

[0070] In another embodiment, the multiplier accumulator circuit may correspond to the case where the weighting value indicating "0" is determined to be the first resistance value for both the first resistive element 321 and the second resistive element 322. Here, the multiplier accumulator circuit is the intermediate voltage V mid So, the turn-on voltage V on A voltage that is only slightly higher is applied to the first input terminal 351 and the second input terminal 352. In this case, the combination of resistance values ​​corresponding to the weight value indicating "1" and the weight value indicating "-1" is the same as in the example above.

[0071] According to one embodiment, the multiplier-accumulator circuit can simultaneously determine the resistance values ​​of each pair of resistive elements 321 and 322. For example, the multiplier-accumulator circuit turns on the transistor and applies an intermediate voltage V to node 301. mid The resistance values ​​of each pair of resistive elements 321 and 322 may be changed simultaneously by applying a weighted value setting voltage to the first input terminal 351 and the second input terminal 352 in a single step. In other words, the multiplier accumulator circuit can simultaneously determine the state of each pair of resistive elements. According to one different embodiment, the multiplier accumulator circuit may determine the state of each pair of resistive elements 321 and 322 by multiplying them by two cycles. For example, the multiplier accumulator circuit may first determine the resistance value of the first resistive element 321 by applying a weighted value setting voltage to the first input terminal 351, and then, after the resistance value of the first resistive element 321 has been determined, determine the resistance value of the second resistive element 322 by applying a weighted value setting voltage to the second input terminal 352.

[0072] Figure 4 illustrates the process by which a multiplier accumulator circuit according to one embodiment precharges the capacitor with a preset voltage before applying the input value to the multiplier.

[0073] In one embodiment, a multiplier-accumulator circuit can determine the resistance values ​​of each pair of resistive elements 421 and 422, record the weighted values ​​in the multiplier, and then apply input values ​​to the corresponding multipliers. The input values ​​applied to the multiplier-accumulator circuit may be determined based on input voltages individually applied to input terminals connected to the other ends of each pair of resistive elements 421 and 422. According to one embodiment, before applying input voltages to each pair of resistive elements 421 and 422, the multiplier-accumulator circuit can precharge the capacitor 430 to a preset voltage by applying a preset voltage to the output line 440 by applying a preset voltage to the input terminals 451 and 452 connected to the other ends of each pair of resistive elements 421 and 422.

[0074] The multiplier accumulator circuit can apply the input voltage to the other end of the resistive element pair 421, 422 via the input terminal, and precharge the voltage across capacitor 430 before applying the input value to the multiplier. The preset voltage is read out at voltage V read This is also acceptable, but not limited to this. Readout voltage V read This voltage, used to read the resistance values ​​of the resistive elements pair 421 and 422, has a magnitude that is relatively smaller than the weighted value setting voltage.

[0075] According to one embodiment, the multiplier-accumulator circuit can turn off the field-effect transistor 410 after determining the resistance values ​​of the resistive element pair 421, 422. For example, the multiplier-accumulator circuit interrupts the supply of a reference voltage to the word line connected to the gate terminal of the field-effect transistor 410. When the supply of the reference voltage to the word line is interrupted, no voltage is applied to the gate terminal of the field-effect transistor 410, and the field-effect transistor 410 is turned off. Next, the multiplier-accumulator circuit reads a voltage V to the first input terminal 451 connected to the other end of the first resistive element 421. read The read voltage V is applied to the second input terminal 452 connected to the other end of the second resistive element 422. read The multiplier accumulator circuit also applies the read voltage V to the output line 440 connected to capacitor 430.read It can be applied.

[0076] In one embodiment of the multiplier accumulator circuit, a read voltage V is connected to the first input terminal 451 and the second input terminal 452. read By applying the voltage V, the read voltage V is also applied to node 401 between the first input terminal 451 and the second input terminal 452. read A voltage can be applied. The voltage applied to the first input terminal 451 and the second input terminal 452 is distributed by the resistance values ​​of the resistive element pair 421, 422, thereby determining the magnitude of the voltage applied to node 401. In this case, the same read voltage V can be applied to both the first input terminal 451 and the second input terminal 452. read Because a voltage is applied, the read voltage V is not affected regardless of the resistance values ​​of the first resistive element 421 and the second resistive element 422. read The read voltage V can be applied to node 401. That is, one end of capacitor 430 connected to node 401 and the other end of capacitor 430 connected to output line 440 are both connected to the read voltage V read A charge can be applied. That is, the multiplier accumulator circuit can be configured so that the capacitor 430 is initialized to a state where it is not charging or discharging before the input value is applied to the multiplier 400.

[0077] Figure 5A is a diagram illustrating the process by which a multiplier accumulator circuit according to one embodiment applies an input value to the multiplier.

[0078] In one exemplary embodiment, the multiplier accumulator circuit may, after determining the resistance values ​​of each pair of resistive elements 521 and 522, individually apply input voltages to input terminals 551 and 552 connected to the other ends of each pair of resistive elements 521 and 522, and then apply the combined input voltages to the multiplier. In one embodiment, the combined input voltages correspond to one of the ternary values ​​representing the output values ​​of nodes included in the layers of the neural network described later, referring to Figure 9 below. The multiplier accumulator circuit can apply one of the ternary values ​​"1", "0", or "-1" as an input value to the multiplier 500 based on the input voltage applied to the first input terminal 551 and the input voltage applied to the second input terminal 552. However, the input values ​​that the multiplier accumulator circuit can apply are not necessarily limited to ternary values. As will be described later with reference to Figure 8, input voltages of various magnitudes may be applied to the first and second input terminals, and as a result, the multiplier accumulator circuit may have various input values ​​resulting from the combined input voltages applied to the multiplier 500.

[0079] Referring to Figure 5B, the multiplier accumulator circuit receives an input value of "1" and outputs 2 × V to the first input terminal 551 and the second input terminal 552, respectively. read This can handle the case where a ground voltage of 0 is applied. Furthermore, the multiplier accumulator circuit can handle the case where the input value indicating "0" is entirely V at the first input terminal 551 and the second input terminal 552. read This can handle the case where a voltage is applied. Furthermore, the multiplier accumulator circuit can handle the case where an input value indicating "-1" is applied to the first input terminal 551 and the second input terminal 552, respectively, with ground voltages of 0 and 2×V. read This can handle the case when the applied value is specified.

[0080] Referring again to Figure 5A, after the resistance values ​​of each pair of resistive elements 521 and 522 have been determined, when an input voltage is applied to input terminals 551 and 552, a voltage may be generated at node 501. The voltage generated at node 501 corresponds to the value calculated by multiplying the input value applied to the multiplier 500 by the recorded weight value. In other words, a multiplier accumulator circuit according to one embodiment can generate a voltage at node 501 that corresponds to the value calculated by multiplying the input value corresponding to the combination of input voltages individually applied to each pair of resistive elements 521 and 522 by the weight value corresponding to the combination of resistive elements 521 and 522.

[0081] More specifically, the voltages applied to the first input terminal 551 and the second input terminal 552, respectively, are distributed according to the determined resistance values ​​of the resistive element pair 521 and 522, thereby generating a voltage at node 501. Table 1 below shows the voltages generated at node 501 according to the weighted value recorded in the multiplier 500 and the applied input value. [Table 1] Referring to Table 1, the weighted value, which has a ternary value, is determined based on the resistance value determined according to the state of the first resistive element 521 and the second resistive element 522 (for example, turn-on state (ON) or turn-off state (OFF)). The input value, which has a ternary value, is determined based on the input voltage applied to the first input terminal 551 and the second input terminal 552.

[0082] The voltage generated at node 501 can be determined based on the input voltage applied to input terminals 551, 552 and the determined resistance values ​​of the resistive element pairs 521, 522.

[0083] For example, when the first resistive element 521 enters the turn-on state and the second resistive element 522 enters the turn-off state, the first resistance value of the first resistive element 521 is relatively smaller than the second resistance value of the second resistive element 522. Therefore, the first resistive element 521 behaves almost like a short circuit, and the voltage generated at node 501 is almost identical in magnitude to the input voltage applied to the first input terminal 551.

[0084] As a different example, when the first resistive element 521 enters the turn-off state and the second resistive element 522 enters the turn-on state, the second resistance value of the first resistive element 521 is relatively larger than the first resistance value of the second resistive element 522. As a result, the second resistive element 522 behaves almost like a short circuit, and the voltage generated at node 501 is almost identical in magnitude to the input voltage applied to the second input terminal 552.

[0085] Referring to Table 1, the voltage generated at node 501 of multiplier 500 corresponds to the value calculated by multiplying the weighted value (a ternary value) by the input value (a ternary value). For example, if the product of the weighted value and the input value is "1", the magnitude of the voltage generated at node 501 is 2 × V. read This is shown. Also, if the value obtained by multiplying the weighted value by the input is "0", the magnitude of the voltage generated at node 501 is V read This is shown. Finally, it is shown that if the product of the weighted value and the input is "-1", then almost no voltage is generated at node 501.

[0086] Figure 6 illustrates the structure of a multiplier accumulator circuit according to one embodiment.

[0087] A multiplier accumulator circuit 600 according to one embodiment includes a plurality of multipliers 611, 612, 613 and an output line 620. Each of the plurality of multipliers 611, 612, 613 may have a structure and operating method as described with reference to Figures 3A to 5B. The output line 620 is connected to each of the plurality of multipliers 611, 612, 613. The output line 620 can output a voltage to each of the plurality of multipliers 611, 612, 613 based on the charge being charged / discharged.

[0088] Output line 620 may be connected to one end of the capacitors included in each of the multiple multipliers 611, 612, and 613. Output line 620 may output a voltage based on the cumulative charge being charged / discharged to each of the capacitors included in the multiple multipliers 611, 612, and 613 via capacitive coupling. After the weighted values ​​for each of the multiple multipliers 611, 612, and 613 are recorded, switch 621 is turned on to read out voltage V read It can be precharged. After the output line 620 is precharged to the read voltage, and the switch 621 is turned off, each of the multiple multipliers 611, 612, and 613 can charge / discharge the capacitors with the voltage output corresponding to the product of the weighted value and the input value. Then, the charge charged / discharged to each of the capacitors included in the multiple multipliers 611, 612, and 613 accumulates in the output line 620, and it can output a voltage based on the accumulated charge.

[0089] For example, the capacitor included in multiplier 611 may receive the voltage generated at the node of multiplier 611 and charge / discharge itself, and the charge being charged / discharged may be shared with output line 620. Similarly, the capacitor included in multiplier 612 may receive the voltage generated at the node of multiplier 612 and charge / discharge itself, and the charge being charged / discharged may be shared with output line 620. In other words, output line 620 is able to output a voltage based on the accumulation of charge being charged or discharged to the capacitors of multipliers 611, 612, and 613 by capacitive coupling.

[0090] Furthermore, a multiplier accumulator circuit according to one embodiment may include multiple output lines. A structure with multiple output lines may also be referred to as a memory array. For example, each of the multiple output lines may be connected to multiple multipliers, and each output line may output a voltage based on the accumulation of charge charged / discharged to the multiple multipliers connected to that output line. The memory array can perform in-memory computing based on the voltages output from each of the multiple output lines included in the memory array.

[0091] A multiplier accumulator circuit according to one embodiment generates a voltage at a node by using a voltage distribution method based on the resistance values ​​of a pair of resistive elements, and the generated voltage can charge / discharge a capacitor. In a multiplier accumulator circuit according to one embodiment, since the voltage is generated at the node of the multiplier by voltage dividing, even if the on / off ratio of the resistive elements is small, as long as the on / off ratio is greater than or equal to the threshold ratio, the voltage generated at the node is almost the same as the voltage corresponding to the value obtained by multiplying the input value by a weighted value. Here, the on / off ratio of the resistive elements represents the ratio of the first resistance value, which is the resistance value when the resistive element is on, to the second resistance value, which is the resistance value when the resistive element is off. Furthermore, because a multiplier accumulator circuit according to one embodiment generates a voltage at the node using a voltage distribution method, it has the advantage of being relatively resistant to the problem of variable resistance values ​​of resistive elements. In other words, even if the resistance value of the resistive elements is changed to some extent, the voltage generated at the node is not greatly changed because it is determined by the ratio of the resistance values ​​of the first resistive element and the second resistive element. Furthermore, in one embodiment, the other multiplier accumulator circuit has the advantage of guaranteeing linearity between the final output voltage and the value calculated by MAC calculation, since it outputs a voltage based on the accumulation of charge charged / discharged to each capacitor by capacitive coupling.

[0092] Figure 7 illustrates the weight values ​​that can be recorded in the multiplier of a multiplier accumulator circuit according to one embodiment.

[0093] A multiplier-accumulator circuit according to one embodiment can record a weighted value in the multiplier based on the combined resistance values ​​of a pair of resistive elements. According to one embodiment, the resistive elements can enter an intermediate state different from the turn-on state and the turn-off state. When the resistive elements enter an intermediate state, the resistive elements have a third resistance value. The multiplier-accumulator circuit can use the third state entered by the resistive elements to record a multi-bit weighted value in the multiplier that is extended from the ternary weighted value.

[0094] For example, referring to FIG. 7, the resistive element can enter an intermediate state depending on the voltage applied across its two ends. The resistive element has a third resistance value in the intermediate state. For example, but not limited to, the third resistance value is greater than the first resistance value R on and less than the second resistance value R off . The third resistance value may be a value that is half of the second resistance value, 0.5R off , but is not limited thereto.

[0095] Referring to FIG. 7, the process by which the multiply-accumulator circuit records a weighted value indicating any one of the five values 3, 1, 0, -1, and -3 in the multiplier will be described. The multiply-accumulator circuit records, in the multiplier, a weighted value indicating one of the values "3", "1", "0", "-1", and "-3" according to the combined resistance value of a pair of resistive elements.

[0096] According to one embodiment, the multiply-accumulator circuit may correspond to the case where the weighted value indicating "3" is determined when the first resistive element 721 and the second resistive element 722 are respectively at the first resistance value R on and the second resistance value R off . The multiply-accumulator circuit may correspond to the case where the weighted value indicating "1" is determined when the first resistive element 721 and the second resistive element 722 are respectively at the third resistance value 0.5R off and the second resistance value R off . The multiply-accumulator circuit may correspond to the case where the weighted value indicating "0" is determined when both the first resistive element 721 and the second resistive element 722 are at the second resistance value R off . The multiply-accumulator circuit may correspond to the case where the weighted value indicating "-1" is determined when the first resistive element 721 and the second resistive element 722 are respectively at the second resistance value R off and the third resistance value 0.5R off . The multiply-accumulator circuit may correspond to the case where the weighted value indicating "-3" is determined when the first resistive element 721 and the second resistive element 722 are respectively at the second resistance value R off and the first resistance value R on .

[0097] The multiplier-accumulator circuit according to one embodiment records a weighted value indicating any one of five values 3, 1, 0, -1, and -3 in the multiplier according to the combined resistance value of a pair of resistive elements, and can apply an input value to the multiplier according to the combined input voltage. Further, the multiplier-accumulator circuit enables the capacitor included in the multiplier to receive a voltage corresponding to the value obtained by multiplying the weighted value by the input value and to charge / discharge electric charge.

[0098] FIG. 8 is a diagram for explaining input values that can be applied to the multiplier by the multiplier-accumulator circuit according to one embodiment.

[0099] The multiplier-accumulator circuit according to one embodiment applies an input value based on the combined input voltage to the multiplier. According to one embodiment, the multiplier-accumulator circuit can apply a voltage greater than 2×V read as the input voltage. When the multiplier-accumulator circuit applies a voltage greater than 2×V read as the input voltage, the number of bits of the input value can be increased. In FIG. 8, as a simple example, the case where the input voltage can be applied up to 4×V read will be described. When the input voltage is applied up to 4×V read , an input value indicating any one of five values (2, 1, 0, -1, -2) can be applied to the multiplier.

[0100] Referring to FIG. 8, the multiplier-accumulator circuit may correspond to a case where an input value indicating "2" has 4×V read applied to the first input terminal 851 and the second input terminal 852, respectively, and a ground voltage 0 is applied. Further, the multiplier-accumulator circuit may correspond to a case where an input value indicating "1" has 3×V read and V read applied to the first input terminal 851 and the second input terminal 852, respectively. The multiplier-accumulator circuit may correspond to a case where an input value indicating "0" has 2×V read applied to both the first input terminal 851 and the second input terminal 852. Further, the multiplier-accumulator circuit may correspond to a case where an input value indicating "-1" has V read and 3×V readThis can handle the case where a voltage is applied. Furthermore, the multiplier accumulator circuit can handle the case where an input value indicating "-2" is applied to the first input terminal 851 and the second input terminal 852, respectively, with ground voltages of 0 and 4 × V. read A multiplier-accumulator circuit according to one embodiment, which can handle the case where a voltage is applied, records a weighted value based on the combined resistance values ​​of a pair of resistive elements in the multiplier, and can apply an input value to the multiplier that represents one of five values ​​(2, 1, 0, -, 1, -2) based on the combined input voltage. The multiplier-accumulator circuit also allows the capacitor included in the multiplier to receive a voltage corresponding to the value obtained by multiplying the weighted value and the input value, and to charge / discharge the capacitor.

[0101] Figure 9 illustrates an example of a neural network operation implemented by a multiplier accumulator circuit according to one embodiment.

[0102] Neural network 900 is an example of a deep neural network (DNN). DNNs include fully connected networks, deep convolutional networks, and recurrent neural networks. Based on deep learning, neural network 900 may perform object classification, object recognition, speech recognition, and image recognition by mapping non-linearly related input and output data to each other. Deep learning is a machine learning method for solving problems such as image or speech recognition from big datasets, and it can map input and output data to each other through supervised or unsupervised learning.

[0103] Figure 9 shows the hidden layer as containing two layers for illustrative purposes, but the hidden layer may contain any number of layers. Also, in Figure 9, the neural network 900 is shown as containing a separate input layer 910 for receiving input data, but the input data may be directly input to the hidden layer. In the neural network 900, the artificial nodes of the layers, excluding the output layer, may be connected to the artificial nodes of the next layer via links for transmitting output signals. The number of links corresponds to the number of artificial nodes in the next layer.

[0104] Each artificial node in the hidden layer may receive a weighted input of the output of an artificial node previously included in that layer. This weighted input is obtained by multiplying the output of an artificial node previously included in that layer by a weight value. The weight value may be referred to as the parameter of the neural network 900. An activation function may be applied to the sum of these weighted inputs and output from the next layer. The activation function may include sigmoid, hyperbolic tangent (tanh), and ReLU (rectified linear unit). The activation function may introduce nonlinearity into the neural network 900. Each artificial node in the output layer may receive a weighted input, which is the output of an artificial node previously included in that layer.

[0105] The multiplier accumulator circuit described above can be applied to in-memory computing to drive deep learning algorithms, with reference to Figures 1 to 8. For example, the calculation of weighted inputs transmitted between nodes 921 of the neural network 900 can be composed of MAC operations, which involve repeated multiplication and addition. The output of any one node 921 of the neural network 900 is shown by equation (1) below.

number

[0106] The above formula (1) gives the output value y of the i-th node 921 for m weighted input values ​​in any layer. i It can be shown that x j This previously showed the j-th output value of the layer (e.g., node value), and w j、i This shows the j-th output value of the previous layer and the weighted value applied to the i-th node 921. j , i、 x j x represents the j-th weighted input among the m weighted input values ​​at the i-th node 921 of the layer, and f() represents the activation function. As shown in equation (1), for the activation function, the node value x j and weighted value w j、i The cumulative result of multiplication may be used. In other words, at the desired point in time, the appropriate node value x j and weighted value w j、i It is possible to repeatedly perform memory access operations that require loading data, and MAC operations that multiply and add them together.

[0107] According to one embodiment, in a multiplier-accumulator circuit, the combined resistance value of a pair of resistive elements corresponds to the weighted value of the connecting lines that connect the multiple nodes in a neural network 900 including a layer containing multiple nodes. According to one embodiment, the input voltage combined in the multiplier-accumulator circuit corresponds to the output value x of the node in a neural network 900 including a layer containing multiple nodes. j This corresponds to the above. Therefore, the multiplier-accumulator circuit can perform at least a portion of the operations required to implement the neural network 900. However, the application of the multiplier-accumulator circuit according to one embodiment is not limited to this, and it can also be used for other computational operations that require the rapid processing of multiple input data using analog circuit characteristics at low power.

[0108] The embodiments described above are embodied in hardware components, software components, or combinations of hardware and software components. For example, the devices and components described in this embodiment are embodied using one or more general-purpose or special-purpose computers, such as a processor, controller, ALU (arithmetic logic unit), digital signal processor, microcomputer, FPA (field programmable array), PLU (programmable logic unit), microprocessor, or different devices that execute and respond to instructions. The processing device executes an operating system (OS) and one or more software applications that run on the OS. The processing device also accesses, stores, manipulates, processes, and generates data in response to the execution of the software. For convenience of understanding, the processing device may sometimes be described as being used as one, but a person with ordinary skill in the art will understand that the processing device includes multiple processing elements and / or multiple types of processing elements. For example, the processing device includes multiple processors or one processor and one controller. Other processing configurations are also possible, such as a parallel processor.

[0109] Software includes computer programs, code, instructions, or a combination of one or more of these, which can configure or instruct a processing unit to operate as desired, either independently or in combination. Software and / or data can be permanently or temporarily embodied in any type of machine, component, physical device, virtual device, computer storage medium or device, or transmitted signal wave, in order to be interpreted by a processing unit or to provide instructions or data to a processing unit. Software can be distributed, stored in a distributed manner, or executed on a networked computer system. Software and data can be stored on a recording medium readable by one or more computers.

[0110] The method according to this embodiment is embodied in the form of program instructions that are implemented via various computer means and recorded on a computer-readable recording medium. The recording medium includes program instructions, data files, data structures, etc., individually or in combination. The recording medium and program instructions may be specifically designed and configured for the purposes of the present invention, or they may be known and usable by those skilled in the art who have technology in the field of computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical recording media such as CD-ROMs and DVDs, magneto-optical media such as floppy disks, and hardware devices specifically configured to store and execute program instructions, such as ROMs, RAMs, and flash memory. Examples of program instructions include not only machine code generated by a compiler, but also high-level language code executed by a computer using an interpreter or the like.

[0111] The hardware device described above may be configured to operate as one or more software modules to perform the operations shown in the present invention, and vice versa.

[0112] As described above, embodiments have been illustrated with limited drawings, but a person with ordinary skill in the art can apply various technical modifications and variations based on the above description. For example, the described techniques may be performed in a different order than described, and / or the components of the described systems, structures, devices, circuits, etc. may be combined or assembled in a different manner than described, or replaced or substituted by other components or equivalents, while still achieving satisfactory results. [Explanation of Symbols]

[0113] 100 multiplier 110 Field-effect transistors 121, 122 Pair of resistive elements 130 Capacitors 140 Output Line 140 900 Neural Networks 921 nodes

Claims

1. A multiply-accumulator (MAC) circuit, It is a multiplier, Intermediate voltage V at the node ｍｉｄ A field-effect transistor to which a voltage is applied, The intermediate voltage V applied to one end connected to the node ｍｉｄ and a pair of resistive elements having resistance values ​​determined based on the weighted value setting voltage applied to the other end, In response to the determination of the individual resistance values ​​of the pair of resistive elements, a capacitor receives a voltage generated at the node and charges / discharges based on the input voltage individually applied to the other end of each of the pair of resistive elements and the combined resistance value of the pair of resistive elements, A multiplier, including, The output line outputs a voltage based on the charge being charged / discharged to the plurality of multipliers, A circuit that includes this.

2. Each pair of resistive elements is one of the following: resistive random access memory (RRAM) and magnetic random access memory (MRAM). The circuit according to claim 1.

3. Each of the aforementioned pairs of resistive elements is a resistive element whose resistance value is variable. The circuit according to claim 1.

4. The aforementioned multiplier / accumulator circuit is, For each of the plurality of multipliers, the resistance value of each pair of resistive elements is determined by applying a voltage across each of the pairs of resistive elements. The weighted value based on the combined resistance values ​​of the pair of resistive elements is recorded in the corresponding multiplier. The circuit according to claim 1.

5. The combined resistance of the pair of resistive elements corresponds to one of the ternary values ​​representing the weighted value of the connecting lines between layers included in the neural network. The circuit according to claim 1.

6. The multiplier accumulator circuit, before applying the input voltage to each of the pairs of resistive elements, A preset voltage is applied to the input terminals connected to the other end of each pair of resistive elements. By applying the preset voltage to the output line, the ends of the capacitor are pre-charged to the preset voltage. The circuit according to claim 1.

7. The multiplier accumulator circuit responds when the resistance values ​​of each pair of resistive elements are determined, The input voltage is individually applied to the input terminals connected to the other end of each pair of resistive elements. The input value resulting from the combined input voltages is applied to the multiplier. The circuit according to claim 1.

8. The combined input voltages correspond to one of the ternary values ​​representing the output values ​​of the nodes included in the layers of the neural network. The circuit according to claim 7.

9. The aforementioned multiplier / accumulator circuit is, The voltage corresponding to the value calculated by multiplying the input value corresponding to the combination of input voltages individually applied to each pair of resistive elements by a weighting value corresponding to the combination of resistance values ​​of the pair of resistive elements, To be generated at the aforementioned node, The circuit according to claim 1.

10. The aforementioned output line is, Each of the capacitors included in each of the aforementioned multiple multipliers is connected to the following: The multiplier outputs a voltage based on the cumulative charge charged / discharged to each of its capacitors via capacitive coupling. The circuit according to claim 1.

11. A computing method performed by a multiplier accumulator circuit, An intermediate voltage V is applied to one end of each pair of resistive elements connected to the node. ｍｉｄ and an operation to determine the resistance value of each pair of resistive elements based on the weight value setting voltage applied to the other end of each pair of resistive elements, In response to the determination of the individual resistance values ​​of the pair of resistive elements, the operation of charging / discharging charges is performed based on the voltage generated at the node, which is determined by the input voltage individually applied to the other end of each of the pair of resistive elements and the combined resistance value of the pair of resistive elements. The operation of outputting a voltage based on the charge being charged / discharged, Methods that include...

12. Each pair of resistive elements is one of either a resistive random access memory (RRAM) or a magnetic random access memory (MRAM). The method according to claim 11.

13. The operation of determining the resistance value of each pair of the resistive elements is as follows: The operation involves applying a voltage across each end of the pair of resistive elements to determine the resistance value of each pair of resistive elements, The operation of recording the weighted value based on the combined resistance values ​​of the pair of resistive elements in a multiplier that includes the pair of resistive elements, The method according to claim 11, including the method described in claim 11.

14. The combined resistance of the pair of resistive elements corresponds to one of the ternary values ​​representing the weighted value of the connecting lines between layers included in the neural network. The method according to claim 11.

15. The operation of charging / discharging the aforementioned charge is performed before applying the input voltage to each of the pairs of resistive elements. A preset voltage is applied to the input terminals connected to the other end of each pair of resistive elements. By applying the preset voltage to the output line, the terminals of the capacitor that charges / discharges are pre-charged to the preset voltage. The method according to claim 11, including the operation.

16. The charging / discharging operation is performed in response to the determination of the resistance values ​​of each pair of resistive elements. The input voltage is individually applied to the input terminals connected to the other end of each pair of resistive elements. The input value resulting from the combined input voltages is applied to the multiplier. The method according to claim 11, including the operation.

17. The combined input voltages correspond to one of the ternary values ​​representing the output values ​​of the nodes included in the layers of the neural network. The method according to claim 16.

18. The operation of charging / discharging the aforementioned charge is, The voltage corresponding to the value calculated by multiplying the input value corresponding to the combination of input voltages individually applied to each pair of resistive elements by a weighting value corresponding to the combination of resistance values ​​of the pair of resistive elements, To be generated at the aforementioned node, The method according to claim 11, including the operation.

19. A computer program that includes multiple instructions, When the computer's processor executes the instruction, The processor is made to carry out the method according to any one of claims 11 to 18. Computer program.

20. A multiplier that constitutes a multiplier accumulator circuit, Intermediate voltage V at the node ｍｉｄ A field-effect transistor to which a voltage is applied, The intermediate voltage V applied to one end connected to the node ｍｉｄ and a pair of resistive elements having resistance values ​​determined based on the weighted value setting voltage applied to the other end, In response to the determination of the individual resistance values ​​of the pair of resistive elements, a capacitor receives a voltage generated at the node and charges / discharges based on the input voltage individually applied to the other end of each of the pair of resistive elements and the combined resistance value of the pair of resistive elements, A multiplier that includes a multiplier.

21. The multiplier is, The voltage corresponding to the value calculated by multiplying the input value corresponding to the combination of input voltages individually applied to each pair of resistive elements by a weighting value corresponding to the combination of resistance values ​​of the pair of resistive elements, To be generated at the aforementioned node, The multiplier according to claim 20.

22. A method performed by a multiplier accumulator (MAC) circuit, An intermediate voltage V is applied to the node corresponding to one end of each of the first and second resistive elements of a multiplier. ｍｉｄ The operation involves applying a voltage, applying a first weighting value setting voltage to the other end of the first resistive element, and applying a second weighting value setting voltage to the other end of the second resistive element, thereby recording the weighting value for one multiplier. The operation involves applying a first input voltage to the other end of the first resistive element and a second input voltage to the other end of the second resistive element, thereby applying an input value to one of the multipliers. The operation involves discharging a capacitor in response to the application of the aforementioned input value to generate the output value of the neural network node, Methods that include...

23. The operation of recording the aforementioned weighted value is: In response to the first weight value setting voltage being greater than the second weight value setting voltage, the operation of recording the first weight value, In response to the first weighting value setting voltage being the same value as the second weighting value setting voltage, the operation of recording the second weighting value, In response to the first weighting value setting voltage being smaller than the second weighting value setting voltage, the operation records a third weighting value, The method according to claim 22, including the method described in claim 22.

24. The operation of applying the aforementioned input value is: An operation to apply a first input value in response to the first input voltage being greater than the second input voltage, The operation of applying the second input value in response to the first input voltage being the same value as the second input voltage, An operation to apply a third input value in response to the first input voltage being smaller than the second input voltage, The method according to claim 22, which includes the method described in claim 22.

25. The operation further includes applying a predetermined voltage to the output line connected to the other end of the first resistive element, the other end of the second resistive element, and one end of the capacitor, in response to the recording of the weighted value. The operation of applying the input value includes the operation of applying the input value in response to the application of the predetermined voltage. The method according to claim 22.

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