Implementation method of dynamic precision approximate multiplication based on partial product decoupling and multiplier

Abstract

The invention provides a partial product decoupling-based dynamic precision approximate multiplication implementation method and a multiplier, and the multiplier comprises a significance evaluation unit which splits a first operand and a second operand into high digits and low digits, and correspondingly generates a first amplitude and a second amplitude; different precision instructions are generated based on the amplitudes and the threshold values; the dynamic precision unit performs zero setting processing on the second low digit based on the precision instruction to form an approximate number, and calculates a partial product of the first high digit and the approximate number; the accurate calculation unit accurately calculates products of the other three parts; and the final addition unit sums the products of the four parts according to the weight. The calculation unit can be used for constructing or optimizing a multiplication calculation array in a neural network hardware accelerator, is particularly suitable for scenes with dense fixed-point number operation such as convolution, and performs efficient approximate operation on the input fixed-point number through a data driving mechanism by utilizing the common sparsity and amplitude difference characteristics of neural network data, so that the calculation efficiency is improved. And self-adaptive management of power consumption is realized.

Description

Technical Field

[0001] This application relates to the field of digital integrated circuits and artificial intelligence hardware accelerators, and in particular to an implementation method and multiplier for dynamic precision approximation multiplication based on partial product decoupling. Background Technology

[0002] With the widespread application of artificial intelligence, especially deep learning technology, in fields such as image recognition and autonomous driving, CNN has become a core algorithm model, and its computation process relies on massive multiply-accumulate (MAC) operations. These intensive arithmetic operations constitute the main source of power consumption and computational load in hardware accelerators.

[0003] However, traditional multiplier architectures typically employ a fixed-bit-width, full-precision computation mode. This "data-independent" approach is significantly incompatible with the inherent characteristics of CNNs. In actual computation, activation data and weights between network layers generally exhibit highly non-uniform distribution and sparsity (e.g., ReLU activation generates a large number of zero values). Faced with these data characteristics, traditional designs still perform complete logic flips and signal transmissions on all inputs, resulting in a large amount of invalid dynamic power consumption and significantly reducing the system's energy efficiency.

[0004] An approximate multiplier is a hardware multiplier circuit designed to sacrifice some computational accuracy in exchange for faster speed, smaller chip area, or lower power consumption. While some approximate computation schemes exist in the industry to attempt to reduce overhead, most existing approximate multipliers simply employ static truncation or logic simplification strategies. These schemes often struggle to find a dynamic balance between computational accuracy and power optimization: the lack of differentiated processing mechanisms for data amplitude and bit importance easily leads to uncontrollable computational errors on critical data, thus affecting algorithm accuracy; simultaneously, for widely existing sparse data (such as zero values), such designs typically lack effective skipping or low-power processing mechanisms, resulting in unnecessary logic flips when processing large amounts of zero input. This static, rigid approximation strategy fails to translate the dynamic characteristics of data into substantial energy efficiency gains, and is particularly unsuitable for power-sensitive edge computing scenarios.

[0005] Therefore, the industry urgently needs a computing architecture that can proactively perceive data characteristics. This architecture needs to be capable of processing sparse data and dynamic precision, thereby significantly reducing dynamic power consumption by adaptively eliminating invalid computations while ensuring algorithm accuracy.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0007] The purpose of this invention is to address the problems of high dynamic power consumption, low resource utilization, and insufficient energy efficiency caused by neglecting data distribution characteristics in existing FPGA-based logic resource (LUT) multipliers when processing deep neural network algorithms. This invention aims to provide a method and multiplier for implementing dynamic precision approximate multiplication based on partial product decoupling. Through resource reuse and dynamic power consumption management, it significantly reduces the implementation cost of soft-core multipliers while ensuring accuracy, providing a high-efficiency, configurable computing power expansion solution.

[0008] To address the aforementioned problems, firstly, a dynamic precision approximation multiplier based on partial product decoupling is provided, comprising: The saliency evaluation unit is used to obtain the first and second operands, which are 8 bits in total, and to split them into the first high bit and the first low bit, as well as the second high bit and the second low bit; to take the absolute value of the first operand and the second operand to generate the first amplitude and the second amplitude; and to generate different precision instructions based on the first amplitude and the second amplitude and a preset threshold. A precise calculation unit is used to precisely calculate the partial product of the first high-order digit and the second high-order digit, the partial product of the first low-order digit and the second high-order digit, and the partial product of the first low-order digit and the second low-order digit, respectively. The dynamic precision unit performs zeroing on the second low-order bits by different numbers of bits based on the precision instruction to form approximate numbers with different precisions; and calculates the partial product of the first high-order bits and the approximate number. The final addition unit is used to sum the three partial products of the precise calculation unit and the one partial product of the dynamic precision unit with predetermined arithmetic weights.

[0009] This solution provides a configurable core computing unit that can be used to build or optimize multiplication arrays in neural network hardware accelerators, especially suitable for scenarios with intensive fixed-point number operations such as convolution. This solution leverages the sparsity and amplitude variation characteristics commonly found in neural network data to perform efficient approximation operations on the input fixed-point numbers through a data-driven mechanism, while achieving adaptive power consumption management.

[0010] The first operand includes first operand a and first operand b, and the second operand includes second operand c. Power consumption can be further reduced through channel resource reuse.

[0011] The saliency evaluation unit includes an absolute value processing module, a first detection module, a second detection module, a third detection module, a fourth detection module, and a priority decision module. The absolute value processing module is used to take the absolute values ​​of the first operand a, the first operand b, and the second operand c, correspondingly generating a first amplitude |a|, a first amplitude |b|, and a second amplitude |c|. The first detection module is used to receive and detect |a| and |b|, and when |a| < 16 and |b| < 16, it generates a valid signal corresponding to the fourth precision instruction. The second detection module is used to receive and detect |a|, |b|, and |c|, and when |a| ≥ 16 or |b| ≥ 16... When |c| < 16, a valid signal corresponding to the first precision instruction is generated. The third detection module receives and detects |a| and |b|. When |a| ≥ 64 or |b| ≥ 64, a valid signal corresponding to the first precision instruction is generated. The fourth detection module receives and detects |a|, |b|, and |c|. When 32 ≤ |a| < 64, 32 ≤ |a| < 64, or |c| ≥ 64, a valid signal corresponding to the second precision instruction is generated. The priority decision module generates the corresponding precision instruction based on the valid signals according to the order from the first detection module to the fourth detection module. When no valid signal is received, a third precision instruction is generated. This scheme introduces a Significance Assessment Logic (SAL), which can execute a hierarchical judgment process and dynamically generate precision control instructions based on the characteristics of the input data, guiding the multiplier to seamlessly switch between full precision, multi-level approximation, and zero compensation modes.

[0012] The dynamic precision unit includes a dynamic mask generation module, a shared partial product generation module, and a dual-channel accumulation module. The dynamic mask generation module generates a first mask 1111 based on the first precision instruction, a second mask 1100 based on the second precision instruction, a third mask 1000 based on the third precision instruction, and a fourth mask 0000 based on the fourth precision instruction. It then performs a bitwise AND operation between the generated masks and the second low-order bits to form the approximate number. The shared partial product generation module receives the approximate number and the first high-order bit corresponding to the first operand a. and the first high-order bit corresponding to the first operand b Parallel generation of the first high-order bits The bit-level partial product row of the approximate number and the first high-order bit The bit-level partial product row of the approximate number is generated; the dual-channel accumulation module is used to shift and accumulate the generated bit-level partial product row to obtain the corresponding partial product. This scheme designs a reconfigurable dynamic precision unit, the core of which lies in the dual-channel sharing and operand isolation mechanism of the control logic. When a low-precision mode is determined, logic masking technology can be used to physically shield the input signal inversion of unnecessary paths. This "on-demand computation" mechanism ensures that the shielded logic gates (such as the partial product generation circuit) enter a silent state, thereby eliminating invalid dynamic power consumption.

[0013] The precise calculation unit includes a combinational logic multiplier. This solution directly utilizes gate-level logic networks to construct precise computational pathways. In modern integrated circuit technology, implementing such small-width multiplication logic requires minimal hardware resources and provides maximum optimization space for EDA tools. It is a cost-effective design that completely eliminates key error sources with minimal hardware overhead.

[0014] The final addition unit includes a first channel and a second channel. The first channel is used to sum the three partial products generated by the first operand 'a' and the second operand 'c' in the precise calculation unit and the one partial product generated in the dynamic precision unit, with predetermined arithmetic weights. The second channel is used to sum the three partial products generated by the first operand 'b' and the second operand 'c' in the precise calculation unit and the one partial product generated in the dynamic precision unit, with predetermined arithmetic weights. The final weighted aggregation adopts an adder tree structure including shifters, which can reconstruct the calculation results of each decoupled part without loss according to the corresponding mathematical weights, ensuring that the dynamic compensation term is correctly integrated into the final output.

[0015] Secondly, this application also provides a method for implementing dynamic precision approximate multiplication based on partial product decoupling, comprising the following steps: Get the 8-bit first operand and second operand, and split them into the first high-bit and first low-bit, and the second high-bit and second low-bit, respectively. Based on the first high digit, the first low digit, the second high digit, and the second low digit, four partial products are generated. Among the four partial products, the partial product of the first high digit and the second low digit is calculated by dynamic precision approximation multiplication, the partial product of the other three partial products is calculated by precise multiplication, and the four partial products are summed. The dynamic precision approximate multiplication calculation includes: Take the absolute values ​​of the first operand and the second operand to generate the first amplitude and the second amplitude respectively; Based on the first amplitude, the second amplitude, and a preset threshold, the second low-digit number is zeroed by different numbers of bits to form approximate numbers with different precision. Calculate the partial product of the first high-order digit and the approximate number.

[0016] This solution is particularly suitable for scenarios with intensive fixed-point number operations, such as convolution. It can take advantage of the sparsity and amplitude differences that are common in neural network data to perform efficient approximation operations on the input fixed-point numbers.

[0017] The first operand includes first operand a and first operand b, and the second operand includes second operand c; a four-term partial product corresponding to the first operand a and the second operand c, and a four-term partial product corresponding to the first operand b and the second operand c are generated respectively; when performing the dynamic precision approximate multiplication calculation, the first operand a and the first operand b share the same approximate number.

[0018] Based on the first amplitude, the second amplitude, and a preset threshold, the process of setting different numbers of bits to zero in the second low-order bits to form approximate numbers with different precisions includes the following steps in sequence: when the first amplitude is <16, all four bits of the second low-order bits are set to zero to obtain the approximate number. When there is a first amplitude value ≥ 16 and a second amplitude value < 16, the second lowest bit is not set to zero to obtain the approximate number; when there is a first amplitude value ≥ 64, the second lowest bit is not set to zero to obtain the approximate number; when there is 32 ≤ the first amplitude value < 64 or the second amplitude value ≥ 64, the lowest two bits of the second lowest bit are set to zero to obtain the approximate number; when the first amplitude value < 32 and the second amplitude value < 64, the lowest three bits of the second lowest bit are set to zero to obtain the approximate number.

[0019] The dynamic precision approximate multiplication calculation includes: taking the absolute values ​​of the first operand a, the first operand b, and the second operand c to generate a first amplitude |a|, a first amplitude |b|, and a second amplitude |c|; based on |a|, |b|, and |c|, and a preset threshold, setting different numbers of bits to zero in the second lower-order bits to form approximate numbers with different precisions, including the following steps in sequence: when |a| < 16 and |b| < 16, setting all four bits of the second lower-order bits to zero to obtain the approximate number. Approximate number; when |a|≥16 or |b|≥16 and |c|<16, the second least significant bit is not set to zero to obtain the approximate number; when |a|≥64 or |b|≥64, the second least significant bit is not set to zero to obtain the approximate number; when 32≤|a|<64 or 32≤|a|<64 or |c|≥64, the lowest two bits of the second least significant bit are set to zero to obtain the approximate number; when |a|<32 and |b|<32 and |c|<64, the lowest three bits of the second least significant bit are set to zero to obtain the approximate number.

[0020] Compared with existing technologies, the beneficial effects of this invention mainly include the following: 1) Significantly better energy efficiency than traditional soft cores: By introducing data-driven significance evaluation, the problem of power consumption of traditional soft logic multipliers being insensitive to data is solved. When processing sparse neural network data, the operand isolation mechanism significantly reduces invalid logic flips, transforming the sparsity and dynamic amplitude changes of data into actual power consumption reduction; 2) Maximization of resource utilization: Through the dual-channel dynamic precision sharing design, the high reuse of control logic between the two computing channels is achieved. This design greatly reduces the area overhead required for soft logic implementation, allowing users to deploy more computing cores within the same chip area, thereby improving the overall computing density; 3) High-precision approximate computing capability: Unlike simple static truncation, this invention, through partial product decoupling and dynamic compensation for the partial product of cross terms, significantly reduces power consumption while maintaining the computational accuracy crucial for neural network inference, achieving a dynamic balance between accuracy and power consumption; 4) Excellent module versatility and system integration: This design has good timing configurability and standard interfaces, allowing designers to flexibly adjust the pipeline stage number according to the timing constraints of the target system. This makes it a universal computing power supplement unit that can be seamlessly adapted to different accelerator architectures. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a high-level internal architecture diagram of the dynamic precision approximation multiplier provided in this application.

[0023] Figure 2 A block diagram of the hardware implementation of the saliency evaluation unit provided in this application.

[0024] Figure 3 The schematic diagram of the bit-level critical path circuit of the saliency evaluation unit provided in this application.

[0025] Figure 4 This is the overall architecture and data flow diagram of the dynamic precision unit provided in this application.

[0026] Figure 5 This is the final internal architecture diagram of the addition unit provided in this application.

[0027] Figure 6 This is a schematic diagram of the 5-stage pipeline structure of the dynamic precision approximation multiplier provided in this application. Detailed Implementation

[0028] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention.

[0029] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0030] The steps in the following embodiments do not correspond one-to-one with the contents of the invention.

[0031] This invention provides a dynamic precision approximation multiplier based on partial product decoupling and its implementation method. Through data saliency evaluation and dynamic precision sharing mechanisms, it deeply optimizes data streams with sparsity and varying numerical amplitude characteristics commonly found in applications such as artificial intelligence and digital signal processing. This multiplier and its implementation method aim to solve the problems of ineffective dynamic power consumption and redundant computational resources in traditional multipliers when processing such data.

[0032] In CNNs, the main computation comes from convolution operations in a large number of convolutional layers, which require a large number of multiplication operations. Taking a typical convolution operation as an example, there are at least two types of numbers: feature values ​​(the value of each pixel in the feature map) and weight values ​​(the weight values ​​of the convolution kernel). Both types of numbers are usually 8-bit signed operands, that is, each operand is 8 bits, of which the highest bit (the 7th bit) is the sign bit, and the rest (bits 6 to 0) are the numerical bits.

[0033] In this application, the input operands include two types: first operands and second operands. The first operands include first operand a and first operand b, and the second operand is second operand c. a, b, and c are all 8-bit signed numbers with a value range of [-128, 127]. It can be understood that the first operand corresponds to the aforementioned weight values, and the second operand corresponds to the aforementioned feature values. Typically, in convolution calculations, the same feature value needs to be multiplied by multiple weight values ​​before being summed, meaning there is a need for multiple first operands to share the same second operand in a multiplication operation.

[0034] In the prior art, in order to decouple the multiplication operation, any 8-bit operand X is first split into a corresponding high-order bit and a low-order bit, which can be decomposed according to the following formula (1): Where: X h The high-order bits of X are defined as the high 4 bits of X (i.e., X[7:4]), and are considered as a 4-bit signed number with a value range of [-8, 7]. l The lower bits of X are defined as the lower 4 bits of X (i.e., X[3:0]) and are treated as a 4-bit unsigned number with a value range of [0,15].

[0035] Based on the above splitting process, in this application, the first operand and the second operand can also be split, that is: Each first operand is split into its first high-order bit and first low-order bit; in this embodiment, the first high-order bit corresponding to the first operand a is denoted as . The corresponding first least significant digit is denoted as The first high-order bit corresponding to the first operand b is denoted as The corresponding first least significant digit is denoted as ; The second operand c is split into two parts, resulting in the second high-order bit and the second low-order bit. In this embodiment, the second high-order bit corresponding to the second operand c is denoted as... The corresponding second least significant digit is denoted as .

[0036] Understandably, let's take the multiplication of the first operand 'a' and the second operand 'c' as an example: In the prior art, a standard 8x8 bit precise multiplication... It can be expanded into the sum of four partial products (i.e., the partial products between different high-order / low-order digits), as shown in formula (2): In existing approximate multiplication methods, only the high-order partial products are typically multiplied precisely, while the remaining three partial products are approximated, and some partial products are even statically truncated. While this process can reduce a significant amount of computation, it results in excessive loss of computational accuracy, making it difficult to achieve a dynamic balance between computational accuracy and power consumption optimization.

[0037] Unlike existing approximation approaches, the core technical idea of ​​this invention lies in implementing an asymmetric, differentiated computational strategy for the four decomposed partial products, rather than using a uniform computational method. This strategy is based on the analysis of the weights and controllability of different partial products in the final error contribution, matching the optimal hardware implementation method to each partial product, thereby achieving an optimal balance between hardware efficiency and computational accuracy.

[0038] First, the product of the highest-order digits (i.e., the product of the two highest-order digits) is calculated. The product of the lowest weighted part (i.e., the product of the two lowest weighted parts). All solutions in this invention employ precise calculations.

[0039] Among them, the product of the higher-order parts has the largest weight (i.e., Therefore, for The use of precise calculations is to ensure the accuracy of the main components of the result, which is consistent with existing approaches. However, in existing approaches, the lowest-weighted partial product (i.e., l) is usually approximated or even truncated. In this scheme, however, the lowest-weighted partial product is calculated precisely. The use of precise calculations is to avoid a fixed, uncontrollable truncation error. This is because the present application also employs a risk assessment system based on high-order digits for detection and management (this will be explained in detail later). The magnitude of the error generated by the low-order partial product is determined only by the low-order digits, which cannot be processed by the risk assessment system of this invention and may compromise the reliability of the final result. Therefore, to achieve high control over calculation accuracy, precise calculations are used for the low-order partial product in this application. Of course, in other embodiments, the possibility of approximate calculations of the low-order partial product is not excluded.

[0040] Secondly, for the remaining two intersecting product (i.e., the product of the high-order and low-order digits), this invention employs different processing methods based on a trade-off between dynamic accuracy requirements and hardware costs, namely... To perform precise calculations, and for An approximate calculation is performed. This choice is made partly because of the high number of digits. The numerical weight is much higher than (The higher-order digits of c represent larger numbers, so their influence is greater.) Approximations introduce huge initial errors, while... The initial error resulting from the approximation is relatively small; more importantly, considering the high-digit risk assessment system used in this application, the cross-part product... The error amplification effect can be caused by the high-digit number The decision is therefore made, and can be incorporated into the risk assessment system and pass the assessment. The magnitude of the error is used to predict and control the final error; and The approximation error is then determined by the lower digits. The decision is difficult to monitor effectively by the risk assessment system of this invention.

[0041] In summary, the solution in this application only applies to the product of the intersection portion. Approximate multiplication is performed, while the partial products of the other three terms are calculated with full precision. Similarly, the same logic is used for the approximate multiplication of the first operand b and the second operand c, which will not be repeated here.

[0042] To further improve efficiency, when performing product on the intersection parts... as well as In approximate multiplication calculations, considering that the first operands a and b share the same second operand c, it is possible to perform multiplication only on the lower bits corresponding to the second operand c. By setting different precision levels (the rules for setting these precision levels are detailed below), the corresponding approximate numbers can be obtained. This allows the two first operands, a and b, to share the same approximate number. This further simplifies the multiplier structure and reduces power consumption. Thus, by sharing the same approximation number... Then, the final formula for calculating the approximate product between the first operands a and b and the second operand c is shown in formula (3): To assess computational accuracy, precisely quantify, and isolate the approximation error introduced by this invention, the formula (2) corresponding to the exact multiplication is subtracted from the formula (3) corresponding to the approximation multiplication of this application. This yields the approximation error of the approximation product of the first operand a and the second operand c. As shown in formula (4): As shown in Equation (4), through the above partial product decoupling and selective approximation strategy, the total approximation error of the approximate product of the first operand a and the second operand c is strictly limited to within... Similarly, the total approximation error of the approximate product of the first operand b and the second operand c. for .

[0043] When evaluating computational accuracy, in addition to the absolute error mentioned above, relative error is also considered. It is another key indicator for measuring the validity of results, especially in computational scenarios where the preservation of significant figures is required. Relative error is defined as the product of absolute error and the true value. The ratio is shown in formula (5): As can be seen from formulas (4) and (5), the absolute error is mainly determined by the error amplification factor. (or The relative error is determined by the ( ) and is simultaneously affected by the ( ) (or ) and overall computational scale (i.e. or The combined effect of the magnitude of the product of the two factors.

[0044] The absolute and relative errors shown above clearly demonstrate the effectiveness of this invention: it makes the magnitude of the error analyzable and predictable, and enables high-digit risk assessment systems to monitor the error amplification factor. / The magnitude is used to dynamically adjust The corresponding approximation This provides a basis for feasibility. Thus, the present invention can use significance assessment to precisely suppress at the microscopic level by monitoring two variables (i.e., the high-order digits of the first operand and the approximate number of the second operand). (or The absolute error introduced by the system is mitigated, while the numerical stability of the system is ensured at the macroscopic level by identifying a large numerical multiplier c. This dual-protection mechanism forms the theoretical foundation for the data-driven, adaptive trade-off between accuracy and power consumption in this invention.

[0045] Example 1 Based on the above theory, this embodiment first provides an implementation method for dynamic precision approximation multiplication based on partial product decoupling: First, obtain the 8-bit first operand and second operand, and then split them into the first high-bit and first low-bit, and the second high-bit and second low-bit, respectively. In this embodiment, the first operand includes first operand a and first operand b, and the second operand includes second operand c; in other embodiments, the first operand can be a single operand, namely first operand a.

[0046] Here, we take the calculation of the first operand 'a' and the second operand 'c' as an example. Based on the first high-order digit, the first low-order digit, the second high-order digit, and the second low-order digit, four partial products can be generated. For details, please refer to formula (2). In the four partial products, the partial product of the first high-order digit and the second low-order digit is calculated by dynamic precision approximation multiplication, and the partial products of the other three terms are calculated by precise multiplication. Finally, the four partial products are summed. Similarly, the calculation of the first operand 'b' and the second operand 'c' is also performed in the same manner.

[0047] In performing dynamic precision approximate multiplication, the absolute values ​​of the first and second operands are first taken to generate the first and second amplitudes respectively. Then, based on the first and second amplitudes and a preset threshold, different numbers of bits in the second lower-order digits are set to zero to form approximate numbers with different precisions. The partial product of the first higher-order digits and the approximate number is calculated, thus realizing dynamic precision approximate multiplication. It can be understood that in this embodiment, the first operand a and the first operand b share the same approximate number during dynamic precision approximate multiplication.

[0048] Specifically, in order to achieve low-digit... By setting different precision levels (i.e., generating approximate numbers with different precision), a risk assessment method based on high digits was adopted. Its basic principle is: by... , as well as Real-time features are analyzed prospectively, and based on their relationship with preset thresholds, low-digit features are processed. Approximations of different precision .

[0049] In this embodiment, four different calculation accuracies are preset: First calculation precision, without processing low-digit numbers. ,Right now = ; The second calculation precision involves reducing the number of lower digits. Set the lowest two bits to zero; The third calculation precision will reduce the number of low-digit numbers. Set the lowest three bits to zero; Fourthly, in terms of calculation precision, the lower digits... All four bits are set to zero, that is... It is 0000.

[0050] It is understandable that the above four calculation accuracies are based on the error amplification factor. , as well as The decision is made based on real-time characteristics. In this embodiment, the specific logic is as follows: First, absolute value preprocessing is performed on the input operands a, b, and c to generate corresponding unsigned magnitude feature vectors, denoted as |a|, |b|, and |c|, respectively. Absolute value preprocessing yields the absolute values ​​of operands a, b, and c. A feasible example is as follows: when the input signed operand is positive, it remains unchanged; when the input signed operand is negative, its sign bit remains unchanged, the value bits are inverted and incremented by one, but the carry is discarded, thus maintaining the same bit width.

[0051] Then, based on the relationship between the amplitude and the preset threshold, the corresponding precision can be judged and selected in sequence.

[0052] The first step is to find and The case where the value is 0; in this case, according to the error formula (4), the approximate error is... Since it is always zero, the fourth precision can be used accordingly. Setting all bits to zero can maximize power saving without theoretical loss. Specifically, this can be determined by whether the first amplitude is in a very small range. That is, when the conditions |a|<16 and |b|<16 are met (i.e., the high 4 bits of the amplitude vector are all logic 0), it indicates that there are no valid values ​​in the high bits of the input data. In this way, the four bits of the second low bit can be set to zero to obtain an approximate number. The second step is to detect a special precision-sensitive scenario: when the base of the calculation result is small (|c|<16), but at least one of the error amplification factors has a high-order significant value (i.e., |a|≥16 or |b|≥16), it can be seen from formula (3) that... or This becomes the sole source of compensation to ensure the accuracy of the final result. In this highly dependent scenario, to avoid irreparable loss of accuracy, a control instruction corresponding to the first calculation accuracy is generated, that is, the second low-order bit is not set to zero to obtain an approximate number; This step primarily aims to prevent significant proportional deviations in the results due to blindly truncating the lower decimal places. This could potentially lead to errors in feature extraction within the neural network, ultimately resulting in incorrect identification. For example, in the calculation of a × c, when c is very small, the true result (Result = a × c) will also be relatively small. However, the absolute error is... If a is very large, then It could also be very large, which would lead to a large absolute error, while the relative error would be Error / Result, which in turn would make the relative error very large.

[0053] Third, when none of the above deterministic conditions are met, it means that the calculation has entered a more complex dynamic risk scenario. At this point, based on the principle of prioritizing the highest risk, a multi-level approximate decision-making process based on the magnitude of the risk can be initiated.

[0054] The process first avoids high risks: when the magnitude of any error amplification coefficient exceeds the preset high risk threshold (i.e., |a|≥64 or |b|≥64), it can be seen from formula (4) that the absolute error is at risk of being amplified sharply. Therefore, the instruction of the first calculation precision is forcibly generated, that is, the second low bit is not set to zero to obtain an approximate number, so as to ensure the core precision.

[0055] Fourth, if the above conditions are not met, a medium-risk assessment is initiated. The determination of medium risk encompasses two sources of risk: firstly, the error amplification factor itself is at a medium level (i.e., 32 ≤ |a| < 64 or 32 ≤ |b| < 64); secondly, the overall magnitude of the calculation is large (i.e., |c| ≥ 64). To efficiently cover these two situations, a second calculation precision can be implemented, that is, setting the lowest two bits of the second lowest bit to zero to obtain an approximate number, thus establishing a safety barrier between system-level accuracy stability and unit-level power consumption.

[0056] Fifth, if none of the above conditions are met, it means that the magnitudes of all operands are below the thresholds (|a|<32, |b|<32, |c|<64), and the calculation is in a low dynamic range. At this point, the amplification effect of the absolute error is the weakest, and the overall magnitude of the calculation is not high. Therefore, a third calculation precision can be generated, and the most aggressive bit width truncation can be performed to achieve deep energy saving, that is, the lowest three bits of the second lowest bit are set to zero to obtain an approximate number.

[0057] This hierarchical decision-making process based on absolute value preprocessing can generate an optimal precision control command for any combination of inputs, achieving refined management of dynamic power consumption while ensuring the overall accuracy of the system.

[0058] In other embodiments, when there is only one first operand, the judgment condition can be simplified, such as: When the first value is less than 16, set all four bits of the second lowest value to zero to obtain an approximate number; When there is a first value ≥ 16 and a second value < 16, the second least significant bit is not set to zero to obtain an approximate number. When there is a first value ≥ 64, the second lowest bit is not set to zero to obtain an approximate number; When there exists a value of 32 ≤ the first amplitude < 64 or a value of the second amplitude ≥ 64, the lowest two bits of the second lowest bit are set to zero to obtain an approximate number. When the first value is less than 32 and the second value is less than 64, the lowest three bits of the second lowest bit are set to zero to obtain an approximate number.

[0059] Example 2 Based on the theory described above, this embodiment also provides a dynamic precision approximation multiplier based on partial product decoupling, which can implement the above scheme at the hardware level.

[0060] refer to Figures 1 to 6 As shown, a dynamic precision approximation multiplier based on partial product decoupling includes a saliency evaluation unit, a precise calculation unit, a dynamic precision unit, and a final addition unit. The saliency evaluation unit obtains 8-bit first and second operands (in this embodiment, the first operands include first operand a and first operand b, and the second operand includes second operand c), and correspondingly splits them into a first high-order bit, a first low-order bit, a second high-order bit, and a second low-order bit; it takes the absolute value of the first and second operands to generate a first amplitude and a second amplitude; based on the first and second amplitudes and a preset threshold, it generates different precision instructions. The precise calculation unit precisely calculates the partial product of the first high-order bit and the second high-order bit, the partial product of the first low-order bit and the second high-order bit, and the partial product of the first low-order bit and the second low-order bit, respectively. The dynamic precision unit performs zeroing on the second low-order bit with different numbers of bits based on the precision instructions to form approximate numbers with different precisions; it calculates the partial product of the first high-order bit and the approximate number. The final addition unit sums the three partial products of the precise calculation unit and one partial product of the dynamic precision unit with predetermined arithmetic weights.

[0061] The approximate multiplier works as follows: Operands a, b, and c are used as inputs and first enter the saliency evaluation unit for a rapid evaluation of the data saliency; then, the evaluation result of the saliency evaluation unit is sent as a control signal to the dynamic precision unit, which dynamically configures the calculation path and generates partial products accordingly; the precise calculation unit generates the remaining partial products; finally, the final addition compensation unit completes the summation of all four partial products and outputs the approximate calculation result.

[0062] To efficiently translate the adaptive computation strategy into hardware circuitry, in this preferred embodiment, a 5-stage pipeline structure is designed inside the approximate multiplier, such as... Figure 6 As shown in the diagram, this pipeline architecture optimizes the critical path timing by decomposing the adaptive computation process into independent pipeline stages, thereby maximizing data throughput under soft logic implementation. The functions of each pipeline stage are described below: First-stage pipeline: Operand fetching and partitioning. In this stage, the approximate multiplier fetches the three operands a, b, and c required for parallel multiplication. Subsequently, the operands are partitioned into high-order and low-order parts according to formula (1). The partitioned operands are then registered in the next-stage pipeline register.

[0063] The second-level pipeline's function is implemented by the saliency evaluation unit. It receives the high-order bits of the operands from the first-level pipeline and analyzes them according to a hierarchical decision-making process to generate an optimized multi-level precision control instruction. This instruction, along with other operands, is then passed to subsequent pipeline stages.

[0064] The third-stage pipeline: dynamic mask generation and operand preprocessing. This stage transforms the decision instructions generated by the second-stage pipeline into specific execution control signals. Its core component is the dynamic mask generation module, which receives the level instructions from the second-stage pipeline and decodes them into corresponding internal mask signals (e.g., 4'b1111, 4'b1100, etc.). This mask signal is then compared with the second lowest bit... Perform a bitwise AND operation to generate a dynamically truncated internal approximation number. This operation precisely adjusts the computational accuracy in the early stages of the computation path and uses the shared approximation. It is provided to the two subsequent parallel computing channels.

[0065] Fourth-stage pipeline: Parallel partial product generation. This stage is the core of the computation, responsible for generating in parallel the four key partial product terms that constitute the final result, specifically including dynamic paths (i.e., dynamic precision units) and static paths (i.e., precise computation units).

[0066] Dynamic precision unit: A shared partial product generation module (i.e., the core multiplication logic of the dynamic precision unit) utilizes shared approximations from the third-stage pipeline. , respectively with the high digit and Perform multiplication to generate dynamic cross terms (i.e., in the formula). and Due to approximate numbers The lower bits may have been masked to zero, which reduces the signal flip rate of this path.

[0067] Precise calculation unit: Simultaneously, this stage of the pipeline performs the calculation of the partial products of the other three terms in parallel, for the higher-order products ( ) and lower-order product ( This invention employs dedicated combinational logic multiplication units for parallel processing. These units directly generate accurate products through optimized gate-level circuits, eliminating the need for dynamic control signals and ensuring numerical stability along the critical path. Unapproximated cross terms ( Similarly, calculations are performed within this clock domain using independent multiplication logic.

[0068] All four-way partial product results are aligned and registered at the end of this level.

[0069] Fifth-stage pipeline: Multi-item fusion and result output. This stage pipeline completes the final weighted summation calculation. A dual-channel adder tree unit receives four sets of partial product results from the fourth-stage pipeline. This unit sums the dynamically generated cross terms with the parallel-acquired exact terms according to the weight relationship defined in formula (3) (i.e., shift operation). Since approximation (i.e., zero-value bits) is introduced in the dynamic cross terms, the bit-flipping activity of some bits in this stage adder is significantly reduced, thereby achieving dynamic power saving at the physical level. The final calculation yields an approximate product. and .

[0070] Specifically, such as Figure 2 The diagram shown is a hardware implementation block diagram of the saliency evaluation unit. Figure 3 This is a schematic diagram of the bit-level critical path circuit for the saliency evaluation unit. The saliency evaluation unit includes an absolute value processing module, a first detection module, a second detection module, a third detection module, a fourth detection module, and a priority decision module. The absolute value processing module receives the input first operand a, first operand b, and second operand c, and performs absolute value processing on them respectively to generate the first amplitude |a|, the first amplitude |b|, and the second amplitude |c|. The first detection module receives and detects |a| and |b|. When |a| < 16 and |b| < 16, it generates a valid signal corresponding to the fourth precision instruction. The second detection module receives and detects |a|, |b|, and |c|. When |a| ≥ 16 or |b| ≥ 16 and |c| < 16, it generates a valid signal corresponding to the first precision instruction. The third detection module receives and detects |a| and |b|. When |a| ≥ 64 or |b| ≥ 64, it generates a valid signal corresponding to the first precision instruction. The fourth detection module receives and detects |a|, |b|, and |c|. When 32 ≤ |a| < 64 or 32 ≤ |a| < 64 or |c| ≥ 64, it generates a valid signal corresponding to the second precision instruction. The priority decision module generates the corresponding precision instruction based on the valid signals according to the order from the first detection module to the fourth detection module. If no valid signal is received, it generates a third precision instruction.

[0071] To implement the aforementioned saliency evaluation decision-making process at the hardware level with minimal area and power consumption, this embodiment designs the following... Figure 3 The physical circuit architecture is shown. (As shown in the image) Figure 3As shown, the saliency evaluation unit adopts a parallel processing structure based on bit extraction. The input operands first pass through the absolute value processing module (i.e., ABS shown in the figure) to generate three sets of unsigned amplitude buses (|a|, |b|, |c|), and then the key feature bits are directly extracted through bus branches. The first detection module determines whether the fourth to seventh bits of |a| and |b| are all 0. If they are all 0, a valid signal corresponding to the fourth precision instruction is generated. The second detection module determines whether the fourth to seventh bits of |a| and |b| contain 1, and also determines whether the fourth to seventh bits of |c| are all 0. If both conditions are met, a valid signal corresponding to the first precision instruction is generated. The third detection module determines whether |a|≥64 or |b|≥64 is satisfied by hard-wiring the 6th and 7th bits of bus |a| and the 6th and 7th bits of bus |b| to a 4-input OR gate. If both conditions are met, a valid signal corresponding to the first precision instruction is generated. The fourth detection module determines whether 32≤|a|<64 or 32≤|a|<64 or |c|≥64 is satisfied by hard-wiring the 5th bit of bus |a|, the 5th bit of bus |b|, and the 6th bit of bus |c| to a 3-input OR gate. If both conditions are met, a valid signal corresponding to the second precision instruction is generated.

[0072] The output signals of the four detection modules mentioned above are all connected to a 4-input priority encoder (i.e., the corresponding priority decision module). This encoder internally stores the physical priorities of "first detection module → second detection module → third detection module → fourth detection module," directly mapping the input logic state to the final two-bit precision control command (level[1:0]). When the signals output by all four detection modules are invalid, the priority encoder defaults to outputting the third precision command. This circuit design, through pure combinational logic gates and specific bit-level connections, eliminates complex arithmetic operation units, significantly reducing critical path delay and circuit area.

[0073] It is understood that in this embodiment, the precision control instructions (level[1:0]) include four: the first precision instruction, level=2'b11; the second precision instruction, level=2'b10; the third precision instruction, level=2'b01; and the fourth precision instruction, level=2'b00. In other embodiments, the remaining instructions can also be used to represent the same information.

[0074] Figure 4This application presents the overall architecture and data flow diagram of the dynamic precision unit. The dynamic precision unit is the technological cornerstone of the adaptive computing architecture of this invention. As a reconfigurable, dedicated cross-term computing unit designed to achieve dynamic matching of power consumption and precision, its core technical concept lies in transforming the abstract precision instructions output by the upstream saliency evaluation unit into quantifiable power savings at the physical circuit level. This concept is achieved by adhering to two major design principles: on-demand computing and logic sharing.

[0075] The principle of on-demand computing is reflected in the fact that dynamic precision units only activate the computing logic that matches the required precision, fundamentally eliminating the power consumption caused by performing unnecessary calculations. The principle of logic sharing, through ingenious circuit reuse, enables two parallel multiplication tasks to share key control and data generation logic, thereby significantly reducing hardware area and control overhead while achieving the same functionality.

[0076] In one specific embodiment, the interface of the dynamic precision unit includes: a control input for receiving precision control commands (level[1:0]); and a control input for receiving high-order bits. , and low digits The data input terminal. The function of the dynamic precision unit is to calculate the dynamic cross-product terms in parallel based on the input level instructions. (Right now ) and (Right now The two 8-bit wide calculation results are then output as data.

[0077] Specifically, such as Figure 4 As shown, the dynamic precision unit includes a dynamic mask generation module, a shared partial product generation module, and a dual-channel accumulation module. These modules work together to achieve dynamic adjustment and power consumption optimization.

[0078] First, the dynamic mask generation module can generate a first mask 1111 based on a first-precision instruction, a second mask 1100 based on a second-precision instruction, a third mask 1000 based on a third-precision instruction, and a fourth mask 0000 based on a fourth-precision instruction. Then, it performs a bitwise AND operation between the generated mask and the second least significant bit to form an approximate number. In other words, the dynamic mask generation module is responsible for decoding the input level instruction into an internal mask signal, `mask`. The decoding logic is specifically defined as follows: when the level instruction is 2'b11, the mask is set to 4'b1111; when the level is 2'b10, the mask is set to 4'b1100; when the level is 2'b01, the mask is set to 4'b1000; and when the level is 2'b00, the mask is set to 4'b0000. Then, this mask signal is subsequently ANDed with the input second least significant bit. Perform a bitwise AND operation to generate a dynamically truncated internal approximation. This approximate number Shared by the subsequent two computation channels, this forms the basis of "logical sharing" and enables "on-demand computation" from the source, because approximate numbers... Bits that are masked and set to zero will not trigger the flipping of subsequent circuits.

[0079] The shared partial product generation module can receive approximate numbers. The first high-order bit corresponding to the first operand a and the first high-order bit corresponding to the first operand b Parallel generation of the first high-order bits The part-order product row with the approximate number and the first high-order number The bit-level partial product row with approximate numbers. Specifically, in the hardware implementation, each 4×4 multiplication can be decomposed into the generation and accumulation of multiple rows of partial products. This shared partial product generation module utilizes... Each one, for example At the same time with and Perform a logical AND operation to generate the following respectively. Bit-level partial product of the channel and Bit-level partial product of the channel The power consumption optimization principle of this invention is reflected in this step: when the level instruction leads to an approximate number of... When some low-order bits are always zero, the corresponding partial product row of the weights (e.g.) , The input will also be a constant zero vector. This constant zero input ensures that there are no signal flips in the data path driving the subsequent adder array, thus achieving operand isolation at the physical level. This allows the corresponding logic gates to enter a silent state, reducing their dynamic power consumption to near zero.

[0080] The dual-channel accumulation module is used to shift and accumulate the generated bit-level partial product rows to obtain the corresponding partial product. For example... Figure 4 As shown, this module contains two parallel miniaturized adder trees, corresponding to... and Two computation channels. Each adder array consists of a set of half-adders and full adders, used to align and accumulate all partial products of their respective channels according to their weights, ultimately outputting an 8-bit dynamic cross-term result. (Right now ) and (Right now The power consumption of this accumulator module is also directly controlled by the state of the preceding partial product generation module. When the lower-order partial product row is set to zero, the inputs to the corresponding levels of the adder array are all zero, and these logic gates do not produce any internal signal toggles. In extreme cases, such as when only the highest-order partial product is non-zero, the entire complex adder array logically degenerates into a simple shifter, thereby achieving maximum power savings.

[0081] In summary, the dynamic precision unit (DPMU) transforms abstract precision instructions into physical gate-level activity control through a series of interconnected technical steps: "mask generation → bit-level partial product control → adder array activity suppression." This achieves a precise match between power consumption and computational precision requirements, and its shared logic characteristics also give it advantages in area efficiency and design regularity.

[0082] In this embodiment, there are three partial products that need to be calculated precisely, and the corresponding precise calculation unit preferably employs hard-wired combinational logic circuits. Specifically, for ( (4-bit signed number × 4-bit signed number) and ( (4-bit unsigned number × 4-bit unsigned number), this invention directly utilizes gate-level logic networks to construct the computation path. In modern integrated circuit technology, the hardware resources required to implement such small-width multiplication logic are minimal, making it a high-performance design that completely eliminates key error sources with minimal hardware overhead; secondly, for the cross-part product, which also uses precise calculation... It is implemented using a conventional combinational logic multiplier to give the EDA tool the maximum optimization space.

[0083] As mentioned above, precise calculations are performed using static logic units, while approximate calculations are implemented using specially designed dynamic precision units. This choice is made because static logic units are physically fixed and cannot directly respond to real-time precision adjustment commands from the saliency evaluation unit. Forcing dynamic control onto static logic would require adding complex multiplexing logic or redundant calculation units, significantly increasing the hardware area, which contradicts the power consumption adaptive design goal of this invention. Therefore, the dynamic approximation operation is concentrated in ( Furthermore, a dedicated dynamic precision unit was designed for it, which is more conducive to achieving the technical effects of the present invention.

[0084] Figure 5 This is the final internal architecture diagram of the addition unit provided in this application. (See diagram below.) Figure 5 As shown, the final addition unit, serving as the data flow endpoint of the dynamic precision approximation multiplier described in this invention, constitutes the reconstruction stage of the approximate calculation result. Its technical task is to receive the output data from the four upstream decoupled calculation paths—that is, the precisely calculated partial product corresponding to the first and second highest digits. The exact partial product corresponding to the first least significant digit and the second most significant digit. Approximate partial product corresponding to the first highest digit and the second lowest digit. And the precise partial product corresponding to the first and second least significant digits. —Based on the hierarchical approximate multiplication mathematical model proposed in this invention, alignment and summation operations with predetermined arithmetic weights are performed on these data to finally generate the complete approximate product of the dual channels.

[0085] like Figure 5 As shown, the internal architecture of the final additive compensation unit is designed as two independent and structurally symmetrical parallel processing paths, corresponding to the first channel and the second channel, respectively. For clarity, the following detailed explanation will focus on the processing path of the first channel: The first channel's processing path, in its physical implementation, can consist of a multi-level adder tree and hardwired networks, configured to execute a weight-based two-stage reconstruction process: The first stage is the intermediate-level synthesis of the cross-term partial product. The core of this stage is a first-stage adder, whose input is coupled to... and The output terminal of the adder is configured to receive... (corresponding to the first operand a) ,Right now ) and (corresponding to the first operand a) ,Right now The two are then arithmetically summed to generate an aggregated intermediate weight partial product. The purpose of this step is to combine all cross-product terms with the same weight (each with a weight of 2). 4 Merge them first to reduce the adder depth of the critical path later.

[0086] The second stage is the final summation of the full-length product. At the core of this stage is a second-level multi-input adder configured to perform the final arithmetic summation of three operands with different arithmetic weights. Specifically, these three operands and their processing logic are as follows: High-weighted operands: derived from the exact partial product of the first and second highest digits. (corresponding to the first operand a) ,Right now Before being fed into the adder, the operand must be processed by the first hardwired shifter, performing a logical left shift of 8 bits (equivalent to multiplying by 2). 8 The operation is performed to align it to the most significant bit segment of the final product [15:8]; Medium-weighted operands: derived from the intermediate-weighted partial product generated in the first stage. Before being fed into the adder, the operand is processed by a second hardwired shifter, performing a logical left shift of 4 bits (equivalent to multiplying by 2). 4 The operation is performed to align it to the middle valid bit segment of the final product [11:4]; Low-weight operands: precisely calculated partial products derived from the first and second least significant bits. (corresponding to the first operand a) ,Right now This operand represents the least significant bit segment [7:0] of the product, so it can be directly connected to the least significant bit input of the adder without any shifting.

[0087] The second-stage multi-input adder described above accumulates the three precisely shift-aligned operands, and its output is the final approximate product of the first channel. Meanwhile, a second-channel processing path, mirroring the structure of the first channel, processes the corresponding input from the second channel in complete parallel. , , , Perform the same "synthesis-route alignment-convergence" operation to synchronously generate the final approximate product of the second channel. .

[0088] In summary, the final addition unit, through its hierarchical adder structure and hard-wired routing, provides a deterministic, low-latency hardware implementation scheme for the core approximate mathematical model of this invention (see Equation 3). This structure ensures that the contributions of all parallel computing paths, especially the dynamic compensation terms dynamically adjusted by the saliency evaluation unit and the dynamic precision unit, are seamlessly integrated into the final result, strictly adhering to the mathematical weights. This completes the closed loop from distributed decoupled computation to unified output, and is the key physical carrier for achieving the high-efficiency, high-precision approximate computation technology described in this invention.

[0089] The common English terms or letters used in this invention for clarity of description are for illustrative purposes only and are not limiting interpretations or specific uses. They should not be used to limit the scope of protection of this invention based on their possible Chinese translations or specific letters.

[0090] It should also be noted that in this article, relational terms such as “first” and “second” are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

Claims

1. A dynamic precision approximate multiplier based on partial product decoupling, characterized in that, include: The significance evaluation unit is used to obtain the first and second operands of 8 bits, and to split them into the first high bit and the first low bit, as well as the second high bit and the second low bit. Take the absolute values ​​of the first operand and the second operand to generate a first amplitude and a second amplitude respectively; based on the first amplitude and the second amplitude, and a preset threshold, generate different precision instructions; A precise calculation unit is used to precisely calculate the partial product of the first high-order digit and the second high-order digit, the partial product of the first low-order digit and the second high-order digit, and the partial product of the first low-order digit and the second low-order digit, respectively. The dynamic precision unit performs zeroing on the second low-order bits by different numbers of bits based on the precision instruction to form approximate numbers with different precisions; and calculates the partial product of the first high-order bits and the approximate number. The final addition unit is used to sum the three partial products of the precise calculation unit and the one partial product of the dynamic precision unit with predetermined arithmetic weights.

2. The dynamic precision approximation multiplier based on partial product decoupling according to claim 1, characterized in that, The first operand includes first operand a and first operand b, and the second operand includes second operand c.

3. A dynamic precision approximate multiplier based on partial product decoupling according to claim 2, characterized in that, The significance assessment unit includes an absolute value processing module, a first detection module, a second detection module, a third detection module, a fourth detection module, and a priority decision module; The absolute value processing module is used to take the absolute values ​​of the first operand a, the first operand b, and the second operand c, and generate the first amplitude |a|, the first amplitude |b|, and the second amplitude |c| accordingly. The first detection module is used to receive and detect |a| and |b|, and when |a|<16 and |b|<16 are satisfied, it generates a valid signal corresponding to the fourth precision instruction; The second detection module is used to receive and detect |a|, |b| and |c|. When |a|≥16 or |b|≥16 and |c|<16, it generates a valid signal corresponding to the first precision instruction. The third detection module is used to receive and detect |a| and |b|, and when |a|≥64 or |b|≥64 is satisfied, it generates a valid signal corresponding to the first precision instruction; The fourth detection module is used to receive and detect |a|, |b| and |c|. When 32≤|a|<64 or 32≤|a|<64 or |c|≥64 is satisfied, a valid signal corresponding to the second precision instruction is generated. The priority decision module generates the corresponding precision instruction based on the valid signal according to the order from the first detection module to the fourth detection module. When no valid signal is received, a third precision instruction is generated.

4. A dynamic precision approximate multiplier based on partial product decoupling according to claim 2, characterized in that, The dynamic precision unit includes a dynamic mask generation module, a shared partial product generation module, and a dual-channel accumulation module; The dynamic mask generation module generates a first mask 1111 based on the first precision instruction, a second mask 1100 based on the second precision instruction, a third mask 1000 based on the third precision instruction, and a fourth mask 0000 based on the fourth precision instruction. The generated mask is then bitwise ANDed with the second low-order bits to form the approximate number. The shared partial product generation module receives the approximate number and the first high-order digit a corresponding to the first operand a. h and the first high-order bit b corresponding to the first operand b h Parallel generation of the first high-order number a h The bit-level partial product row of the approximate number and the first high-order bit b h Product row with the bit-level portion of the approximate number; The dual-channel accumulation module is used to shift and accumulate the generated bit-level partial product rows to obtain the corresponding partial product.

5. A dynamic precision approximate multiplier based on partial product decoupling according to claim 1, characterized in that, The precise calculation unit includes a combinational logic multiplier.

6. A dynamic precision approximate multiplier based on partial product decoupling according to claim 2, characterized in that, The final addition unit includes a first channel and a second channel; The first channel is used to perform a summation with predetermined arithmetic weights on the three partial products generated by the first operand a and the second operand c in the precision calculation unit and the one partial product generated in the dynamic precision unit. The second channel is used to perform a summation with predetermined arithmetic weights on the three partial products generated by the first operand b and the second operand c in the precision calculation unit and the one partial product generated in the dynamic precision unit.

7. A method for implementing dynamic precision approximate multiplication based on partial product decoupling, characterized in that, Includes the following steps: Get the 8-bit first operand and second operand, and split them into the first high-bit and first low-bit, and the second high-bit and second low-bit, respectively. Based on the first high digit, the first low digit, the second high digit, and the second low digit, four partial products are generated. Among the four partial products, the partial product of the first high digit and the second low digit is calculated by dynamic precision approximation multiplication, the partial product of the other three partial products is calculated by precise multiplication, and the four partial products are summed. The dynamic precision approximate multiplication calculation includes: Take the absolute values ​​of the first operand and the second operand to generate the first amplitude and the second amplitude respectively; Based on the first amplitude, the second amplitude, and a preset threshold, the second low-digit number is zeroed by different numbers of bits to form approximate numbers with different precision. Calculate the partial product of the first high-order digit and the approximate number.

8. The method for implementing dynamic precision approximate multiplication based on partial product decoupling according to claim 7, characterized in that, The first operand includes first operand a and first operand b, and the second operand includes second operand c; Generate the four-term partial product corresponding to the first operand a and the second operand c, and the four-term partial product corresponding to the first operand b and the second operand c, respectively; When performing the dynamic precision approximation multiplication calculation, the first operand a and the first operand b share the same approximation number.

9. The method for implementing dynamic precision approximate multiplication based on partial product decoupling according to claim 7, characterized in that, Based on the first amplitude, the second amplitude, and a preset threshold, the process of setting different numbers of zeros to the second low-order bits to form approximate numbers of different precisions includes the following steps in sequence: When the first value is less than 16, set all four bits of the second lowest value to zero to obtain the approximate number; When there is a first amplitude value ≥ 16 and a second amplitude value < 16, the second low-order bit is not set to zero to obtain the approximate number; When there is a first value ≥ 64, the second low-order bit is not set to zero to obtain the approximate number; When there exists a value of 32 ≤ first amplitude < 64 or second amplitude ≥ 64, the lowest two bits of the second low-order number are set to zero to obtain the approximate number; When the first amplitude value is less than 32 and the second amplitude value is less than 64, the lowest three bits of the second low-order bit are set to zero to obtain the approximate number.

10. The method for implementing dynamic precision approximate multiplication based on partial product decoupling according to claim 8, characterized in that, The dynamic precision approximate multiplication calculation includes: Take the absolute values ​​of the first operand a, the first operand b, and the second operand c to generate the first amplitude |a|, the first amplitude |b|, and the second amplitude |c| respectively; Based on |a|, |b|, and |c|, and a preset threshold, the second low-order bits are zeroed out by different numbers of bits to form approximate numbers of different precisions, including performing the following steps in sequence: When |a|<16 and |b|<16, set all four bits of the second lowest bit to zero to obtain the approximate number; When |a|≥16 or |b|≥16 and |c|<16, the second lower digit is not set to zero to obtain the approximate number; When |a|≥64 or |b|≥64, the second least significant digit is not set to zero to obtain an approximate number; When 32≤|a|<64 or 32≤|a|<64 or |c|≥64, the lowest two bits of the second lowest bit are set to zero to obtain an approximate number; When |a|<32 and |b|<32 and |c|<64, the lowest three bits of the second lowest bit are set to zero to obtain an approximate number.

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