Cubic spline interpolation circuit suitable for up-sampling
The cubic spline interpolation circuit solves the problems of large chip interpolation circuit area and low reusability, and achieves efficient signal upsampling. The hardware circuit area is small and highly reusable, making it suitable for different application scenarios.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- THE 54TH RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
- Filing Date
- 2026-01-13
- Publication Date
- 2026-05-08
AI Technical Summary
Interpolation circuits in existing chips have large area overhead or low reusability, making them difficult to reuse in different application scenarios. Furthermore, zero-placing causes mirror frequency generation, increasing development costs and time.
A cubic spline interpolation circuit is adopted, including a data weighting module, a cubic spline interpolation function coefficient generation module, an interpolation calculation module, and an interpolation module. The interpolation signal is generated by calculating the constant term, first power coefficient, second power coefficient, and third power coefficient of the cubic spline interpolation function, thereby realizing signal upsampling.
It achieves good interpolation results without relying on signal frequency characteristics, has a small hardware circuit area, an equivalent gate count of 32,900, a clock frequency of up to 56.4 MHz, and good reusability.
Smart Images
Figure CN121996201A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of digital integrated circuit technology, and more specifically, relates to a cubic spline interpolation circuit suitable for upsampling. Background Technology
[0002] In many common chips, signals such as audio and images often need to be upsampled, which requires interpolation to increase the signal sampling rate. Common chips on the market typically use zero-placing for upsampling. However, zero-placing introduces image frequencies, requiring significant area for filter design. Furthermore, filters implemented this way are highly sensitive to signal frequency characteristics, making them difficult to reuse across different applications, thus greatly increasing development costs and time. In contrast, cubic spline interpolation is independent of signal frequency characteristics, has a simpler algorithm, and offers greater reusability and practical value. Therefore, researching a cubic spline interpolation circuit suitable for chip applications has significant market value. Summary of the Invention
[0003] In view of the shortcomings of the prior art, the purpose of this invention is to provide a cubic spline interpolation circuit suitable for chip applications, which aims to solve the problems of large area overhead or low reusability of interpolation circuits in chips provided by the prior art.
[0004] The technical solution provided by this invention is as follows: A cubic spline interpolation circuit suitable for upsampling includes: a data weighting module, a cubic spline interpolation function coefficient generation module, an interpolation calculation module, and an interpolation module; The input terminal of the data weighting module is used to receive the input signal sig, and outputs the weighted signal sig_r of the input signal according to the signal received at the input terminal; The first input terminal of the cubic spline interpolation function coefficient generation module is used to receive the input signal sig, and the second input terminal is connected to the output terminal of the data weighting module. It is used to calculate the constant term a of the cubic spline interpolation function output by the first output terminal, the first power coefficient b of the cubic spline interpolation function output by the second output terminal, the second power coefficient c of the cubic spline interpolation function output by the third output terminal, and the third power coefficient d of the cubic spline interpolation function output by the fourth output terminal based on the input signal sig and the weighting signal sig_r of the input signal. The first, second, third, and fourth input terminals of the interpolation calculation module are respectively connected to the first, second, third, and fourth output terminals of the cubic spline interpolation function coefficient generation module, and are used to output the interpolation value sig_int based on the constant term a, the first power coefficient b, the second power coefficient c, and the third power coefficient d of the cubic spline interpolation function. The first input terminal of the interpolation module is used to receive the input signal sig, and the second input terminal is connected to the output terminal of the interpolation calculation module, and is used to output the interpolated signal sig_out based on the weighted signal sig_r of the input signal and the interpolation value sig_int.
[0005] Furthermore, the data weighting module includes: a first register, a second register, and a weight acquisition circuit; The input terminal of the first register and the first input terminal of the weight acquisition circuit are jointly used as the input terminal of the data weighting module. The input terminal of the second register and the second input terminal of the weight acquisition circuit are connected to the output terminal of the first register. The third input terminal of the weight acquisition circuit is connected to the output terminal of the second register. The output terminal of the weight acquisition circuit is used as the output terminal of the data weighting module. The weight acquisition circuit is used to obtain the weighted value of the input data.
[0006] Furthermore, the cubic spline interpolation function coefficient generation module includes: a constant term a generation module, a first power coefficient b generation module, a second power coefficient c generation module, and a cubic power coefficient d generation module; The input terminal of the constant term a generation module is used to receive the input signal sig, and the first output terminal of the constant term a generation module is used as the first output terminal of the cubic spline interpolation function coefficient generation module. The first input terminal of the first power coefficient b generation module is connected to the second output terminal of the constant term a generation module, the second input terminal is connected to the third output terminal of the constant term a generation module, the third input terminal is connected to the second output terminal of the second power coefficient c generation module, the fourth input terminal is connected to the third output terminal of the second power coefficient c generation module, and the output terminal of the first power coefficient b generation module serves as the second output terminal of the cubic spline interpolation function coefficient generation module. The input of the quadratic coefficient c generation module is connected to the output of the data weighting module, and the first output of the quadratic coefficient c generation module serves as the third output of the cubic spline interpolation function coefficient generation module. The first input terminal of the cubic power coefficient d generation module is connected to the second input terminal of the quadratic power coefficient c generation module, the second input terminal is connected to the third output terminal of the quadratic power coefficient c generation module, and the output terminal of the cubic power coefficient d generation module serves as the fourth output terminal of the cubic spline interpolation function coefficient generation module.
[0007] The above-described technical solution conceived by this invention has the following beneficial effects: It can achieve good interpolation results without relying on signal frequency characteristics, and also has a smaller area than traditional zero-placing interpolation. The hardware implementation of the algorithm has a circuit area of 167496µm. 2 The equivalent gate count is 32,900. Compared with existing technologies, it has better reusability and occupies less space. Attached Figure Description
[0008] Figure 1 This is a schematic diagram of the overall structure provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the data weighting module structure provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the cubic spline interpolation function coefficient generation module provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the interpolation calculation module structure provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the interpolation module structure provided in an embodiment of the present invention; Detailed Implementation
[0009] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0010] To address the shortcomings of existing technologies, the present invention aims to provide a cubic spline interpolation circuit suitable for increasing the sampling rate of chips, characterized by its small footprint and high reusability. Its main function is to upsample the input signal based on a cubic spline function, thereby increasing the sampling frequency of the output signal.
[0011] To achieve the above objectives, this invention provides a cubic spline interpolation circuit suitable for chips. The overall structure is as follows: Figure 1 As shown, it includes a data weighting module, a cubic spline interpolation function coefficient generation module, an interpolation calculation module, and an interpolation module.
[0012] The input terminal of the data weighting module is connected to the acquired input signal (sig), and outputs a weighted signal (sig_r) of the input signal based on the signal received at the input terminal. The first input terminal of the cubic spline interpolation function coefficient generation module is connected to the acquired input signal (sig), and the second input terminal is connected to the output terminal of the data weighting module. It is used to calculate the constant term (a) of the cubic spline interpolation function output by the first output terminal, the first power coefficient (b) of the cubic spline interpolation function output by the second output terminal, the second power coefficient (c) of the cubic spline interpolation function output by the third output terminal, and the third power coefficient (d) of the cubic spline interpolation function output by the fourth output terminal based on the input signal (sig) and the weighted signal (sig_r) of the input signal. The first, second, third, and fourth input terminals of the interpolation calculation module are respectively connected to the first, second, third, and fourth output terminals of the cubic spline interpolation function coefficient generation module, and are used to output interpolated values (sig_int) based on the constant term (a), the first power coefficient (b), the second power coefficient (c), and the third power coefficient (d) of the cubic spline interpolation function. The first input terminal of the interpolation module is used to receive the input signal (sig), and the second input terminal is connected to the output terminal of the interpolation calculation module, and is used to output the interpolated signal (sig_out) based on the weighted signal (sig_r) and the interpolation value (sig_int) of the input signal. The structure of the data weighting module is as follows: Figure 2 As shown, it includes: two registers and a weight acquisition circuit; the input terminal of the first register and the first input terminal of the weight acquisition circuit jointly serve as the input terminal of the data weighting module; the input terminal of the second register and the second input terminal of the weight acquisition circuit are connected to the output terminal of the first register; the third input terminal of the weight acquisition circuit is connected to the output terminal of the second register; and the output terminal of the weight acquisition circuit serves as the output terminal of the data weighting module. The weight acquisition circuit is used to acquire the weighted value of the input data. The data weighting section can select more data for weighting; increasing the data can improve the interpolation accuracy, but it leads to an increase in area. The data weighting module is an optimized arrangement that comprehensively considers accuracy and area.
[0013] The structure of the cubic spline interpolation function coefficient generation module is as follows: Figure 3As shown, it includes: a constant term a generation module, a first power coefficient b generation module, a second power coefficient c generation module, and a cubic power coefficient d generation module; the input terminal of the constant term a generation module is used to receive the input signal sig, and the first output terminal of the constant term a generation module serves as the first output terminal of the cubic spline interpolation function coefficient generation module; the first input terminal of the first power coefficient b generation module is connected to the second output terminal of the constant term a generation module, the second input terminal is connected to the third output terminal of the constant term a generation module, the third input terminal is connected to the second output terminal of the second power coefficient c generation module, and the fourth input terminal is connected to the third output terminal of the second power coefficient c generation module. The first power coefficient b generation module is connected to the second output of the cubic spline interpolation function coefficient generation module. The second power coefficient c generation module is connected to the output of the data weighting module, and the first output of the second power coefficient c generation module is connected to the third output of the cubic spline interpolation function coefficient generation module. The first input of the cubic power coefficient d generation module is connected to the second input of the second power coefficient c generation module, and the second input is connected to the third output of the second power coefficient c generation module. The output of the cubic power coefficient d generation module is connected to the fourth output of the cubic spline interpolation function coefficient generation module. The constant term a generation module is used to generate the constant term (a) in the cubic spline interpolation function. The constant term (a) is obtained by delaying the current input signal (sig) by two time steps. The first power coefficient b generation module is used to generate the first power coefficient (b) in the cubic spline interpolation function. The first power coefficient (b) is obtained by operating on the constant term (a), the constant term (a_n) at the next time step, the second power coefficient (c), and the second power coefficient (c_n) at the next time step (a_n-a-c_n / 3-2c / 3). The second power coefficient c generation module is used to generate the second power coefficient (c) in the cubic spline interpolation function. The second power coefficient (c) is obtained by shifting the weighted signal (sig_r) of the input signal two bits to the right and delaying by one time step. The cubic power coefficient d generation module is used to generate the cubic power coefficient (d) in the cubic spline interpolation function. The cubic power coefficient (d) is obtained by operating on the second power coefficient (c) and the second power coefficient (c_n) at the next time step (c_n / 3-c / 3).
[0014] The structure of the interpolation calculation module is as follows: Figure 4As shown, it includes: two accumulators, a square multiplication circuit, and an adder; the first input terminal of the first accumulator is connected to the first output terminal of the cubic spline interpolation function coefficient generation module, the second input terminal of the first accumulator is connected to the second output terminal of the cubic spline interpolation function coefficient generation module, and the output terminal of the first accumulator is connected to the first input terminal of the adder; the first input terminal of the second accumulator is connected to the third output terminal of the cubic spline interpolation function coefficient generation module, the second input terminal of the second accumulator is connected to the fourth output terminal of the cubic spline interpolation function coefficient generation module, and the output terminal of the second accumulator is connected to the input terminal of the square multiplication circuit; the output terminal of the square multiplication circuit is connected to the second input terminal of the adder; the output terminal of the adder serves as the output terminal of the interpolation calculation module. The interpolation calculation module is used to calculate the interpolation value (sig_int). The first accumulator is used to calculate a+bi, the second accumulator is used to calculate c+di, the square multiplication is used to calculate ci^2+di^3, and the adder is used to calculate a+bi+ci^2+di^3. The calculation result is the interpolation value (sig_int).
[0015] The structure of the interpolation module is as follows: Figure 5 As shown, it includes a counter and a selector; the selector selects whether to output an input signal (sig) or an interpolated value (sig_int) based on the value of the counter. When the value of the counter is 0, it outputs an input signal (sig); when the value of the counter is not 0, it outputs an interpolated value (sig_int). The output result is the interpolated signal (sig_out).
[0016] In the overall circuit structure of this invention embodiment, the input signal is the input signal (sig), and the output signal is the interpolated signal (sig_out). ASIC verification analysis shows that the circuit area for the hardware implementation of this algorithm is 167496µm. 2 The equivalent gate count is 32,900, and the highest clock frequency can reach 56.4 MHz. Compared with existing technologies, it has better reusability and occupies less space.
Claims
1. A cubic spline interpolation circuit suitable for upsampling, characterized in that, include: The module includes a data weighting module, a cubic spline interpolation function coefficient generation module, an interpolation calculation module, and an interpolation module. The input terminal of the data weighting module is used to receive the input signal sig, and outputs the weighted signal sig_r of the input signal according to the signal received at the input terminal; The first input terminal of the cubic spline interpolation function coefficient generation module is used to receive the input signal sig, and the second input terminal is connected to the output terminal of the data weighting module. It is used to calculate the constant term a of the cubic spline interpolation function output by the first output terminal, the first power coefficient b of the cubic spline interpolation function output by the second output terminal, the second power coefficient c of the cubic spline interpolation function output by the third output terminal, and the third power coefficient d of the cubic spline interpolation function output by the fourth output terminal based on the input signal sig and the weighting signal sig_r of the input signal. The first, second, third, and fourth input terminals of the interpolation calculation module are respectively connected to the first, second, third, and fourth output terminals of the cubic spline interpolation function coefficient generation module, and are used to output the interpolation value sig_int based on the constant term a, the first power coefficient b, the second power coefficient c, and the third power coefficient d of the cubic spline interpolation function. The first input terminal of the interpolation module is used to receive the input signal sig, and the second input terminal is connected to the output terminal of the interpolation calculation module, and is used to output the interpolated signal sig_out based on the weighted signal sig_r of the input signal and the interpolation value sig_int.
2. The cubic spline interpolation circuit suitable for upsampling according to claim 1, characterized in that, The data weighting module includes: a first register, a second register, and a weight acquisition circuit; The input terminal of the first register and the first input terminal of the weight acquisition circuit are jointly used as the input terminal of the data weighting module. The input terminal of the second register and the second input terminal of the weight acquisition circuit are connected to the output terminal of the first register. The third input terminal of the weight acquisition circuit is connected to the output terminal of the second register. The output terminal of the weight acquisition circuit is used as the output terminal of the data weighting module. The weight acquisition circuit is used to obtain the weighted value of the input data.
3. A cubic spline interpolation circuit suitable for upsampling according to claim 1 or 2, characterized in that, The cubic spline interpolation function coefficient generation module includes: a constant term a generation module, a first power coefficient b generation module, a second power coefficient c generation module, and a cubic power coefficient d generation module; The input terminal of the constant term a generation module is used to receive the input signal sig, and the first output terminal of the constant term a generation module is used as the first output terminal of the cubic spline interpolation function coefficient generation module. The first input terminal of the first power coefficient b generation module is connected to the second output terminal of the constant term a generation module, the second input terminal is connected to the third output terminal of the constant term a generation module, the third input terminal is connected to the second output terminal of the second power coefficient c generation module, the fourth input terminal is connected to the third output terminal of the second power coefficient c generation module, and the output terminal of the first power coefficient b generation module serves as the second output terminal of the cubic spline interpolation function coefficient generation module. The input of the quadratic coefficient c generation module is connected to the output of the data weighting module, and the first output of the quadratic coefficient c generation module serves as the third output of the cubic spline interpolation function coefficient generation module. The first input terminal of the cubic power coefficient d generation module is connected to the second input terminal of the quadratic power coefficient c generation module, the second input terminal is connected to the third output terminal of the quadratic power coefficient c generation module, and the output terminal of the cubic power coefficient d generation module serves as the fourth output terminal of the cubic spline interpolation function coefficient generation module.