Semiconductor devices and electronic systems including the same

Abstract

To provide a semiconductor device and an electronic system containing the same.SOLUTION: A semiconductor device contains: a substrate containing a memory cell region and a connection region; a plurality of gate lines which is overlapped on each memory cell region of the substrate in a vertical direction each other, and is structured from a first metal; a step type connection part that is arranged on the connection region, is integrally connected to the plurality of gate lines, and contains a plurality of conductive pad regions structured by a first metal; a plurality of contact structure material which is constructed so as to be connected to the plurality of conductive pad regions at a position where it is overlapped with the step type connection part in the vertical direction, and is structured by a second metal; and at least one metal silicide film formed in at least one connection part of the plurality of connection parts between the plurality of conductive pad regions and the plurality of contact structure material.SELECTED DRAWING: Figure 5A

Description

Technical Field

[0001] The technical idea of the present invention relates to a semiconductor device and an electronic system including the same, and particularly to a semiconductor device including a non-volatile vertical memory element and an electronic system including the same.

Background Art

[0002] In an electronic system that requires data storage, a semiconductor device capable of storing high-capacity data is required. Accordingly, a scheme for increasing the data storage capacity of the semiconductor device has been studied. For example, as one of the methods for increasing the data storage capacity of the semiconductor device, a semiconductor device including a vertical memory element having three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells has been proposed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The technical problem to be solved by the technical idea of the present invention is to provide a semiconductor device that can maintain excellent electrical characteristics even when the number of stacked word lines increases and the number of contacts and wirings connected to the word lines increase in order to improve the integration degree in a semiconductor device including three-dimensionally arranged memory cells.

[0005] Another technical problem that the technical concept of the present invention aims to solve is to provide an electronic system including a semiconductor device that can maintain excellent electrical characteristics even when the number of stacked word lines increases, and the number of contacts and wirings connected to the word lines increases, in order to improve integration density, in a semiconductor device equipped with three-dimensionally arranged memory cells. [Means for solving the problem]

[0006] A semiconductor device according to one aspect of the technical concept of the present invention includes: a substrate including a memory cell region and a connecting region; a plurality of gate lines made of a first metal that overlap each other vertically on the memory cell region of the substrate; a stepped connecting portion disposed on the connecting region and integrally connected to the plurality of gate lines, including a plurality of conductive pad regions made of the first metal; a plurality of contact structures made of a second metal that are configured to be connected to the plurality of conductive pad regions at a position that overlaps vertically with the stepped connecting portion; and at least one metal silicide film formed on at least one of a plurality of connecting portions between the plurality of conductive pad regions and the plurality of contact structures.

[0007] A semiconductor device according to another aspect of the technical concept of the present invention includes: a substrate including a memory cell region and a connecting region; a gate stack including a first gate line extending horizontally on the memory cell region of the substrate parallel to the main surface of the substrate, and a first conductive pad region integrally connected to the first gate line, extending horizontally on the connecting region, and composed of a first metal; a contact structure extending vertically on the first conductive pad region and composed of a second metal; and a metal silicide film interposed between the first conductive pad region and the contact structure, and in contact with the first conductive pad region and the contact structure.

[0008] An electronic system according to one aspect of the technical concept of the present invention includes a main substrate; a semiconductor device on the main substrate; and a controller on the main substrate that is electrically connected to the semiconductor device; wherein the semiconductor device includes a substrate including a memory cell region and a connection region; a gate stack including a gate line extending horizontally parallel to the main surface of the substrate on the memory cell region of the substrate, and a conductive pad region integrally connected to the gate line and extending horizontally on the connection region, and composed of a first metal; a contact structure extending vertically on the conductive pad region and composed of a second metal; a metal silicide film interposed between the conductive pad region and the contact structure; a peripheral circuit region positioned at a location separated from the gate stack; and input / output pads formed on the substrate. [Effects of the Invention]

[0009] According to the semiconductor device based on the technical concept of the present invention, in a semiconductor device equipped with three-dimensionally arranged memory cells, even if the number of stacked word lines increases in order to improve integration density, and the number of contacts and wirings connected to the word lines increases, the contact resistance at the interface between the conductive line and the contact plug connected to the conductive line is reduced, thereby maintaining excellent electrical characteristics in the semiconductor device and improving the reliability of the semiconductor device. [Brief explanation of the drawing]

[0010] [Figure 1] This is a block diagram of a semiconductor device according to an embodiment based on the technical concept of the present invention. [Figure 2] This is a schematic perspective view of a semiconductor device according to an embodiment based on the technical concept of the present invention. [Figure 3] This is an equivalent circuit diagram of a memory cell array of a semiconductor device according to an embodiment based on the technical concept of the present invention. [Figure 4] This is a plan view showing the main components of a semiconductor device according to an embodiment based on the technical concept of the present invention. [Figure 5A]Figure 4 shows cross-sectional views of the cross-sectional configuration along lines A1-A1' and A2-A2', as well as a cross-sectional view of a portion of the surrounding circuit region. [Figure 5B] This is a cross-sectional view along the line B-B' in Figure 4. [Figure 5C] This is an enlarged cross-sectional view of the local area indicated as "EX1" in Figure 5A. [Figure 6A] This is a cross-sectional view showing a magnified view of the area indicated as "BX" in Figure 5B. [Figure 6B] This is a cross-sectional view showing an exemplary structure of the gate dielectric film. [Figure 6C] This is a cross-sectional view showing an exemplary structure of the gate dielectric film. [Figure 6D] This is a cross-sectional view showing an exemplary structure of the gate dielectric film. [Figure 7A] This is a cross-sectional view illustrating a modified example of a semiconductor device according to another embodiment based on the technical concept of the present invention. [Figure 7B] This is a cross-sectional view illustrating a modified example of a semiconductor device according to another embodiment based on the technical concept of the present invention. [Figure 7C] This is a cross-sectional view illustrating a modified example of a semiconductor device according to another embodiment based on the technical concept of the present invention. [Figure 8A] This is a cross-sectional view illustrating further modifications of a semiconductor device according to other embodiments based on the technical concept of the present invention. [Figure 8B] (A) is an enlarged cross-sectional view of the local area indicated as "EX31" in Figure 8A, and (B) is an enlarged cross-sectional view of the local area indicated as "EX32" in Figure 8A. [Figure 9] This is a cross-sectional view illustrating a semiconductor device according to yet another embodiment based on the technical concept of the present invention. [Figure 10] This is a cross-sectional view illustrating a semiconductor device according to yet another embodiment based on the technical concept of the present invention. [Figure 11] This is a cross-sectional view illustrating a semiconductor device according to yet another embodiment based on the technical concept of the present invention. [Figure 12]A cross-sectional view for explaining a semiconductor device according to another embodiment based on the technical idea of the present invention. [Figure 13] A drawing schematically showing an electronic system including a semiconductor device according to an exemplary embodiment of the present invention. [Figure 14] A perspective view schematically showing an electronic system including a semiconductor device according to an exemplary embodiment of the present invention. [Figure 15] A cross-sectional view schematically showing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 16] A cross-sectional view schematically showing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 17A] A cross-sectional view shown in the order of processes for explaining a method of manufacturing a semiconductor device according to an embodiment based on the technical idea of the present invention. [Figure 17B] A cross-sectional view shown in the order of processes for explaining a method of manufacturing a semiconductor device according to an embodiment based on the technical idea of the present invention. [Figure 17C] A cross-sectional view shown in the order of processes for explaining a method of manufacturing a semiconductor device according to an embodiment based on the technical idea of the present invention. [Figure 17D] A cross-sectional view shown in the order of processes for explaining a method of manufacturing a semiconductor device according to an embodiment based on the technical idea of the present invention. [Figure 17E] A cross-sectional view shown in the order of processes for explaining a method of manufacturing a semiconductor device according to an embodiment based on the technical idea of the present invention. [Figure 18A] A cross-sectional view shown in the order of processes for explaining a process of forming a metal silicide film and a contact structure by a method of manufacturing a semiconductor device according to an embodiment based on the technical idea of the present invention. [Figure 18B] A cross-sectional view shown in the order of processes for explaining a process of forming a metal silicide film and a contact structure by a method of manufacturing a semiconductor device according to an embodiment based on the technical idea of the present invention. [Figure 18C]This cross-sectional view shows the steps in order to illustrate the process of forming a metal silicide film and a contact structure by a semiconductor device manufacturing method according to an embodiment of the technical concept of the present invention. [Figure 18D] This cross-sectional view shows the steps in order to illustrate the process of forming a metal silicide film and a contact structure by a semiconductor device manufacturing method according to an embodiment of the technical concept of the present invention. [Figure 18E] This cross-sectional view shows the steps in order to illustrate the process of forming a metal silicide film and a contact structure by a semiconductor device manufacturing method according to an embodiment of the technical concept of the present invention. [Modes for carrying out the invention]

[0011] Embodiments of the present invention will be described in detail below with reference to the attached drawings. The same reference numerals are used for identical components in the drawings, and redundant descriptions of them are omitted.

[0012] Figure 1 is a block diagram of a semiconductor device 10 according to an embodiment of the technical concept of the present invention.

[0013] Referring to Figure 1, the semiconductor device 10 includes a memory cell array 20 and peripheral circuits 30. The memory cell array 20 includes a plurality of memory cell blocks BLK1, BLK2, ..., BLKn. Each of the plurality of memory cell blocks BLK1, BLK2, ..., BLKn contains a plurality of memory cells. The memory cell blocks BLK1, BLK2, ..., BLKn can be connected to the peripheral circuits 30 via bit lines BL, gate stacks GS, string selection lines SSL and ground selection lines GSL.

[0014] The peripheral circuitry 30 includes a row decoder 32, a page buffer 34, a data input / output circuit 36, control logic 38, and a common source line driver (CSL driver) 39. Although not shown in Figure 1, the peripheral circuitry 30 may further include various circuits such as a voltage generation circuit to generate the various voltages necessary for the operation of the semiconductor device 10, an error correction circuit to correct errors in the data read from the memory cell array 20, and an input / output interface.

[0015] The memory cell array 20 is connectable to the page buffer 34 via the bit line BL, and to the row decoder 32 via the gate stack GS, string selection line SSL, and ground selection line GSL. In the memory cell array 20, the multiple memory cells contained in the multiple memory cell blocks BLK1, BLK2, ..., BLKn are each also flash memory cells. The memory cell array 20 includes a three-dimensional memory cell array. The three-dimensional memory cell array may include multiple NAND strings, and each of the multiple NAND strings may include multiple memory cells connected to a vertically stacked gate stack GS.

[0016] The peripheral circuit 30 can receive the address ADDR, command CMD, and control signal CTRL from outside the semiconductor device 10, and can send and receive data DATA with a device located outside the semiconductor device 10.

[0017] The row decoder 32 can select at least one of a plurality of memory cell blocks BLK1, BLK2, ..., BLKn in response to an external address ADDR, and can select the gate stack GS, string selection line SSL, and ground selection line GSL of the selected memory cell block. The row decoder 32 can transmit a voltage to the gate stack GS of the selected memory cell block for performing memory operations.

[0018] The page buffer 34 can be connected to the memory cell array 20 via the bit line BL. During program operation, the page buffer 34 acts as a write driver and can apply a voltage to the bit line BL based on the data DATA to be stored in the memory cell array 20. During read operation, it acts as a sensing amplifier and can sense the data DATA stored in the memory cell array 20. The page buffer 34 can be operated by the control signal PCTL provided by the control logic 38.

[0019] The data input / output circuit 36 ​​can be connected to the page buffer 34 via multiple data lines DLs. During program operation, the data input / output circuit 36 ​​can receive data DATA from a memory controller (not shown) and provide program data DATA to the page buffer 34 based on the column address C_ADDR provided by the control logic 38. During read operations, the data input / output circuit 36 ​​can provide read data DATA stored in the page buffer 34 to the memory controller based on the column address C_ADDR provided by the control logic 38.

[0020] The data input / output circuit 36 ​​can transmit the input address or instruction word to the control logic 38 or the row decoder 32. The peripheral circuit 30 may further include an ESD (Electrostatic Discharge) circuit and a pull-up / pull-down driver.

[0021] The control logic 38 can receive command CMD and control signal CTRL from the memory controller. The control logic 38 can provide the row address R_ADDR to the row decoder 32 and the column address C_ADDR to the data input / output circuit 36. In response to the control signal CTRL, the control logic 38 can generate various internal control signals used within the semiconductor device 10. For example, when performing memory operations such as program operation or erase operation, the control logic 38 can adjust the voltage levels provided to the gate stack GS and bit line BL.

[0022] The common source line driver 39 is connectable to the memory cell array 20 via the common source line CSL. Based on the control of the control logic 38, the common source line driver 39 can apply a common source voltage (e.g., power supply voltage) or a ground voltage to the common source line CSL. In an exemplary embodiment, the common source line driver 39 is located below the memory cell array 20. The common source line driver 39 may be positioned to overlap at least a portion of the memory cell array 20 vertically.

[0023] Figure 2 is a schematic perspective view of a semiconductor device 10 according to an embodiment of the technical concept of the present invention.

[0024] Referring to Figure 2, the semiconductor device 10 includes a cell array structure CAS and a peripheral circuit structure PCS that overlap each other in the vertical direction (Z direction). The cell array structure CAS includes a memory cell array 20 as described with reference to Figure 1. The peripheral circuit structure PCS includes a peripheral circuit 30 as described with reference to Figure 1.

[0025] The cell array structure CAS includes multiple tiles 24. Each of the multiple tiles 24 includes multiple memory cell blocks BLK1, BLK2, ..., BLKn. Each of the multiple memory cell blocks BLK1, BLK2, ..., BLKn includes memory cells arranged in three dimensions.

[0026] In exemplary embodiments, two tiles 24 constitute one mat, but are not limited thereto. The memory cell array 20 described with reference to Figure 1 includes, but is not limited to, multiple mats, for example, four mats.

[0027] Figure 3 is an equivalent circuit diagram of a memory cell array MCA of a semiconductor device according to an embodiment of the technical concept of the present invention. Figure 3 shows an equivalent circuit diagram of a vertical NAND flash memory element having a vertical channel structure. The plurality of memory cell blocks BLK1, BLK2, ..., BLKn shown in Figure 2 each include a memory cell array MCA having the circuit configuration shown in Figure 3.

[0028] Referring to Figure 3, the memory cell array MCA includes multiple memory cell strings MS. The memory cell array MCA includes multiple bit lines BL (BL1, BL2, ..., BLm), multiple word lines WL (WL1, WL2, ..., WLn-1, WLn), at least one string selection line SSL, at least one ground selection line GSL, and a common source line CSL. Multiple memory cell strings MS can be formed between the multiple bit lines BL and the common source line CSL. Figure 3 shows a case where each of the multiple memory cell strings MS includes two string selection lines SSL, but the technical concept of the present invention is not limited thereto. For example, each of the multiple memory cell strings MS may include one string selection line SSL.

[0029] Each of the multiple memory cell strings MS includes a string selection transistor SST, a ground selection transistor GST, and multiple memory cell transistors MC1, MC2, ..., MCn-1, MCn. The drain region of the string selection transistor SST is connected to the bit line BL, and the source region of the ground selection transistor GST is connectable to the common source line CSL. The common source line CSL is also the region where the source regions of the multiple ground selection transistors GST are commonly connected.

[0030] The string selection transistor SST can be connected to the string selection line SSL, and the ground selection transistor GST can be connected to the ground selection line GSL. Multiple memory cell transistors MC1, MC2, ..., MCn-1, MCn can each be connected to multiple word lines WL.

[0031] Figure 4 is a plan view showing the main components of a semiconductor device 100 according to an embodiment of the technical concept of the present invention. Figure 5A is a cross-sectional view showing the cross-sectional configuration along lines A1-A1' and A2-A2' in Figure 4, as well as a cross-sectional view of a portion of the peripheral circuit region PERI of the semiconductor device 100. Figure 5B is a cross-sectional view showing the cross-sectional configuration along line B-B' in Figure 4. Figure 5C is an enlarged cross-sectional view of the local region indicated as "EX1" in Figure 5A.

[0032] Referring to Figures 4 and 5A to 5C, the semiconductor device 100 includes a substrate 102 having a memory cell region MEC, a linking region CON, and a peripheral circuit region PERI. The substrate 102 may have a main surface 102M that extends horizontally along the XY plane. The substrate 102 may contain Si, Ge, or SiGe. A memory cell array MCA can be formed on the active region AC of the memory cell region MEC.

[0033] The junction region CON can be positioned adjacent to the edge of the memory cell region MEC. The memory cell region MEC is separated from the peripheral circuit region PERI by the junction region CON. Figure 5A shows only the junction region CON positioned on one side of the memory cell region MEC, but it is also possible to position junction regions CON on both sides of the memory cell region MEC in the first horizontal direction (X direction).

[0034] A gate stack GS is arranged on the memory cell region MEC and the linking region CON of the substrate 102. The gate stack GS includes a plurality of gate lines GL and a plurality of conductive pad regions 112 integrally linked to the plurality of gate lines GL. The portion of the gate stack GS arranged on the memory cell region MEC can constitute a memory stack ST. The memory stack ST includes, but is not limited to, 48, 64, 96, or 128 gate lines GL stacked in the vertical direction (Z direction). The plurality of gate lines GL included in the gate stack GS are arranged on the memory cell region MEC, extend horizontally parallel to the main surface 102M of the substrate 102, and overlap each other in the vertical direction (Z direction). The plurality of gate lines GL include a plurality of word lines WL (WL1, WL2, ..., WLn-1, WLn), at least one ground selection line GSL, and at least one string selection line SSL. Figures 5A and 5B show a case where multiple gate lines GL include two ground selection lines GSL and two string selection lines SSL, but the technical concept of the present invention is not limited thereto.

[0035] Multiple conductive pad regions 112 included in the gate stack GS are arranged on the connecting region CON, forming a stepped connecting section 110. Each of the multiple conductive pad regions 112 can be integrally connected to one gate line GL selected from among multiple gate lines GL.

[0036] As shown in Figures 4 and 5B, multiple word line cut regions (WLCs) extend in a first horizontal direction (X direction) parallel to the main surface 102M of the substrate 102. Multiple word line cut regions (WLCs) can limit the width of the gate stack GS in a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction). Each gate stack GS is spaced apart from each other at a constant interval by multiple word line cut regions (WLCs) and can be arranged repeatedly.

[0037] As shown in Figure 5B, multiple common source regions 106 extend along the first horizontal direction (X direction) on the substrate 102. In an exemplary embodiment, the multiple common source regions 106 are also impurity regions highly doped with n-type impurities. Multiple common source lines CSL extend along the first horizontal direction (X direction) on the multiple common source regions 106. The multiple common source lines CSL can be formed to fill a portion of the word line cut region WLC on one side of each gate stack GS. Within the word line cut region WLC, the common source lines CSL are surrounded by insulating spacers 192. The common source lines CSL and insulating spacers 192 can constitute a word line cut structure WCS that penetrates the memory stack ST.

[0038] Two adjacent string selection lines SSL in the second horizontal direction (Y direction) are separated from each other by a string selection line cut region SSLC. The string selection line cut region SSLC is also filled with an insulating film 174. The insulating film 174 may consist of an oxide film, a nitride film, or a combination thereof. In an exemplary embodiment, at least a portion of the string selection line cut region SSLC is also filled with an air gap.

[0039] Multiple gate lines GL and multiple conductive pad regions 112 may each be composed of a metal, a conductive metal nitride, or a combination thereof. For example, multiple gate lines GL and multiple conductive pad regions 112 may each be composed of, but are not limited to, tungsten, nickel, cobalt, tantalum, tungsten nitride, titanium nitride, tantalum nitride, or a combination thereof.

[0040] As shown in Figures 5A and 5B, insulating films 156 are interposed between the substrate 102 and the ground selection line GSL, between each of the pair of ground selection lines GSL, the multiple word lines WL (WL1, WL2, ..., WLn-1, WLn), and the pair of string selection lines SSL. Of the multiple insulating films 156 on the substrate 102, the insulating film 156 closest to the substrate 102 may have a thinner thickness than the other insulating films 156. The multiple insulating films 156 may be made of silicon oxide, silicon nitride, or SiON.

[0041] On the memory cell region MEC, multiple channel structures 180 penetrate multiple gate lines GL and multiple insulating films 156, extending long in the vertical direction (Z direction). The multiple channel structures 180 can be arranged spaced apart from each other at predetermined intervals along the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0042] Each of the multiple channel structures 180 includes a gate dielectric film 182, a channel region 184, a buried insulating film 186, and a drain region 188. The channel region 184 includes doped polysilicon and / or undoped polysilicon. The channel region 184 may have a cylindrical shape. The internal space of the channel region 184 is also filled with the buried insulating film 186. The buried insulating film 186 may be made of an insulating material. For example, the buried insulating film 186 may be made of silicon oxide, silicon nitride, SiON, or a combination thereof. In exemplary embodiments, the buried insulating film 186 is optional, in which case the channel region 184 may have a pillar structure without internal space. The drain region 188 may be made of impurity-doped polysilicon, a metal, a conductive metal nitride, or a combination thereof. Examples of metals that can constitute the drain region 188 include tungsten, nickel, cobalt, and tantalum.

[0043] Multiple drain regions 188 are insulated from each other by an intermediate insulating film 187. Each of the intermediate insulating films 187 may be composed of an oxide film, a nitride film, or a combination thereof.

[0044] Figures 5A and 5B show a case where the channel structure 180 includes a gate dielectric film 182, and the gate dielectric film 182 has a shape that extends long in the vertical direction (Z direction) along the channel region 184. However, the technical concept of the present invention is not limited thereto, and various modifications and changes are possible.

[0045] Figure 6A is a cross-sectional view that provides a more detailed explanation of the gate dielectric film 182 shown in Figures 5A and 5B, and is an enlarged view of the region indicated as "BX" in Figure 5B.

[0046] Referring to Figure 6A, the gate dielectric film 182 can have a structure that includes a tunneling dielectric film TD, a charge-storage film CS, and a blocking dielectric film BD, which are formed sequentially from the channel region 184. The relative thicknesses of the tunneling dielectric film TD, the charge-storage film CS, and the blocking dielectric film BD are not limited to those shown in Figure 6A, but can be varied in many ways.

[0047] The tunneling dielectric film TD may contain silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, etc. The charge-conserving film CS is a region where electrons that have passed from the channel region 184 through the tunneling dielectric film TD can be conserved, and may contain silicon nitride, boron nitride, silicon-boron nitride, or polysilicon doped with impurities. The blocking dielectric film BD may consist of silicon oxide, silicon nitride, or a metal oxide with an even higher dielectric constant than silicon oxide. The metal oxide may consist of hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination thereof.

[0048] Figures 6B to 6D are cross-sectional views showing exemplary structures of gate dielectric films 182A, 182B, and 182C that can be used instead of the gate dielectric film 182 shown in Figure 6A.

[0049] In an exemplary embodiment, the semiconductor device 100 may include a gate dielectric film 182A, shown in Figure 6B, instead of the gate dielectric film 182. The gate dielectric film 182A has substantially the same configuration as the gate dielectric film 182 shown in Figure 6A, except that the gate dielectric film 182A includes a first blocking dielectric film BD1 and a second blocking dielectric film BD2 instead of the blocking dielectric film BD. The first blocking dielectric film BD1 extends alongside the channel region 184, and the second blocking dielectric film BD2 is positioned to surround the gate line GL. The first blocking dielectric film BD1 and the second blocking dielectric film BD2 may each be composed of a silicon oxide, silicon nitride, or metal oxide. For example, the first blocking dielectric film BD1 may be composed of a silicon oxide film, and the second blocking dielectric film BD2 may be composed of a metal oxide film with a dielectric constant even higher than that of a silicon oxide film.

[0050] In another exemplary embodiment, the semiconductor device 100 may include a gate dielectric film 182B, as shown in Figure 6C, instead of the gate dielectric film 182. The gate dielectric film 182B can be formed to cover the surface of the gate line GL facing the channel region 184 and the surface facing the insulating film 156. The gate dielectric film 182B may include a tunneling dielectric film TD, a charge-conserving film CS, and a blocking dielectric film BD, which are formed sequentially from the channel region 184.

[0051] In yet another exemplary embodiment, the semiconductor device 100 may include a gate dielectric film 182C, as shown in Figure 6D, instead of the gate dielectric film 182. The gate dielectric film 182C is interposed between the gate line GL and the channel region 184, covering the sidewalls of the gate line GL but not the bottom and top surfaces of the gate line GL. The gate dielectric film 182C may also include a tunneling dielectric film TD, a charge-conserving film CS, and a blocking dielectric film BD, which are formed sequentially from the channel region 184.

[0052] The configuration and shape of the gate dielectric film included in the semiconductor device according to the embodiment of the technical concept of the present invention are not limited to the gate dielectric films 182, 182A, 182B, and 182C shown in Figures 6A to 6D, and various modifications and changes are possible within the scope of the technical concept of the present invention.

[0053] Referring again to Figures 4 and 5A to 5C, on the connecting region CON, the multiple conductive pad regions 112 that constitute the stepped connecting portion 110 can each have a width that gradually narrows as they move away from the substrate 102 in the horizontal direction.

[0054] In an exemplary embodiment, multiple dummy channel structures (not shown) can be arranged on the connecting region CON, penetrating the stepped connecting portion 110. These multiple dummy channel structures support the edges of each gate stack GS and the multiple conductive pad regions 112, preventing unwanted structural deformations such as bending or breaking of these portions.

[0055] In the memory cell region (MEC), multiple bit lines BL can be arranged on top of the memory stack ST. Multiple bit line contact pads 194 are interposed between multiple channel structures 180 and multiple bit lines BL. The drain region 188 of each of the multiple channel structures 180 can be connected to a corresponding bit line BL from among the multiple bit lines BL via the bit line contact pads 194. The multiple bit line contact pads 194 are insulated from each other by an upper insulating film 193. The multiple bit lines BL are insulated from each other by an interlayer insulating film 195. The multiple bit line contact pads 194 and the multiple bit lines BL may each be made of a metal, a metal nitride, or a combination thereof. For example, the multiple bit line contact pads 194 and the multiple bit lines BL may each be made of tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof. The upper insulating film 193 and the interlayer insulating film 195 may each be made of an oxide film, a nitride film, or a combination thereof.

[0056] On the connecting region CON, an insulating film 114 covering the stepped connecting portion 110 is placed between the substrate 102 and the intermediate insulating film 187. The insulating film 114 can cover multiple conductive pad regions 112. The insulating film 114, the intermediate insulating film 187, and the upper insulating film 193 can constitute an insulating structure INS.

[0057] On the connecting region CON, multiple contact structures CTS, which are elongated in the vertical direction (Z direction), can be arranged on multiple conductive pad regions 112 of the stepped connecting portion 110. Multiple metal silicide films 118 are interposed in the multiple connecting portions between the multiple contact structures CTS and the multiple conductive pad regions 112.

[0058] Each of the multiple contact structures CTS includes a contact plug 116 that extends vertically (Z-direction) and an insulating plug 115 surrounding the contact plug 116. Each contact plug 116 of the multiple contact structures CTS can be connected to the conductive pad area 112 of the stepped connection section 110 via multiple metal silicide films 118.

[0059] As shown in detail in Figure 5C, the metal silicide film 118 and the contact structure CTS extend into the interior of the conductive pad region 112 to a vertical level even lower than the vertical level of the upper surface of the conductive pad region 112, with the lowest surface of the metal silicide film 118 separated from the bottom surface of the conductive pad region 112. The term “vertical level” as used herein refers to the distance along the vertical direction (Z-direction or -Z-direction) from the upper surface of the substrate 102. The vertical level of the uppermost surface of the metal silicide film 118 is approximately the same as the vertical level of the upper surface of the conductive pad region 112. The metal silicide film 118 can surround the lower end of the contact structure CTS at a vertical level that is the same as, or even lower than, the vertical level of the upper surface of the conductive pad region 112. The metal silicide film 118 can contact the contact plug 116 of the contact structure CTS at a vertical level even lower than the vertical level of the upper surface of the conductive pad region 112. The insulating plug 115 may include a portion interposed between the lower end of the contact plug 116 and the metal silicide film 118.

[0060] As shown in Figure 5A, each of the multiple contact structures CTS extends from the metal silicide film 118 that is in contact with each of the multiple conductive pad regions 112, through the insulating structure INS which is composed of an insulating film 114, an intermediate insulating film 187, and an upper insulating film 193, and extends in the direction away from the substrate 102 to a first vertical level LV1 which is higher than the memory stack ST. Of the multiple conductive pad regions 112, the contact structure CTS connected to the conductive pad region 112 furthest from the substrate 102 extends from the conductive pad region 112, through the insulating film 156, the intermediate insulating film 187, and the upper insulating film 193, and extends to the first vertical level LV1.

[0061] On the connection region CON, multiple wiring layers ML can be arranged on multiple contact structures CTS. Multiple wiring layers ML can be formed at the same level as multiple bit lines BL arranged on the memory cell region MEC. Each of the multiple wiring layers ML can be connected to a contact plug 116 of the contact structure CTS at a first vertical level LV1. Each of the multiple wiring layers ML is configured to be electrically connected to one conductive pad region 112 selected from multiple conductive pad regions 112 via one contact plug 116 selected from multiple contact plugs 116. Multiple wiring layers ML may not include portions that overlap vertically with the memory stack ST. On the connection region CON, multiple wiring layers ML are insulated from each other by an interlayer insulating film 195.

[0062] Multiple contact plugs 116 and multiple wiring layers ML may each be composed of tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof. Multiple insulating plugs 115 may be composed of silicon nitride film, silicon oxide film, or a combination thereof.

[0063] In some embodiments, the first metal contained in the multiple metal silicide films 118 and the second metal contained in the multiple contact plugs 116 are the same metal. In other embodiments, the first metal contained in the multiple metal silicide films 118 and the second metal contained in the multiple contact plugs 116 are different metals.

[0064] In exemplary embodiments, the metal silicide film 118 may further contain at least one element selected from nitrogen (N) and oxygen (O). For example, the metal silicide film 118 may consist of WSi, WSiN, WSiO, or a combination thereof. As used herein, the terms “WSi,” “WSiN,” and “WSiO” refer to materials composed of the elements contained in each term, and are not chemical formulas representing stoichiometric relationships.

[0065] Multiple circuit CTs can be formed on the peripheral circuit region (PERI). These multiple circuit CTs can be formed at the same vertical level as the substrate 102, or at a higher vertical level. Each of the multiple circuit CTs includes at least some of the row decoder 32, page buffer 34, data input / output circuit 36, control logic 38, and common source line driver 39 included in the peripheral circuit 30 described with reference to Figure 1.

[0066] An element isolation film 103 defining a peripheral active region PAC can be formed in the peripheral circuit region PERI of the substrate 102. A peripheral transistor TR can be formed on the peripheral active region PAC. The peripheral transistor TR can constitute a portion of a plurality of circuit CTs formed on the peripheral circuit region PERI. The peripheral transistor TR is configured to be electrically connectable to the memory cell region MEC via a wiring structure located in the connection region CON. The peripheral transistor TR includes a peripheral gate PG and peripheral source / drain regions PSD formed within the peripheral active region PAC on both sides of the peripheral gate PG. In an exemplary embodiment, unit elements such as resistors and capacitors may be further arranged on the peripheral circuit region PERI.

[0067] Multiple peripheral contact structures PTS can be placed on the peripheral circuit region PERI. These multiple peripheral contact structures PTS extend vertically (Y direction) from the peripheral transistor TR through the insulating film 114 to the first vertical level LV1.

[0068] Each peripheral contact structure PTS includes a peripheral contact plug P116 that extends vertically (Z-direction) and a peripheral insulating plug P115 that surrounds the peripheral contact plug P116.

[0069] Multiple peripheral wiring layers PML can be arranged on multiple peripheral contact plugs P116. The multiple peripheral wiring layers PML extend horizontally at a first vertical level LV1, which is the same level as the multiple wiring layers ML formed in the connecting region CON. Each of the multiple peripheral wiring layers PML can be connected to either the peripheral gate PG or the peripheral source / drain region PSD via any one of the multiple peripheral contact plugs P116. At least some of the multiple peripheral wiring layers PML can be configured to connect to other circuits or wiring located on the peripheral circuit region PERI. The multiple peripheral wiring layers PML are insulated from each other by an interlayer insulating film 195.

[0070] Multiple peripheral contact plugs P116 and multiple peripheral wiring layers PML may be composed of tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof. Multiple peripheral insulating plugs P115 may be composed of silicon nitride film, silicon oxide film, or a combination thereof.

[0071] Figures 7A to 7C are cross-sectional views illustrating modified examples of semiconductor devices according to other embodiments based on the technical concept of the present invention. Figures 7A to 7C show enlarged cross-sectional views of the portion corresponding to the local area indicated as "EX1" in Figure 5A. In Figures 7A to 7C, the same reference numerals as in Figures 4 and 5A to 5C represent the same components, and a detailed explanation of them is omitted here.

[0072] Referring to Figure 7A, the semiconductor device 200A has substantially the same configuration as the semiconductor device 100 described with reference to Figures 4 and 5A to 5C. However, the semiconductor device 200A includes a contact structure CTSA that extends vertically (Z direction) over the conductive pad region 112, and a metal silicide film 118A formed at the connection portion between the contact structure CTSA and the conductive pad region 112.

[0073] The contact structure CTSA includes a contact plug 116A that extends vertically (Z-direction) and an insulating plug 115A surrounding the contact plug 116A. The contact plug 116A can be connected to a conductive pad region 112 via a metal silicide film 118A.

[0074] The contact structure CTSA extends into the interior of the conductive pad region 112 to a vertical level even lower than the vertical level of the upper surface of the conductive pad region 112, and the metal silicide film 118A is separated from the upper and lower surfaces of the conductive pad region 112. Therefore, the lowest surface of the metal silicide film 118A is located separated from the lower surface of the conductive pad region 112. The vertical level of the uppermost surface of the metal silicide film 118A is even lower than the vertical level of the upper surface of the conductive pad region 112, and the vertical level of the lowest surface of the metal silicide film 118A is even higher than the vertical level of the lower surface of the conductive pad region 112. The metal silicide film 118A can contact the lower surface of the contact plug 116A at a vertical level even lower than the vertical level of the upper surface of the conductive pad region 112.

[0075] In the horizontal direction (e.g., the X direction), the width W2 of the metal silicide film 118A is even narrower than the width W1 of the contact structure CTSA. In the vertical direction (Z direction), the height of the metal silicide film 118A is even lower than the height of the conductive pad area 112.

[0076] Referring to Figure 7B, the semiconductor device 200B has substantially the same configuration as the semiconductor device 100 described with reference to Figures 4 and 5A to 5C. However, the semiconductor device 200B includes a contact structure CTSB that extends vertically (Z-direction) over the conductive pad region 112, and a metal silicide film 118B formed at the connection between the contact structure CTSB and the conductive pad region 112.

[0077] The contact structure CTSB includes a contact plug 116B that extends vertically (Z-direction) and an insulating plug 115B surrounding the contact plug 116B. The contact plug 116B can be connected to a conductive pad region 112 via a metal silicide film 118B.

[0078] The contact structure CTSB and the metal silicide film 118B extend into the interior of the conductive pad region 112 to a vertical level even lower than the vertical level of the upper surface of the conductive pad region 112. The vertical distance DR2 from the upper surface of the conductive pad region 112 to the lowest surface of the contact structure CTSB is even shorter than the vertical (Z-direction) thickness of the conductive pad region 112. The metal silicide film 118B can contact the upper and bottom surfaces of the conductive pad region 112. The vertical level of the uppermost surface of the metal silicide film 118B is approximately the same as or similar to the vertical level of the upper surface of the conductive pad region 112, and the vertical level of the lowest surface of the metal silicide film 118B is approximately the same as or similar to the vertical level of the bottom surface of the conductive pad region 112. Therefore, in the vertical direction (Z-direction), the height of the metal silicide film 118B is approximately the same as or similar to the height of the conductive pad region 112. The metal silicide film 118B can come into contact with the upper and lower surfaces of the conductive pad region 112.

[0079] The metal silicide film 118B can contact the bottom surface of the contact plug 116B at a vertical level even lower than the vertical level of the upper surface of the conductive pad area 112. The insulating plug 115B may include a portion interposed between the lower end of the contact plug 116B and the metal silicide film 118B.

[0080] Referring to Figure 7C, the semiconductor device 200C has substantially the same configuration as the semiconductor device 100 described with reference to Figures 4 and 5A to 5C. However, the semiconductor device 200C includes a contact structure CTSC that extends vertically (Z-direction) over the conductive pad region 112, and a metal silicide film 118C formed at the connection portion between the contact structure CTSC and the conductive pad region 112.

[0081] The contact structure CTSC includes a contact plug 116C that extends vertically (Z-direction) and an insulating plug 115C surrounding the contact plug 116C. The contact plug 116C can be connected to a conductive pad region 112 via a metal silicide film 118C.

[0082] The metal silicide film 118C extends into the conductive pad region 112 to a vertical level even lower than the vertical level of the upper surface of the conductive pad region 112. The contact structure CTSC is separated from the conductive pad region 112 in the vertical direction (Z direction). The vertical level LV21 of the upper surface of the conductive pad region 112 is even lower than the vertical level LV22 of the bottom surface of the contact plug 116C that constitutes the contact structure CTSC.

[0083] In the vertical direction (Z direction), the lowest surface of the metal silicide film 118C is at a lower level than the uppermost surface of the conductive pad region 112, and the uppermost surface of the metal silicide film 118C is at a higher level than the uppermost surface of the conductive pad region 112. The vertical level of the lowest surface of the metal silicide film 118C is higher than the vertical level of the bottom surface of the conductive pad region 112. The metal silicide film 118C can contact the bottom surface of the contact plug 116C at a vertical level higher than the vertical level of the upper surface of the conductive pad region 112. The metal silicide film 118C can contact the upper surface of the conductive pad region 112.

[0084] Figure 8A is a cross-sectional view illustrating a modified semiconductor device according to yet another embodiment based on the technical concept of the present invention, Figure 8B(A) is an enlarged cross-sectional view of the local area indicated as "EX31" in Figure 8A, and Figure 8B(B) is an enlarged cross-sectional view of the local area indicated as "EX32" in Figure 8A. In Figures 8A and 8B, the same reference numerals as in Figures 4 and 5A to 5C represent the same components, and a detailed explanation of them is omitted here.

[0085] Referring to Figures 8A and 8B, the semiconductor device 300 has substantially the same configuration as the semiconductor device 100 described with reference to Figures 4 and 5A to 5C. However, in the semiconductor device 300, a metal silicide film 118 is not interposed between at least one conductive pad region 112, including the uppermost conductive pad region 112 furthest from the substrate 102, and at least one contact structure CTS configured to be connected to the at least one conductive pad region 112.

[0086] Of the multiple conductive pad regions 112, the metal silicide film 118 may not be placed on at least one conductive pad region 112, including the uppermost conductive pad region 112 furthest from the substrate 102. The at least one conductive pad region 112, including the uppermost conductive pad region 112, can directly contact a contact structure CTS, among the multiple contact structures CTS, that is configured to be connected to the at least one conductive pad region 112.

[0087] In the semiconductor device 300, among the multiple conductive pad regions 112, the conductive pad region 112 facing the contact structure CTS across the metal silicide film 118 is located at an even lower vertical level than the uppermost conductive pad region 112. Therefore, the vertical distance (i.e., the distance in the Z direction) from the conductive pad region 112 facing the contact structure CTS across the metal silicide film 118 to the substrate 102 is even shorter than the vertical distance from the uppermost conductive pad region 112 to the substrate 102.

[0088] Figure 9 is a cross-sectional view illustrating a semiconductor device according to yet another embodiment based on the technical concept of the present invention. In Figure 9, the same reference numerals as in Figures 4 and 5A to 5C represent the same components, and a detailed description of them is omitted here.

[0089] Referring to Figure 9, the semiconductor device 400 includes a memory cell array MCA4 formed on the active region AC of the memory cell region MEC. The memory cell array MCA4 includes a lower memory stack STA and an upper memory stack STB arranged on the substrate 102 so as to overlap vertically (in the Z direction). The upper memory stack STB is separated from the substrate 102, with the lower memory stack STA in between.

[0090] A lower gate stack GSA is arranged on the memory cell region MEC and the connecting region CON of the substrate 102. The lower gate stack GSA includes a plurality of lower gate lines GL1 and a plurality of conductive pad regions 112 integrally connected to the plurality of lower gate lines GL1. Of the lower gate stack GSA, the portion arranged on the memory cell region MEC can constitute a lower memory stack STA. The plurality of conductive pad regions 112 are arranged on the connecting region CON to constitute a stepped lower connecting portion 110.

[0091] An upper gate stack GSB is arranged on the lower gate stack GSA. The upper gate stack GSB includes a plurality of upper gate lines GL2 and a plurality of conductive pad areas 122 integrally connected to the plurality of upper gate lines GL2. The portion of the upper gate stack GSB arranged on the memory cell area MEC can constitute an upper memory stack STB. The plurality of conductive pad areas 122 are arranged on the connecting area CON to constitute a stepped upper connecting section 120.

[0092] The lower memory stack STA includes 48, 64, or 96 lower gate lines GL1 stacked so as to overlap each other in the vertical direction (Z direction), and the upper memory stack STB includes 48, 64, or 96 upper gate lines GL2 stacked so as to overlap each other in the vertical direction (Z direction), but is not limited to the examples given above. In the exemplary embodiment, the sum of the number of lower gate lines GL1 and the number of upper gate lines GL2 is at least 128.

[0093] Multiple lower gate lines GL1 and multiple upper gate lines GL2 include multiple word lines WL (WL1, WL2, ..., WLn-1, WLn), at least one grounding selection line GSL, and at least one string selection line SSL. Figure 9 shows a case where multiple lower gate lines GL1 and multiple upper gate lines GL2 include two grounding selection lines GSL and two string selection lines SSL, but the technical concept of the present invention is not limited thereto. More detailed configurations of multiple lower gate lines GL1 and multiple upper gate lines GL2 are as described for gate lines GL with reference to Figures 5A and 5B.

[0094] Insulating films 156A and 156B are interposed between the substrate 102 and the ground selection line GSL, between the pair of ground selection lines GSL, the plurality of word lines WL (WL1, WL2, ..., WLn-1, WLn), and between the pair of string selection lines SSL. The plurality of insulating films 156A and 156B on the substrate 102 include a plurality of insulating films 156A constituting the lower memory stack STA and a plurality of insulating films 156B constituting the upper memory stack STB. Of the plurality of insulating films 156A constituting the lower memory stack STA, the insulating film 156A closest to the substrate 102 may have a thinner thickness than the other insulating films 156A. Of the plurality of insulating films 156B constituting the upper memory stack STB, the insulating film 156B furthest from the substrate 102 may cover the upper surface of the string selection line SSL furthest from the substrate 102. The plurality of insulating films 156A and 156B may be made of silicon oxide, silicon nitride, or SiON.

[0095] An interlayer insulating film 130 and a separation insulating film 140 are interposed between the lower memory stack STA and the upper memory stack STB. The interlayer insulating film 130 and the separation insulating film 140 may each be composed of a silicon oxide film.

[0096] On the memory cell region MEC, multiple channel structures 180A and 180B extend vertically (Z direction) through multiple lower gate lines GL1, multiple insulating films 156A, interlayer insulating film 130, isolation insulating film 140, multiple upper gate lines GL2, and multiple insulating films 156B. The multiple channel structures 180A and 180B can be arranged along the X and Y directions, spaced apart from each other at predetermined intervals.

[0097] The multiple channel structures 180A and 180B each include a lower channel structure 180A that penetrates multiple lower gate lines GL1 and an upper channel structure 180B that penetrates multiple upper gate lines GL2. The lower channel structure 180A and the upper channel structure 180B each include a gate dielectric film 182, a channel region 184, an embedded insulating film 186, and a drain region 188, respectively.

[0098] Multiple drain regions 188 constituting multiple lower channel structures 180A are insulated from each other by a lower intermediate insulating film 187A, and multiple drain regions 188 constituting multiple upper channel structures 180B are insulated from each other by an upper intermediate insulating film 187B. The lower intermediate insulating film 187A and the upper intermediate insulating film 187B may each be composed of an oxide film, a nitride film, or a combination thereof. The bottom surface of the upper channel structure 180B can be in contact with the top surface of the lower channel structure 180A. In the horizontal direction, the width of the bottom surface of the upper channel structure 180B is even narrower than the width of the top surface of the lower channel structure 180A. More detailed configurations of the multiple lower channel structures 180A and the multiple upper channel structures 180B are as described for the multiple channel structures 180 with reference to Figures 4, 5A, and 5B.

[0099] On the connecting region CON, the multiple conductive pad regions 112 constituting the stepped lower connecting portion 110 and the multiple conductive pad regions 122 constituting the stepped upper connecting portion 120 can each have a width that gradually narrows as they move away from the substrate 102 in the horizontal direction.

[0100] In an exemplary embodiment, a plurality of dummy channel structures (not shown) can be arranged on the connecting region CON, penetrating the stepped lower connecting portion 110 and the stepped upper connecting portion 120. The plurality of dummy channel structures support the edges of the plurality of lower gate lines GL1 and the plurality of upper gate lines GL2, as well as the plurality of conductive pad regions 112 and the plurality of conductive pad regions 122, and serve to prevent problems such as unwanted structural deformation occurring, such as bending or breaking of these portions.

[0101] In the memory cell region (MEC), multiple bit lines BL can be arranged on top of the upper memory stack (STB). Multiple bit line contact pads 194 are interposed between the multiple upper channel structures 180B and the multiple bit lines BL. The drain region 188 of each of the multiple upper channel structures 180B can be connected to a corresponding bit line BL from among the multiple bit lines BL via the bit line contact pads 194. On the connection region CON, an insulating film 114 covering the stepped lower connection portion 110 can be arranged between the substrate 102 and the lower intermediate insulating film 187A. The insulating film 114 can cover multiple conductive pad regions 112 and insulating film 156A.

[0102] On the connecting region CON, an upper insulating film 124 covering the stepped upper connecting portion 120 can be placed between the separating insulating film 140 and the upper intermediate insulating film 187B. The upper insulating film 124 can cover multiple conductive pad regions 122 and insulating film 156B.

[0103] On the connecting region CON, multiple conductive pad regions 112 constituting the stepped lower connecting portion 110 and multiple conductive pad regions 122 constituting the stepped upper connecting portion 120 can be arranged, and multiple contact structures CTS that are elongated in the vertical direction (Z direction) can be arranged on these regions. Metal silicide films 118 are interposed between the multiple contact structures CTS and the multiple conductive pad regions 112, and between the multiple contact structures CTS and the multiple conductive pad regions 122. Each of the multiple contact structures CTS includes a contact plug 116 that is elongated in the vertical direction (Z direction) and an insulating plug 115 surrounding the contact plug 116. Each contact plug 116 of the multiple contact structures CTS can be connected to the multiple conductive pad regions 112, 122 via the multiple metal silicide films 118. More detailed configurations and various modifications of the interconnections between the multiple conductive pad regions 112, 122, the multiple metal silicide films 118, and the multiple contact structures CTS are described with reference to Figures 5A to 5C and 7A to 7C, regarding the interconnections between the metal silicide films 118, 118A, 118B, 118C, the conductive pad regions 112, and the contact structures CTS, CTSA, CTSB, CTSC.

[0104] In other exemplary embodiments, as described with reference to Figures 8A and 8B, in the semiconductor device 400, the metal silicide film 118 may not be present at the connection between at least one conductive pad region, including the uppermost conductive pad region 122 furthest from the substrate 102, and at least one contact structure CTS configured to connect to the at least one conductive pad region.

[0105] Of the multiple contact structures CTS, those configured to connect to multiple conductive pad regions 112 of the stepped lower connecting portion 110 each extend from the conductive pad region 112, penetrating the insulating film 114 and the lower intermediate insulating film 187A, to a first vertical level LV41 that is higher than the lower memory stack STA and lower than the upper memory stack STB, in a direction away from the substrate 102. Of the multiple conductive pad regions 112, the contact structure CTS configured to connect to the conductive pad region 112 furthest from the substrate 102 extends from the conductive pad region 112, penetrating the insulating film 156A and the lower intermediate insulating film 187A, to the first vertical level LV41.

[0106] Multiple lower wiring layers MA can be formed on multiple lower contact plugs 116. Multiple lower wiring layers MA are connected to multiple contact structures CTS and extend horizontally along the first vertical level LV41. Multiple lower wiring layers MA are configured to be electrically connectable to at least one of multiple lower gate lines GL1 selected from among multiple lower gate lines GL1 via the multiple contact structures CTS. On the connection region CON, multiple lower wiring layers MA are insulated from each other by an interlayer insulating film 130.

[0107] Of the multiple contact structures CTS, those configured to connect to multiple conductive pad regions 122 of the stepped upper connecting portion 120 extend from the conductive pad region 122, through the upper insulating film 124, the upper intermediate insulating film 187B, and the insulating film 193, in a direction away from the substrate 102, up to a second vertical level LV42 which is higher than the upper memory stack STB. Of the multiple conductive pad regions 122, the contact structure CTS configured to connect to the conductive pad region 122 furthest from the substrate 102 extends from the conductive pad region 122, through the insulating film 156B, the upper intermediate insulating film 187B, and the insulating film 193, up to the second vertical level LV42. The second vertical level LV42 is also a level higher than the uppermost surface level of the multiple upper channel structures 180B that penetrate the upper memory stack STB.

[0108] Multiple upper wiring layers MB can be formed on multiple contact structures CTS configured to connect to multiple conductive pad regions 122. The multiple upper wiring layers MB are connected to the multiple contact structures CTS and extend horizontally along the second vertical level LV42. The multiple upper wiring layers MB are configured to be electrically connectable to at least one upper gate line GL2 selected from a plurality of upper gate lines GL2 via the multiple contact structures CTS and the metal silicide film 118. The multiple upper wiring layers MB located on the connection region CON can be formed at the same level as the multiple bit lines BL located on the memory cell region MEC. On the connection region CON, the multiple upper wiring layers MB are insulated from each other by an upper interlayer insulating film 195.

[0109] In another exemplary embodiment, unlike in Figure 9, among the multiple contact structures CTS, the multiple contact structures CTS configured to connect to the multiple conductive pad regions 112 of the stepped lower connecting portion 110 each extend from the conductive pad region 112, through the insulating film 114, the lower intermediate insulating film 187A, the interlayer insulating film 130, the isolation insulating film 140, the upper insulating film 124, the upper intermediate insulating film 187B, and the insulating film 193, in a direction away from the substrate 102 to the second vertical level LV42. In this case, the multiple upper wiring layers MB are configured to be electrically connectable to at least one of the multiple lower gate lines GL1 selected via the multiple contact structures CTS and the metal silicide film 118, and the multiple lower wiring layers MA are optional.

[0110] Multiple contact structures CTS, multiple lower wiring layers MA, and multiple upper wiring layers MB may each be composed of tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof.

[0111] Multiple circuit CTs 4 can be formed on the peripheral circuit region PERI. These multiple circuit CTs 4 can be formed at the same level as the substrate 102, or at an even higher level. A more detailed configuration of the multiple circuit CTs 4 is described with reference to Figure 5A.

[0112] Multiple lower peripheral contact structures PTS1 can be arranged on the peripheral circuit region PERI. The multiple lower peripheral contact structures PTS1 extend vertically (Z direction) from the peripheral transistor TR through the insulating film 114 to the first vertical level LV41. Each of the multiple lower peripheral contact structures PTS1 includes a peripheral contact plug P116 that extends vertically (Z direction) and a peripheral insulating plug P115 that surrounds the peripheral contact plug P116.

[0113] Multiple lower peripheral wiring layers (PMAs) can be arranged on multiple lower peripheral contact structures (PTS1), connected to the multiple lower peripheral contact structures (PTS1). The multiple lower peripheral wiring layers (PMAs) extend horizontally along the first vertical level (LV41). Each of the multiple lower peripheral wiring layers (PMAs) can be connected to either a peripheral gate (PG) or a peripheral source / drain region (PSD) via any one of the multiple lower peripheral contact structures (PTS1). At least some of the multiple lower peripheral wiring layers (PMAs) can be configured to connect to other circuits or wiring located on the peripheral circuit region (PERI). The multiple lower peripheral wiring layers (PMAs) are insulated from each other by an interlayer insulating film (130).

[0114] Multiple upper peripheral contact structures PTS2 can be arranged on multiple lower peripheral wiring layers PMA, connected to the multiple lower peripheral wiring layers PMA. The multiple upper peripheral contact structures PTS2 extend from the multiple lower peripheral wiring layers PMA, through the isolation insulating film 140 and the upper insulating film 124, to the second vertical level LV42. Each of the multiple upper peripheral contact structures PTS2 includes a peripheral contact plug P116 that extends long in the vertical direction (Z direction) and a peripheral insulating plug P115 that surrounds the peripheral contact plug P116.

[0115] Multiple upper peripheral contact structures PTS2 can be arranged on the multiple upper peripheral wiring layers PMBs that are connected to the multiple upper peripheral contact structures PTS2. The multiple upper peripheral wiring layers PMBs are extended horizontally at a second vertical level LV42, which is at the same level as the multiple upper wiring layers MB formed on the connecting region CON. Each of the multiple upper peripheral wiring layers PMBs can be configured to be connected to other circuits or wiring located on the peripheral circuit region PERI. The multiple upper peripheral wiring layers PMBs are insulated from each other by an interlayer insulating film 195.

[0116] Multiple lower peripheral wiring layers (PMA) and multiple upper peripheral wiring layers (PMB) may each be composed of tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof.

[0117] Figure 10 is a cross-sectional view illustrating a semiconductor device according to yet another embodiment of the technical concept of the present invention.

[0118] Referring to Figure 10, the semiconductor device 500A has substantially the same configuration as the semiconductor device 100 described with reference to Figures 4 and 5A to 5C. However, the semiconductor device 500A includes a peripheral circuit region PERI5 formed at a level lower than the level of the substrate 102.

[0119] The memory cell region MEC and the junction region CON can be arranged so as to overlap perpendicularly with the peripheral circuit region PERI5. On the junction region CON, multiple contact structures CTS, which are elongated in the vertical direction (Z direction), can be arranged on multiple conductive pad regions 112 of the stepped junction portion 110. Multiple metal silicide films 118 are interposed in the multiple connecting portions between the multiple contact structures CTS and the multiple conductive pad regions 112.

[0120] The peripheral circuit region PERI5 includes a peripheral circuit board 502 located below the substrate 102, and a plurality of circuit CTs 5 located between the peripheral circuit board 502 and the substrate 102. A more detailed configuration of the peripheral circuit board 502 and the circuit CTs 5 is as described for the substrate 102 and the plurality of circuit CTs with reference to Figures 5A and 5B.

[0121] A peripheral circuit active region PAC5 is defined on the peripheral circuit substrate 502 by an element isolation film 504. Multiple transistors TR5 can be formed on the peripheral circuit active region PAC5. Each of the multiple transistors TR5 includes a peripheral gate PG5 and a peripheral source / drain region PSD5 formed within the peripheral active region PAC5 on both sides of the peripheral gate PG5. In an exemplary embodiment, unit elements such as resistors and capacitors may be further arranged on the peripheral circuit region PERI5. A peripheral interlayer insulating film 510 can be formed on the multiple transistors TR5. The peripheral interlayer insulating film 510 may include silicon oxide, SiON, SiOCN, and the like.

[0122] The peripheral circuit region PERI5 includes a plurality of peripheral circuit wiring layers 508 and a plurality of peripheral circuit contacts 509. Some of the plurality of peripheral circuit wiring layers 508 are configured to be electrically connectable to a plurality of transistors TR5. The plurality of peripheral circuit contacts 509 can be configured to connect a selected subset of the plurality of peripheral circuit wiring layers 508 to each other. The plurality of peripheral circuit wiring layers 508 and the plurality of peripheral circuit contacts 509 are covered by a peripheral interlayer insulating film 510. Some of the plurality of peripheral circuit wiring layers 508 can face the memory stack ST across the substrate 102.

[0123] The multiple peripheral circuit wiring layers 508 and the multiple peripheral circuit contacts 509 may each be composed of a metal, a conductive metal nitride, a metal silicide, or a combination thereof. For example, the multiple peripheral circuit wiring layers 508 and the multiple peripheral circuit contacts 509 may each contain conductive materials such as tungsten, molybdenum, titanium, cobalt, tantalum, nickel, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide, and nickel silicide. Figure 10 shows that the multiple peripheral circuit wiring layers 508 have a three-layer wiring structure along the vertical direction (Z direction), but the technical concept of the present invention is not limited to what is shown in Figure 10. For example, the multiple peripheral circuit wiring layers 508 may also have a multilayer wiring structure of two or four or more layers.

[0124] In the semiconductor device 500A, through-holes 102H can be formed in the substrate 102. The through-holes 102H are filled with a substrate-embedded insulating film 512. The substrate-embedded insulating film 512 may be made of a silicon oxide film.

[0125] In the semiconductor device 500A, the wiring structure located on the connecting region CON can be configured to be electrically connected to a plurality of peripheral circuit wiring layers 508 located in the peripheral circuit region PERI 5 via a peripheral contact structure PTS 5 that extends vertically (Z direction). The peripheral contact structure PTS 5 includes a peripheral contact plug P116 that extends long vertically (Z direction) and a peripheral insulating plug P115 that surrounds the peripheral contact plug P116. At least a portion of the plurality of wiring layers ML located on the connecting region CON and the peripheral wiring layer PML can be configured to be electrically connected to a plurality of peripheral circuit wiring layers 508 located in the peripheral circuit region PERI 5 via the peripheral contact structure PTS 5.

[0126] The peripheral contact structure PTS5 extends vertically (in the Z direction) from one of the multiple peripheral circuit wiring layers 508, through the peripheral interlayer insulating film 510 and the substrate embedded insulating film 512, to the peripheral wiring layer PML. The peripheral contact structure PTS5 penetrates the substrate 102 through the through-hole 102H and is surrounded by the substrate embedded insulating film 512 within the through-hole 102H.

[0127] Figure 11 is a cross-sectional view illustrating a semiconductor device according to yet another embodiment based on the technical concept of the present invention. In Figure 11, the same reference numerals as in Figures 5A, 5B and 10 represent the same components, and a detailed description of them is omitted here.

[0128] Referring to Figure 11, the semiconductor device 500B has substantially the same configuration as the semiconductor device 500A described with reference to Figure 10. However, the semiconductor device 500B further includes a metal silicide film P118 formed at the connection portion between the peripheral contact structure PTS5 and the peripheral circuit wiring layer 508 to which the peripheral contact structure PTS5 is connected. The peripheral contact structure PTS5 can be connected to the peripheral circuit wiring layer 508 via the metal silicide film P118. The metal silicide film P118 has substantially the same configuration as the metal silicide film 118 described with reference to Figures 5A to 5C.

[0129] In some embodiments, the metal contained in the metal silicide film P118 and the metal contained in the peripheral contact structure PTS5 are the same metal. In other embodiments, the metal contained in the metal silicide film P118 and the metal contained in the peripheral contact structure PTS5 are different metals.

[0130] More detailed configurations and various modifications of the interconnection portions between the metal silicide film P118, the peripheral circuit wiring layer 508 in contact with the metal silicide film P118, and the peripheral contact structure PTS5 are described with reference to Figures 5A to 5C and 7A to 7C, regarding the interconnection portions between the metal silicide films 118, 118A, 118B, and 118C, the conductive pad region 112, and the contact structures CTS, CTSA, CTSB, and CTSC.

[0131] Figure 12 is a cross-sectional view illustrating a semiconductor device according to yet another embodiment based on the technical concept of the present invention. In Figure 12, the same reference numerals as in Figures 5A, 5B and 10 represent the same components, and a detailed description of them is omitted here.

[0132] Referring to Figure 12, the semiconductor device 600 can have a C2C (chip-to-chip) structure. The C2C structure means that an upper chip including a cell region (CELL) is fabricated on a first wafer, a lower chip including a peripheral circuit region (PERI) is fabricated on a second wafer different from the first wafer, and then the upper chip and the lower chip are connected to each other by a bonding method. For example, the bonding method means a method of electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip including the cell region (CELL) and a bonding metal formed on the uppermost metal layer of the lower chip including the peripheral circuit region (PERI). In an exemplary embodiment, if the bonding metal is made of copper (Cu), the bonding method is also a Cu-Cu bonding method. In other exemplary embodiments, the bonding metal may be made of aluminum or tungsten.

[0133] In the semiconductor device 600, the peripheral circuit area PERI and the cell area CELL each include a pad bonding area PA. The cell area CELL may further include a linking area CON and a memory cell area MEC.

[0134] The peripheral circuit region (PERI) includes a first substrate 610, an interlayer insulating film 615, a plurality of circuit elements 620a, 620b, 620c formed on the first substrate 610, first metal layers 630a, 630b, 630c connected to each of the plurality of circuit elements 620a, 620b, 620c, and second metal layers 640a, 640b, 640c formed on the first metal layers 630a, 630b, 630c. In an exemplary embodiment, the first metal layers 630a, 630b, 630c are made of tungsten, and the second metal layers 640a, 640b, 640c are made of copper.

[0135] In other exemplary embodiments, at least one additional metal layer may be formed on the second metal layers 640a, 640b, and 640c. At least a portion of the at least one metal layer formed on top of the second metal layers 640a, 640b, and 640c may be made of aluminum.

[0136] The interlayer insulating film 615 can cover a plurality of circuit elements 620a, 620b, 620c, the first metal layers 630a, 630b, 630c, and the second metal layers 640a, 640b, 640c. The interlayer insulating film 615 may be composed of silicon oxide, silicon nitride, or a combination thereof.

[0137] In the peripheral circuit region PERI, in the region that overlaps with the connecting region CON in the vertical direction (Z direction), the lower bonding metals 671b and 672b can be placed on the second metal layer 640b. On the connecting region CON, the lower bonding metals 671b and 672b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 371b and 372b of the cell region CELL by bonding. The lower bonding metals 671b and 672b and the upper bonding metals 371b and 372b may be made of aluminum, copper, or tungsten.

[0138] The cell region CELL includes a second substrate 310 and a common source line 320. A gate stack GS can be arranged on the second substrate 310, which includes a plurality of gate lines GL and a plurality of conductive pad regions 112 connected to the plurality of gate lines GL. The detailed configuration of structures on the connecting region CON and the memory cell region MEC in the cell region CELL is described with reference to Figures 5A to 5C.

[0139] In the memory cell region (MEC), the channel structure 180 is connectable to the upper bonding metals 371c and 372c via the bit line contact pads 194 and bit line BL. The bit line BL is electrically connectable to circuit elements included in the peripheral circuit region (PERI), such as the circuit element 620c providing the page buffer 393, via the upper bonding metals 371c and 372c. The upper bonding metals 371c and 372c are connectable to the lower bonding metals 671c and 672c connected to the circuit element 620c of the page buffer 393.

[0140] In the connecting region CON, each of the multiple conductive pad regions 112 extends along a direction parallel to the upper surface of the second substrate 310 and can be connected to the contact structure CTS via the metal silicide film 118. In each of the multiple contact structure CTS, the other end opposite to the end connected to the metal silicide film 118 can be connected to the upper bonding metals 371b and 372b. The multiple contact structures CTS can be connected to the peripheral circuit region PERI via the upper bonding metals 371b and 372b of the cell region CELL and the lower bonding metals 671b and 672b of the peripheral circuit region PERI.

[0141] Multiple contact structures CTS are each electrically connectable to a circuit element 620b providing a row decoder 394 in the peripheral circuit region PERI. In an exemplary embodiment, the operating voltage of the circuit element 620b providing the row decoder 394 may differ from the operating voltage of the circuit element 620c providing the page buffer 393. For example, the operating voltage of the circuit element 620c providing the page buffer 393 may be higher than the operating voltage of the circuit element 620b providing the row decoder 394.

[0142] Multiple common source line contact plugs 380 can be arranged in the pad bonding region PA. Each of the multiple common source line contact plugs 380 can be electrically connected to a common source line 320. Each of the multiple common source line contact plugs 380 may be made of metal, a metal compound, polysilicon, or a combination thereof. A metal layer 350a can be connected to the other end of each common source line contact plug 380 opposite to the end connected to the common source line 320. The metal layer 350a can be connected to upper metal patterns 371a and 372a. The upper metal patterns 371a and 372a can be connected to the corresponding lower metal patterns 671a, 672a, and 673a of the peripheral circuit region PERI, respectively.

[0143] Multiple input / output pads 305, 605 can be arranged in the pad bonding region PA. A lower insulating film 601 can be formed on the lower part of the first substrate 610, covering the bottom surface of the first substrate 610, and the first input / output pads 605 can be formed on the lower insulating film 601. The first input / output pads 605 can be connected to at least one of multiple circuit elements 620a, 620b, 620c arranged in the peripheral circuit region PERI via a first input / output contact plug 603 that penetrates the lower insulating film 201 and the first substrate 610. An insulating film 612 is placed between the first input / output contact plug 603 and the first substrate 610, allowing the first input / output contact plug 603 and the first substrate 610 to be electrically isolated.

[0144] An upper insulating film 301 can be formed on the upper part of the second substrate 310, covering the upper surface of the second substrate 310. A second input / output pad 305 can be placed on the upper insulating film 301. The second input / output pad 305 can be connected to at least one of the multiple circuit elements 620a, 620b, and 620c located in the peripheral circuit region PERI via a second input / output contact plug 303.

[0145] The second input / output contact plug 303 can be positioned at a location separated from the second substrate 310 and the common source line 320. The second input / output pad 305 may not overlap with multiple conductive pad regions 112 in the vertical direction (Z direction). The second input / output contact plug 303 can penetrate the interlayer insulating film 315 and the upper insulating film 301 and be connected to the second input / output pad 305.

[0146] In an exemplary embodiment, either the first input / output pad 605 or the second input / output pad 305 can be omitted.

[0147] In the pad bonding region PA, the upper metal patterns 371a and 372a formed on the uppermost metal layer of the cell region CELL can be connected to the corresponding lower metal patterns 671a, 672a, and 673a formed on the uppermost metal layer of the peripheral circuit region PERI. The lower metal pattern 673a formed on the uppermost metal layer of the peripheral circuit region PERI may not be connected to any other contacts in the peripheral circuit region PERI. Similarly, in the pad bonding region PA, an upper metal pattern identical in form to the lower metal pattern of the peripheral circuit region PERI can be formed on the upper metal layer of the cell region CELL, corresponding to the lower metal pattern formed on the uppermost metal layer of the peripheral circuit region PERI.

[0148] Lower bonding metals 671b and 672b can be formed on the second metal layer 640b of the connecting region CON. The lower bonding metals 671b and 672b can be electrically connected to the upper bonding metals 371b and 372b of the cell region CELL by bonding.

[0149] In the memory cell region (MEC), the upper metal pattern 392 can be placed on the uppermost metal layer of the cell region (CELL) corresponding to the lower bonding metals 651 and 652 formed on the uppermost metal layer of the peripheral circuit region (PERI).

[0150] Referring to Figures 4 to 12, semiconductor devices 100, 200A, 200B, 200C, 300, 400, 500A, 500B, and 600 demonstrate that in a semiconductor device equipped with three-dimensionally arranged memory cells, even if the number of stacked word lines increases to improve integration density, and the number of contacts and wirings connected to the word lines increases, the contact resistance between the conductive pad region and the contact plug can be reduced by forming a metal silicide film at the connection portion between the conductive pad region and the contact plug connected to the conductive pad region. Therefore, excellent electrical characteristics can be maintained in the semiconductor device, and the reliability of the semiconductor device can be improved.

[0151] Figure 13 is a schematic diagram showing an electronic system including a semiconductor device according to an exemplary embodiment of the present invention.

[0152] Referring to Figure 13, an exemplary embodiment of the present invention, the electronic system 1000, includes a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 is a storage device including one or more semiconductor devices 1100, or an electronic device including a storage device. For example, the electronic system 1000 is an SSD (solid state drive device) including at least one semiconductor device 1100, or a USB (Universal) It is a Serial Bus, computing system, medical device, or communication device.

[0153] The semiconductor device 1100 is also a non-volatile memory device. For example, the semiconductor device 1100 is also a NAND flash memory device that includes at least one of the structures described above for semiconductor devices 100, 200A, 200B, 200C, 300, 400, 500A, 500B, and 600, with reference to Figures 4 to 12. The semiconductor device 1100 includes a first structure 1100F and a second structure 1100S on the first structure 1100F. In an exemplary embodiment, the first structure 1100F may also be located next to the second structure 1100S. The first structure 1100F is also a peripheral circuit structure that includes a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S is also a memory cell structure that includes a bit line BL, a common source line CSL, a plurality of word lines WL, first and second gate upper lines UL1, UL2, first and second gate lower lines LL1, LL2, and a plurality of memory cell strings CSTR located between the bit line BL and the common source line CSL.

[0154] In the second structure 1100S, each of the multiple memory cell strings CSTR includes lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and multiple memory cell transistors MCT arranged between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 can be varied in various ways depending on the embodiment.

[0155] In exemplary embodiments, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. Multiple gate lower lines LL1 and LL2 are also gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL is also a gate electrode of the memory cell transistor MCT, and the gate upper lines UL1 and UL2 are also gate electrodes of the upper transistors UT1 and UT2.

[0156] The common source line CSL, multiple gate lower lines LL1, LL2, multiple word lines WL, and multiple gate upper lines UL1, UL2 can be electrically connected to the decoder circuit 1110 via multiple first connecting wires 1115 that extend from the first structure 1100F to the second structure 1100S. The multiple bit lines BL can be electrically connected to the page buffer 1120 via multiple second connecting wires 1125 that extend from the first structure 1100F to the second structure 1100S.

[0157] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one of the multiple memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 are controllable by the logic circuit 1130.

[0158] The semiconductor device 1100 can communicate with the controller 1200 via input / output pads 1101 that are electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via input / output connecting wiring 1135 that extends from the first structure 1100F to the second structure 1100S.

[0159] The controller 1200 includes a processor 1210, a NAND controller 1220, and a host interface 1230. Depending on the embodiment, the electronic system 1000 may also include a plurality of semiconductor devices 1100, in which case the controller 1200 can control the plurality of semiconductor devices 1100.

[0160] The processor 1210 can control the overall operation of the electronic system 1000, including the controller 1200. The processor 1210 can operate by predetermined firmware and can control the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 includes a NAND interface 1221 that handles communication with the semiconductor device 1100. Through the NAND interface 1221, control commands for controlling the semiconductor device 1100, data to be written to the multiple memory cell transistors (MCTs) of the semiconductor device 1100, and data to be read from the multiple memory cell transistors (MCTs) of the semiconductor device 1100 are transmitted. The host interface 1230 can provide communication functionality between the electronic system 1000 and an external host. Upon receiving control commands from an external host through the host interface 1230, the processor 1210 can control the semiconductor device 1100 in response to the control commands.

[0161] Figure 14 is a schematic perspective view showing an electronic system including a semiconductor device according to an exemplary embodiment of the present invention.

[0162] Referring to Figure 14, an exemplary embodiment of the present invention, an electronic system 2000, includes a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 are interconnected with the controller 2002 by a plurality of wiring patterns 2005 formed on the main board 2001.

[0163] The main board 2001 includes a connector 2006 which includes a plurality of pins that connect to an external host. In the connector 2006, the number and arrangement of the plurality of pins may vary depending on the communication interface between the electronic system 2000 and the external host. In an exemplary embodiment, the electronic system 2000 is USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced The system can communicate with an external host via one of the following interfaces: Technology Attachment, M-Phy for UFS (Universal Flash Storage), etc. In an exemplary embodiment, the electronic system 2000 can be powered by a power supply from the external host through connector 2006. The electronic system 2000 uses a PMIC (Power Microcontroller) to distribute the power supplied from the external host to controller 2002 and semiconductor package 2003. It may further include a Management Integrated Circuit.

[0164] The controller 2002 can write data to or read data from the semiconductor package 2003, thereby improving the operating speed of the electronic system 2000.

[0165] DRAM 2004 also serves as a buffer memory to mitigate the speed difference between the semiconductor package 2003, which is the data storage space, and the external host. DRAM included in electronic system 2000 2004 can also function as a type of cache memory, providing space for temporarily storing data during control operations on the semiconductor package 2003. If the electronic system 2000 includes the DRAM 2004, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004, in addition to the NAND controller for controlling the semiconductor package 2003.

[0166] The semiconductor package 2003 includes first and second semiconductor packages 2003a and 2003b, which are spaced apart from each other. The first and second semiconductor packages 2003a and 2003b are also semiconductor packages that each include a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b includes a package substrate 2100, a plurality of semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each of the plurality of semiconductor chips 2200, a connecting structure 2400 that electrically connects the plurality of semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 that covers the plurality of semiconductor chips 2200 and the connecting structure 2400 on the package substrate 2100.

[0167] The package substrate 2100 is also a printed circuit board including a plurality of package top pads 2130. Each of the plurality of semiconductor chips 2200 includes an input / output pad 2210. The input / output pad 2210 corresponds to the input / output pad 1101 in Figure 13. Each of the plurality of semiconductor chips 2200 includes a plurality of gate stacks 3210 and a plurality of channel structures 3220. Each of the plurality of semiconductor chips 2200 includes at least one of the semiconductor devices 100, 200A, 200B, 200C, 300, 400, 500A, 500B, and 600, referring to Figures 4 to 12.

[0168] In exemplary embodiments, the connecting structure 2400 is also a bonding wire that electrically connects the input / output pads 2210 and the package top pads 2130. Thus, in the first and second semiconductor packages 2003a and 2003b, the multiple semiconductor chips 2200 can be electrically connected to each other by a bonding wire method and can be electrically connected to the package top pads 2130 of the package substrate 2100. In embodiments, in the first and second semiconductor packages 2003a and 2003b, the multiple semiconductor chips 2200 can also be electrically connected to each other by a connecting structure including through silicon vias (TSVs) instead of the bonding wire connecting structure 2400.

[0169] In an exemplary embodiment, the controller 2002 and the multiple semiconductor chips 2200 may be contained in a single package. In an exemplary embodiment, the controller 2002 and the multiple semiconductor chips 2200 may be mounted on a separate interposer substrate distinct from the main substrate 2001, and the controller 2002 and the multiple semiconductor chips 2200 may be connected to each other by wiring formed on the interposer substrate.

[0170] Figure 15 is a schematic cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present invention. Figure 15 shows in more detail the configuration along the cross-section of line II-II' in Figure 14.

[0171] Referring to Figure 15, in the semiconductor package 2003, the package substrate 2100 is also a printed circuit board. The package substrate 2100 includes a package substrate body (main body) portion 2120, a plurality of package upper pads 2130 (Figure 14) located on the upper surface of the package substrate body portion 2120, a plurality of lower pads 2125 located on the lower surface of the package substrate body portion 2120 or exposed through the lower surface, and a plurality of internal wirings 2135 that electrically connect the plurality of upper pads 2130 and the plurality of lower pads 2125 inside the package substrate body portion 2120. The plurality of upper pads 2130 can be electrically connected to a plurality of connecting structures 2400. The plurality of lower pads 2125 can be connected to a plurality of wiring patterns 2005 on the main substrate 2001 of the electronic system 2000 shown in Figure 14 via a plurality of conductive connecting portions 2800.

[0172] Each of the multiple semiconductor chips 2200 includes a semiconductor substrate 3010, and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 includes a peripheral circuit region including a plurality of peripheral wirings 3110. The second structure 3200 includes a common source line 3205, a gate stack 3210 on the common source line 3205, a channel structure 3220 penetrating the gate stack 3210, a bit line 3240 electrically connected to the channel structure 3220, and the gate stack 3210. The gate stack 3210 includes a plurality of word lines WL (Figure 13) and a plurality of conductive pad regions 112 integrally connected to the plurality of word lines. Furthermore, each of the multiple semiconductor chips 2200 includes multiple contact structures CTS electrically connected to multiple conductive pad regions 112 of the gate stack 3210, and multiple metal silicide films 118 interposed between the multiple conductive pad regions 112 and the multiple contact structures CTS. Each of the multiple conductive pad regions 112 can be connected to the contact structures CTS via the metal silicide films 118. More detailed configurations and various modifications of the interconnections between the multiple conductive pad regions 112, the multiple metal silicide films 118, and the multiple contact structures CTS are described in Figures 5A to 5C and 7A to 7C, relating to the interconnections between the metal silicide films 118, 118A, 118B, 118C, the conductive pad regions 112, and the contact structures CTS, CTSA, CTSB, CTSC.

[0173] Each of the multiple semiconductor chips 2200 includes through-wiring 3245 that is electrically connected to a plurality of peripheral wirings 3110 of the first structure 3100 and extends into the second structure 3200. The through-wiring 3245 is located outside the gate stack 3210. In other exemplary embodiments, the semiconductor package 2003 may further include through-wiring that penetrates the gate stack 3210. Each of the multiple semiconductor chips 2200 may further include input / output pads 2210 (Figure 14) that are electrically connected to a plurality of peripheral wirings 3110 of the first structure 3100.

[0174] Figure 16 is a schematic cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present invention. Figure 16 shows the configuration of the portion corresponding to the cross-section along line II-II' in Figure 14.

[0175] Referring to Figure 16, the semiconductor package 2003A has substantially the same configuration as the semiconductor package 2003 described with reference to Figure 15. However, the semiconductor package 2003A includes a plurality of semiconductor chips 2200A. Each of the plurality of semiconductor chips 2200A includes a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 bonded to the first structure 4100 by a wafer bonding method.

[0176] The first structure 4100 includes a peripheral circuit region including peripheral wiring 4110 and a plurality of first junction structures 4150. The second structure 4200 includes a common source line 4205, a gate stack 4210 between the common source line 4205 and the first structure 4100, and a channel structure 4220 penetrating the gate stack 4210. The gate stack 4210 includes a plurality of word lines WL (Figure 13) and a plurality of conductive pad regions 112 integrally connected to the plurality of word lines. Each of the plurality of semiconductor chips 2200A includes a plurality of contact structures CTS electrically connected to the plurality of conductive pad regions 112 of the gate stack 3210, and a plurality of metal silicide films 118 interposed between the plurality of conductive pad regions 112 and the plurality of contact structures CTS. Each of the plurality of conductive pad regions 112 can be connected to the contact structures CTS via the metal silicide films 118. More detailed configurations and various modifications of the interconnections between the multiple conductive pad regions 112, the multiple metal silicide films 118, and the multiple contact structures CTS are described with reference to Figures 5A to 5C and 7A to 7C, regarding the interconnections between the metal silicide films 118, 118A, 118B, 118C, the conductive pad regions 112, and the contact structures CTS, CTSA, CTSB, CTSC.

[0177] Furthermore, each of the multiple semiconductor chips 2200A includes multiple second junction structures 4250 which are electrically connected to multiple word lines WL (Figure 13) of the gate stack 4210. For example, the multiple second junction structures 4250 can be electrically connected to the channel structure 4220 and the word lines WL (Figure 1) via bit lines 4240 which are electrically connected to the channel structure 4220, and contact structures CTS which are electrically connected to the word lines WL (Figure 13).

[0178] Multiple first connecting structures 4150 of the first structure 4100 and multiple second connecting structures 4250 of the second structure 4200 can be joined together while in contact with each other. The joined portions of the multiple first connecting structures 4150 and the multiple second connecting structures 4250 can be formed of, for example, copper (Cu).

[0179] The multiple semiconductor chips 2200 shown in Figure 15 and the multiple semiconductor chips 2200A shown in Figure 16 can be electrically connected to each other by a plurality of connecting structures 2400 in the form of bonding wires (Figure 14). In another exemplary embodiment, the multiple semiconductor chips 2200 shown in Figure 15 and the multiple semiconductor chips 2200A shown in Figure 16 can also be electrically connected to each other by connecting structures including through-swivels (TSVs).

[0180] Figures 17A to 17E are cross-sectional views showing the process sequence to illustrate a method for manufacturing a semiconductor device according to an embodiment of the technical concept of the present invention. In this example, the method for manufacturing the semiconductor device 100 shown in Figures 4 and 5A to 5C will be explained as an example.

[0181] Referring to Figure 17A, an active region AC is defined in the memory cell region MEC of the substrate 102, and a peripheral active region PAC is defined in the peripheral circuit region PERI. The peripheral active region PAC is defined by the element isolation film 103.

[0182] Multiple insulating films 156 and multiple sacrificial films PL are alternately stacked one layer at a time on the memory cell region MEC and the connecting region CON of the substrate 102, and peripheral transistors TR are formed in the peripheral circuit region PERI. The multiple sacrificial films PL may be composed of silicon nitride, silicon carbide, or polysilicon. Each of the multiple sacrificial films PL serves to secure space for forming the gate stack GS (Figure 17C) in a subsequent process.

[0183] Referring to Figure 17B, after removing a portion of each of the multiple insulating films 156 and multiple sacrificial films PL so that the multiple insulating films 156 and multiple sacrificial films PL form a stepped structure STP, an insulating film 114 covering the stepped structure STP and the surrounding transistor TR is formed on the substrate 102.

[0184] Subsequently, in the memory cell region MEC, multiple lower channel holes 180H are formed that penetrate multiple insulating films 156 and multiple sacrificial films PL and extend in the vertical direction (Z direction). Inside each of the multiple lower channel holes 180H, a gate dielectric film 182, a channel region 184, and a burying insulating film 186 are formed, thereby forming multiple lower channel hole burying structures.

[0185] Next, an intermediate insulating film 187 is formed in the memory cell region MEC, the junction region CON, and the peripheral circuit region PERI, covering the plurality of lower channel hole embedding structures, the stepped structure STP, and the insulating film 114. A plurality of contact holes 187H are formed in the intermediate insulating film 187 to expose the upper surfaces of the plurality of lower channel hole embedding structures, and a plurality of drain regions 188 are formed within the plurality of contact holes 187H to form the channel structure 180. The intermediate insulating film 187 can be formed to have a flattened upper surface that extends across the memory cell region MEC, the junction region CON, and the peripheral circuit region PERI.

[0186] Referring to Figure 17C, after forming multiple word line cut regions (WLCs) (Figures 4 and 5B) that penetrate multiple insulating films 156 and multiple sacrificial films PL (Figure 17B) and expose the substrate 102, impurity ions are implanted into the substrate 102 through the multiple word line cut regions WLC to form multiple common source regions 106 (Figure 5B), and the multiple sacrificial films PL (Figure 17B) are replaced with multiple gate lines GL and multiple conductive pad regions 112. On the connecting region CON, the multiple conductive pad regions 112 can constitute a stepped connecting portion 110.

[0187] In an exemplary embodiment, in order to replace multiple sacrificial films PL (Figure 17B) with multiple lower word lines WLA, multiple sacrificial films PL (Figure 17B) exposed through multiple word line cut regions WLC can be selectively removed, creating gaps between each of the multiple insulating films 156, and then conductive material can be embedded in the gaps to form multiple gate lines GL and multiple conductive pad regions 112.

[0188] Subsequently, as shown in Figure 5B, insulating spacers 192 and common source lines CSLs can be formed inside each of the multiple word line cut regions (WLCs) to form a word line cut structure (WCS). The insulating spacers 192 may be made of silicon oxide, silicon nitride, SiON, SiOCN, SiCN, or a combination thereof. The common source line CSL may be made of a metal such as tungsten, copper, or aluminum; a conductive metal nitride such as titanium nitride or tantalum nitride; a transition metal such as titanium or tantalum; or a combination thereof. In some embodiments, a metal silicide film (not shown) may be interposed between the common source region 106 and the common source line CSL to reduce contact resistance. The metal silicide film is made of, but is not limited to, cobalt silicide. In some embodiments, if a common source line (not shown) is embedded in the substrate 102, the multiple word line cut regions (WLCs) can be filled with insulating material alone, and the common source line CSL formation step can be omitted.

[0189] Referring to Figure 17D, after forming the upper insulating film 193 on the result of Figure 17C, multiple bit line contact pads 194 are formed in the memory cell region MEC, penetrating the upper insulating film 193 and connected to multiple channel structures 180. The insulating film 114, the intermediate insulating film 187, and the upper insulating film 193 can constitute an insulating structure INS.

[0190] Using a mask pattern (not shown) as an etching mask, the insulating structure INS is anisotropically etched on the connecting region CON and the peripheral circuit region PERI, forming multiple first contact holes H11 on the connecting region CON that expose multiple conductive pad regions 112, and multiple second contact holes H12 on the peripheral circuit region PERI that expose the peripheral gate PG and the peripheral source / drain region PSD. The multiple first contact holes H11 and the multiple second contact holes H12 can be formed simultaneously.

[0191] Referring to Figure 17E, a metal silicide film 118 is formed on the surface of the conductive pad area 112 exposed through each of the multiple first contact holes H11 on the connecting region CON, and a contact structure CTS is formed on the metal silicide film 118 inside each of the multiple first contact holes H11. Furthermore, on the peripheral circuit region PERI, peripheral insulating plugs P115 and peripheral contact plugs P116 are sequentially formed within the multiple second lower contact holes H12 to form a peripheral contact structure PTS.

[0192] Figures 18A to 18E are cross-sectional views showing the process sequence in order to explain in more detail the process of forming a metal silicide film 118 on the surface of the conductive pad region 112 on the connecting region CON, and forming a contact structure CTS on the metal silicide film 118, according to the process in Figure 17E. Figures 18A to 18E show enlarged cross-sectional configurations of the region corresponding to the local region indicated as "EX2" in Figure 17D, according to the process sequence.

[0193] Referring to FIG. 18A, as described with reference to FIG. 17D, a plurality of first contact holes H11 are formed. To form the plurality of first contact holes H11, a hard mask HM can be used as an etching mask. The hard mask HM may be composed of a material capable of providing an etching selectivity ratio during the etching of the insulating structure INS. For example, the hard mask HM may be composed of a silicon nitride film, a polysilicon film, a spin-on hard mask (SOH), or a combination thereof, but is not limited thereto. on hardmask: SOH) or a combination thereof, but is not limited thereto.

[0194] Thereafter, the resultant product with the first contact holes H11 formed is pretreated in an atmosphere TRT containing O2 or oxygen plasma, and a metal-containing film 117 is formed on the surface of the conductive pad region 112 exposed through the first contact holes H11.

[0195] For example, when the conductive pad region 112 includes a tungsten film, before forming the first contact holes H11, the conductive pad region 112 is in a state where tungsten-containing gases such as WF6-based or WCl6-based gases are outgassing from the tungsten film constituting the conductive pad region 112. In such a state, after forming the plurality of first contact holes H11 that expose the plurality of conductive pad regions 112 as described with reference to FIG. 17D, when pretreating in an atmosphere TRT containing O2 or oxygen plasma, a metal-containing film 117 composed of tungsten oxide (WOx, 0 < x ≦ 3) can be formed on the surface of the conductive pad region 112 exposed through the first contact holes H11.

[0196] Referring to FIG. 18B, after washing the resultant product of FIG. 18A by a strip process, an insulating liner 115L that conformally covers the inner surface of the first contact holes H11 is formed.

[0197] In exemplary embodiments, the insulating liner 115L may be composed of a silicon nitride film, a silicon oxide film, or a combination thereof. Monochlorosilane (SiH3Cl), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), silicon tetrachloride (SiCl4), hexachlorodisilane (Si2Cl6), or a combination thereof may be used as the silicon (Si) precursor to form the insulating liner 115L, but are not limited thereto. When the insulating liner 115L is composed of a silicon nitride film, NH3 gas may be used as the nitriding gas to form the insulating liner 115L, but are not limited thereto. When the insulating liner 115L is composed of a silicon oxide film, O2, O3, O2 plasma, H2O, etc., may be used as the oxidizing gas, but are not limited thereto.

[0198] While forming the insulating liner 115L on the result of Figure 18A, a metal silicide film 118 can be formed from the metal-containing film 117 shown in Figure 18A. For example, while forming the insulating liner 115L on the result of Figure 18A, the tungsten oxide constituting the metal-containing film 117 shown in Figure 18A and the tungsten-containing gas such as WF6 or WCl6 that remains in the conductive pad region 112 due to out-gushing react with the Si precursor used when forming the insulating liner 115L, and a metal silicide film 118 composed of a tungsten silicide film can be formed.

[0199] In exemplary embodiments, the metal silicide film 118 may contain at least one element selected from nitrogen (N) and oxygen (O). For example, the metal silicide film 118 may consist of WSi, WSiN, WSiO, or a combination thereof. As used herein, the terms “WSi,” “WSiN,” and “WSiO” refer to materials composed of the elements contained in each term, and are not chemical formulas representing stoichiometric relationships.

[0200] In forming the metal silicide film 118, the metal silicide film 118 can be formed to have the configuration shown in Figure 5C, the configurations of metal silicide films 118A, 118B, and 118C shown in Figures 7A to 7C, and various configurations modified and changed therefrom, depending on the thickness, volume, and / or area of ​​the conductive pad region 112, the process temperature and process pressure when forming the insulating liner 115L, the type of Si precursor and nitride gas used when forming the insulating liner 115L, and the depth to which the first contact hole H11 extends into the interior of the conductive pad region 112.

[0201] Referring to Figure 18C, the insulating liner 115L is etched back so that the metal silicide film 118 is exposed through the first contact hole H11 in the result shown in Figure 18B. As a result, the insulating plug 115 remains inside the first contact hole H11. The metal silicide film 118 is exposed through the insulating plug 115 inside the first contact hole H11.

[0202] Referring to Figure 18D, in the result shown in Figure 18C, a conductive layer 116L is formed covering the upper surface of the hard mask HM while filling the first contact hole H11. The conductive layer 116L may be composed of tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof.

[0203] Referring to Figure 18E, the result of Figure 18D is flattened so that the upper surface of the insulating structure INS is exposed, and a contact plug 116 is formed in the first contact hole H11. The contact plug 116 is composed of the portion of the conductive layer 116L that remains inside the first contact hole H11.

[0204] Referring again to Figure 17E, after forming an interlayer insulating film 195 covering the result of Figure 17E on the memory cell region MEC, the linking region CON, and the peripheral circuit region PERI, a plurality of bit lines BL, a plurality of wiring layers ML, and a plurality of peripheral wiring layers PML are formed penetrating a portion of the interlayer insulating film 195, thereby manufacturing the semiconductor device 100 described with reference to Figures 4 and 5A to 5C.

[0205] A method for manufacturing the semiconductor device 100 has been described with reference to Figures 17A to 17E and Figures 18A to 18E, and also with reference to Figures 4 and 5A to 5C. However, within the scope of the technical concept of the present invention, it will be understood by those skilled in the art that, by making various modifications and changes from what has been described above, it is possible to manufacture semiconductor devices 200A, 200B, 200C, 300, 400, 500A, 500B, and 600, as well as semiconductor devices having various structures obtained by making various modifications and changes from therewith within the scope of the technical concept of the present invention, with reference to Figures 7A to 12.

[0206] Although the present invention has been described in detail above with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications and changes can be made by persons with ordinary skill in the art within the technical spirit and scope of the present invention. [Industrial applicability]

[0207] The present invention is applicable, for example, to the field of semiconductor equipment. [Explanation of Symbols]

[0208] 100 Semiconductor Equipment 102 circuit boards 102M main surface 103 Element Separation Membrane 110 Staircase connection 112 Conductive pad area 114 Insulating Film 115 Insulated plug 116 Contact Plug 118 Metal silicide film 156 Insulating film 180 Channel Structures 182 Gate Dielectric Film 184 channel area 186 Embedded insulating film 187 Intermediate insulating film 188 Drain area 193 Upper insulating film 194-bit line contact pad 195 Interlayer insulating film AC active area BL Bitline CON concatenation area CT circuit CTS Contact Structure GL Gate Line GS Gate Stack GSL Grounding Selection Line INS Insulating Structure LV1 First Vertical Level MCA Memory Cell Array MEC memory cell area ML wiring layer P115 Peripheral Insulation Plug P116 Peripheral Contact Plug PAC peripheral active region PERI Peripheral Circuit Region PG surrounding gates PML peripheral wiring layer PSD Peripheral Source / Drain Area PTS surrounding contact structures ST Memory Stack SSL String Selection Line TR Peripheral Transistors WL1, WL2, WLn-1, WLn word line

Claims

1. A substrate including a memory cell region and a linking region, Multiple gate lines made of a first metal are arranged vertically and overlap each other on the memory cell region of the substrate, A stepped connecting portion is arranged on the connecting region, integrally connected to the plurality of gate lines, and includes a plurality of conductive pad regions made of the first metal, Multiple contact structures made of a second metal are configured to be connected to the multiple conductive pad regions at a position that overlaps vertically with the aforementioned stepped connecting portion, A semiconductor device comprising a metal silicide film formed by silicide application only to the plurality of conductive pad regions, wherein the metal silicide film is located at each of the connecting portions of a plurality of connecting portions between the plurality of conductive pad regions and the plurality of contact structures, characterized in that the uppermost surface of the metal silicide film is below the upper surface of the corresponding conductive pad region, and the bottom surface of the metal silicide film is above the lower surface of the corresponding conductive pad region.

2. The first metal is tungsten (W), The semiconductor device according to claim 1, characterized in that the metal silicide film is composed of WSi, WSiN, WSiO, or a combination thereof.

3. A substrate including a memory cell region and a linking region, A gate stack comprising: a first gate line extending horizontally parallel to the main surface of the substrate on the memory cell region of the substrate; a first conductive pad region integrally connected to the first gate line, extending horizontally on the connecting region, and made of a first metal; a second gate line overlapping vertically with the first gate line; and a second conductive pad region integrally connected to the second gate line, extending horizontally on the connecting region, made of the first metal, and having a length shorter than the horizontal length of the first conductive pad region; First and second contact structures, which are made of a second metal and extend vertically over the first conductive pad region and the second conductive pad region, respectively, A first metal silicide film formed by silicide application only to the first conductive pad region, wherein the first metal silicide film is interposed between the first conductive pad region and the first contact structure and is in contact with the first conductive pad region and the first contact structure, A second metal silicide film formed by silicide application only to the second conductive pad region, comprising a second metal silicide film interposed between the second conductive pad region and the second contact structure, and in contact with the second conductive pad region and the second contact structure, A semiconductor device characterized in that the uppermost surface of each of the first and second metal silicide films is below the upper surface of the corresponding conductive pad region, and the bottom surface of each of the first and second metal silicide films is above the lower surface of the corresponding conductive pad region.

4. The semiconductor device according to claim 3, characterized in that the first metal and the second metal are the same metal.

5. The semiconductor device according to claim 3, characterized in that the first metal and the second metal are different metals.

6. The semiconductor device according to any one of claims 3 to 5, characterized in that the first and second metal silicide films contain at least one element selected from nitrogen (N) and oxygen (O).

7. The semiconductor device according to any one of claims 3 to 6, characterized in that the vertical distance from the first conductive pad region to the substrate is even shorter than the vertical distance from the uppermost conductive pad region among the plurality of conductive pad regions to the substrate.

8. A peripheral circuit region, which includes a peripheral circuit wiring layer made of a third metal, is located across the aforementioned substrate from the gate stack, A peripheral contact structure made of a fourth metal extends vertically through the substrate to the peripheral circuit wiring layer, The semiconductor device according to any one of claims 3 to 7, further comprising a peripheral metal silicide film interposed between the peripheral circuit wiring layer and the peripheral contact structure, and in contact with the peripheral circuit wiring layer and the peripheral contact structure.

Images