Semiconductor equipment

Abstract

To provide a semiconductor device capable of recording the amount of voltage change (dV / dt) over time when the voltage changes suddenly.SOLUTION: A semiconductor device includes: a main element that has a first semiconductor region, a first electrode, a second electrode, a first gate electrode, and a first insulating member located between the first gate electrode and the first semiconductor region, and in which a gate voltage of the first gate electrode controls a current flowing between the first electrode and the second electrode via the first semiconductor region; and a recording element electrically connected to the first electrode and recording a maximum value of a change amount dV / dt in voltage of the first electrode over time as analog data.SELECTED DRAWING: Figure 1A

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] For example, in power semiconductor devices, there is a demand for functions such as deterioration prediction and lifetime prediction associated with use.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention aim to provide a semiconductor device capable of recording the amount of voltage change dV / dt with respect to time when the voltage changes steeply.

Means for Solving the Problems

[0005] According to an embodiment of the present invention, a semiconductor device includes a first semiconductor region, a first electrode, a second electrode, a first gate electrode, and a first insulating member positioned between the first gate electrode and the first semiconductor region. A main element controls the current flowing between the first electrode and the second electrode through the first semiconductor region by the gate voltage of the first gate electrode, and a recording element is electrically connected to the first electrode and records the maximum value of the change amount dV / dt of the voltage of the first electrode with respect to time as analog data.

Brief Description of the Drawings

[0006] [Figure 1A] It is a schematic diagram showing the configuration of a semiconductor device according to an embodiment. [Figure 1B] It is a schematic diagram showing the configuration of a semiconductor device according to an embodiment. [Figure 2] This is a schematic diagram showing the configuration of a semiconductor device according to an embodiment. [Figure 3] (a) is a schematic cross-sectional view of the main element of the embodiment, and (b) is a schematic cross-sectional view of the recording element of the embodiment. [Figure 4] This is a schematic diagram showing the configuration of a semiconductor device of another embodiment. [Figure 5] This is a schematic cross-sectional view of the main element and recording element of the embodiment. [Figure 6] This is a schematic perspective view of the main element of the embodiment. [Figure 7] This is a schematic perspective view of the main element of the embodiment. [Figure 8] This is a schematic cross-sectional view of the main element of the embodiment. [Figure 9] (a) and (b) are schematic perspective views of the main element of the embodiment. [Figure 10] This is a schematic perspective view of the recording element of the embodiment. [Figure 11] This is a schematic cross-sectional view of the recording element of the embodiment. [Figure 12] This is a schematic cross-sectional view of the recording element of the embodiment. [Modes for carrying out the invention]

[0007] Each embodiment will be described below with reference to the drawings. Drawings are schematic or conceptual, and the relationships between the thickness and width of each part, as well as the ratios of the sizes of different parts, are not necessarily identical to those of reality. Even when representing the same part, the dimensions and ratios may be depicted differently in different drawings. Furthermore, identical or similar elements are assigned the same symbol.

[0008] As shown in Figures 1A, 1B, and 2, the semiconductor device of the embodiment comprises a main element 210 and a recording element 220. The main element 210 is, for example, a power semiconductor element that controls or converts power. The main element 210 has, for example, a vertical MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure.

[0009] As shown in Figure 3(a), the main element 210 has a first semiconductor region 211, a first electrode 221, a second electrode 222, and a first gate electrode 231. The gate voltage of the first gate electrode 231 controls the current flowing between the first electrode 221 and the second electrode 222 via the first semiconductor region 211.

[0010] The main element 210 may further include a substrate 201. The first semiconductor region 211 is provided on the first surface 201A of the substrate 201. One direction parallel to the first surface 201A of the substrate 201 is defined as the X-axis direction. A direction parallel to the first surface 201A and perpendicular to the X-axis direction is defined as the Y-axis direction. A direction perpendicular to both the X-axis and Y-axis directions is defined as the Z-axis direction. For example, in the main element, the direction along the Y-axis is defined as the first direction Y, the direction along the X-axis is defined as the second direction X, and the direction along the Z-axis is defined as the third direction Z. In the third direction Z, the direction in which the Z-axis arrow points is defined as "upwards" or "upper side".

[0011] The first semiconductor region 211 includes a first semiconductor portion 211A of a first conductivity type provided on the first surface 201A of the substrate 201, a second semiconductor portion 211B of a second conductivity type provided on the first semiconductor portion 211A, and a third semiconductor portion 211C of a first conductivity type provided on the second semiconductor portion 211B. In this specification, for example, the first conductivity type is n-type and the second conductivity type is p-type. The first conductivity type may be p-type and the second conductivity type may be n-type.

[0012] The substrate 201 is, for example, n-type and functions as a drain layer. The n-type impurity concentration of the substrate 201 is higher than that of the first semiconductor portion 211A. The first semiconductor portion 211A functions as a drift layer. The second semiconductor portion 211B functions as a base layer. The third semiconductor portion 211C functions as a source layer. The n-type impurity concentration of the third semiconductor portion 211C is higher than that of the first semiconductor portion 211A.

[0013] The main element 210 has, for example, a trench gate structure. On the upper surface side of the first semiconductor region 211, a plurality of first gate electrodes 231 are arranged in the second direction X. The side surfaces of the first gate electrodes 231 face the second semiconductor portion 211B. In one trench formed on the upper surface side of the first semiconductor region 211, for example, two first gate electrodes 231 are located apart from each other in the second direction X.

[0014] The first electrode 221 is provided on the second surface 201B located on the opposite side of the first surface 201A of the substrate 201. The first electrode 221 is electrically connected to the substrate (drain layer) 201. The first electrode 221 functions as a drain electrode.

[0015] The second electrode 222 is provided on the upper surface of the first semiconductor region 211 and is electrically connected to the third semiconductor portion 211C. The second electrode 222 functions as a source electrode. Also, the second electrode 222 is in contact with the second semiconductor portion 211B.

[0016] The main element 210 can further include a first insulating member 241. The first insulating member 241 is provided between two first gate electrodes 231 in one trench, between the first gate electrode 231 and the first semiconductor region 211, and between the first gate electrode 231 and the second electrode 222. In the first insulating member 241, the portion provided between the first gate electrode 231 and the second semiconductor portion 211B functions as a first gate insulating film. When a gate voltage equal to or higher than the threshold value is applied to the first gate electrode 231, a channel (inversion layer) is formed in the portion of the second semiconductor portion 211B facing the first gate electrode 231. In the on state of the main element 210, current flows between the first electrode 221 and the second electrode 222 through the substrate (drain layer) 201, the first semiconductor portion (drift layer) 211A, the channel, and the third semiconductor portion (source layer) 211C.

[0017] The main element 210 can further include a field plate electrode 251 provided below the first gate electrode 231. The first insulating member 241 is also provided between the field plate electrode 251 and the first semiconductor region 211, and between the field plate electrode 251 and the first gate electrode 231. The field plate electrode 251 is supplied with, for example, the potential (source potential) of the second electrode 222. The source potential is, for example, the ground potential. The field plate electrode 251 can relax the electric field (vertical electric field) applied in the third direction Z and improve the breakdown voltage.

[0018] The first electrode 221 of the main element 210 is electrically connected to the power supply 1000, and a voltage Vd is applied to the first electrode 221 from the power supply 1000. The second electrode 222 of the main element 210 is grounded. The first gate electrode 231 of the main element 210 is electrically connected to the gate driver 300, and a gate voltage Vg is applied to the first gate electrode 231 from the gate driver 300.

[0019] The recording element 220 has a vertical MOSFET structure similar to that of the main element 210. As shown in Figure 3(b), the recording element 220 includes a substrate 202, a second semiconductor region 212, a third electrode 223, a fourth electrode 224, and at least one pair of second gate electrodes 232. One direction parallel to the first surface 202A of the substrate 202 is defined as the X-axis direction. A direction parallel to the first surface 202A and perpendicular to the X-axis direction is defined as the Y-axis direction. A direction perpendicular to both the X-axis and Y-axis directions is defined as the Z-axis direction. In the recording element 220, the direction along the Y-axis is defined as the fourth direction Y, the direction along the X-axis is defined as the fifth direction X, and the direction along the Z-axis is defined as the sixth direction Z. The orientations of the main element 210 and the recording element 220 are independent of each other and do not necessarily coincide. However, for simplicity, we will explain this by assuming that the X-axis, Y-axis, and Z-axis directions defined by the main element 210 coincide with the X-axis, Y-axis, and Z-axis directions defined by the recording element 220.

[0020] The second semiconductor region 212 includes a fourth semiconductor portion 212A of a first conductivity type provided on the first surface 202A of the substrate 202, a fifth semiconductor portion 212B of a second conductivity type provided on the fourth semiconductor portion 212A, and a sixth semiconductor portion 212C of a first conductivity type provided on the fifth semiconductor portion 212B.

[0021] Substrate 202 functions as a drain layer, similar to the main element 210. The n-type impurity concentration of substrate 202 is higher than that of the fourth semiconductor section 212A. The fourth semiconductor section 212A functions as a drift layer. The fifth semiconductor section 212B functions as a base layer. The sixth semiconductor section 212C functions as a source layer. The n-type impurity concentration of the sixth semiconductor section 212C is higher than that of the fourth semiconductor section 212A.

[0022] On the upper surface of the second semiconductor region 212, at least one pair of second gate electrodes 232 are aligned in the fifth direction X. Of the pair of second gate electrodes 232, the side of one second gate electrode 232 facing the other second gate electrode 232, and the side of the other second gate electrode 232 facing the one second gate electrode 232, each face the fifth semiconductor region 212B.

[0023] The third electrode 223 is located on the second surface 202B of the substrate 202, which is opposite the first surface 202A. The third electrode 223 is electrically connected to the substrate (drain layer) 202 and functions as a drain electrode.

[0024] The fourth electrode 224 is provided on the upper surface of the second semiconductor region 212 and is electrically connected to the sixth semiconductor portion 212C. The fourth electrode 224 functions as a source electrode. The fourth electrode 224 is also in contact with the fifth semiconductor portion 212B.

[0025] The recording element 220 may further have a second insulating member 244. The second insulating member 244 is provided between the second gate electrode 232 and the second semiconductor region 212, and between the second gate electrode 232 and the fourth electrode 224. In the second insulating member 244, the portion provided between the second gate electrode 232 and the fifth semiconductor portion 212B functions as a second gate insulating film.

[0026] The recording element 220 is electrically connected to the first electrode 221 of the main element 210 and records the maximum value of the change in voltage of the first electrode 221 with respect to time, dV / dt, as analog data.

[0027] For example, the recording element 220 has a capacitor 502 that holds an amount of charge proportional to the voltage dV / dt of the first electrode 221. In the example shown in Figure 3(b), the capacitor 502 has a pair of second gate electrodes 232 facing each other in the fifth direction X, and a part of the second semiconductor region 212 (fifth semiconductor portion 212B) located between the pair of second gate electrodes 232.

[0028] When capacitor 502 is charged with a charge corresponding to a gate voltage above a threshold, a channel (inversion layer) is formed in the portion of the fifth semiconductor section 212B facing the second gate electrode 232. When a voltage is applied between the third electrode 223 and the fourth electrode 224, the magnitude of the current flowing between the third electrode 223 and the fourth electrode 224 changes according to the amount of charge in capacitor 502, via the substrate (drain layer) 202, the fourth semiconductor section (drift layer) 212A, the channel, and the sixth semiconductor section (source layer) 212C.

[0029] In the example shown in Figure 1A, the recording element 220 is electrically connected to the first electrode 221 of the main element 210 via the differentiating circuit 400 and the peak hold circuit 500.

[0030] The voltage at the first electrode 221 of the main element 210 is differentiated by the differentiating circuit 400. As shown in Figure 1B, the differentiating circuit 400 is a CR circuit including, for example, a capacitor 401 and a resistor 402. The differentiating circuit 400 outputs the time derivative (dV / dt) of the voltage at the first electrode 221.

[0031] The peak hold circuit 500 includes, for example, a first diode 501 and a capacitor 502. In the example shown in Figure 1, the recording element 220 records the maximum positive dV / dt when the main element 210 is turned on. In this case, the anode of the first diode 501 is connected to the differentiating circuit 400, and the cathode of the first diode 501 is connected to the capacitor 502. The cathode of the second diode 601 is connected between the cathode of the first diode 501 and the capacitor 502. The anode of the second diode 601 is connected to ground.

[0032] When the output dV / dt of the differentiating circuit 400, which is the input voltage to the peak hold circuit 500, is greater than the voltage charging the capacitor 502 (the potential of the second gate electrode 232), current flows forward through the first diode 501, charging the capacitor 502. When the input voltage to the peak hold circuit 500 (the output dV / dt of the differentiating circuit 400) becomes equal to the voltage charging the capacitor 502, no current flows through the first diode 501. Therefore, the capacitor 502 analogously holds the maximum value of dV / dt applied to the first electrode 221 of the main element 210 as the amount of charge.

[0033] When a voltage is applied between the third electrode 223 and the fourth electrode 224 of the recording element 220, the magnitude of the current (readout current) flowing between the third electrode 223 and the fourth electrode 224 through the second semiconductor region 212 changes according to the amount of charge held by the capacitor 502 (potential of the second gate electrode 232). From the magnitude of this readout current, the amount of charge held by the capacitor 502 can be determined, and from the amount of charge held by the capacitor 502, the maximum value of dV / dt applied to the first electrode 221 of the main element 210 can be determined. From this maximum value of dV / dt, it is possible to predict the degradation and lifespan of the main element 210 as it is used. For example, the main element 210 can be replaced before its performance deteriorates due to its lifespan or before it fails.

[0034] The recording element 220 records the maximum value of the voltage dV / dt of the first electrode 221 of the main element 210 as a continuously changing charge amount, i.e., analog data. Therefore, compared to digital recording using, for example, a CMOS circuit and a non-volatile counter, this embodiment eliminates the need for a large-scale configuration and reduces costs.

[0035] The third electrode 223 and fourth electrode 224 of the recording element 220 need to be voltageed independently of the first electrode 221 and second electrode 222 of the main element 210. For this reason, for example, the main element 210 and the recording element 220 can be formed on the same wafer or on a different wafer using a similar process, then separated into individual chips. Alternatively, the main element 210 and the recording element 220 can be integrated into a single chip. In this case, the third electrode 223 and fourth electrode 224 of the recording element 220 need to be electrically isolated from the first electrode 221 and second electrode 222 of the main element 210.

[0036] Figure 2 shows an example circuit in which the recording element 220 records the maximum value of negative dV / dt when the main element 210 is turned off. The orientation of the first diode 501 and the second diode 601 is reversed compared to the circuit in Figure 1B. In the example in Figure 2, the cathode of the first diode 501 is connected to the differentiating circuit 400, and the anode of the first diode 501 is connected to the capacitor 502. The anode of the second diode 601 is connected between the anode of the first diode 501 and the capacitor 502. The cathode of the second diode 601 is connected to ground.

[0037] As shown in Figure 4, the semiconductor device may include a plurality of recording elements 220 whose electrical connection to the first electrode 221 of the main element 210 is sequentially switched.

[0038] Each of the multiple recording elements 220 is connected to a corresponding peak-hold circuit 500. Each of the multiple peak-hold circuits 500 is connected to a differentiating circuit 400 via a corresponding switching element 802. Each of the multiple switching elements 802 is switched on or off by the Q output signal of the corresponding flip-flop 801. The multiple flip-flops 801 constitute a ring counter, and the output of the final stage flip-flop 801 is supplied to the input of the first stage flip-flop 801.

[0039] The rising edge of the gate voltage (gate signal) output by the gate driver 300 causes the flip-flop 801 to turn on the corresponding switching element 802, and the recording element 220 corresponding to the turned-on switching element 802 is electrically connected to the differentiating circuit 400 and the peak-hold circuit 500. The reset circuit 803 applies the gate potential of the recording element 220 to the D input of the first-stage flip-flop 801. As the recording elements 220 connected to the differentiating circuit 400 are switched sequentially, the maximum values ​​of dV / dt for several periods immediately before the main element 210 fails, for example, can be recorded.

[0040] As shown below with reference to Figures 5 to 11, other examples of main elements and recording elements with independent electrodes can be easily formed on the same chip.

[0041] As shown in Figure 6, the main element 110 is mounted on the support 100. As shown in Figure 10, the recording element 120 is mounted on the support 100. The support 100 has a first surface 100A. The first direction Y and the second direction X are parallel to the first surface 100A.

[0042] The main element 110 will be described with reference to Figures 6 to 9(b). Figure 7 shows the state in which the second conductive part 22b and the second insulating member 42 have been removed.

[0043] The support 100 has a substrate 101. The substrate 101 extends in a first direction Y and a second direction X. For example, a silicon substrate can be used as the substrate 101. The main element 110 has a first semiconductor region 11 provided on the substrate 101 in a third direction Z. The support 100 may further have an insulating layer 102 provided between the substrate 101 and the first semiconductor region 11 in the third direction Z. In this example, the upper surface of the insulating layer 102 becomes the first surface 100A of the support 100. For example, a silicon oxide layer can be used as the insulating layer 102.

[0044] The conductivity type of the first semiconductor region 11 is a first conductivity type. The first conductivity type is either n-type or p-type. Hereafter, the first conductivity type will be referred to as n-type. The first semiconductor region 11 is, for example, a silicon layer. The first semiconductor region 11 may also be a silicon carbide layer or a gallium nitride layer.

[0045] The main element 110 further comprises a first electrode 21 and a second electrode 22. The first electrode 21 and the second electrode 22 are located apart from each other in a first direction Y. The first semiconductor region 11 is provided between the first electrode 21 and the second electrode 22 in the first direction Y and is electrically connected to the first electrode 21 and the second electrode 22. The first electrode 21, the second electrode 22, and the first semiconductor region 11 extend in a third direction Z above the first surface 100A. This configuration allows for an increase in the density of the main elements 110 on the first surface 100A of the support 100, for example, by lowering the on-resistance per unit area.

[0046] The first electrode 21 may include, for example, at least one selected from the group consisting of Al, Cu, Mo, W, Ta, Co, Ru, Ti, and Pt.

[0047] The second electrode 22 has a first conductive portion 22a and a second conductive portion 22b. The first conductive portion 22a is in contact with the first semiconductor region 11. The first semiconductor region 11 and the first conductive portion 22a form a first Schottky junction S1. The first conductive portion 22a is located between the first semiconductor region 11 and the second conductive portion 22b in a first direction Y. The second conductive portion 22b is electrically connected to the first conductive portion 22a.

[0048] The first conductive portion 22a may include, for example, at least one selected from the group consisting of Ti, W, Mo, Ta, Zr, Al, Sn, V, Re, Os, Ir, Pt, Pd, Rh, Ru, Nb, Sr, and Hf. The second conductive portion 22b may include, for example, at least one selected from the group consisting of Al, Cu, Mo, W, Ta, Co, Ru, Ti, and Pt.

[0049] The main element 110 further has a first gate electrode 31. Multiple first gate electrodes 31 are arranged in a second direction X. The first gate electrodes 31 face the first Schottky junction S1 in the second direction X. For example, polycrystalline silicon can be used as the material for the first gate electrodes 31. As shown in Figure 7, the first gate electrodes 31 extend in a third direction Z. With this configuration, transistors can be provided at high density on the first surface 100A of the support 100, and the channel area per unit area can be increased. This can reduce, for example, the on-resistance.

[0050] The first electrode 21 is given a potential higher than the potential of the second electrode 22, and the second electrode 22 is given a potential lower than the potential of the first electrode 21 (for example, the ground potential). The first electrode 21 functions as a drain electrode, and the second electrode 22 functions as a source electrode. In addition, the n-type impurity concentration in the region in contact with the first electrode 21 in the first semiconductor region 11 may be made higher than the n-type impurity concentration in other regions. This can reduce the contact resistance between the first electrode 21 and the first semiconductor region 11.

[0051] The potential of the first gate electrode 31 allows control over the thickness of the Schottky barrier (distance in the first direction Y) at the first Schottky junction S1. When the Schottky barrier is thick, virtually no current flows between the second electrode 22 and the first semiconductor region 11. This results in an off state. In the off state, a depletion layer extends from the first Schottky junction S1 into the first semiconductor region 11, maintaining breakdown voltage.

[0052] By controlling the potential of the first gate electrode 31, the Schottky barrier is thinned, allowing a tunnel current to flow between the second electrode 22 and the first semiconductor region 11. The flow of this tunnel current results in an ON state.

[0053] The main element 110 may further include a field plate electrode 51, a first insulating member 41, and a second insulating member 42.

[0054] The field plate electrode 51 is provided within a trench formed in the first semiconductor region 11 and extends in the first direction Y and the third direction Z. The field plate electrode 51 is electrically connected to, for example, the second electrode 22. The field plate electrode 51 can mitigate the electric field applied to the first semiconductor region 11 in the first direction Y, thereby increasing the breakdown voltage. For example, polycrystalline silicon can be used as the material for the field plate electrode 51.

[0055] The first insulating member 41 is provided between the first gate electrode 31 and the first semiconductor region 11, between the field plate electrode 51 and the first semiconductor region 11, between the first gate electrode 31 and the field plate electrode 51, and between adjacent first gate electrodes 31 in the second direction X, and extends in the third direction Z. The first insulating member 41 has a first gate insulating portion 41a. The first gate insulating portion 41a is provided between the first gate electrode 31 and the first semiconductor region 11, between the first gate electrode 31 and the first Schottky junction S1, and between the first gate electrode 31 and the first conductive portion 22a. The first gate electrode 31 faces the first Schottky junction S1 in the second direction X via the first gate insulating portion 41a. For example, silicon oxide can be used as the material for the first insulating member 41.

[0056] The second insulating member 42 is provided between the first gate electrode 31 and the second conductive portion 22b, and between the first insulating member 41 and the second conductive portion 22b, and extends in the third direction Z. For example, silicon oxide can be used as the material for the second insulating member 42.

[0057] As shown in Figure 9(a), the substrate 101 has a second surface 101B located opposite the first surface 100A in the third direction Z. A first wiring section D is provided on the second surface 101B of the substrate 101, which is electrically connected to the first electrode 21. The first electrode 21 can be electrically connected to an external circuit via the first wiring section D. In the third direction Z, a second wiring section S can be provided above the first semiconductor region 11, above the first gate electrode 31, and above the field plate electrode 51 via an interlayer insulating layer. The second wiring section S is electrically connected to the second conductive portion 22b of the second electrode 22. The second electrode 22 can be electrically connected to an external circuit via the second wiring section S. A first gate wiring G1 extending in the second direction X is provided on a plurality of first gate electrodes 31 arranged in the second direction X, and the plurality of first gate electrodes 31 can be electrically connected to the first gate wiring G1.

[0058] Alternatively, as shown in Figure 9(b), a second wiring section S electrically connected to the second conductive portion 22b of the second electrode 22 may be provided on the second surface 101B of the substrate 101. In the third direction Z, a first wiring section D electrically connected to the first electrode 21 via an interlayer insulating layer can be provided above the first semiconductor region 11, above the first gate electrode 31, and above the field plate electrode 51.

[0059] As shown in Figure 5, multiple cell groups (first to fourth cell groups 71 to 74) are provided in the region where the main element 110 of the semiconductor device is located. In the first direction Y, the second cell group 72 is located between the first cell group 71 and the fourth cell group 74, and the third cell group 73 is located between the second cell group 72 and the fourth cell group 74. In each cell group, the structures shown in Figures 6 to 8 described above are repeated multiple times in the second direction X.

[0060] The direction from the first electrode 21 of the first cell group 71 to the second electrode 22 of the first cell group 71 is the opposite of the direction from the first electrode 21 of the second cell group 72 to the second electrode 22 of the second cell group 72. The direction from the first electrode 21 of the third cell group 73 to the second electrode 22 of the third cell group 73 is the opposite of the direction from the first electrode 21 of the fourth cell group 74 to the second electrode 22 of the fourth cell group 74. The direction from the first electrode 21 of the first cell group 71 to the second electrode 22 of the first cell group 71 is the same as the direction from the first electrode 21 of the third cell group 73 to the second electrode 22 of the third cell group 73. The direction from the first electrode 21 of the second cell group 72 to the second electrode 22 of the second cell group 72 is the same as the direction from the first electrode 21 of the fourth cell group 74 to the second electrode 22 of the fourth cell group 74.

[0061] In the second cell group 72 and the third cell group 73, the first electrode 21 is shared. In the first cell group 71 and the second cell group 72, the second electrode 22 is shared. In the third cell group 73 and the fourth cell group 74, the second electrode 22 is shared.

[0062] The main element 110 can, for example, constitute a high-side switching element and a low-side switching element in a voltage converter.

[0063] Next, the recording element 120 will be described with reference to Figures 10 and 11. In this example, the recording element 120 is provided on the same substrate 101 as the main element 110, the fourth direction of the recording element 120 coincides with the first direction Y of the main element 110, the fifth direction of the recording element 120 coincides with the second direction X of the main element 110, and the sixth direction of the recording element 120 coincides with the third direction Z of the main element 110.

[0064] The recording element 120 has a second semiconductor region 12 provided on the substrate 101 in the third direction (sixth direction) Z. The conductivity type of the second semiconductor region 12 is the first conductivity type. The material of the second semiconductor region 12 can be the same as the material of the first semiconductor region 11 of the main element 110.

[0065] The recording element 120 further includes a third electrode 23 and a fourth electrode 24. The third electrode 23 and the fourth electrode 24 are located apart from each other in the first direction (fourth direction) Y. The second semiconductor region 12 is provided between the third electrode 23 and the fourth electrode 24 in the first direction (fourth direction) Y and is electrically connected to the third electrode 23 and the fourth electrode 24. The third electrode 23, the fourth electrode 24, and the second semiconductor region 12 extend in the third direction (sixth direction) Z above the first surface 100A of the support 100.

[0066] The fourth electrode 24 has a third conductive portion 24a and a fourth conductive portion 24b. The third conductive portion 24a is in contact with the second semiconductor region 12. The second semiconductor region 12 and the third conductive portion 24a form a second Schottky junction S2. The third conductive portion 24a is located between the second semiconductor region 12 and the fourth conductive portion 24b in the first direction (fourth direction) Y. The fourth conductive portion 24b is electrically connected to the third conductive portion 24a.

[0067] The material of the third electrode 23 can be the same as the material of the first electrode 21 of the main element 110. The material of the third conductive part 24a can be the same as the material of the first conductive part 22a of the main element 110. The material of the fourth conductive part 24b can be the same as the material of the second conductive part 22b of the main element 110.

[0068] The recording element 120 further has a second gate electrode 32. Multiple second gate electrodes 32 are arranged in the second direction (fifth direction) X. The second gate electrodes 32 face the second Schottky junction S2 in the second direction (fifth direction) X. The second gate electrodes 32 extend in the third direction (sixth direction) Z. The material of the second gate electrodes 32 can be the same material as the first gate electrode 31 of the main element 110.

[0069] The potential of the second gate electrode 32 allows control over the thickness of the Schottky barrier in the second Schottky junction S2 (distance in the first direction (fourth direction) Y). By controlling the potential of the second gate electrode 32, the Schottky barrier becomes thinner, allowing a tunnel current to flow between the fourth electrode 24 and the second semiconductor region 12. This allows a current to flow between the third electrode 23 and the fourth electrode 24 via the second semiconductor region 12.

[0070] The recording element 120 may further include a third insulating member 43 and a fourth insulating member 44.

[0071] The third insulating member 43 is provided between the second gate electrode 32 and the second semiconductor region 12 and extends in the third direction (sixth direction) Z. As shown in Figure 11, the third insulating member 43 has a second gate insulating portion 43a. The second gate insulating portion 43a is provided between the second gate electrode 32 and the second semiconductor region 12, between the second gate electrode 32 and the second Schottky junction S2, and between the second gate electrode 32 and the third conductive portion 24a. The second gate electrode 32 faces the second Schottky junction S2 in the second direction (fifth direction) X via the second gate insulating portion 43a. The material of the third insulating member 43 can be the same material as the first insulating member 41 of the main element 110.

[0072] The fourth insulating member 44 is provided between the second gate electrode 32 and the fourth conductive part 24b, and between the third insulating member 43 and the fourth conductive part 24b, and extends in the third direction (sixth direction) Z. The material of the fourth insulating member 44 can be the same as the material of the second insulating member 42 of the main element 110.

[0073] The semiconductor device of the embodiment can be configured by replacing the main element 210 shown in Figures 1A, 1B, 2, and 4 with the main element 110 shown in Figures 5 to 9(b), and by replacing the recording element 220 shown in Figures 1A, 1B, 2, and 4 with the recording element 120 shown in Figures 10 and 11.

[0074] Specifically, the first electrode 21 of the main element 110 is electrically connected to the power supply 1000, and a voltage Vd is applied to the first electrode 21 from the power supply 1000. The second electrode 22 of the main element 110 is grounded. The first gate electrode 31 of the main element 110 is electrically connected to the gate driver 300, and a gate voltage Vg is applied to the first gate electrode 31 from the gate driver 300.

[0075] When the output dV / dt of the differentiating circuit 400, which is the input voltage to the peak hold circuit 500, is greater than the voltage charging the capacitor 502 (the potential of the second gate electrode 32), current flows forward through the first diode 501, charging the capacitor 502. When the input voltage to the peak hold circuit 500 (the output dV / dt of the differentiating circuit 400) becomes equal to the voltage charging the capacitor 502, no current flows through the first diode 501. Therefore, the capacitor 502 analogously holds the maximum value of dV / dt applied to the first electrode 21 of the main element 110 as the amount of charge.

[0076] When a voltage is applied between the third electrode 23 and the fourth electrode 24 of the recording element 120, the magnitude of the current (readout current) flowing between the third electrode 23 and the fourth electrode 24 through the second semiconductor region 12 changes according to the amount of charge held by the capacitor 502 (potential of the second gate electrode 32). From the magnitude of this readout current, the amount of charge held by the capacitor 502 can be determined, and from the amount of charge held by the capacitor 502, the maximum value of dV / dt applied to the first electrode 21 of the main element 110 can be determined. From this maximum value of dV / dt, it is possible to predict the degradation and lifespan of the main element 110 as it is used. For example, the main element 210 can be replaced before its performance deteriorates due to its lifespan or before it fails.

[0077] In this example as well, the recording element 120 records the maximum value of the voltage dV / dt of the first electrode 221 of the main element 210 as a continuously changing charge amount, i.e., analog data, thus eliminating the need for a large-scale configuration and reducing costs.

[0078] As shown in Figures 5 to 11, the main element 110 and recording element 120 can be formed using the same process simply by changing the mask patterns used during film deposition and etching to form each component of the main element 110 and the recording element 120. For example, the first semiconductor region 11 and the second semiconductor region 12 can be formed on the same substrate 101, and the main element 110 and the recording element 120 can be configured as a single chip. This makes it possible to integrate a power semiconductor device with a built-in recording element 120 into a single chip at a low cost. When the main element 110 and the recording element 120 are integrated into a single chip, it becomes possible to reduce the parasitic inductance of the wiring that electrically connects the main element 110 and the recording element 120.

[0079] The semiconductor device may incorporate multiple recording elements 120. On the substrate 101, a fifth insulating member 60 can be provided between the main element 110 and the recording elements 120, as shown in Figure 5. The fifth insulating member 60 can also be provided between the multiple recording elements 120. For example, silicon oxide can be used as the material for the fifth insulating member 60.

[0080] Alternatively, the first semiconductor region 11 and the second semiconductor region 12 may be formed on the same substrate 101, and then separated into a main element chip 110 and a recording element chip 120. In this case, the main element chip 110 and the recording element chip 120 can be mounted on the same wiring board and packaged. In this case, the wiring board can be included as a support for the main element 110 and the recording element 120.

[0081] The third electrode 23 of the recording element 120 can be electrically connected to an external circuit via a third wiring section provided above the second semiconductor region 12 in the third direction (sixth direction) Z. The fourth electrode 24 can be electrically connected to an external circuit via a fourth wiring section provided above the second semiconductor region 12 in the third direction (sixth direction) Z. The second gate electrode 32 is provided on the second gate electrode 32 and can be electrically connected to a second gate wiring G2 extending in the second direction (fifth direction) X.

[0082] Preferably, the third electrode 23 and fourth electrode 24 of the recording element 120 are located on the first surface 100A and not on the second surface 101B. This makes it possible to suppress leakage current between the aforementioned first wiring section D or second wiring section S of the main element 110 on the second surface 101B of the substrate 101 and the main electrodes (third electrode 23 and fourth electrode 24) of the recording element 120.

[0083] The voltage applied between the first electrode 21 and the second electrode 22 of the main element 110 is higher than the voltage applied between the third electrode 23 and the fourth electrode 24 of the recording element 120. For example, the voltage applied between the first electrode 21 and the second electrode 22 of the main element 110 is 100V or more, while the voltage applied between the third electrode 23 and the fourth electrode 24 of the recording element 120 is only a few volts. Therefore, in order to increase the breakdown voltage of the main element 110, it is preferable that the thickness of the first semiconductor region 11 of the main element 110 in the first direction Y is greater than the thickness of the second semiconductor region 12 of the recording element 120 in the first direction (fourth direction) Y.

[0084] As shown in Figure 12, for example, a resistive random-access memory can be used as the recording element 700. The recording element 700 has a resistive random-access layer 703 whose resistance changes in accordance with the charge supplied from the gate driver each time the main element is turned on.

[0085] The resistive change layer 703 is provided between the fifth electrode 701 and the sixth electrode 702 in the third direction Z. The sixth electrode 702 has a first portion 702A and a second portion 702B. The second portion 702B is provided between the first portion 702A and the resistive change layer 703. The fifth electrode 701 extends in the second direction X, and the first portion 702A of the sixth electrode 702 extends in the first direction Y. The second portion 702B and the resistive change layer 703 are provided in a columnar shape at the intersection of the fifth electrode 701 and the first portion 702A of the sixth electrode 702. The side surface of the sixth electrode 702, the side surface of the resistive change layer 703, and the upper surface of the fifth electrode 701 are covered with an insulating member 704.

[0086] For example, titanium nitride can be used as the material for the fifth electrode 701 and the first portion 702A of the sixth electrode 702. For example, titanium can be used as the material for the second portion 702B of the sixth electrode 702. For example, silicon oxide can be used as the material for the resistive change layer 703. For example, silicon nitride can be used as the material for the insulating member 704.

[0087] The voltage dV / dt of the first electrode of the main element is applied to the fifth electrode 701 and the sixth electrode 702. In accordance with dV / dt, the resistance of the resistive change layer 703 continuously increases (or decreases). When a dV / dt greater than the previously applied dV / dt is applied to the fifth electrode 701 and the sixth electrode 702, the resistance of the resistive change layer 703 increases (or decreases). When a dV / dt less than or equal to the previously applied dV / dt is applied to the fifth electrode 701 and the sixth electrode 702, the resistance of the resistive change layer 703 does not change. Therefore, the resistive change layer 703 can maintain the maximum value of dV / dt.

[0088] When reading the resistance of the resistive transition layer 703, applying a voltage between the fifth electrode 701 and the sixth electrode 702 changes the magnitude of the current (read current) flowing between the fifth electrode 701 and the sixth electrode 702, depending on the resistance of the resistive transition layer 703. From the magnitude of this read current, the resistance of the resistive transition layer 703 can be determined, and from the resistance of the resistive transition layer 703, the maximum value of dV / dt applied to the first electrode of the main element can be determined.

[0089] In the recording element 700, the maximum value of the voltage dV / dt of the first electrode of the main element is recorded as analog data, i.e., as the continuously changing resistance of the resistive switching layer 703. This eliminates the need for a large-scale configuration and reduces costs.

[0090] The recording element 700 can be formed, for example, on the main element 110 shown in Figures 5 to 9(b), with an interlayer insulating layer in between, allowing the main element 110 and the recording element 700 to be integrated into a single chip.

[0091] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0092] 11...First semiconductor region, 12...Second semiconductor region, 21...First electrode, 22...Second electrode, 23...Third electrode, 24...Fourth electrode, 31...First gate electrode, 32...Second gate electrode, 100...Support, 101...Substrate, 110...Main element, 120...Recording element, 201...Substrate, 210...Main element, 211...First semiconductor region, 212...Second semiconductor region, 220...Recording element, 221...First electrode Electrode, 222...Second electrode, 223...Third electrode, 224...Fourth electrode, 231...First gate electrode, 232...Second gate electrode, 300...Gate driver, 400...Differentiation circuit, 500...Peak hold circuit, 502...Capacitor, 700...Recording element, 701...Fifth electrode, 702...Sixth electrode, 703...Resistivity layer, S1...First Schottky junction, S2...Second Schottky junction

Claims

1. A main element comprising a first semiconductor region, a first electrode, a second electrode, a first gate electrode, and a first insulating member located between the first gate electrode and the first semiconductor region, wherein the gate voltage of the first gate electrode controls the current flowing between the first electrode and the second electrode via the first semiconductor region. A recording element electrically connected to the first electrode, which records the maximum value of the change in voltage of the first electrode with respect to time dV / dt as analog data, Equipped with, The recording element has a capacitor that holds the maximum value of dV / dt as an electric charge. The capacitor is a semiconductor device having a second semiconductor region, a third electrode, a fourth electrode, a second gate electrode, and a second insulating member located between the second gate electrode and the second semiconductor region.

2. The semiconductor device according to claim 1, wherein the recording element records the maximum value of dV / dt when the main element is turned on.

3. The semiconductor device according to claim 1, wherein the recording element records the maximum value of dV / dt at the time of turn-off of the main element.

4. The semiconductor device according to claim 1, comprising a plurality of recording elements whose electrical connection to the first electrode is sequentially switched.

5. The support further comprises a support having a first surface and supporting the main element and the recording element, The first electrode and the second electrode of the main element are positioned apart from each other in a first direction along the first surface. The first semiconductor region of the main element is provided between the first electrode and the second electrode in a first direction, and forms a first Schottky junction with the second electrode. The first gate electrode of the main element faces the first Schottky junction in a second direction that intersects the first direction along the first surface. The third electrode and the fourth electrode of the recording element are positioned apart from each other in a fourth direction along the first surface. The second semiconductor region of the recording element is provided between the third electrode and the fourth electrode in the fourth direction, and forms a second Schottky junction with the fourth electrode. The semiconductor device according to claim 1, wherein the second gate electrode of the recording element faces the second Schottky junction in a fifth direction that intersects the fourth direction along the first surface.

6. The support has a substrate, The semiconductor device according to claim 5, wherein the first semiconductor region and the second semiconductor region are provided on the same substrate.

7. The substrate has a second surface located on the opposite side of the first surface in a third direction intersecting the first and second directions, The semiconductor device according to claim 6, wherein the third electrode and the fourth electrode of the recording element are located on the first surface and not on the second surface.

8. A main element comprising a first semiconductor region, a first electrode, a second electrode, a first gate electrode, and a first insulating member located between the first gate electrode and the first semiconductor region, wherein the gate voltage of the first gate electrode controls the current flowing between the first electrode and the second electrode via the first semiconductor region, A recording element electrically connected to the first electrode, which records the maximum value of the change in voltage of the first electrode with respect to time dV / dt as analog data, Equipped with, The recording element is a semiconductor device having a resistance change layer whose resistance changes according to the dV / dt.

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